JP6987015B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device.

Japanese Patent Application Laid-Open No. 2009-141067 (Patent Document 1) discloses a semiconductor device including an active region and a peripheral region surrounding the active region. A semiconductor element such as an insulated gate bipolar transistor (IGBT) is formed in the active region. A guard ring is formed in the peripheral region in order to secure the withstand voltage of the semiconductor element.

Japanese Unexamined Patent Publication No. 2009-141067

An object of the present invention is to improve the short circuit tolerance of a semiconductor device.

The semiconductor device of the present invention includes a semiconductor substrate. The semiconductor substrate includes an active region and an outer peripheral region surrounding the active region. The semiconductor substrate has a front surface and a back surface. The semiconductor device includes an n ^- drift region and a p ⁺ collector layer. The outer peripheral region includes an n ^- drift region and a p ⁺ back surface outer peripheral layer. The p ⁺ back surface outer layer is provided on the back surface side of the ^{n-drift region.} The first hole concentration in the p ⁺ back surface peripheral layer is higher than the second hole concentration in the ^{p + collector layer.}

At the time of load short circuit, holes are injected into the ^{n- drift region not only from the p +} collector layer but also from the p ⁺ back surface outer peripheral layer. The backside electric field strength at the pn junction formed by the n ^- drift region and the p ^{+ collector layer is reduced.} The semiconductor device of the present invention can improve the short circuit tolerance.

It is a schematic partial enlarged sectional view of the semiconductor device which concerns on Embodiment 1. FIG. It is a schematic partial enlarged sectional view which shows one step of the manufacturing method of the semiconductor device which concerns on Embodiment 1 and Embodiment 3. It is a schematic partial enlarged sectional view which shows the next process of the process shown in FIG. 2 in the manufacturing method of the semiconductor device which concerns on Embodiment 1 and Embodiment 3. It is a schematic partial enlarged sectional view which shows the next process of the process shown in FIG. 3 in the manufacturing method of the semiconductor device which concerns on Embodiment 1 and Embodiment 3. It is a schematic partial enlarged sectional view which shows the next process of the process shown in FIG. 4 in the manufacturing method of the semiconductor device which concerns on Embodiment 1 and Embodiment 3. It is a schematic partial enlarged sectional view of the semiconductor device which concerns on Embodiment 2. FIG. It is a schematic partial enlarged sectional view of the semiconductor device which concerns on Embodiment 3. FIG. It is a schematic partial enlarged sectional view which shows the next process of the process shown in FIG. 5 in the manufacturing method of the semiconductor device which concerns on Embodiment 3. FIG. It is a schematic partial enlarged sectional view of the semiconductor device which concerns on Embodiment 4. FIG.

Hereinafter, embodiments of the present invention will be described. The same reference number is assigned to the same configuration, and the description thereof will not be repeated.

Embodiment 1.
The semiconductor device 1 according to the first embodiment will be described with reference to FIG. The semiconductor device 1 mainly includes a semiconductor substrate 2, a first electrode 20, and a second electrode 30.

The semiconductor substrate 2 is, for example, a silicon substrate or a silicon carbide substrate. The semiconductor substrate 2 has a front surface 2a and a back surface 2b facing the front surface 2a. The semiconductor substrate 2 includes an active region 6 in which the semiconductor element 3 is provided, and an outer peripheral region 7 surrounding the active region 6. The semiconductor element 3 is, for example, an insulated gate bipolar transistor (IGBT).

The semiconductor element 3 includes an n ^- drift region 5, a p-base region 10, an n ⁺ type emitter region 14, a gate insulating film 17, a gate electrode 18, a p ⁺ collector layer 25, and a first electrode 20. , The second electrode 30 and the like. The semiconductor device 3 further includes an n-buffer layer 24 and a p ⁺ contact layer 15. The semiconductor device 3 ^{further includes an n +} charge storage layer 11.

The p-base region 10 is provided on the front surface 2a side with respect to the ^{n-drift region 5.} The p-base region 10 is formed from the front surface 2a to the first depth. The n ⁺ charge storage layer 11 is ^{formed between the n-} drift region 5 and the p-base region 10. n-type carriers (electrons) concentration of n ⁺ charge storage layer 11, n ^- larger than the n-type carrier concentration of the drift region 5.

The n ⁺ type emitter region 14 is formed in a part of the p-base region 10. Specifically, the n ⁺ type emitter region 14 is formed from the front surface 2a to a second depth. The second depth is smaller than the first depth. The n ⁺ type emitter region 14 is formed in a part of the front surface 2a. The p-type carrier (hole) concentration of the p ⁺ contact layer 15 is higher than the p-type carrier concentration of the p-base region 10. The p ⁺ contact layer 15 is formed on a part of the front surface 2a on which ^{the n + type emitter region 14 is not formed.}

The gate insulating film 17 is provided on the portion 12 of the p-base region 10 sandwiched between ^{the n +} type emitter region 14 and the n ^{-drift region 5.} When the semiconductor device 3 is turned on, a channel is formed in the portion 12 of the p-base region 10. Specifically, the gate insulating film 17 is formed on the side wall and the bottom surface of the trench 16 ^{that penetrates the n +} type emitter region 14, the p-base region 10 and the n ⁺ charge storage layer 11 and ^{reaches the n-drift region 5.} Has been done. The gate insulating film 17 is, for example, a SiO ₂ film.

The gate electrode 18 faces the portion 12 of the p-base region 10 with the gate insulating film 17 interposed therebetween. As an example, the gate electrode 18 is a trench gate electrode, and the semiconductor element 3 is a trench gate type IGBT. The gate electrode 18 is provided in the trench 16 via the gate insulating film 17.

The n-buffer layer 24 is provided on the back surface 2b side with respect to the ^{n-drift region 5.} The n-buffer layer 24 is in contact with the n ^- drift region 5 and the p ⁺ collector layer 25 in the active region 6. The first n-type carrier concentration in the n-buffer layer 24 is higher than the second n-type carrier concentration in the ^{n-drift region 5.} The n-buffer layer 24 contains an n-type dopant. The n-type dopant is, for example, phosphorus or arsenic. The thickness of the n-buffer layer 24 is smaller than the thickness ^{of the n-drift region 5.} In one example, the thickness of the n-buffer layer 24 is 0.5 times or less the thickness ^{of the n-drift region 5.} In another example, the thickness of the n-buffer layer 24 is 0.3 times or less the thickness ^{of the n-drift region 5.} In yet another example, the thickness of the n-buffer layer 24 is less than or equal to 0.1 times the thickness ^{of the n-drift region 5.} The thickness of the n-buffer layer 24 is, for example, 0.1 μm or more.

The p ⁺ collector layer 25 is provided on the back surface 2b of the semiconductor substrate 2. The p ⁺ collector layer 25 is provided on the back surface 2b side with respect to the ^{n-drift region 5.} The p ⁺ collector layer 25 is in contact with the n-buffer layer 24. The p ⁺ collector layer 25 contains a p-type dopant such as boron. The p-type carrier (hole) concentration of the p ⁺ collector layer 25 is higher than the p-type carrier concentration of the p-base region 10. The thickness of the p ⁺ collector layer 25 is, for example, 0.1 μm or more. The thickness of the p ⁺ collector layer 25 is, for example, 10 μm or less.

The semiconductor device 3 further includes a first electrode 20 and a second electrode 30. The first electrode 20 is ^{formed on the n +} type emitter region 14 on the front surface 2a. The first electrode 20 is also formed on the ^{p + contact layer 15 on the front surface 2a.} The first electrode 20 is in ^{contact with the n +} type emitter region 14 and the p ⁺ contact layer 15. The first electrode 20 functions as an emitter electrode. The first electrode 20 is electrically connected to the p base region 10 via ^{the p + contact layer 15.} The first electrode 20 is electrically insulated from the gate electrode 18 by the interlayer insulating film 19. The second electrode 30 is formed on the ^{p + collector layer 25 in the active region 6.} The second electrode 30 is in contact with the p ⁺ collector layer 25. The second electrode 30 functions as a collector electrode.

The outer peripheral region 7 includes an n ^- drift region 5 and a p ⁺ back surface outer peripheral layer 26. The n ^- drift region 5 and the second electrode 30 extend from the active region 6 to the outer peripheral region 7. The outer peripheral region 7 includes the n-buffer layer 24. The n-buffer layer 24 extends from the active region 6 to the outer peripheral region 7. The p-base region 10, the n ⁺ type emitter region 14, and the n ⁺ charge storage layer 11 are not formed in the outer peripheral region 7. The second electrode 30 is ^{formed on the p +} back surface outer peripheral layer 26 in the outer peripheral region 7.

The p ⁺ back surface outer peripheral layer 26 is provided on the back surface 2b side of the ^{n-drift region 5.} The p ⁺ back surface outer peripheral layer 26 is ^{formed between the n-} drift region 5 and the second electrode 30. The p ⁺ back surface outer peripheral layer 26 is in contact with the n-buffer layer 24. The p ⁺ back surface outer peripheral layer 26 is in contact with the second electrode 30. The p ⁺ back surface outer peripheral layer 26 is formed on the back surface 2b of the semiconductor substrate 2. The p ⁺ back surface outer peripheral layer 26 is in contact with the p ⁺ collector layer 25. For example, ^{the thickness of the p +} back surface outer peripheral layer 26 is 0.1 μm or more and 10 μm or less.

The first p-type carrier concentration in the p ⁺ back surface outer peripheral layer 26 is higher than the second p-type carrier concentration in the ^{p + collector layer 25.} In one example, the first p-type carrier concentration in the ^{p +} back surface peripheral layer 26 is more than twice the second p-type carrier concentration in the ^{p + collector layer 25.} In another example, the first p-type carrier concentration in the ^{p +} back surface peripheral layer 26 is more than five times the second ^{p-type carrier concentration in the p + collector layer 25.} In yet another example, the first p-type carrier concentration in the ^{p +} back surface peripheral layer 26 is more than 10 times the second ^{p-type carrier concentration in the p + collector layer 25.} In one example, in a plan view of the back surface 2b of the semiconductor substrate 2, the p ⁺ back surface outer peripheral layer 26 is formed so as to surround the active region 6. In another example, in the plan view of the back surface 2b of the semiconductor substrate 2, the p ⁺ back surface outer peripheral layer 26 is formed only in a part of the outer peripheral region 7 without surrounding the active region 6.

The outer peripheral region 7 includes an electric field limiting ring structure (FLR structure) 21 on the front surface 2a of the semiconductor substrate 2. In the plan view of the front surface 2a of the semiconductor substrate 2, the electric field limiting ring structure 21 surrounds the active region 6. The electric field limiting ring structure 21 is a p-type region. The electric field limiting ring structure 21 relaxes the electric field concentration in the outer peripheral region 7 and improves the withstand voltage of the semiconductor device 1. The electric field limiting ring structure 21 is separated from the first electrode 20 and is electrically isolated from the first electrode 20.

An example of the manufacturing method of the semiconductor device 1 according to the first embodiment will be described with reference to FIGS. 1 to 5.

As shown in FIG. 2, the manufacturing method of the semiconductor device 1 of the present embodiment includes preparing a semiconductor substrate 2 in which a part of the configuration of the semiconductor element 3 is formed on the front surface 2a side thereof. .. ^{Specifically, by a known method, the p-base region 10, the n +} type emitter region 14, and the p ⁺ contact are on the front surface 2a side of the active region 6 of the semiconductor substrate 2 (n ^{-drift region 5).} A layer 15, an n ⁺ charge storage layer 11, a gate insulating film 17, and a gate electrode 18 are formed. By a known method, the electric field limiting ring structure 21 is formed on the front surface 2a side of the outer peripheral region 7 of the semiconductor substrate 2 (n ^{-drift region 5).} The interlayer insulating film 19 and the first electrode 20 are formed on the front surface 2a of the active region 6 of the semiconductor substrate 2. The first electrode 20 is separated from the electric field limiting ring structure 21 and is electrically isolated from the electric field limiting ring structure 21. The first electrode 20 is ^{conductive to the n +} type emitter region 14 and the p ⁺ contact layer 15.

By processing the back surface 2b of the semiconductor substrate 2, the semiconductor substrate 2 (n ^- drift region 5) is thinned. In one example, the back surface 2b of the semiconductor substrate 2 (n ^- drift region 5) is ground using a grinder. In another example, the back surface 2b of the semiconductor substrate 2 (n ^- drift region 5) is wet-etched. The semiconductor substrate 2 (n ^- drift region 5) is not particularly limited, but is thinned to a thickness of 3 μm or more and 800 μm or less.

As shown in FIG. 3, the manufacturing method of the semiconductor device 1 of the present embodiment includes forming the n-buffer layer 24 on the back surface 2b by doping the back surface 2b with an n-type dopant. The n-buffer layer 24 is in contact with the n ^- drift region 5 and is provided on the back surface 2b side with respect to the ^{n-drift region 5.} The n-buffer layer 24 is formed in the active region 6 and the outer peripheral region 7. The n-type dopant is, for example, phosphorus or arsenic. The n-buffer layer 24 is annealed to activate the n-type dopant.

^{As shown in FIG. 4, in the manufacturing method of the semiconductor device 1 of the present embodiment, the p +} collector layer 25 is formed on the back surface 2b of the active region 6 of the semiconductor substrate 2 by doping the back surface 2b with a p-type dopant. Prepare to form. The p ⁺ collector layer 25 is also formed on the back surface 2b of the outer peripheral region 7 of the semiconductor substrate 2. The p ⁺ collector layer 25 is in contact with the n-buffer layer 24. The p-type dopant is, for example, boron.

As shown in FIG. 5, in the manufacturing method of the semiconductor device 1 of the present embodiment, the back surface 2b of the outer peripheral region 7 of the semiconductor substrate 2 is selectively doped with the p-type dopant on the back surface 2b of the outer peripheral region 7. It is provided with forming a p ⁺ back surface outer peripheral layer 26. Specifically, the mask 35 is formed on the back surface 2b of the active region 6 of the semiconductor substrate 2. A p-type dopant such as boron is selectively implanted into the back surface 2b of the outer peripheral region 7 using an ion implanter. The p ⁺ back surface outer peripheral layer 26 is in contact with the n-buffer layer 24. The p ⁺ back surface outer peripheral layer 26 is in contact with the p ⁺ collector layer 25. The p ⁺ back surface outer peripheral layer 26 is formed on the back surface 2b of the semiconductor substrate 2. The first p-type carrier concentration in the p ⁺ back surface outer peripheral layer 26 is higher than the second p-type carrier concentration in the ^{p + collector layer 25.} The p ⁺ collector layer 25 and the p ⁺ back surface outer peripheral layer 26 are annealed in order to activate the p-type dopant contained in the p ⁺ collector layer 25 and the p ^{+ back surface outer peripheral layer 26.}

The manufacturing method of the semiconductor device 1 of the present embodiment includes ^{forming a second electrode 30 on the p +} collector layer 25 and the p ⁺ back surface outer peripheral layer 26. The second electrode 30 is, for example, an Al / Ti / Ni / Au laminated film or an AlSi / Ti / Ni / Au laminated film. To ohmic contact with the second electrode 30 on the p ⁺ collector layer 25 and the p ⁺ back surface outer peripheral layer 26, and the second electrode 30 and the p ⁺ collector layer 25 and the p ⁺ back surface outer peripheral layer 26 is annealed. In this way, the semiconductor device 1 of the present embodiment shown in FIG. 1 is obtained.

The operation and operation of the semiconductor device 1 of the present embodiment will be described while comparing with the semiconductor device of the comparative example. The semiconductor device of the comparative example has the same configuration as the semiconductor device 1 of the present embodiment, but is different from the semiconductor device 1 of the present embodiment in ^{that the p + back surface outer peripheral layer 26 is not formed.}

In the latter half of the turn-on process of the semiconductor device (semiconductor device 1 of the present embodiment, the semiconductor device of the comparative example), the initial stage of the turn-off process, and the switching-on state, between the first electrode 20 and the second electrode 30. A relatively low voltage is applied. As used herein, the turn-on process of a semiconductor device means a process in which the semiconductor device transitions from an off state to an on state. The turn-off process of a semiconductor device means a process in which the semiconductor device transitions from an on state to an off state.

During the low voltage period, channels are formed in portion 12 of the p-base region 10. In the present specification, the low voltage period includes a turn-on process of the semiconductor device, a turn-off process of the semiconductor device, and a period in which the semiconductor device 1 is in the switching-on state. Electrons are injected from the first electrode 20 into the n ^- drift region 5 via this channel and the n ^{+ charge storage layer 11.} The injected electrons forward bias between ^{the p +} collector layer 25 and the n ^- drift region 5 via the n-buffer layer 24. Holes are injected from the second electrode 30 and the p ^{+ collector layer 25 into the n-} drift region 5 via the n-buffer layer 24. In this way, electrons and holes are ^{accumulated in the n-} drift region 5 at a high density. the n ^- drift region 5 conductivity modulation occurs, n ^- resistance of the drift region 5 is greatly reduced. The voltage between the first electrode 20 and the second electrode 30 is relatively low.

On the other hand, in the normal switching operation of the semiconductor device (semiconductor device 1 of the present embodiment, the semiconductor device of the comparative example), the first is in the early stage of the turn-on process of the semiconductor device and the latter half of the turn-off process of the semiconductor device. A high voltage is applied between the electrode 20 and the second electrode 30. Further, even when the load is short-circuited, a high voltage is applied between the first electrode 20 and the second electrode 30. In the present specification, when the load is short-circuited, it means a period during which the load (motor or the like) connected to the semiconductor device is short-circuited and the power supply voltage is directly applied to the semiconductor device.

Therefore, in the high voltage period, in a semiconductor device of the comparative example, n ^- holes stored at high have a density in the drift region 5 the n ^- are discharged from the drift region 5, n ^- the hole in the drift region 5 The density is greatly reduced. As used herein, the high voltage period includes the early stage of the turn-on process of the semiconductor device, the latter stage of the turn-off process of the semiconductor device, and the time of load short circuit. The backside electric field strength at the pn junction formed by the n ^- drift region 5 and the p ^{+ collector layer 25 increases.} In this embodiment, the pn junction is ^{formed by the n-} drift region 5 and the p ⁺ collector layer 25 via the n-buffer layer 24. In the semiconductor device of the comparative example, a high backside electric field is continuously applied to the pn junction formed by the ^n- drift region 5 and the p ^{+ collector layer 25 during the high voltage period including the time of load short circuit.} Therefore, in the high voltage period including the time of load short circuit, the time until the semiconductor device of the comparative example is destroyed is short, and the short circuit tolerance of the semiconductor device of the comparative example is low.

On the other hand, the semiconductor device 1 of the present embodiment includes the p ⁺ back surface outer peripheral layer 26 in the outer peripheral region 7. Therefore, in the high voltage period including the time of load short circuit, the holes are not only injected into the ^{n- drift region 5 from the second electrode 30 and the p +} collector layer 25 in the active region 6, but also the second holes in the outer peripheral region 7. It is also injected into the ^n- drift region 5 from the electrode 30 and the p ⁺ back surface outer peripheral layer 26 of the above. Since the first p-type carrier concentration in the ^{p + back surface outer peripheral layer 26 is higher than the second p-type carrier concentration in the p +} collector layer 25, more ^{positives are obtained from the p +} back surface outer peripheral layer 26 to the n ^- drift region 5. Holes can be injected. Thus, the backside electric field strength at the pn junction formed by ^{the n-} drift region 5 and the p ^{+ collector layer 25 is reduced.} The semiconductor device 1 of the present embodiment can lengthen the time until the semiconductor device 1 is destroyed in a high voltage period including a load short circuit, and can improve the short circuit tolerance of the semiconductor device 1. ..

The effect of the semiconductor device 1 of the present embodiment will be described.
The semiconductor device 1 of the present embodiment includes a semiconductor substrate 2. The semiconductor substrate 2 includes an active region 6 provided with a semiconductor element 3 and an outer peripheral region 7 surrounding the active region 6. The semiconductor substrate 2 has a front surface 2a and a back surface 2b. The semiconductor device 3 includes an n ^- drift region 5, a p-base region 10, an n ⁺ type emitter region 14, a gate insulating film 17, a gate electrode 18, and a p ⁺ collector layer 25. The gate insulating film 17 is provided on the portion 12 of the p-base region 10 between the ^{n +} type emitter region 14 and the n ^{-drift region 5.} The gate electrode 18 faces the portion 12 of the p-base region 10 with the gate insulating film 17 interposed therebetween. The p ⁺ collector layer 25 is provided on the back surface 2b. The outer peripheral region 7 includes an n ^- drift region 5 and a p ⁺ back surface outer peripheral layer 26. The n ^- drift region 5 extends from the active region 6 to the outer peripheral region 7. The p ⁺ back surface outer peripheral layer 26 is provided on the back surface 2b side of the ^{n-drift region 5.} The first hole concentration in the p ⁺ back surface outer layer 26 is higher than the second hole concentration in the ^{p + collector layer 25.}

At the time of load short circuit, holes are injected into the ^{n- drift region 5 not only from the p +} collector layer 25 but also from the p ⁺ back surface outer peripheral layer 26. The backside electric field strength at the pn junction formed by the n ^- drift region 5 and the p ^{+ collector layer 25 is reduced.} In the semiconductor device 1 of the present embodiment, when the load is short-circuited, the time until the semiconductor device 1 is destroyed can be made longer, and the short-circuit tolerance of the semiconductor device 1 can be improved.

In the semiconductor device 1 of the present embodiment, the p ⁺ back surface outer peripheral layer 26 is in contact with the p ⁺ collector layer 25. Therefore, at the time of load short circuit, holes can be efficiently injected into the ^{n- drift region 5 from the p +} back surface outer peripheral layer 26 ^{via the p +} collector layer 25. The semiconductor device 1 of the present embodiment can improve the short-circuit tolerance of the semiconductor device 1.

In the semiconductor device 1 of this embodiment, the semiconductor element 3 and the outer peripheral region 7, n ^- includes n buffer layer 24 on the side of the back surface 2b of the drift region 5. The first electron concentration in the n-buffer layer 24 is higher than the second electron concentration in the ^{n-drift region 5.} In the active region 6, the n-buffer layer 24 is in contact with the n ^- drift region 5 and the p ⁺ collector layer 25. In the outer peripheral region 7, the p ⁺ back surface outer peripheral layer 26 is provided on the back surface 2b side of the n buffer layer 24. The n-buffer layer 24 functions as a field stop layer. The n-buffer layer 24 improves the withstand voltage of the semiconductor device 1.

Embodiment 2.
The semiconductor device 1b according to the second embodiment will be described with reference to FIG. The semiconductor device 1b of the present embodiment has the same configuration as the semiconductor device 1 of the first embodiment and has the same effect, but is mainly different in the following points.

In the semiconductor device 1b of the present embodiment, the p ⁺ back surface outer peripheral layer 26 is ^{thicker than the p +} collector layer 25. ^{Therefore, more holes are injected from the p +} back surface outer layer 26 into the n ^- drift region 5 during the high voltage period including the load short circuit. The backside electric field strength at the pn junction formed by the n ^- drift region 5 and the p ^{+ collector layer 25 is further reduced.} The semiconductor device 1b of the present embodiment can lengthen the time until the semiconductor device 1b is destroyed in a high voltage period including a load short circuit, and can improve the short circuit tolerance of the semiconductor device 1b. ..

In the semiconductor device 1b of the present embodiment, ^{the first end 41 of the n-} drift region 5 in the active region 6 is located on the back surface 2b side of the second end 42 ^{of the n-} drift region 5 in the outer peripheral region 7. .. The first end 41 is the proximal end of the back surface 2b ^{of the n-drift region 5 in the active region 6.} The second end 42 is the proximal end of the back surface 2b ^{of the n-} drift region 5 in the outer peripheral region 7. ^{Therefore, the thickness of the n-} drift region 5 in the active region 6 increases. The withstand voltage of the semiconductor device 1b can be improved.

Embodiment 3.
The semiconductor device 1c according to the third embodiment will be described with reference to FIG. 7. The semiconductor device 1c of the present embodiment has the same configuration as the semiconductor device 1 of the first embodiment, but is mainly different in the following points.

In the semiconductor device 1c of the present embodiment, the outer peripheral region 7 further includes n back surface outer peripheral layer 27 in contact with ^{p + back surface outer peripheral layer 26.} n The back surface outer peripheral layer 27 is provided on the back surface 2b side of ^{p + back surface outer peripheral layer 26.} n The back surface outer peripheral layer 27 is in contact with the p ⁺ collector layer 25. n The back surface outer peripheral layer 27 is in contact with the second electrode 30. n The back surface outer peripheral layer 27 is provided on the back surface 2b of the semiconductor substrate 2. n The back surface outer layer 27 is ^{thinner than p +} back surface outer layer 26. The ^{n back surface outer peripheral layer 27 is configured so that the withstand voltage of the pn junction formed by the p +} back surface outer peripheral layer 26 and the n back surface outer peripheral layer 27 is larger than the on voltage of the semiconductor element 3. For example, when the semiconductor substrate 2 is a Si substrate, the n back surface outer peripheral layer 27 has a thickness d of 0.1 μm or more. Therefore, in the on state of the semiconductor element 3, ^{it is prevented that electric charges are injected from the pn junction formed by the p +} back surface outer peripheral layer 26 and the n back surface outer peripheral layer 27, and the switching loss of the semiconductor device 1c is reduced. be able to.

n-type carrier concentration of the n backside peripheral layer 27, n ^- larger than the n-type carrier concentration of the drift region 5. The n-type carrier concentration of the n-back surface outer peripheral layer 27 is higher than the n-type carrier concentration of the n-buffer layer 24. The n-back outer peripheral layer 27 has, for example, an n-type carrier concentration of ^{1.0 × 10 18} cm ^{-3 or more.} In the n back surface outer peripheral layer 27 having such an electron concentration, the ^{pn junction formed by the p +} back surface outer peripheral layer 26 and the n back surface outer peripheral layer 27 may easily exhibit the tunnel effect when the load is short-circuited.

An example of the manufacturing method of the semiconductor device 1c according to the present embodiment will be described with reference to FIGS. 2 to 5 and 8. The manufacturing method of the semiconductor device 1c of the present embodiment includes the same steps as the manufacturing method of the semiconductor device 1 of the first embodiment, but is mainly different in the following points.

As shown in FIG. 8, in the method of manufacturing the semiconductor device 1c of the present embodiment, after the steps shown in FIGS. 2 to 5, the back surface 2b of the outer peripheral region 7 is selectively doped with an n-type dopant. The back surface 2b of the outer peripheral region 7 of the semiconductor substrate 2 is provided with the n back surface outer peripheral layer 27. Specifically, the mask 36 is formed on the back surface 2b of the active region 6 of the semiconductor substrate 2. Using an ion implanter, an n-type dopant such as phosphorus is selectively implanted into the back surface 2b of the outer peripheral region 7. n The back surface outer peripheral layer 27 is in contact with p ⁺ back surface outer peripheral layer 26. n The back surface outer peripheral layer 27 is formed on the back surface 2b of the semiconductor substrate 2. n The back surface outer peripheral layer 27 is in contact with the p ⁺ collector layer 25. The n-back surface outer layer 27 is annealed in order to activate the n-type dopant contained in the n-back surface outer layer 27.

The method for manufacturing the semiconductor device 1c according to the present embodiment includes ^{forming a second electrode 30 on the p +} collector layer 25 and the n back surface outer peripheral layer 27. In the active region 6, the second electrode 30 is in contact with the p ⁺ collector layer 25. In the outer peripheral region 7, the second electrode 30 is in contact with the n back surface outer peripheral layer 27. In order to make the second electrode 30 ohmic contact with the p ⁺ collector layer 25 and the n back surface outer peripheral layer 27, the second electrode 30, the p ⁺ collector layer 25 and the n back surface outer peripheral layer 27 are annealed. In this way, the semiconductor device 1c shown in FIG. 7 is obtained.

The operation and operation of the semiconductor device 1c according to this embodiment will be described.
A ^{pn junction is formed by the p +} back surface outer peripheral layer 26 and the n back surface outer peripheral layer 27. In the low voltage period, a relatively small on-voltage is applied between the first electrode 20 and the second electrode 30, so ^{that the pn formed by the p +} back surface outer peripheral layer 26 and n back surface outer peripheral layer 27 is formed. The absolute value of the reverse bias voltage applied to the junction is small. Holes cannot pass through this pn junction. In the low voltage period, this pn junction prevents holes from being injected into the ^n- drift region 5 from the outer peripheral portion 30p of the second electrode 30 and the p ⁺ back surface outer peripheral layer 26 ^{, and in the n-} drift region 5. It is possible to suppress an increase in the concentration of holes. ^{The holes accumulated in the n-} drift region 5 in the turn-off process of the semiconductor device 1c are ^{discharged from the n-} drift region 5 in a shorter time. In the turn-off process, the power loss of the semiconductor device 1c can be reduced.

On the other hand, in the high voltage period, since a large power supply voltage is applied between the first electrode 20 and the second electrode 30, ^{it is formed by the p +} back surface outer peripheral layer 26 and the n back surface outer peripheral layer 27. The absolute value of the reverse bias voltage applied to the pn junction is large. Holes can pass through this pn junction due to the avalanche breakdown phenomenon occurring in the pn junction formed by the p ^{+ back surface outer peripheral layer 26 and the n back surface outer peripheral layer 27.} Alternatively, holes can pass through this pn junction due to the tunneling effect of the pn junction formed by ^{the p + back surface outer layer 26 and the n back surface outer layer 27.} Holes are injected into the ^{n- drift region 5 from the outer peripheral portion 30p and p +} back surface outer peripheral layer 26 of the second electrode 30 in the outer peripheral region 7. During the high voltage period, the backside electric field strength at the pn junction formed by ^{the n-} drift region 5 and the p ^{+ collector layer 25 can be reduced.} The semiconductor device 1c of the present embodiment can lengthen the time until the semiconductor device 1c is destroyed in a high voltage period including a load short circuit, and can improve the short circuit tolerance of the semiconductor device 1c.

The effect of the semiconductor device 1c according to this embodiment will be described. The semiconductor device 1c of the present embodiment has the following effects in addition to the effects of the semiconductor device 1 of the first embodiment.

In the semiconductor device 1c of the present embodiment, the outer peripheral region 7 further includes n back surface outer peripheral layer 27 in contact with ^{p + back surface outer peripheral layer 26.} n The back surface outer peripheral layer 27 is provided on the back surface 2b side of ^{p + back surface outer peripheral layer 26.} According to the semiconductor device 1c of the present embodiment, it is possible to improve the short-circuit tolerance of the semiconductor device 1c while reducing the power loss of the semiconductor device 1c generated during the turn-off process of the semiconductor device 1c.

In the semiconductor device 1c of the present embodiment, the n back surface outer peripheral layer 27 is ^{thinner than the p +} back surface outer peripheral layer 26. Therefore, it is possible to suppress a decrease in the amount of holes injected into the ^{n- drift region 5 from the p +} back surface outer peripheral layer 26 when the load is short-circuited. The short circuit tolerance of the semiconductor device 1c can be improved.

Embodiment 4.
The semiconductor device 1d according to the fourth embodiment will be described with reference to FIG. The semiconductor device 1d of the present embodiment has the same configuration as the semiconductor device 1c of the third embodiment, but is mainly different in the following points.

In the semiconductor device 1d of the present embodiment, the n back surface outer peripheral layer 27 is ^{provided between the p +} back surface outer peripheral layer 26 and the p ⁺ collector layer 25. The n back surface outer peripheral layer 27 is in contact with the n buffer layer 24. n The back surface outer peripheral layer 27 is in contact with p ⁺ collector layer 25. n The back surface outer peripheral layer 27 is in contact with the second electrode 30. In one example, the n back surface outer peripheral layer 27 has the ^{same thickness as p +} back surface outer peripheral layer 26. In another example, the n back surface outer layer 27 is ^{thinner than p +} back surface outer layer 26. n The width w of the back surface outer peripheral layer 27 is ^{smaller than the width of p + the} back surface outer peripheral layer 26. n The back surface outer peripheral layer 27 has a width w of, for example, 0.1 μm or more. n-type carrier concentration of the n backside peripheral layer 27, n ^- larger than the n-type carrier concentration of the drift region 5. The n-type carrier concentration of the n-back surface outer peripheral layer 27 is higher than the n-type carrier concentration of the n-buffer layer 24.

The semiconductor device 1d of the present embodiment has the same operation and effect as the semiconductor device 1c of the third embodiment as follows.

The n back surface outer peripheral layer 27 of the present embodiment has the same function as the n back surface outer peripheral layer 27 of the third embodiment. Specifically, a pn junction is formed by the p ⁺ back surface outer peripheral layer 26 and the n back surface outer peripheral layer 27. During the low voltage period, the holes injected from the outer peripheral portion 30p of the second electrode 30 in the outer peripheral region 7 cannot pass through this pn junction. In the low voltage period, this pn junction prevents holes from being injected into the ^n- drift region 5 from the outer peripheral portion 30p of the second electrode 30 and the p ⁺ back surface outer peripheral layer 26 ^{, and in the n-} drift region 5. It is possible to suppress an increase in the concentration of holes. ^{The holes accumulated in the n-} drift region 5 in the turn-off process of the semiconductor device 1d are ^{discharged from the n-} drift region 5 in a shorter time. In the turn-off process, the power loss of the semiconductor device 1d can be reduced.

On the other hand, in the high voltage period, since a large power supply voltage is applied between the first electrode 20 and the second electrode 30, ^{it is formed by the p +} back surface outer peripheral layer 26 and the n back surface outer peripheral layer 27. The absolute value of the reverse bias voltage applied to the pn junction is large. The holes injected from the outer peripheral portion 30p of the second electrode 30 in the outer peripheral region 7 exceed the built-in potential of this pn junction and are injected into the ^{n-drift region 5.} During the high voltage period, the backside electric field strength at the pn junction formed by ^{the n-} drift region 5 and the p ^{+ collector layer 25 can be reduced.} The semiconductor device 1d of the present embodiment can lengthen the time until the semiconductor device 1d is destroyed in a high voltage period including a load short circuit, and can improve the short circuit tolerance of the semiconductor device 1d.

It should be considered that the embodiments 1-4 disclosed this time are exemplary in all respects and are not restrictive. As long as there is no contradiction, at least two of Embodiments 1-4 disclosed this time may be combined. The scope of the present invention is shown by the scope of claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

1,1b, 1c, 1d semiconductor device, 2 semiconductor substrate, 2a front surface, 2b back surface, 3 semiconductor element, 5 n ^- drift region, 6 active region, 7 outer peripheral region, 10 p base region, 11 n ⁺ charge Storage layer, 12 parts, 14 n ⁺ type emitter region, 15 p ⁺ contact layer, 16 trench, 17 gate insulating film, 18 gate electrode, 19 interlayer insulating film, 20 first electrode, 21 electric field limiting ring structure, 24 n Buffer layer, 25 p ⁺ collector layer, 26 p ⁺ back surface outer peripheral layer, 27 n back surface outer peripheral layer, 30 second electrode, 30 p outer peripheral portion, 35, 36 mask, 41 first end, 42 second end.

Claims (8)

A semiconductor substrate including an active region provided with a semiconductor element and an outer peripheral region surrounding the active region is provided, and the semiconductor substrate has a front surface and a back surface.
The semiconductor device is provided on a portion of the p-base region between the ^n- drift region, the p-base region, the n ⁺ -type emitter region, and the n ⁺ -type emitter region and the n ^{-drift region.} The gate insulating film includes a gate electrode facing the portion of the p-base region with the gate insulating film interposed therebetween, and a p ⁺ collector layer provided on the back surface thereof.
The outer peripheral region includes the n ^- drift region and the p ⁺ back surface outer peripheral layer, the n ^- drift region extends from the active region to the outer peripheral region, and the p ⁺ back surface outer peripheral layer includes the p + back surface outer peripheral layer. It is provided on the back surface side of the n ^{-drift region, and is provided.}
The first hole concentration in the p ⁺ back surface peripheral layer is higher than the second hole concentration in the ^{p + collector layer.}
The p ⁺ back surface outer peripheral layer is thicker than the p ⁺ collector layer, a semi-conductor device. The first end of the ^n- drift region in the active region is located on the back surface side of the second end of the ^{n-drift region in the outer peripheral region.}
The first end is the proximal end of the back surface of the ^{n-drift region in the active region.}
The semiconductor device according to claim 1, wherein the second end is a proximal end of the back surface of the ^n- drift region in the outer peripheral region. A semiconductor substrate including an active region provided with a semiconductor element and an outer peripheral region surrounding the active region is provided, and the semiconductor substrate has a front surface and a back surface.
The semiconductor device is provided on a portion of the p-base region between the ^n- drift region, the p-base region, the n ⁺ -type emitter region, and the n ⁺ -type emitter region and the n ^{-drift region.} The gate insulating film includes a gate electrode facing the portion of the p-base region with the gate insulating film interposed therebetween, and a p ⁺ collector layer provided on the back surface thereof.
The outer peripheral region includes the n ^- drift region and the p ⁺ back surface outer peripheral layer, the n ^- drift region extends from the active region to the outer peripheral region, and the p ⁺ back surface outer peripheral layer includes the p + back surface outer peripheral layer. It is provided on the back surface side of the n ^{-drift region, and is provided.}
The first hole concentration in the p ⁺ back surface peripheral layer is higher than the second hole concentration in the ^{p + collector layer.}
The outer peripheral region further includes n back surface outer peripheral layer in contact with the ^{p + back surface outer peripheral layer.}
Wherein n backside peripheral layer is provided on the side of the back surface of the p ⁺ back surface peripheral layer,
A semiconductor device in which the p ⁺ back surface outer peripheral layer and the n back surface outer peripheral layer are in contact with the p ⁺ collector layer , respectively. The semiconductor device according to claim 3 , wherein the n back surface outer peripheral layer is ^{thinner than the p +} back surface outer peripheral layer. The semiconductor device according to claim 1 or 2 , wherein the p ⁺ back surface outer peripheral layer is in contact with the p ⁺ collector layer. The outer peripheral region further includes n back surface outer peripheral layer in contact with the ^{p + back surface outer peripheral layer.}
The semiconductor device according to claim 1 or 2 , wherein the n back surface outer peripheral layer is provided between the ^{p +} back surface outer peripheral layer and the p ^{+ collector layer.} The semiconductor element and the outer peripheral region, the n ^- comprises n buffer layer on the side of the back surface of the drift region,
The first electron concentration in the n-buffer layer is higher than the second electron concentration in the ^{n-drift region.}
In the active region, the n-buffer layer is in contact with the n ^- drift region and the p ⁺ collector layer.
The semiconductor device according to any one of claims 1 to 6 , wherein in the outer peripheral region, the p ⁺ back surface outer peripheral layer is provided on the back surface side of the n buffer layer. The semiconductor device according to any one of claims 1 to 7 , wherein the outer peripheral region includes an electric field limiting ring structure on the front surface.

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