JP6988262B2 - Nitride semiconductor device and its manufacturing method - Google Patents

Description

The techniques disclosed herein relate to nitride semiconductor devices.

A vertical nitride semiconductor device has been developed, and an example thereof is disclosed in Patent Document 1. This type of nitride semiconductor device includes a body layer of a p-type nitride semiconductor provided on the surface layer of the nitride semiconductor layer and a source layer of an n-type nitride semiconductor provided on the body layer. Be prepared.

Japanese Unexamined Patent Publication No. 2016-115831

In this type of nitride semiconductor device, the concentration of p-type impurities on the lower side of the body layer is relatively high in consideration of withstand voltage, and the concentration of p-type impurities on the upper side of the body layer is relatively high in consideration of channel resistance. It is desirable to make it thinner. On the other hand, considering the ohmic contact with the source electrode provided on the surface of the nitride semiconductor layer, a contact portion having a high concentration of p-type impurities is formed in a part of the body layer exposed on the surface of the nitride semiconductor layer. Need to form.

Patent Document 1 discloses that an ion implantation technique is used to form a body layer that satisfies these requirements. However, it is known that it is difficult to form a p-type semiconductor region in a nitride semiconductor by using an ion implantation technique. Therefore, it is actually difficult to form a body layer of a p-type nitride semiconductor by using an ion implantation technique as in Patent Document 1.

It is an object of the present specification to provide a nitride semiconductor device capable of forming a body layer of a p-type nitride semiconductor without utilizing an ion implantation technique.

The nitride semiconductor device disclosed in the present specification includes a body layer of a p-type nitride semiconductor provided in a groove formed in a groove formed in a surface layer portion of the nitride semiconductor layer, and n provided on the body layer. A source layer of a type nitride semiconductor can be provided. The body layer has a high-concentration epitaxial layer and a low-concentration epitaxial layer. The high-concentration epitaxial layer and the low-concentration epitaxial layer have portions in the groove in which they are laminated in this order. The high-concentration epitaxial layer has a contact portion exposed on the surface of the nitride semiconductor layer. The p-type impurity concentration of the high-concentration epitaxial layer is higher than the p-type impurity concentration of the low-concentration epitaxial layer. The source layer is provided on the low-concentration epitaxial layer. In this nitride semiconductor device, a p-type nitride semiconductor body layer is formed by sequentially forming a high-concentration epitaxial layer and a low-concentration epitaxial layer in a groove formed on the surface layer of the nitride semiconductor layer. .. Since the high-concentration epitaxial layer is formed in the groove prior to the film formation of the low-concentration epitaxial layer, the high-concentration epitaxial layer is arranged under the body layer and is in contact with the position adjacent to the side surface of the groove. The part is also formed. Since the low-concentration epitaxial layer is formed on the high-concentration epitaxial layer, the low-concentration epitaxial layer is arranged above the body layer. As described above, the nitride semiconductor device has a structure capable of forming a body layer having a desired form without using an ion implantation technique.

The cross-sectional view of the main part of the nitride semiconductor apparatus of 1st Embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the nitride semiconductor apparatus of 1st Embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the nitride semiconductor apparatus of 1st Embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the nitride semiconductor apparatus of 1st Embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the nitride semiconductor apparatus of 1st Embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the nitride semiconductor apparatus of 1st Embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the nitride semiconductor apparatus of the modification of 1st Embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the semiconductor device of the modification of the nitride semiconductor device of the first embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the semiconductor device of the modification of the nitride semiconductor device of the first embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the semiconductor device of the modification of the nitride semiconductor device of the first embodiment is schematically shown. The cross-sectional view of the main part of the nitride semiconductor device of the second embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the nitride semiconductor apparatus of 2nd Embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the nitride semiconductor apparatus of 2nd Embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the nitride semiconductor apparatus of 2nd Embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the nitride semiconductor apparatus of 2nd Embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the nitride semiconductor apparatus of 2nd Embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the nitride semiconductor apparatus of 2nd Embodiment is schematically shown. A schematic cross-sectional view of a main part during a manufacturing process of one manufacturing method for forming a contact portion having a large area is shown schematically. A schematic cross-sectional view of a main part during a manufacturing process of one manufacturing method for forming a contact portion having a large area is shown schematically. A schematic cross-sectional view of a main part during a manufacturing process of one manufacturing method for forming a contact portion having a large area is shown schematically. A schematic cross-sectional view of a main part during a manufacturing process of another manufacturing method for forming a contact portion having a large area is shown schematically. A schematic cross-sectional view of a main part during a manufacturing process of another manufacturing method for forming a contact portion having a large area is shown schematically. A schematic cross-sectional view of a main part during a manufacturing process of another manufacturing method for forming a contact portion having a large area is shown schematically.

(First Embodiment) As shown in FIG. 1, the nitride semiconductor device 1 is a type of semiconductor device called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and has a nitride semiconductor layer 10 and a nitride semiconductor. It includes a drain electrode 22 that covers the back surface of the layer 10, a source electrode 24 that covers a part of the surface of the nitride semiconductor layer 10, and a planar gate 30 provided on a part of the surface of the nitride semiconductor layer 10. ..

The nitride semiconductor layer 10 includes a drift layer 12 of n-type gallium nitride (GaN), a body layer 14 of p-type gallium nitride, a source layer 16 of n-type gallium nitride, an n-type surface layer 17 of n-type gallium nitride, and an n-type. It has a JFET region 18 of gallium nitride. In this example, the drift layer 12, the body layer 14, the source layer 16, the n-type surface layer 17, and the JFET region 18 are all made of gallium nitride, but some layers and / or regions are required. May be composed of different nitride semiconductors.

As will be described later, the drift layer 12 is prepared as an n-type GaN substrate and is also a base substrate for forming the body layer 14. The back surface of the drift layer 12 makes ohmic contact with the drain electrode 22.

The body layer 14 is provided on a part of the surface of the drift layer 12, and is provided in the groove T1 formed on the surface layer portion of the nitride semiconductor layer 10. The body layer 14 has a high-concentration epitaxial layer 14a and a low-concentration epitaxial layer 14b. The high-concentration epitaxial layer 14a and the low-concentration epitaxial layer 14b have a portion laminated in this order in the groove T1.

The high-concentration epitaxial layer 14a is arranged substantially below the groove T1 and is arranged between the drift layer 12 and the low-concentration epitaxial layer 14b. The concentration of the p-type impurity in the high-concentration epitaxial layer 14a is adjusted to be higher than that of the low-concentration epitaxial layer 14b, and the concentration is set based on the withstand voltage design. Further, the high-concentration epitaxial layer 14a is configured to have a concave cross section in the groove T1. As a result, the high-concentration epitaxial layer 14a has a contact portion 15 at a position adjacent to the side surface of the groove T1, and the contact portion 15 is exposed on the surface of the nitride semiconductor layer 10 and makes ohmic contact with the source electrode 24. do. By exposing the contact portion 15 of the high-concentration epitaxial layer 14a to the surface of the nitride semiconductor layer 10 in this way, the body layer 14 can make good ohmic contact with the source electrode 24. As the material of the source electrode 24, it is desirable that a metal having a high work function is adopted in order to secure good ohmic contact with the contact portion 15 of the high concentration epitaxial layer 14a. The source electrode 24 is composed of a single or a combination of metal materials such as Pt, Au, Pd, and Ni.

The low-concentration epitaxial layer 14b is provided on the surface of the high-concentration epitaxial layer 14a and is exposed on the surface of the nitride semiconductor layer 10. The concentration of the p-type impurity in the low-concentration epitaxial layer 14b is adjusted to be lower than that of the high-concentration epitaxial layer 14a, and the concentration is set based on the channel design. Further, the low-concentration epitaxial layer 14b is provided in the groove of the high-concentration epitaxial layer 14a having a concave cross section.

The source layer 16 is provided on the surface of the low-concentration epitaxial layer 14b of the body layer 14, is exposed on the surface of the nitride semiconductor layer 10, and makes ohmic contact with the source electrode 24. The source layer 16 is separated from the drift layer 12 and the JFET region 18 by the body layer 14.

The n-type surface layer 17 is provided on the surface of the high-concentration epitaxial layer 14a located between the low-concentration epitaxial layer 14b and the JFET region 18, and is in contact with both the low-concentration epitaxial layer 14b and the JFET region 18. , Exposed on the surface of the nitride semiconductor layer 10. The n-type surface layer 17 is arranged adjacent to the channel formed in the low-concentration epitaxial layer 14b. In this example, the n-type surface layer 17 is provided only on one side of the source layer 16. However, as shown in FIGS. 6A-6C described later, by forming the contact portion 15 at a position away from the groove T1, n-type surface layers 17 are provided on both sides of the source layer 16 to increase the channel area. It can also be widened.

The JFET region 18 is provided on a part of the surface of the drift layer 12, is arranged between the adjacent body layers 14, is provided on the surface layer portion of the nitride semiconductor layer 10, and is a nitride semiconductor. It is exposed on the surface of layer 10. The JFET region 18 is a portion that protrudes convexly from the drift layer 12, and can be evaluated as a part of the drift layer 12.

The planar gate 30 is provided on the low-concentration epitaxial layer 14b so as to form a channel in the low-concentration epitaxial layer 14b located between the source layer 16 and the n-type surface layer 17, and the gate electrode 32 and the gate are provided. It has an insulating film 34. The gate electrode 32 faces the low-concentration epitaxial layer 14b via the gate insulating film 34.

Next, the operation of the nitride semiconductor device 1 will be described. When a voltage higher than that of the source electrode 24 is applied to the drain electrode 22 and a voltage higher than the threshold voltage is applied to the gate electrode 32, the nitride semiconductor device 1 is turned on. At this time, a channel is formed in the low-concentration epitaxial layer 14b located between the source layer 16 and the n-type surface layer 17. The electrons injected from the source layer 16 reach the JFET region 18 via the channel and the n-type surface layer 17, flow vertically through the JFET region 18 and the drift layer 12, and reach the drain electrode 22. In this way, the nitride semiconductor device 1 operates as a vertical semiconductor device. When the voltage applied to the gate electrode 32 falls below the threshold voltage, the channel of the low-concentration epitaxial layer 14b disappears and the nitride semiconductor device 1 is turned off.

Next, a method for manufacturing the nitride semiconductor device 1 according to the first embodiment will be described with reference to FIGS. 2A-2E. First, as shown in FIG. 2A, the drift layer 12 is prepared as an n-type GaN substrate. In the following, it may be referred to as an n-type GaN substrate 12 as necessary.

Next, as shown in FIG. 2B, a groove T1 extending in the depth direction from the surface of the n-type GaN substrate 12 is formed by using a dry etching method or a wet etching method. The groove T1 is formed at a position corresponding to the body layer 14 (see FIG. 1). By forming the groove T1, the JFET region 18 is formed between the adjacent grooves T1.

Next, as shown in FIG. 2C, a high concentration lower epitaxial layer 114a of p-type gallium nitride and a low concentration of p-type gallium nitride are used in the groove T1 by using the MOCVD (Metal Organic Chemical Vapor Deposition) method. The upper epitaxial layer 114b of the above is formed in order. At this time, at least a part of the upper epitaxial layer 114b is formed so as to be filled in the groove T1.

Next, as shown in FIG. 2D, the epitaxial layers 114a and 114b are removed until the surface of the n-type GaN substrate 12 is exposed using CMP technology. As a result, the lower epitaxial layer 114a and the upper epitaxial layer 114b filled in the groove T1 are processed into the high-concentration epitaxial layer 14a and the low-concentration epitaxial layer 14b, respectively, to form the body layer 14. Further, at this stage, the high-concentration epitaxial layer 14a is processed into a concave cross section in the groove T1. As a result, the contact portion 15 exposed on the surface of the n-type GaN substrate 12 is formed at a position adjacent to the side surface of the groove T1.

Next, as shown in FIG. 2E, silicon (Si) is implanted into a part of the low-concentration epitaxial layer 14b of the body layer 14 to form the source layer 16 by utilizing the ion implantation technique. Further, using the ion implantation technique, silicon (Si) is implanted into the surface of the high-concentration epitaxial layer 14a located between the low-concentration epitaxial layer 14b and the JFET region 18 to form the n-type surface layer 17. The source layer 16 and the n-type surface layer 17 may be formed simultaneously in a common ion implantation step, or may be formed separately in different ion implantation steps. Finally, when the gate insulating film 34, the gate electrode 32 and the source electrode 24 are patterned on the surface of the n-type GaN substrate 12 and the drain electrode 22 is formed on the back surface of the n-type GaN substrate 12, the nitride shown in FIG. 1 is formed. The semiconductor device 1 is completed.

Next, with reference to FIGS. 3A-3D, a method of manufacturing a semiconductor device as a modification of the nitride semiconductor device 1 of the first embodiment will be described. First, in the same manner as described above, the groove T1 is formed on the surface of the n-type GaN substrate 12 (see FIG. 2B).

Next, as shown in FIG. 3A, the lower epitaxial layer 114a having a high concentration of p-type gallium nitride and the upper epitaxial layer 114b having a low concentration of p-type gallium nitride are sequentially placed in the groove T1 by using the MOCVD method. Form a film. Further, a CVD (Chemical Vapor Deposition) method is used to form a protective film 42 of _{silicon oxide (SiO 2) on the surface of the upper epitaxial layer 114b.} At this time, at least a part of the protective film 42 is formed so as to be located in the groove T1.

Next, as shown in FIG. 3B, the protective film 42 and the epitaxial layers 114a and 114b are removed until the surface of the n-type GaN substrate 12 is exposed by using CMP technology. As a result, the lower epitaxial layer 114a and the upper epitaxial layer 114b filled in the groove T1 are processed into the high-concentration epitaxial layer 14a and the low-concentration epitaxial layer 14b, respectively, to form the body layer 14. As shown in FIG. 3B, since the surface of the low-concentration epitaxial layer 14b is protected by the protective film 42, it is possible to reduce processing damage to the surface of the low-concentration epitaxial layer 14b by the polishing treatment. As a result, it is possible to prevent the acceptor concentration on the surface of the low-concentration epitaxial layer 14b from decreasing or becoming a donor. Further, at this stage, the high-concentration epitaxial layer 14a is processed into a concave cross section in the groove T1. As a result, the contact portion 15 exposed on the surface of the n-type GaN substrate 12 is formed at a position adjacent to the side surface of the groove T1.

Next, as shown in FIG. 3C, the protective film 42 is removed by using a wet etching method. For the etching process at this time, an etching material in which the etching rate of the protective film 42 is higher than the etching rate of the body layer 14 and the n-type GaN substrate 12 is selected. In this example, the protective film 42 is selectively removed with hydrofluoric acid. As a result, a shallow groove corresponding to the thickness of the protective film 42 is formed on the surface of the low-concentration epitaxial layer 14b. As the material of the protective film 42, a material that can be selectively etched with respect to the body layer 14 and the n-type GaN substrate 12, which are nitride semiconductors, may be adopted, for example, silicon oxide, silicon nitride, and aluminum oxide. Alternatively, aluminum nitride or the like may be adopted.

Next, as shown in FIG. 3D, silicon (Si) is implanted into a part of the shallow groove of the low-concentration epitaxial layer 14b of the body layer 14 to form the source layer 16 by using the ion implantation technique. .. Further, using ion implantation technology, the surface of the low-concentration epitaxial layer 14b around the shallow groove of the low-concentration epitaxial layer 14b, and the high-concentration epitaxial layer 14a located between the low-concentration epitaxial layer 14b and the JFET region 18 Silicon (Si) is implanted into the surface of the n-type surface layer 17 to form an n-type surface layer 17. The source layer 16 and the n-type surface layer 17 may be formed simultaneously in a common ion implantation step, or may be formed separately in different ion implantation steps. As described above, the bottom surface of the shallow groove of the low-concentration epitaxial layer 14b protected by the protective film 42 is less likely to be damaged by polishing, and the acceptor concentration may decrease or become a donor. Is suppressed. Since the channel between the source layer 16 and the n-type surface layer 17 is formed on the bottom surface of the shallow groove of the low-concentration epitaxial layer 14b, deterioration of the electrical characteristics of the nitride semiconductor device is suppressed. Finally, when the gate insulating film 34, the gate electrode 32 and the source electrode 24 are patterned on the surface of the n-type GaN substrate 12 and the drain electrode 22 is formed on the back surface of the n-type GaN substrate 12, the nitride semiconductor of the modified example is formed. The device is completed.

(Second Embodiment) FIG. 4 schematically shows a cross-sectional view of a main part of the nitride semiconductor device 2 of the second embodiment. The components substantially in common with the nitride semiconductor device 1 of the first embodiment shown in FIG. 1 are designated by a common reference numeral, and the description thereof will be omitted. Compared with the nitride semiconductor device 1 of the first embodiment shown in FIG. 1, the nitride semiconductor device 2 shown in FIG. 4 is characterized in that the form of the body layer 214 is different.

Next, a method for manufacturing the nitride semiconductor device 2 according to the second embodiment will be described with reference to FIGS. 5A-5F. First, in the same manner as above, the drift layer 12 is prepared as an n-type GaN substrate (see FIG. 2B).

Next, as shown in FIG. 5A, a groove T2 extending in the depth direction from the surface of the n-type GaN substrate 12 is formed by using a dry etching method or a wet etching method. The groove T2 is formed at a position corresponding to the body layer 214 and the JFET region 18 (see FIG. 4).

Next, as shown in FIG. 5B, the lower epitaxial layer 314a having a high concentration of p-type gallium nitride and the upper epitaxial layer 314b having a low concentration of p-type gallium nitride are sequentially placed in the groove T2 by using the MOCVD method. Form a film. At this time, at least a part of the upper epitaxial layer 314b is formed so as to be filled in the groove T2.

Next, as shown in FIG. 5C, a groove T3 extending in the depth direction from the surface of the upper epitaxial layer 314b located in the groove T2 is formed by using a dry etching method or a wet etching method. The groove T3 penetrates the upper epitaxial layer 314b and the lower epitaxial layer 314a and reaches the drift layer 12. In this example, the groove T3 also penetrates a part of the surface of the drift layer 12.

Next, as shown in FIG. 5D, an n-type semiconductor layer 118 of n-type gallium nitride is formed in the groove T3 by using the MOCVD method. The n-type semiconductor layer 118 is also formed on the surface of the upper epitaxial layer 314b.

Next, as shown in FIG. 5E, the n-type semiconductor layer 118 and the epitaxial layers 314a and 314b are removed until the surface of the n-type GaN substrate 12 is exposed by using CMP technology. As a result, the lower epitaxial layer 314a and the upper epitaxial layer 314b filled in the groove T2 are processed into the high-concentration epitaxial layer 214a and the low-concentration epitaxial layer 214b, respectively, to form the body layer 214. The n-type semiconductor layer 118 filled in the groove T3 is processed into the JFET region 18. Further, at this stage, the high-concentration epitaxial layer 214a is processed into a concave cross section in the groove T2. As a result, the contact portion 15 exposed on the surface of the n-type GaN substrate 12 is formed at a position adjacent to the side surface of the groove T2.

Next, as shown in FIG. 5F, silicon (Si) is implanted into a part of the low-concentration epitaxial layer 214b of the body layer 214 to form the source layer 16 by using the ion implantation technique. Finally, when the gate insulating film 34, the gate electrode 32 and the source electrode 24 are patterned on the surface of the n-type GaN substrate 12 and the drain electrode 22 is formed on the back surface of the n-type GaN substrate 12, the nitride shown in FIG. 4 is formed. The semiconductor device 2 is completed. As described above, the nitride semiconductor device 2 manufactured by the above manufacturing method does not need to form the n-type surface layer 17 as compared with the nitride semiconductor device 1 shown in FIG. 1, whereby the source layer 16 and the nitride semiconductor device 16 do not need to be formed. The distance between the JFET regions 18, that is, the channel distance can be shortened. The nitride semiconductor device 2 has an advantageous form for reducing the size. The technique using the protective film shown in FIG. 3 can also be applied to the manufacturing method shown in FIG.

In the nitride semiconductor device 1 shown in FIG. 1 and the nitride semiconductor device 2 shown in FIG. 4, it may be desired to secure a large area of the contact portion 15 of the body layer. Hereinafter, two manufacturing methods for securing a wide area of the contact portion 15 will be described with reference to FIGS. 6 and 7. Both of the two manufacturing methods described below can be applied to any of the manufacturing methods of FIGS. 2, 3 and 5.

First, as shown in FIG. 6A, a first groove T11 and a second groove T12 extending in the depth direction from the surface of the n-type GaN substrate 12 are formed by using a dry etching method or a wet etching method. The depth of the first groove T11 is shallower than the depth of the second groove T12. The first groove T11 and the second groove T12 are adjacent to each other. Therefore, the first groove T11 and the second groove T12 can be understood as one groove. The first groove T11 is formed corresponding to the formation range of the contact portion. The second groove T12 is formed corresponding to the formation range of the body layer.

Next, as shown in FIG. 6B, using the MOCVD method, the lower epitaxial layer 414a having a high concentration of p-type gallium nitride and the upper epitaxial layer 414b having a low concentration of p-type gallium nitride in the grooves T11 and T12. Are formed in order. At this time, the first groove T11 is formed so that only the lower epitaxial layer 414a is filled, and the second groove T12 is filled with both the lower epitaxial layer 414a and the upper epitaxial layer 314b. Is formed into a film. That is, the film thickness process is adjusted so that the film thickness of the lower epitaxial layer 414a is larger than the depth of the first groove T11.

Next, as shown in FIG. 6C, the epitaxial layers 414a and 414b are removed until the surface of the n-type GaN substrate 12 is exposed by using the CMP technique. As a result, the lower epitaxial layer 414a filled in the first groove T11 is processed into the contact portion 15. The lower epitaxial layer 414a and the upper epitaxial layer 414b filled in the second groove T12 are processed into a high-concentration epitaxial layer 514a and a low-concentration epitaxial layer 514b, respectively, to form a body layer 514. In this way, by forming the first groove T11 for the contact portion 15 adjacent to the second groove T12 for forming the body layer 514, a wide area of the contact portion 15 can be secured. In the above manufacturing method, in the film forming process, the first groove T11 was adjusted so that only the lower epitaxial layer 414a was filled. Instead of this example, both the lower epitaxial layer 414a and the upper epitaxial layer 414b may be filled in the first groove T11. In this case, if the upper epitaxial layer 414b in the first groove T11 is removed so that the lower epitaxial layer 414a in the first groove T11 is exposed in the polishing process, the contact portion 15 substantially similar to the above can be obtained. It is formed.

In the manufacturing method shown in FIGS. 6A-6C, it is necessary to form the first groove T11 and the second groove T12 having different depths. Therefore, in order to form the first groove T11 and the second groove T12, two-step etching is required using the mask for the first groove T11 and the mask for the second groove T12. Hereinafter, a manufacturing method capable of securing a wide area of the contact portion 15 with one mask will be described.

First, as shown in FIG. 7A, a third groove T13 and a fourth groove T14 extending in the depth direction from the surface of the n-type GaN substrate 12 are formed by using a dry etching method or a wet etching method. The third groove T13 and the fourth groove T14 are formed by one-step etching using a common mask, and the depth of the third groove T13 and the depth of the fourth groove T14 are equal to each other. The third groove T13 and the fourth groove T14 are connected by a cross section (not shown). Therefore, the third groove T13 and the fourth groove T14 can be understood as one groove. The third groove T13 is formed corresponding to the formation range of the contact portion. The fourth groove T14 is formed corresponding to the formation range of the body layer.

Next, as shown in FIG. 7B, using the MOCVD method, the lower epitaxial layer 614a having a high concentration of p-type gallium nitride and the upper epitaxial layer 614b having a low concentration of p-type gallium nitride in the grooves T13 and T14. Are formed in order. At this time, the film is formed so that only the lower epitaxial layer 614a is filled in the third groove T13, and both the lower epitaxial layer 614a and the upper epitaxial layer 614b are filled in the fourth groove T14. Is formed into a film. As shown in FIG. 7B, when the width 52 of the third groove T13 is set to be less than twice the film thickness 54 of the lower epitaxial layer 614a, the lower epitaxial layer is contained in the third groove T13. The film is formed so that only 614a is filled.

Next, as shown in FIG. 7C, the epitaxial layers 614a and 614b are removed until the surface of the n-type GaN substrate 12 is exposed using CMP technology. As a result, the lower epitaxial layer 614a filled in the third groove T13 is processed into the contact portion 15. The lower epitaxial layer 614a and the upper epitaxial layer 614b filled in the fourth groove T14 are processed into a high-concentration epitaxial layer 714a and a low-concentration epitaxial layer 714b, respectively, to form a body layer 714. By forming the third groove T13 for the contact portion 15 in this way, a wide area of the contact portion 15 can be secured. Further, by forming the third groove T13 for the contact portion 15 at a position away from the fourth groove T14 for forming the body layer 714, a wide channel area can be secured on the surface layer portion of the body layer 714. Therefore, the channel resistance can be reduced.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples exemplified above. Further, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in the present specification or the drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

1: Nitride semiconductor device 10: Nitride semiconductor layer 12: Drift layer 14: Body layer 14a: High-concentration epitaxial layer 14b: Low-concentration epitaxial layer 15: Contact portion 16: Source layer 17: n-type surface layer 18: JFET region 22: Drain electrode 24: Source electrode 30: Planar gate 32: Gate electrode 34: Gate insulating film

Claims (6)

Nitride semiconductor device
A body layer of a p-type nitride semiconductor provided in a groove formed on the surface layer of the nitride semiconductor layer, and a body layer of the p-type nitride semiconductor.
The source layer of the n-type nitride semiconductor provided on the body layer and
The n-type surface layer of the n-type nitride semiconductor provided on the body layer and
It is equipped with a gate insulating film and a planar gate having a gate electrode.
The body layer has a high-concentration epitaxial layer and a low-concentration epitaxial layer.
The high-concentration epitaxial layer and the low-concentration epitaxial layer have a portion laminated in this order in the groove.
The high-concentration epitaxial layer has a contact portion exposed on the surface of the nitride semiconductor layer.
The p-type impurity concentration of the high-concentration epitaxial layer is higher than the p-type impurity concentration of the low-concentration epitaxial layer.
The source layer is provided on the low-concentration epitaxial layer, and the source layer is provided on the low-concentration epitaxial layer .
The n-type surface layer is provided on the high-concentration epitaxial layer so that the low-concentration epitaxial layer is located between the n-type surface layer and the source layer.
The planar gate is a nitride semiconductor device provided on the low-concentration epitaxial layer located between the source layer and the n-type surface layer. A body layer of a p-type nitride semiconductor provided in a groove formed on the surface layer of the nitride semiconductor layer, and a body layer of the p-type nitride semiconductor.
The source layer of the n-type nitride semiconductor provided on the body layer and
The n-type surface layer of the n-type nitride semiconductor provided on the body layer and
It is equipped with a gate insulating film and a planar gate having a gate electrode.
The body layer has a high-concentration epitaxial layer and a low-concentration epitaxial layer.
The high-concentration epitaxial layer and the low-concentration epitaxial layer have a portion laminated in this order in the groove.
The high-concentration epitaxial layer has a contact portion exposed on the surface of the nitride semiconductor layer.
The p-type impurity concentration of the high-concentration epitaxial layer is higher than the p-type impurity concentration of the low-concentration epitaxial layer.
The source layer is provided on the low-concentration epitaxial layer, and the source layer is provided on the low-concentration epitaxial layer.
The n-type surface layer is provided on the high-concentration epitaxial layer so that the low-concentration epitaxial layer is located between the n-type surface layer and the source layer.
The planar gate is a method for manufacturing a nitride semiconductor device provided on the low-concentration epitaxial layer located between the source layer and the n-type surface layer.
A groove forming step of forming the groove on the surface layer portion of the nitride semiconductor layer, and
An epitaxial layer film forming step of sequentially forming the high-concentration epitaxial layer and the low-concentration epitaxial layer in the groove,
An epitaxial layer removing step of removing the low-concentration epitaxial layer and the high-concentration epitaxial layer formed on the surface of the nitride semiconductor layer until the surface of the nitride semiconductor layer is exposed.
A source layer forming step of forming the source layer on a part of the low-concentration epitaxial layer,
An n-type surface layer forming step of forming the n-type surface layer on a part of the high-concentration epitaxial layer,
A method for manufacturing a nitride semiconductor device, comprising a planar gate forming step for forming the planar gate. The method for manufacturing a nitride semiconductor device according to claim 2, wherein the source layer forming step and the n-type surface layer forming step are carried out by a common ion implantation step. A step of forming a protective film on the surface of the low-concentration epitaxial layer between the epitaxial layer forming step and the epitaxial layer removing step, in which at least a part of the protective film is located in the groove. , Protective film film formation process,
Between the epitaxial layer removing step and the source layer forming step, a step of removing the protective film by using a wet etching method is further provided.
The nitride according to claim 2 or 3, wherein in the source layer forming step, the source layer is formed in a part of the low-concentration epitaxial layer which is a part of the groove formed by removing the protective film. Manufacturing method of physical semiconductor equipment. In the groove forming step, the groove is formed so as to have a relatively deep groove and a relatively shallow groove adjacent to the deep groove.
In the epitaxial layer film forming step, the deep groove is formed so that both the high-concentration epitaxial layer and the low-concentration epitaxial layer are filled, and only the high-concentration epitaxial layer is formed in the shallow groove. The method for manufacturing a nitride semiconductor device according to any one of claims 2 to 4, wherein the film is formed so as to be filled. In the groove forming step, the groove is formed so as to have a relatively wide groove and a narrow groove connected to the wide groove.
In the epitaxial layer film forming step, the wide groove is formed so that both the high-concentration epitaxial layer and the low-concentration epitaxial layer are filled, and the narrow groove is filled with the high-concentration epitaxial layer. The method for manufacturing a nitride semiconductor device according to any one of claims 2 to 4, wherein the film is formed so that only the layer is filled.

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