JP6989404B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a protection circuit of a semiconductor integrated circuit.

In order to improve the reliability of the semiconductor integrated circuit, an overvoltage protection (OVP) circuit, an undervoltage lockout (UVLO) circuit, an overheat protection circuit and the like are implemented. These protection circuits determine the presence or absence of an abnormality by comparing the sense signal according to the voltage and temperature to be monitored with a predetermined threshold value. FIG. 1 is a circuit diagram of a semiconductor integrated circuit 100R including a protection circuit 102. Generally, the protection circuit 102 includes a sense circuit 104, a comparator 106, and a logic circuit 108. The sense circuit 104 generates _{a sense signal V SNS} according to the voltage, current and temperature to be monitored. The comparator 106 compares the sense signal V _SNS with a predetermined threshold value V _TH, and generates a _{determination signal S ABN} indicating the comparison result.

The protection circuit 102 in FIG. 1 is an overvoltage protection circuit, and the monitoring target is the power supply voltage _VDD . The sense circuit 104 is a resistance voltage dividing circuit that divides _{the power supply voltage VDD at a predetermined voltage dividing ratio K.}
V _SNS = V _DD × K
K = R ₂ / (R ₁ + R ₂ )
The comparator 106 compares the sense signal V _SNS with the overvoltage threshold V _TH and asserts (eg, high level) the determination signal S _{ABN when V SNS} > V _TH. The logic circuit 108 executes a predetermined protection process in response to the assertion of _{the determination signal SABN.}

Japanese Unexamined Patent Publication No. 9-22439

As a result of examining the protection circuit 102 of FIG. 1, the present inventor has come to recognize the following problems. If the protection circuit 102 itself has a failure or abnormality, the abnormal state cannot be correctly determined. For example, when the voltage division ratio K of the sense circuit 104 is larger than the design value, it may be determined as an overvoltage abnormality even _{when the power supply voltage VDD is included in the normal voltage range.} On the contrary, when the voltage division ratio K of the sense circuit 104 is smaller than the design value, the overvoltage abnormality may not be detected even _{when the power supply voltage VDD is higher than the normal voltage range.}

Even if the sense circuit 104 is normal, if there is an abnormality in the comparator 106, the abnormal state cannot be correctly determined.

The present invention has been made in view of such circumstances, and one of the exemplary purposes of the embodiment is to provide a semiconductor integrated circuit with improved reliability.

One aspect of the invention comprises a semiconductor integrated circuit. The semiconductor integrated circuit includes a plurality of abnormality detection circuits having a common monitoring target, and a test circuit for inspecting a plurality of abnormality detection circuits. Each of the plurality of abnormality detection circuits has the same circuit type, and the sense circuit that generates a sense signal according to the monitoring target and the sense signal are compared with a predetermined threshold value to generate a judgment signal indicating the presence or absence of an abnormality. Includes a comparator and. The test circuit detects an abnormality in a plurality of abnormality detection circuits based on a plurality of sense signals generated in the plurality of abnormality detection circuits.

Since the plurality of sense circuits have the same circuit type, the plurality of sense signals generated when the plurality of sense circuits are normal have the expected relative relationship. On the contrary, if one of the sense circuits has an abnormality, the relationship between the plurality of sense signals deviates from the expected one. According to this aspect, an abnormality of a plurality of sense circuits can be detected, and the reliability of the semiconductor integrated circuit can be improved.

The test circuit may detect anomalies in a plurality of anomaly detection circuits based on a plurality of sense signals at substantially the same time. When the monitoring target fluctuates on a short time scale, the accuracy of the test circuit can be improved by aligning the monitoring timings of a plurality of sense signals. The “substantially the same time” may be the same time to the extent that the change over time of the monitored object is negligible.

The test circuit may detect anomalies in the plurality of sense circuits based on the ratio of the plurality of sense signals.
When a plurality of sense circuits amplify or attenuate the signal to be monitored, the abnormality of the plurality of sense circuits can be detected by comparing the ratio of the plurality of detection signals with the expected value.

The test circuit may detect an abnormality in a plurality of abnormality detection circuits based on the difference or sum of the plurality of sense signals.

The sense circuit of each of the plurality of abnormality detection circuits may include a voltage dividing circuit that divides the voltage to be monitored and generates a sense signal.

One of the plurality of abnormality detection circuits may be an overvoltage detection circuit, and the other may be an undervoltage detection circuit.

The plurality of abnormality detection circuits may determine the presence or absence of an abnormality based on the same criteria. That is, the plurality of abnormality detection circuits may be redundant circuits that determine the same monitoring target based on the same criteria.

The plurality of abnormality detection circuits may be temperature abnormality detection circuits.

The sense circuit includes a diode and a current source that supplies a constant current to the diode, and the voltage drop of the diode may be a sense signal.

The test circuit may include an A / D converter that converts each of the plurality of sense signals into digital values.

The test circuit may be configured to be able to supply an adjustable test signal to the generation node of the sense signal of each of the plurality of abnormality detection circuits. This makes it possible to determine the presence or absence of an abnormality in the comparators of each of the plurality of abnormality detection circuits.

The test circuit uses a sequential comparison type A / D converter that converts each of multiple sense signals into digital values, and an output signal of the sub-D / A converter of the A / D converter, which is the sense signal of each of the multiple abnormality detection circuits. It may include a selector supplied to the generation node and a digital processing unit that controls an input code to the sub-D / A converter. By diverting the sub-D / A converter of the sequential comparison type A / D converter to the generation of the test signal, the increase in the circuit area can be suppressed.

It should be noted that any combination of the above components or components or expressions of the present invention that are mutually replaced between methods, devices, systems, etc. are also effective as aspects of the present invention.

According to an aspect of the present invention, the reliability of a semiconductor integrated circuit can be enhanced.

It is a circuit diagram of a semiconductor integrated circuit provided with a protection circuit. It is a block diagram of the semiconductor integrated circuit which concerns on 1st Embodiment. It is a circuit diagram of the semiconductor integrated circuit which concerns on one Example. It is a circuit diagram of the sense circuit which concerns on one Example. It is a circuit diagram of the abnormality detection circuit which concerns on one Example. It is a circuit diagram of the sense circuit which concerns on one Example. It is a block diagram of the semiconductor integrated circuit which concerns on 2nd Embodiment. It is a circuit diagram of the test circuit which concerns on one Example. It is a circuit diagram which shows the structural example of A / D converter and D / A converter.

Hereinafter, the present invention will be described with reference to the drawings based on the preferred embodiments. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and duplicate description thereof will be omitted as appropriate. Further, the embodiment is not limited to the invention, but is an example, and all the features and combinations thereof described in the embodiment are not necessarily essential to the invention.

In the present specification, the "state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected to each other, and the member A and the member B are electrically connected to each other. It also includes the case of being indirectly connected via other members that do not affect the connection state or impair the function.

Similarly, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, and also electrically. It also includes the case of being indirectly connected via other members that do not affect the connection state or impair the function.

(First Embodiment)
FIG. 2 is a block diagram of the semiconductor integrated circuit 100 according to the first embodiment. FIG. 2 shows only the portion of the semiconductor integrated circuit 100 related to the protection circuit 300.

The protection circuit 300 includes a plurality of abnormality detection circuits 310, a logic circuit 320, and a test circuit 330. The plurality of abnormality detection circuits 310 have a common monitoring target 301. The monitoring targets include, but are not limited to, (i) the voltage of a certain node or pin, (ii) the current flowing in a certain path, and (iii) the temperature inside or around the semiconductor integrated circuit 100. Here, the case where there are two abnormality detection circuits 310 will be described for ease of understanding and concise explanation.

The abnormality determination criteria in the plurality of abnormality detection circuits 310 may be the same or different. When the determination criteria are the same, the plurality of abnormality detection circuits 310 have a redundant relationship, and double abnormality detection is performed.

When the judgment criteria are different, there are cases where overvoltage detection and undervoltage detection are performed for the same monitored target voltage, and cases where high temperature abnormality (overheat abnormality) and low temperature abnormality are judged for the same monitored target temperature are exemplified. To. It can also be applied to detect a heavenly fault and a ground fault for a certain pin.

The test circuit 330 inspects a plurality of abnormality detection circuits 310. In the first embodiment, the inspection target of the test circuit 330 is a plurality of sense circuits 312 included in the plurality of abnormality detection circuits 310.

The plurality of abnormality detection circuits 310 are similarly configured. The anomaly detection circuit 310 includes a sense circuit 312 and a comparator 314. The plurality of sense circuits 312 included in the plurality of abnormality detection circuits 310 have the same circuit type.

In other words, in the plurality of sense circuits 312, the conversion formula (function) from the value x to be monitored to the value y of the sense signal may be the same. In addition, "the conversion formula is the same" includes not only the case where the coefficients and constants included in the conversion formula are completely the same, but also the case where they are different. For example, when the function is expressed by a linear expression, the coefficients a and b may be different in the plurality of sense circuits 312.
y = ax + b (where a ≠ 0)

The sense circuit 312 of the abnormality detection circuit 310_1 and the sense circuit 312 of the abnormality detection circuit 310_2 may be integrally configured.

The comparator 314 compares the corresponding sense signal V _SNS with a predetermined threshold value V _TH and generates a _{determination signal SABN} indicating the presence or absence of an abnormality.

The test circuit 330 detects the abnormality of the plurality of abnormality detection circuits 310_1 and _{310_2 based on the plurality of sense signals V SNS1} and V SNS2 generated by the plurality of abnormality detection circuits 310_1 and 310_2.

The above is the configuration of the semiconductor integrated circuit 100. Subsequently, the operation of the self-test in the semiconductor integrated circuit 100 will be described.

As an example, the abnormal value _{y 1} of the sense signal _{V SNS1} the detection circuit 310_1, it is assumed that Equation (1) holds between the monitored value x.
y ₁ = a ₁ × x… (1)
Similarly, in the abnormality detection circuit 310_2, it is _assumed that the equation (2) holds between the value y _{2 of the sense signal V SNS 2 and the value x to be monitored.}
y ₂ = a ₂ × x… (2)

_{The test circuit 330 acquires} the values of the _{two sense signals V SNS1} and V SNS2 during the self-test period. The self-test may be executed once after the start-up of the semiconductor integrated circuit 100 is completed, or may be executed periodically. When acquiring the two sense signals V _SNS1 and V _SNS2 , it is required that the values x to be monitored are the same. Therefore, when the value x to be monitored fluctuates during the self-test period, the test circuit 330 may acquire a _{plurality of sense signals V SNS1} and V _{SNS2 at substantially the same time.} It should be noted that the value x to be monitored is uncontrollable when executing the self-test.

Since the plurality of sense circuits 312 have the same circuit type, the plurality of sense signals V _SNS1 and V _SNS2 generated when the plurality of sense circuits 312 are normal have the expected relative relationship. is doing. In this example, when the sense circuits 312 in the two anomaly detection circuits 310 are both normal, _{the values of the two sense signals V SNS1} and V _SNS2 are represented by equations (1) and (2), y ₁ , It becomes y _2. If any of the sense circuits 312 has an abnormality _{, the relationship between the plurality of sense signals V SNS1} and V _SNS2 deviates from the expected one.

When the ratio r = y ₁ / y ₂ is taken as a relative relationship, the expected value r _EXP of the ratio r is given by the equation (3).
r _EXP = a ₁ / a ₂
Test circuit 330 _calculates the ratio _V SNS1 _{/ V SNS2} of V _{SNS1, V SNS2,} compared with the expected value _{r EXP.} Then, when the calculated ratio V _SNS1 / V _SNS2 matches (or is included in the expected range) the expected value r _EXP , it can be determined that the plurality of sense circuits 312 are normal. Conversely, when the calculated ratio V _SNS1 / V _SNS2 does not match (or is out of the expected range) the expected value r _EXP , it can be determined that at least one of the plurality of sense circuits 312 is abnormal.

Relative relationships are not limited to ratios. For example, when a ₁ = a ₂ , the difference may be taken as a relative relationship. In this case, the expected value of the difference is zero.

As a result of the self-test, S ₁ is input to the logic circuit 320. Logic circuit 320, when shown results _{S 1} is the normal self-test, and has high reliability of the determination signal _{S ABN1, S ABN2,} in response to the assertion of the determination signal _{S ABN1} and _{S ABN2,} predetermined protection process To execute.

On the contrary, when the result of the self-test test S ₁ shows an abnormality, the logic circuit 320 may notify the external processor.

The above is the operation of the semiconductor integrated circuit 100. According to the semiconductor integrated circuit 100, an abnormality of a plurality of sense circuits 312 can be detected, and the reliability of the semiconductor integrated circuit 100 can be improved.

The present invention extends to various devices and circuits grasped as the block diagram and circuit diagram of FIG. 2 or derived from the above description, and is not limited to a specific configuration. Hereinafter, more specific configuration examples and modification examples will be described in order to help understanding the essence of the invention and circuit operation, and to clarify them, not to narrow the scope of the present invention.

FIG. 3 is a circuit diagram of the semiconductor integrated circuit 100A according to the embodiment. In this embodiment, the monitored object is the voltage of any pin or node. For example, the monitoring subject may be a power supply voltage _{V DD} supplied to the power supply (VDD) pins of the semiconductor integrated circuit 100A. Further, the abnormality detection circuit 310_1 is an overvoltage detection circuit, and the abnormality detection circuit 310_2 is an undervoltage detection circuit.

Each of the plurality of abnormality detection circuits 310_1 and 310_2 sense circuits 312 divides the voltage _{VDD to be monitored} and generates sense signals V _{SNS_OV} and V SNS_UV. Sense circuit 312_1 of the abnormality detection circuit 310_1 includes a resistor _R 1, _{R 2.} The voltage division ratio R ₂ / (R ₁ + R ₂ ) corresponds to _{a 1} in the equation (1). The comparator 314_1 compares the sense signal V _{SNS_OV} with the threshold value V _{TH_OV,} and asserts the determination signal S _{ABN_OV when V SNS_OV} > V _{TH_OV.}

The sense circuit 312_2 of the anomaly detection circuit 310_2 includes resistors R ₃ and R ₄ . The voltage division ratio R ₄ / (R ₃ + R ₄ ) corresponds to _{a 2} of the equation (2). The comparator 314_2 compares the sense signal V _{SNS_UV} with the threshold value V _{TH_UV,} and asserts the determination signal S _{ABN_UV when V SNS_UV} <V _{TH_UV.}

The test circuit 330 includes a selector 332, an A / D converter 334, and a digital processing unit 336. _{The selector 332 selects one} of the sense signals V _{SNS_OV} and V _{SNS_UV} according to the selection signal SEL 1 generated by the digital processing unit 336. For example, the digital processing unit 336 may generate the selection signal SEL _{1 so that the sense signals V SNS_OV} and V _{SNS_UV are sequentially selected.} The A / D converter 334 converts the sense signals V _{SNS_OV} and V _{SNS_UV,} which are sequentially selected by the selector 332, into the digital signals D _{SNS_OV} and D _{SNS_UV} . When measuring two sense signals V _{SNS_OV} and V _{SNS_UV} at substantially the same time, the sample hold function may be executed on the selector 332.

The digital processing unit 336 determines whether or not there is an abnormality in the sense circuits 312_1 and 312_2 based on _{the digital signals D SNS_OV} and D _{SNS_UV.} For example, the digital processing unit 336 calculates the ratio D _{SNS_OV} / D _{SNS_UV of the two digital signals D SNS_OV} and D _{SNS_UV} , and determines whether or not they match the expected value. The expected value is {R ₂ / (R ₁ + R ₂ )} / {R ₄ / (R ₃ + R ₄ )}. The digital processing unit 336 may be a part of the logic circuit 320.

According to this semiconductor integrated circuit 100A, it is possible to detect an abnormality in the overvoltage detection circuit and the undervoltage detection circuit.

FIG. 4 is a circuit diagram of the sense circuits 312_1 and 312_2 according to the embodiment. In FIG. 4, the sense circuits 312_1 and 312_2 are integrally configured. _VIN represents the voltage to be monitored.
V _SNS1 = (R ₂ + R ₃ ) / (R ₁ + R ₂ + R ₃ ) × V _IN
V _SNS2 = R ₃ / (R ₁ + R ₂ + R ₃ ) × V _IN

FIG. 5 is a circuit diagram of the abnormality detection circuits 310_1 and 310_2 according to the embodiment. The detection target of the abnormality detection circuit 310_1 is the temperature, and the overheat abnormality is detected. The anomaly detection circuit 310_1 includes a diode 340 and a current source 342. Current source 342 supplies a constant current _{I C} in the diode 340. The diode 340, a voltage drop corresponding to the temperature (forward voltage) _{V F} is generated. This forward voltage becomes the sense signal V _SNS1 .

The abnormality detection circuit 310_2 is a perfect replica of the abnormality detection circuit 310_1, and V _SNS1 = V _SNS2 holds in the normal state of the sense circuits 312_1 and 312_2. Further, V _TH1 = V _TH2 , and the abnormality detection circuits 310_ and 310_2 are redundant circuits that detect an overheat abnormality based on the same reference.

Also in the embodiment of FIG. 5, the abnormality of the sense circuits 312_1 and 312_2 is based on the relative relationship between the _{two sense signals V SNS1} and V _SNS2 acquired when the temperatures to be monitored are substantially the same. Can be detected.

FIG. 6 is a circuit diagram of the sense circuit 312 according to the embodiment. The sense circuit 312 includes an amplifier, and the gain of the amplifier is associated with _{the constants a 1} and a _{2 of the equations (1) and (2).} For example, the monitored object of the sense circuit 312 is a current, and _{may include a sense resistor RS} provided in the path of the current to be monitored and an amplifier 313 that amplifies the voltage drop of the sense resistor _RS.

(Second embodiment)
In the first embodiment, the configuration for detecting the abnormality of the plurality of sense circuits 312 in the abnormality detection circuit 310 has been described. In the second embodiment, the configuration for detecting the abnormality of the comparator 314 will be described. FIG. 7 is a block diagram of the semiconductor integrated circuit 200 according to the second embodiment. FIG. 2 shows only the portion of the semiconductor integrated circuit 200 related to the protection circuit 400.

Since the abnormality detection circuit 310 and the logic circuit 320 are the same as those in the first embodiment, the description thereof will be omitted. The test circuit in the second embodiment 430, the generating node _N 1, _{N 2} of the plurality of abnormality detection circuit 310_1,310_2 respective sense signal _{V SNS1, V SNS2,} in other words the comparator 314_1,314_2 respective one input The adjustable test signals V _TEST1 and V TEST 2 can be supplied to the _vehicle. While the test signals V _TEST1 and V _TEST2 are being supplied, the sense circuit 312 is stopped.

When the comparator 314_1 is normal, when a test signal V _{TEST1 higher than the threshold value V TH1} is given, the determination signal S _ABN1 takes a predetermined first level and gives a test signal V _{TEST1 lower than the threshold value V TH1.} , The determination signal S _ABN1 takes a predetermined second level. If the comparator 314 is out of order or the threshold value _VTH1 is not a normal value, this relationship is broken.

Therefore, the test circuit 430 gives a test signal V _TEST1 of a predetermined level, and can detect an abnormality of the comparator 314_1 based on whether or not the determination signal _{SABN1 at that time matches the expected value.} The test circuit 430 _{outputs the result S 2} to the logic circuit 320.

Preferably the test circuit 430 includes a test signal _{V TEST1,} switching between the smaller and greater than the threshold value _{V TH1,} it may obtain a judgment signal _{S ABN1} in each. _{Then, when the determination signal SABN1} corresponding to the values of the two test signals V _TEST1 matches the expected value of each, the comparator 314_1 may be determined to be normal.

It is possible to determine whether or not the comparator 314_2 is normal in the same manner.

FIG. 8 is a circuit diagram of a test circuit 430 according to an embodiment. The test circuit 430 includes a selector 432 and a D / A converter 434 in addition to the selector 332, the A / D converter 334, and the digital processing unit 336 of FIG. The D / A converter 434 converts the digital code CODE generated by the digital processing unit 336 into an analog test signal V _TEST . The selector 432 supplies the test signal V _TEST to one of a plurality of nodes N _{1 to} N _{2 according to the selection signal SEL 2} generated by the digital processing unit 336.

The digital processing unit 336 generates the selection signal SEL ₂ and the code CODE so that the test signal V _{TEST of an appropriate level is supplied to each of the plurality of nodes N 1 to} N _2. Then, the determination signals S _ABN1 and S _ABN2 obtained corresponding to the test signals V _TEST1 and V _TEST2 are compared with the expected values, and the normality / abnormality of the comparators 314_1 and 314_2 is determined.

FIG. 9 is a circuit diagram showing a configuration example of the A / D converter 334 and the D / A converter 434. The A / D converter 334 is a sequential comparison type A / D converter that converts a _{plurality of sense signals V SNS1} and V _{SNS2 into digital values.} The configuration of the successive approximation type A / D converter is known and includes a sample hold circuit 350, a comparator 352, a sequential comparison register (SAR) 354, and a sub D / A converter 356. The selector 332 is incorporated in the A / D converter 334.

In FIG. 9, the sub D / A converter 356 functions as a D / A converter 434. That is, when operating the A / D converter 334, the value of the sequential comparison register 354 is input to the sub D / A converter 356, and when operating the sub D / A converter 356 as the D / A converter 434, , The code CODE from the digital processing unit 336 is input. A buffer 436 may be provided to drive the nodes N ₁ and N _2.

According to this configuration, the increase in the circuit area can be suppressed by using the sub-D / A converter 356 provided in the sequential comparison type A / D converter 334 also as the D / A converter 434.

The present invention has been described using specific terms and phrases based on the embodiments, but the embodiments merely indicate the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangements can be changed without departing from the ideas of the present invention.

100 ... semiconductor integrated circuit, 300 ... protection circuit, 310 ... abnormality detection circuit, 320 ... logic circuit, 312 ... sense circuit, 314 ... comparator, 330 ... test circuit, 332 ... selector, 334 ... A / D converter, 336 ... digital Processing unit, 340 ... diode, 342 ... current source, 350 ... sample hold circuit, 352 ... comparator, 354 ... sequential comparison register, 356 ... sub-D / A converter, 200 ... semiconductor integrated circuit, 400 ... protection circuit, 430 ... test Circuit, 432 ... Selector, 434 ... D / A converter.

Claims (11)

Multiple anomaly detection circuits that share a common monitoring target,
A test circuit that inspects the plurality of abnormality detection circuits and
Equipped with
Each of the plurality of abnormality detection circuits
A sense circuit that has the same circuit type and generates a sense signal according to the monitoring target,
A comparator that compares the sense signal with a predetermined threshold value and generates a determination signal indicating the presence or absence of an abnormality.
Including
The test circuit is a semiconductor integrated circuit characterized by detecting an abnormality in the plurality of abnormality detection circuits based on a plurality of sense signals generated in the plurality of abnormality detection circuits. The semiconductor integrated circuit according to claim 1, wherein the test circuit detects an abnormality in the plurality of abnormality detection circuits based on the plurality of sense signals at substantially the same time. The semiconductor integrated circuit according to claim 1 or 2, wherein the test circuit detects an abnormality in the plurality of abnormality detection circuits based on the ratio of the plurality of sense signals. The invention according to any one of claims 1 to 3, wherein the sense circuit of each of the plurality of abnormality detection circuits includes a voltage dividing circuit that divides the voltage to be monitored and generates the sense signal. Semiconductor integrated circuit. The semiconductor integrated circuit according to any one of claims 1 to 4, wherein one of the plurality of abnormality detection circuits is an overvoltage detection circuit, and the other is an undervoltage detection circuit. The semiconductor integrated circuit according to any one of claims 1 to 4, wherein the plurality of abnormality detection circuits determine the presence or absence of an abnormality based on the same criteria. The semiconductor integrated circuit according to claim 5, wherein the plurality of abnormality detection circuits are temperature abnormality detection circuits. The sense circuit is
With a diode
A current source that supplies a constant current to the diode,
7. The semiconductor integrated circuit according to claim 7, wherein the voltage drop of the diode is the sense signal. The test circuit is
An A / D converter that converts each of the plurality of sense signals into a digital value,
A digital processing unit that processes a plurality of digital values corresponding to the plurality of sense signals, and a digital processing unit.
The semiconductor integrated circuit according to any one of claims 1 to 8, wherein the semiconductor integrated circuit comprises. The semiconductor according to any one of claims 1 to 9, wherein the test circuit is configured to be configured to be able to supply an adjustable test signal to the generation node of the sense signal of each of the plurality of abnormality detection circuits. Integrated circuit. The test circuit is
A successive approximation type A / D converter that converts each of the plurality of sense signals into a digital value, and
A selector that supplies the output signal of the sub-D / A converter of the A / D converter to the node that generates the sense signal of each of the plurality of abnormality detection circuits.
A digital processing unit that controls the input code to the sub-D / A converter,
The semiconductor integrated circuit according to any one of claims 1 to 8, wherein the semiconductor integrated circuit comprises.

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