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JP6992406B2 - Manufacturing method of semiconductor device - Google Patents
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JP6992406B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP6992406B2
JP6992406B2 JP2017206654A JP2017206654A JP6992406B2 JP 6992406 B2 JP6992406 B2 JP 6992406B2 JP 2017206654 A JP2017206654 A JP 2017206654A JP 2017206654 A JP2017206654 A JP 2017206654A JP 6992406 B2 JP6992406 B2 JP 6992406B2
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conductor member
resin
mold
laminated body
hole
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JP2019079966A (en
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裕理 今井
智弘 宮崎
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Denso Corp
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07351Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07354Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/341Dispositions of die-attach connectors, e.g. layouts
    • H10W72/347Dispositions of multiple die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/381Auxiliary members
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本明細書が開示する技術は、半導体装置の製造方法に関する。 The techniques disclosed herein relate to methods of manufacturing semiconductor devices.

特許文献1に、半導体装置の製造方法が開示されている。この製造方法は、半導体素子と放熱板とが積層された積層体を金型内に配置するとともに、金型内に樹脂を注入することによって、積層体を樹脂で封止する工程を有する。放熱板には切り欠き部が設けられており、金型内に注入された樹脂に生じる気泡は、放熱板の切り欠き部から金型外に排出される。これによって、樹脂の内部に気泡が生じることが抑制される。 Patent Document 1 discloses a method for manufacturing a semiconductor device. This manufacturing method includes a step of arranging a laminate in which a semiconductor element and a heat sink are laminated in a mold, and injecting a resin into the mold to seal the laminate with the resin. The heat radiating plate is provided with a notch, and air bubbles generated in the resin injected into the mold are discharged from the notch of the heat radiating plate to the outside of the mold. This suppresses the generation of air bubbles inside the resin.

特開2016-134591号公報Japanese Unexamined Patent Publication No. 2016-134591

上記の技術では、放熱板の放熱面(即ち、外部に露出する面)に切り欠き部が設けられるので、放熱板による半導体装置の放熱効果が著しく低下し得る。本明細書では、半導体装置の放熱性を著しく低下させることなく、半導体素子近傍に気泡が生じることを抑制するための技術を開示する。 In the above technique, since the cutout portion is provided on the heat radiating surface (that is, the surface exposed to the outside) of the heat radiating plate, the heat radiating effect of the semiconductor device by the heat radiating plate can be significantly reduced. This specification discloses a technique for suppressing the generation of bubbles in the vicinity of a semiconductor element without significantly reducing the heat dissipation of the semiconductor device.

本明細書が開示する半導体装置の製造方法は、半導体素子と前記半導体素子に接合された導体部材を有する積層体を準備する工程と、積層体を金型内に配置するとともに、金型内に樹脂を注入することによって、積層体を前記樹脂で封止する工程と、を備える。導体部材には、積層体の積層方向に沿って延びる周側面に開口を有する穴又は溝が形成されている。封止する工程では、導体部材の穴又は溝の開口が、積層体を二方向から回り込んで合流する樹脂の合流予定箇所に位置するように、積層体を金型内に配置する。 The method for manufacturing a semiconductor device disclosed in the present specification includes a step of preparing a laminate having a semiconductor element and a conductor member bonded to the semiconductor element, arranging the laminate in a mold, and in a mold. A step of sealing the laminate with the resin by injecting the resin is provided. The conductor member is formed with a hole or a groove having an opening on the peripheral side surface extending along the stacking direction of the laminated body. In the sealing step, the laminated body is arranged in the mold so that the opening of the hole or the groove of the conductor member is located at the planned merging point of the resin that wraps around the laminated body from two directions and merges.

積層体を配置した金型内へ樹脂を注入していくと、金型内を流動する樹脂は積層体を二方向から回り込んで合流する。その合流箇所において、樹脂の内部に気泡が形成されやすい。この点に関して、上記した製造方法では、導体部材に穴又は溝が形成されており、その穴又は溝の開口が樹脂の合流予定箇所に位置するように、積層体は金型内に配置される。これにより、樹脂の合流箇所において生じた気泡は、導体部材の穴又は溝に流入するか、導体部材の穴又は溝を通過した樹脂によって押し流される。これにより、半導体素子近傍に気泡が生じることを抑制することができる。また、上記の構成によると、前述したような放熱面に及ぶ切り欠き部を必ずしも必要としないので、半導体装置の放熱性を比較的に維持することができる。 When the resin is injected into the mold in which the laminate is arranged, the resin flowing in the mold wraps around the laminate from two directions and merges. Bubbles are likely to be formed inside the resin at the confluence. In this regard, in the above-mentioned manufacturing method, a hole or a groove is formed in the conductor member, and the laminate is arranged in the mold so that the opening of the hole or the groove is located at the planned merging point of the resin. .. As a result, the bubbles generated at the confluence of the resins flow into the holes or grooves of the conductor member, or are washed away by the resin that has passed through the holes or grooves of the conductor member. As a result, it is possible to suppress the generation of bubbles in the vicinity of the semiconductor element. Further, according to the above configuration, since the notch portion extending to the heat radiating surface as described above is not always required, the heat radiating property of the semiconductor device can be relatively maintained.

半導体装置の断面図を示す。The sectional view of the semiconductor device is shown. 金型に配置された積層体の上面図を示す。The top view of the laminated body arranged in a mold is shown. 封止する工程における導体部材の拡大図を示す。The enlarged view of the conductor member in the sealing process is shown. 第2実施例の封止する工程における導体部材の拡大図を示す。The enlarged view of the conductor member in the sealing process of 2nd Example is shown. 第3~5実施例の導体部材の上面図を示す。The top view of the conductor member of 3rd to 5th Examples is shown. 第6実施例の半導体装置の断面図を示す。The sectional view of the semiconductor device of 6th Example is shown. 第7実施例の半導体装置の断面図を示す。The sectional view of the semiconductor device of 7th Example is shown.

(第1実施例)
図面を参照して、実施例の半導体装置10の説明をする。図1は、半導体装置10の断面図である。半導体装置10は、積層体12と、モールド樹脂36と、を備える。積層体12は、モールド樹脂36内に封止されている。モールド樹脂36は、絶縁性を有する材料で構成されている。特に限定されないが、モールド樹脂36を構成する材料は、例えば、エポキシ樹脂といった熱硬化性の樹脂材料である。積層体12は、上面側放熱板20と、導体部材26aと、半導体素子30と、下面側放熱板34と、が積層された構造を有する。
(First Example)
The semiconductor device 10 of the embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view of the semiconductor device 10. The semiconductor device 10 includes a laminate 12 and a mold resin 36. The laminate 12 is sealed in the mold resin 36. The mold resin 36 is made of a material having an insulating property. Although not particularly limited, the material constituting the mold resin 36 is a thermosetting resin material such as an epoxy resin. The laminated body 12 has a structure in which the upper surface side heat sink 20, the conductor member 26a, the semiconductor element 30, and the lower surface side heat sink 34 are laminated.

半導体素子30は、例えばMOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)、又はIGBT(Insulated Gate Bipolar Transistor)などのパワー半導体素子である。また半導体素子30は、例えばシリコン(Si)、炭化ケイ素(SiC)、又は窒化ガリウム(GaN)といった各種の半導体材料を用いて構成される。また、図示省略しているが、半導体素子30の上面及び下面には、例えばアルミニウム系又はその他の金属によって構成される上面電極及び下面電極が形成されている。 The semiconductor element 30 is a power semiconductor element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). Further, the semiconductor element 30 is configured by using various semiconductor materials such as silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). Further, although not shown, upper surface electrodes and lower surface electrodes made of, for example, aluminum or other metals are formed on the upper surface and the lower surface of the semiconductor element 30.

導体部材26aは、例えば銅、又はその他の金属といった導電性を有する材料を用いて構成されている。導体部材26aは、概して板形状あるいはブロック形状の部材であり、上面と、上面とは反対側に位置する下面と、積層体12の積層方向に沿って延びる4つの側面を有する。導体部材26aは、モールド樹脂36内に位置している。導体部材26aの上面は、上面側放熱板20の下面と、はんだ層22によって接合されている。また、導体部材26aの下面は、半導体素子30の上面と、はんだ層28によって接合されている。これにより、半導体素子30は、導体部材26aを介して上面側放熱板20に電気的、及び、熱的に接続されている。また、導体部材26aは、4つの角のそれぞれに開口を有する4個の穴24aを有する(図2参照)。穴24aは、開口から導体部材26aの中心付近まで延びており、導体部材26aを貫通していない。なお、半導体装置10の放熱性を維持するために、穴24aは半導体素子30から離れた位置に形成するのが好ましい。 The conductor member 26a is made of a conductive material such as copper or other metal. The conductor member 26a is generally a plate-shaped or block-shaped member, and has an upper surface, a lower surface located on the side opposite to the upper surface, and four side surfaces extending along the stacking direction of the laminated body 12. The conductor member 26a is located in the mold resin 36. The upper surface of the conductor member 26a is joined to the lower surface of the heat sink 20 on the upper surface side by a solder layer 22. Further, the lower surface of the conductor member 26a is joined to the upper surface of the semiconductor element 30 by a solder layer 28. As a result, the semiconductor element 30 is electrically and thermally connected to the upper surface side heat sink 20 via the conductor member 26a. Further, the conductor member 26a has four holes 24a having openings at each of the four corners (see FIG. 2). The hole 24a extends from the opening to the vicinity of the center of the conductor member 26a and does not penetrate the conductor member 26a. In order to maintain the heat dissipation of the semiconductor device 10, it is preferable that the hole 24a is formed at a position away from the semiconductor element 30.

上面側放熱板20及び下面側放熱板34は、例えば銅、又は、その他の金属といった導電性を有する材料を用いて構成されている。上面側放熱板20は、概して板形状の部材である。上面側放熱板20の下面は、モールド樹脂36の内部において、導体部材26aの上面とはんだ層22を介して接合されている。これにより、上面側放熱板20は、導体部材26aを介して、半導体素子30と電気的に接続されている。一方、上面側放熱板20の上面は、モールド樹脂36の外部に露出しており、放熱面として機能する。上面側放熱板20は、導体部材26aを介して、半導体素子30と熱的にも接続されており、半導体素子30で発生した熱は上面側放熱板20の上面から半導体装置10外へと放熱される。 The upper surface side heat sink 20 and the lower surface side heat sink 34 are made of a conductive material such as copper or other metal. The upper surface side heat sink 20 is generally a plate-shaped member. The lower surface of the heat radiating plate 20 on the upper surface side is joined to the upper surface of the conductor member 26a via the solder layer 22 inside the mold resin 36. As a result, the upper surface side heat sink 20 is electrically connected to the semiconductor element 30 via the conductor member 26a. On the other hand, the upper surface of the heat radiating plate 20 on the upper surface side is exposed to the outside of the mold resin 36 and functions as a heat radiating surface. The upper surface side heat sink 20 is also thermally connected to the semiconductor element 30 via the conductor member 26a, and the heat generated by the semiconductor element 30 is dissipated from the upper surface of the upper surface side heat sink 20 to the outside of the semiconductor device 10. Will be done.

同様に、下面側放熱板34もまた、概して板形状の部材である。下面側放熱板34の上面は、モールド樹脂36の内部において、半導体素子30の下面とはんだ層32を介して接合されている。これにより、下面側放熱板34は、半導体素子30と電気的に接続されている。一方、下面側放熱板34の下面は、モールド樹脂36の外部に露出しており、放熱面として機能する。下面側放熱板34は、半導体素子30と熱的にも接続されており、半導体素子30で発生した熱は下面側放熱板34の下面から半導体装置10外へと放熱される。 Similarly, the lower surface side heat sink 34 is also a generally plate-shaped member. The upper surface of the lower surface side heat sink 34 is joined to the lower surface of the semiconductor element 30 via the solder layer 32 inside the mold resin 36. As a result, the lower surface side heat sink 34 is electrically connected to the semiconductor element 30. On the other hand, the lower surface of the lower surface side heat radiating plate 34 is exposed to the outside of the mold resin 36 and functions as a heat radiating surface. The lower surface side heat sink 34 is also thermally connected to the semiconductor element 30, and the heat generated by the semiconductor element 30 is radiated from the lower surface of the lower surface side heat sink 34 to the outside of the semiconductor device 10.

続いて、図2及び図3を参照して、半導体装置10の製造方法を説明する。なお、積層体12を準備する工程は既知の方法により行われるため、その詳細な説明は省略する。そのため、以下では、積層体12をモールド樹脂36で封止する工程のみを説明する。 Subsequently, a method for manufacturing the semiconductor device 10 will be described with reference to FIGS. 2 and 3. Since the step of preparing the laminated body 12 is performed by a known method, detailed description thereof will be omitted. Therefore, in the following, only the step of sealing the laminated body 12 with the mold resin 36 will be described.

まず、積層体12をモールド樹脂36で封止する工程では、既知の方法で準備した積層体12を金型60内に配置する。図2は、金型60に配置された積層体12を上面視した図である。金型60は、モールド樹脂36を形成する樹脂を金型60内に注入するためのゲート62を備える。なお、理解の容易化のために、図2では、積層体12が備える上面側放熱板20と、はんだ層22の図示を省略している。また、図2では、導体部材26aが有する4個の穴24aを破線で示している。一般的に、ゲート62から金型60内に樹脂を注入すると、樹脂は積層体12を二方向から回り込んでゲート62の反対側で合流する。本実施例では、少なくとも1個の穴24aの開口が、樹脂が合流すると予想される合流予定箇所に位置するように、積層体12を金型60内に配置する。樹脂の合流予定箇所は、積層体12及び金型60の具体的な構成や、樹脂の流動性等に応じて定まるものであり、実験やシミュレーションによって比較的に正確に予想することができる。 First, in the step of sealing the laminate 12 with the mold resin 36, the laminate 12 prepared by a known method is placed in the mold 60. FIG. 2 is a top view of the laminated body 12 arranged in the mold 60. The mold 60 includes a gate 62 for injecting the resin forming the mold resin 36 into the mold 60. For ease of understanding, FIG. 2 omits the illustration of the upper surface side heat sink 20 and the solder layer 22 included in the laminated body 12. Further, in FIG. 2, the four holes 24a included in the conductor member 26a are shown by broken lines. Generally, when the resin is injected into the mold 60 from the gate 62, the resin wraps around the laminate 12 from two directions and joins on the opposite side of the gate 62. In this embodiment, the laminated body 12 is arranged in the mold 60 so that the openings of at least one hole 24a are located at the planned merging points where the resins are expected to merge. The planned merging point of the resin is determined according to the specific configuration of the laminated body 12 and the mold 60, the fluidity of the resin, and the like, and can be predicted relatively accurately by experiments and simulations.

図3は、金型60内に樹脂が注入されている状態における導体部材26aの拡大図を示す。理解の容易化のため、図3では、注入された樹脂にハッチングを付している。図3(a)に示すように、注入された樹脂は、導体部材26aを二方向から回り込んで合流する。一般的に、金型60内を流れる樹脂では、金型60又は積層体12に直接接している部分と、金型60又は積層体12に直接接していない部分と、の間での流速差が生じる。即ち、金型60又は積層体12に直接接している部分における流速は、金型60又は積層体12との間の摩擦により、金型60又は積層体12に直接接していない部分の流速よりも遅くなる。このために、図3(b)に示すように、樹脂が合流した後に、樹脂の合流箇所において気泡70が生じ得る。本実施例では、金型60内に樹脂が満たされた後に、金型60内の圧力が一定(例えば数十MPa)に保圧される。この保圧の過程において、図3(c)に示すように、気泡70が穴24a内に流入する。 FIG. 3 shows an enlarged view of the conductor member 26a in a state where the resin is injected into the mold 60. In FIG. 3, the injected resin is hatched for ease of understanding. As shown in FIG. 3A, the injected resin wraps around the conductor member 26a from two directions and merges. Generally, in the resin flowing in the mold 60, the difference in flow velocity between the portion directly in contact with the mold 60 or the laminated body 12 and the portion not directly in contact with the mold 60 or the laminated body 12 Occurs. That is, the flow velocity in the portion directly in contact with the mold 60 or the laminated body 12 is higher than the flow velocity in the portion not directly in contact with the mold 60 or the laminated body 12 due to friction between the mold 60 or the laminated body 12. Become slow. For this reason, as shown in FIG. 3B, after the resins have merged, bubbles 70 may be generated at the junctions of the resins. In this embodiment, after the mold 60 is filled with the resin, the pressure in the mold 60 is kept constant (for example, several tens of MPa). In the process of holding the pressure, as shown in FIG. 3C, the bubble 70 flows into the hole 24a.

上記のように、本実施例では、少なくとも1個の穴24aの開口が、樹脂が合流すると予想される合流予定箇所に位置するように、積層体12を金型60内に配置する。従って、変形例では、導体部材26aは、4個の穴24aを有しなくてもよく、少なくとも1個の穴24aを有すればよい。しかしながら、本実施例のように、導体部材26aが4個の穴24aを有する構成では、積層体12を準備する工程において、導体部材26aを配置する向きに配慮する必要がない。従って、積層体12を準備する工程における利便性が向上する。 As described above, in this embodiment, the laminated body 12 is arranged in the mold 60 so that the opening of at least one hole 24a is located at the planned merging point where the resin is expected to merge. Therefore, in the modified example, the conductor member 26a does not have to have four holes 24a, and may have at least one hole 24a. However, in the configuration in which the conductor member 26a has four holes 24a as in the present embodiment, it is not necessary to consider the orientation in which the conductor member 26a is arranged in the step of preparing the laminated body 12. Therefore, the convenience in the process of preparing the laminated body 12 is improved.

(本実施例の効果)
本実施例では、導体部材26aに穴24aが形成されており、穴24a開口が樹脂の合流予定箇所に位置するように、積層体12は金型60内に配置される。これにより、樹脂の合流箇所において生じた気泡70は、樹脂の合流予定箇所に位置する穴24aに流入する。従って、半導体素子30近傍に気泡が生じることを抑制することができる。また、本実施例では、穴24aは、放熱面として機能しない導体部材26aに形成される。従って、半導体装置10の放熱性を比較的に維持することができる。
(Effect of this example)
In this embodiment, the laminated body 12 is arranged in the mold 60 so that the hole 24a is formed in the conductor member 26a and the opening of the hole 24a is located at the planned merging point of the resin. As a result, the bubbles 70 generated at the resin merging point flow into the hole 24a located at the resin merging point. Therefore, it is possible to suppress the generation of bubbles in the vicinity of the semiconductor element 30. Further, in this embodiment, the hole 24a is formed in the conductor member 26a that does not function as a heat dissipation surface. Therefore, the heat dissipation of the semiconductor device 10 can be relatively maintained.

(第2実施例)
続いて、図4を参照して、第2実施例を説明する。第2実施例は、積層体12が導体部材26aに代えて導体部材26bを備える点が、第1実施例とは異なる。従って、以下では、第1実施例とは異なる点のみを説明し、その他の説明は省略する。図4は、本実施例の積層体12が配置された金型60内に樹脂が注入されている状態における導体部材26bの拡大図を示す。図4に示すように、導体部材26bは、一つの角から当該一つの角に対向する角まで貫通している2個の穴24bを有する。なお、第2実施例においても、積層体12を樹脂で封止する工程において、少なくとも1個の穴24bの開口が、樹脂の合流予定箇所に位置するように、積層体12が金型60内に配置されている。
(Second Example)
Subsequently, a second embodiment will be described with reference to FIG. The second embodiment is different from the first embodiment in that the laminated body 12 includes the conductor member 26b instead of the conductor member 26a. Therefore, in the following, only the points different from those of the first embodiment will be described, and other explanations will be omitted. FIG. 4 shows an enlarged view of the conductor member 26b in a state where the resin is injected into the mold 60 in which the laminated body 12 of this embodiment is arranged. As shown in FIG. 4, the conductor member 26b has two holes 24b penetrating from one corner to the angle facing the one corner. Also in the second embodiment, in the step of sealing the laminated body 12 with the resin, the laminated body 12 is inside the mold 60 so that the opening of at least one hole 24b is located at the planned merging point of the resin. Is located in.

図4(a)では、注入された樹脂が、導体部材26bを二方向から回り込んで合流する。また、導体部材26bには、注入された樹脂が、ゲート62に最も近い穴24bの開口から流入する。次いで、図4(b)では、樹脂が合流した後に、樹脂の合流箇所において気泡80が生じ得る。導体部材26bには、合流予定箇所に位置する穴24bの開口以外の開口から注入された樹脂がさらに流入する。そして、図4(c)では、金型60内に樹脂が満たされた後に、金型60内の圧力が一定(例えば数十MPa)に保圧される。この保圧の過程において生じる圧力勾配によって、樹脂が穴24bを通過し、合流予定箇所に位置する穴24bの開口から導体部材26b外に樹脂が流出する。この結果、流出した樹脂によって、気泡70が半導体素子30の近傍から押し流される。 In FIG. 4A, the injected resin wraps around the conductor member 26b from two directions and joins. Further, the injected resin flows into the conductor member 26b through the opening of the hole 24b closest to the gate 62. Then, in FIG. 4B, after the resins have merged, bubbles 80 may be generated at the junctions of the resins. The resin injected from an opening other than the opening of the hole 24b located at the planned merging point further flows into the conductor member 26b. Then, in FIG. 4C, after the mold 60 is filled with the resin, the pressure in the mold 60 is kept constant (for example, several tens of MPa). Due to the pressure gradient generated in the pressure holding process, the resin passes through the hole 24b, and the resin flows out of the conductor member 26b from the opening of the hole 24b located at the planned confluence. As a result, the bubbles 70 are swept away from the vicinity of the semiconductor element 30 by the outflowing resin.

(本実施例の効果)
本実施例では、樹脂の合流箇所において生じた気泡80は、導体部材26bの穴24bを通過した樹脂によって押し流される。従って、半導体素子30近傍に気泡が生じることを抑制することができる。また、穴24bが導体部材26bに形成されるので、半導体装置10の放熱性を比較的に維持することができる。
(Effect of this example)
In this embodiment, the bubbles 80 generated at the confluence of the resins are swept away by the resin that has passed through the holes 24b of the conductor member 26b. Therefore, it is possible to suppress the generation of bubbles in the vicinity of the semiconductor element 30. Further, since the hole 24b is formed in the conductor member 26b, the heat dissipation of the semiconductor device 10 can be relatively maintained.

(第3実施例)
続いて、図5を参照して、第3実施例を説明する。第3実施例では、積層体12が導体部材26aに代えて導体部材26cを備える点が、第1実施例とは異なる。図5(a)は、導体部材26cの上面図を示す。導体部材26cは、その一つの角の近傍に開口を有する1個の穴24cを有する。理解の容易化のために、図5(a)では、導体部材26cが有する穴24cを破線で示している。本実施例では、積層体12を樹脂で封止する工程において、穴24cの開口が樹脂の合流予定箇所に位置するように、積層体12を金型60内に配置する。これにより、樹脂の合流箇所において生じた気泡70は、合流予定箇所に位置する穴24cに流入する。従って、本実施例においても、半導体素子30近傍に気泡が生じることを抑制することができる。また、穴24cが導体部材26cに形成されるので、半導体装置10の放熱性を比較的に維持することができる。
(Third Example)
Subsequently, a third embodiment will be described with reference to FIG. The third embodiment is different from the first embodiment in that the laminated body 12 includes the conductor member 26c instead of the conductor member 26a. FIG. 5A shows a top view of the conductor member 26c. The conductor member 26c has one hole 24c with an opening in the vicinity of one corner thereof. For ease of understanding, in FIG. 5A, the hole 24c included in the conductor member 26c is shown by a broken line. In this embodiment, in the step of sealing the laminated body 12 with the resin, the laminated body 12 is arranged in the mold 60 so that the opening of the hole 24c is located at the planned merging point of the resin. As a result, the bubbles 70 generated at the confluence of the resins flow into the holes 24c located at the confluence. Therefore, also in this embodiment, it is possible to suppress the generation of bubbles in the vicinity of the semiconductor element 30. Further, since the hole 24c is formed in the conductor member 26c, the heat dissipation of the semiconductor device 10 can be relatively maintained.

(第4実施例)
続いて、図5を参照して、第4実施例を説明する。第4実施例では、積層体12が導体部材26aに代えて導体部材26dを備える点が、第1実施例とは異なる。図5(b)は、導体部材26dの上面図を示す。導体部材26dは、その4つの側面のそれぞれに開口を有する4個の穴24dを有する。理解の容易化のために、図5(b)では、導体部材26dが有する穴24dを破線で示している。第1実施例とは異なり、樹脂の合流予定箇所が、導体部材26dの4つの側面のうちのいずれかの近傍である場合には、樹脂の合流箇所で生じた気泡が穴24aに十分に流入しない可能性がある。これに対し、本実施例では、導体部材26dがその側面に開口を有する穴24dを有するので、樹脂の合流箇所で生じた気泡が穴24dに十分に流入する。従って、本実施例においても、半導体素子30近傍に気泡が生じることを抑制することができる。また、穴24dが導体部材26dに形成されるので、半導体装置10の放熱性を比較的に維持することができる。
(Fourth Example)
Subsequently, a fourth embodiment will be described with reference to FIG. The fourth embodiment is different from the first embodiment in that the laminated body 12 includes the conductor member 26d instead of the conductor member 26a. FIG. 5B shows a top view of the conductor member 26d. The conductor member 26d has four holes 24d with openings on each of its four sides. For ease of understanding, in FIG. 5B, the hole 24d included in the conductor member 26d is shown by a broken line. Unlike the first embodiment, when the resin merging point is in the vicinity of any one of the four side surfaces of the conductor member 26d, air bubbles generated at the resin merging point sufficiently flow into the hole 24a. May not. On the other hand, in this embodiment, since the conductor member 26d has a hole 24d having an opening on the side surface thereof, air bubbles generated at the confluence of the resins sufficiently flow into the hole 24d. Therefore, also in this embodiment, it is possible to suppress the generation of bubbles in the vicinity of the semiconductor element 30. Further, since the hole 24d is formed in the conductor member 26d, the heat dissipation of the semiconductor device 10 can be relatively maintained.

(第5実施例)
続いて、図5を参照して、第5実施例を説明する。第5実施例では、積層体12が導体部材26bに代えて導体部材26eを備える点が、第2実施例とは異なる。図5(c)は、導体部材26eの上面図を示す。導体部材26eは、その1つの側面から当該一つの側面に対向する側面まで貫通している2個の穴24eを有する。理解の容易化のために、図5(b)では、導体部材26eが有する穴24eを破線で示している。第2実施例とは異なり、樹脂の合流予定箇所が、導体部材26eの4つの側面のうちのいずれかの近傍である場合には、樹脂の合流箇所で生じた気泡が穴24bに十分に流入しない可能性がある。これに対し、本実施例では、導体部材26eがその側面に開口を有する穴24eを有するので、樹脂の合流箇所で生じた気泡が穴24eに十分に流入する。従って、本実施例においても、半導体素子30近傍に気泡が生じることを抑制することができる。また、穴24eが導体部材26eに形成されるので、半導体装置10の放熱性を比較的に維持することができる。
(Fifth Example)
Subsequently, a fifth embodiment will be described with reference to FIG. The fifth embodiment is different from the second embodiment in that the laminated body 12 includes the conductor member 26e instead of the conductor member 26b. FIG. 5C shows a top view of the conductor member 26e. The conductor member 26e has two holes 24e that penetrate from one side surface to the side surface facing the one side surface. For ease of understanding, in FIG. 5B, the hole 24e included in the conductor member 26e is shown by a broken line. Unlike the second embodiment, when the resin merging point is in the vicinity of any one of the four side surfaces of the conductor member 26e, air bubbles generated at the resin merging point sufficiently flow into the hole 24b. May not. On the other hand, in this embodiment, since the conductor member 26e has a hole 24e having an opening on the side surface thereof, air bubbles generated at the confluence of the resins sufficiently flow into the hole 24e. Therefore, also in this embodiment, it is possible to suppress the generation of bubbles in the vicinity of the semiconductor element 30. Further, since the hole 24e is formed in the conductor member 26e, the heat dissipation of the semiconductor device 10 can be relatively maintained.

(第6実施例)
続いて、図6を参照して、第6実施例を説明する。第6実施例では、積層体12が導体部材26aに代えて導体部材26fを備える点が、第1実施例とは異なる。従って、以下では、第1実施例とは異なる点のみを説明し、その他の説明は省略する。図6は、本実施例の半導体装置10の断面図を示す。導体部材26fは、その上面に形成された溝24fを有する。溝24fは、導体部材26fの側面に開口を有する。溝24fは、導体部材26fの上面に接しているはんだ層22のはんだが溝24fに流入しないよう、その表面に凹凸が形成されている。当該凹凸は、例えば、めっき剥ぎ、めっき処理、表面粗化等によって形成される。本実施例では、積層体12を樹脂で封止する工程において、溝24fの開口が樹脂の合流予定箇所に位置するように、積層体12を金型60内に配置する。これにより、樹脂の合流箇所において生じた気泡70は、合流予定箇所に位置する溝24fに流入する。従って、本実施例においても、半導体素子30近傍に気泡が生じることを抑制することができる。また、溝24fが導体部材26fに形成されるので、半導体装置10の放熱性を比較的に維持することができる。
(6th Example)
Subsequently, a sixth embodiment will be described with reference to FIG. The sixth embodiment is different from the first embodiment in that the laminated body 12 includes the conductor member 26f instead of the conductor member 26a. Therefore, in the following, only the points different from those of the first embodiment will be described, and other explanations will be omitted. FIG. 6 shows a cross-sectional view of the semiconductor device 10 of this embodiment. The conductor member 26f has a groove 24f formed on its upper surface. The groove 24f has an opening on the side surface of the conductor member 26f. The groove 24f is formed with irregularities on its surface so that the solder of the solder layer 22 in contact with the upper surface of the conductor member 26f does not flow into the groove 24f. The unevenness is formed by, for example, stripping of plating, plating treatment, surface roughening, or the like. In this embodiment, in the step of sealing the laminated body 12 with the resin, the laminated body 12 is arranged in the mold 60 so that the opening of the groove 24f is located at the planned merging point of the resin. As a result, the bubbles 70 generated at the confluence of the resins flow into the groove 24f located at the confluence. Therefore, also in this embodiment, it is possible to suppress the generation of bubbles in the vicinity of the semiconductor element 30. Further, since the groove 24f is formed in the conductor member 26f, the heat dissipation of the semiconductor device 10 can be relatively maintained.

(第7実施例)
続いて、図7を参照して、第7実施例を説明する。第7実施例では、積層体12が上面側放熱板20、導体部材26aに代えて上面側放熱板21を備える点が、第1実施例とは異なる。従って、以下では、第1実施例とは異なる点のみを説明し、その他の説明は省略する。図7は、本実施例の半導体装置10の断面図を示す。上面側放熱板21は、その下面に凸部21aを有する。
(7th Example)
Subsequently, a seventh embodiment will be described with reference to FIG. 7. The seventh embodiment is different from the first embodiment in that the laminated body 12 includes the upper surface side heat sink 21 instead of the upper surface side heat sink 20 and the conductor member 26a. Therefore, in the following, only the points different from those of the first embodiment will be described, and other explanations will be omitted. FIG. 7 shows a cross-sectional view of the semiconductor device 10 of this embodiment. The upper surface side heat sink 21 has a convex portion 21a on the lower surface thereof.

凸部21aは、例えば銅、又はその他の金属といった導電性を有する材料を用いて、上面側放熱板21と一体的に構成されている。凸部21aは、上面と、上面とは反対側に位置する下面と、積層体12の積層方向に沿って延びる4つの側面を有する。凸部21aは、モールド樹脂36内に位置している。凸部21aの上面は、上面側放熱板21の下面に接合されている。また、凸部21aの下面は、半導体素子30の上面と、はんだ層28によって接合されている。これにより、半導体素子30は、凸部21aを介して上面側放熱板21に電気的、熱的に接続されている。また、凸部21aは、四つ角のそれぞれに開口を有する4個の穴24gを有する。穴24gは、開口から凸部21aの中心付近まで延びており、凸部21aを貫通していない。 The convex portion 21a is integrally configured with the upper surface side heat sink 21 by using a conductive material such as copper or other metal. The convex portion 21a has an upper surface, a lower surface located on the side opposite to the upper surface, and four side surfaces extending along the stacking direction of the laminated body 12. The convex portion 21a is located in the mold resin 36. The upper surface of the convex portion 21a is joined to the lower surface of the heat sink 21 on the upper surface side. Further, the lower surface of the convex portion 21a is joined to the upper surface of the semiconductor element 30 by a solder layer 28. As a result, the semiconductor element 30 is electrically and thermally connected to the heat radiating plate 21 on the upper surface side via the convex portion 21a. Further, the convex portion 21a has four holes 24g having openings in each of the four corners. The hole 24g extends from the opening to the vicinity of the center of the convex portion 21a and does not penetrate the convex portion 21a.

本実施例では、積層体12を樹脂で封止する工程において、少なくとも1個の穴24gの開口が樹脂の合流予定箇所に位置するように、積層体12を金型60内に配置する。これにより、樹脂の合流箇所において生じた気泡70は、合流予定箇所に位置する穴24gに流入する。従って、本実施例においても、半導体素子30近傍に気泡が生じることを抑制することができる。また、穴24gが、上面側放熱板21の放熱面とは異なる凸部21aに形成されるので、半導体装置10の放熱性を比較的に維持することができる。 In this embodiment, in the step of sealing the laminated body 12 with the resin, the laminated body 12 is arranged in the mold 60 so that the opening of at least one hole 24 g is located at the planned merging point of the resin. As a result, the bubbles 70 generated at the confluence of the resins flow into the hole 24g located at the confluence. Therefore, also in this embodiment, it is possible to suppress the generation of bubbles in the vicinity of the semiconductor element 30. Further, since the hole 24g is formed in the convex portion 21a different from the heat radiating surface of the upper surface side heat radiating plate 21, the heat radiating property of the semiconductor device 10 can be relatively maintained.

以上、いくつかの具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。本明細書又は図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものである。 Although some specific examples have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples exemplified above. The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations.

10:半導体装置
12:積層体
20,21:上面側放熱板
21a:凸部
22,28,32:はんだ層
24a,24b,24c,24d,24e,24g:穴
24f:溝
26a,26b,26c,26d,26e,26f,26g:導体部材
30:半導体素子
34:下面側放熱板
36:モールド樹脂
60:金型
62:ゲート
70,80:気泡
10: Semiconductor device 12: Laminated body 20, 21: Top surface side heat sink 21a: Convex portion 22, 28, 32: Solder layer 24a, 24b, 24c, 24d, 24e, 24g: Hole 24f: Groove 26a, 26b, 26c, 26d, 26e, 26f, 26g: Conductor member 30: Semiconductor element 34: Bottom side heat sink 36: Mold resin 60: Mold 62: Gate 70, 80: Bubbles

Claims (1)

半導体装置の製造方法であって、
半導体素子と前記半導体素子に接合された導体部材を有する積層体を準備する工程と、
前記積層体を金型内に配置するとともに、前記金型内に樹脂を注入することによって、前記積層体を前記樹脂で封止する工程と、を備え、
前記導体部材には、前記積層体の積層方向に沿って延びる周側面に開口を有するとともに前記開口から前記導体部材の中心部分に向けて延びる穴が、封止後の前記樹脂から露出しない位置に形成されており、
前記封止する工程では、前記導体部材の前記穴の前記開口が、前記積層体を二方向から回り込んで合流する前記樹脂の合流予定箇所に位置するように、前記積層体を前記金型内に配置する、製造方法。
It is a manufacturing method of semiconductor devices.
A step of preparing a laminate having a semiconductor element and a conductor member bonded to the semiconductor element, and
A step of arranging the laminate in a mold and injecting a resin into the mold to seal the laminate with the resin is provided.
The conductor member has an opening on the peripheral side surface extending along the stacking direction of the laminated body, and a hole extending from the opening toward the central portion of the conductor member is located at a position not exposed from the resin after sealing. Is formed and
In the sealing step, the laminated body is placed in the mold so that the opening of the hole of the conductor member is located at a planned merging point of the resin that wraps around the laminated body from two directions and merges. Place in the manufacturing method.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010267850A (en) 2009-05-15 2010-11-25 Mitsui High Tec Inc Semiconductor device and manufacturing method of semiconductor device
JP2015126057A (en) 2013-12-26 2015-07-06 トヨタ自動車株式会社 Manufacturing method of semiconductor module
JP2016134591A (en) 2015-01-22 2016-07-25 株式会社デンソー Manufacturing method of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010267850A (en) 2009-05-15 2010-11-25 Mitsui High Tec Inc Semiconductor device and manufacturing method of semiconductor device
JP2015126057A (en) 2013-12-26 2015-07-06 トヨタ自動車株式会社 Manufacturing method of semiconductor module
JP2016134591A (en) 2015-01-22 2016-07-25 株式会社デンソー Manufacturing method of semiconductor device

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