JP6998419B2 - Control program - Google Patents

Description

The present invention relates to an information processing apparatus, a program, and a recording medium having a function of operating a virtual machine across a plurality of different hypervisors.

In recent years, computer architecture virtualization technology has attracted attention in various fields. Virtualization technology is a technology that abstracts computer resources and treats computer hardware as virtual. A virtual machine (virtual machine: VM) is known as one of the virtualization technologies of computer architecture.

A virtual machine refers to software that emulates the behavior of a computer or the emulated virtual computer itself. By introducing the concept of a virtual machine, it is possible to operate multiple OSs (operating systems) on one computer. Then, when operating a plurality of OSs on one computer, there is a control program that controls those OSs. This is the hypervisor.

By running the hypervisor on the server, it is possible to run multiple virtual machines (ie, multiple kernels). This makes it possible to operate different OSs (called guest OSs) on a single server. Then, it is possible to provide the user with various interfaces depending on each OS.

By the way, conventionally, the hypervisor operates for each server and cannot cooperate with other hypervisors operating on other servers. For example, as shown in FIG. 14, it is assumed that a plurality of OSs 12 to 14 are operating under the control of a hypervisor 11 operating on a certain server. At this time, each OS 12 to 14 is actually processed by the CPU (central processing unit) (not shown) in the hypervisor 11, and can only access the memory (not shown) in the hypervisor 11. That is, the hypervisor 11 can use only the resources existing in the server on which it operates.

Similarly, it is assumed that another OS 15 is operating under the control of another hypervisor 22 operating on another server. As mentioned above, since resources cannot be shared between hypervisors, different hypervisors 11 and 22 can only control OSs 12 to 15 independently, and one OS straddles the hypervisors. (Virtual machine) could not be operated.

As a result, when it is necessary to improve the server performance or when it is necessary to secure redundancy to deal with server troubles, the only effective countermeasure is to increase the degree of parallelism of the server and deal with it (scale out). There was a problem that software development cost and operation cost became high.

In order to deal with such a problem, in recent years, as a parallel processing technology of a computer, a technology of sharing a memory between physically separated CPUs has been developed. For example, in Patent Document 1, the hypervisor detects the arrangement relationship between the local memory, the remote memory, and the CPU, and the memory that becomes the remote memory when viewed from the CPU allocated to the virtual machine is viewed from the CPU. A technique for moving necessary data to a memory that becomes a local memory is described.

Further, Patent Document 2 describes a process of performing address translation using a memory table in a blade server and accessing a memory on another blade. That is, a technique for making a blade server function as an SMP (Symmetric Multiple Processor) server is described.

Japanese Unexamined Patent Publication No. 2011-238278 Japanese Unexamined Patent Publication No. 2012-11604

However, the techniques described in Patent Documents 1 and 2 do not integrate and control virtual machines under the control of different hypervisors, but are merely distributed to CPUs under the control of different hypervisors. It is intended to perform processing. Therefore, although the processing load of each CPU can be reduced, it is necessary to perform communication for synchronizing the processing results with each other, and the overhead caused by the communication processing is a factor that hinders the processing efficiency of the entire system as a result. It was also accompanied.

Further, when the CPU is to perform distributed processing, for example, even if an additional CPU is newly required to operate a certain virtual machine, a server equipped with 16 CPUs as an expansion unit. In some cases, it may be necessary to procure extra hardware resources in excess of the required resources, such as the need to prepare separately.

The present invention was created to overcome such obstacles, and is an information processing device, program, and storage that enables integrated control of multiple virtual machines under the control of different hypervisors. It provides a medium.

The information processing apparatus according to the embodiment of the present invention has an address of a memory managed by a first hypervisor, an address of a memory managed by a second hypervisor connected to the first hypervisor, and the second hyper. It includes an address management table that records an identifier that identifies a visor, and a issuing unit that refers to the address management table and issues instructions and control information from the first hypervisor to the second hypervisor. The control information is information indicating the state of the logic processor operating in the second hypervisor.

In the information processing apparatus according to the embodiment of the present invention, the address of the virtual memory space managed by the first hypervisor, the identifier that identifies the second hypervisor different from the first hypervisor, and the second hypervisor. An address management table that stores the addresses of the memory managed by the hypervisor in association with each other, and control information storage that stores control information indicating the state of the logical processor operating in the first hypervisor or the second hypervisor. The first hypervisor can send and receive the control information to and from the second hypervisor, and the address of the virtual memory space can be referred to with reference to the address management table. The address of the memory managed by the second hypervisor associated with is accessible.

The control information may be at least one of a register value indicating the state of the logical processor, a program counter value, and a pointer to a memory.

The first hypervisor and the second hypervisor may be connected by a general-purpose network in which a destination can be specified by an identifier.

The first hypervisor has the second hypervisor when the processing target data does not exist in the memory managed by the first hypervisor and the processing target data exists in the memory managed by the second hypervisor. The control information may be transmitted to the visor.

The control information includes the first hypervisor and the second hypervisor according to the usage status of the resource managed by the first hypervisor or the usage status of the resource managed by the second hypervisor. May be sent and received between. In particular, it is preferable that the control information is transmitted to the hypervisor that manages the resource having a surplus in the usage status.

Along with sending and receiving the control information, it is preferable to send and receive data related to the control information (for example, data having a high reference frequency such as data cached by a logical processor).

According to the present invention, a plurality of CPUs under the control of different hypervisors can be integrated and controlled, and higher processing performance can be realized.

In addition, it is possible to improve the inefficiency of having to procure extra resources required for desired processing and perform distributed processing, and to realize higher utilization efficiency of hardware resources.

It is a block diagram which shows the information processing system which concerns on 1st Embodiment of this invention. It is a block diagram which shows the information processing apparatus which concerns on 1st Embodiment of this invention. It is a conceptual diagram which shows the principle in the information processing system of 1st Embodiment of this invention. It is a figure explaining the role of the control information implemented in the information processing system which concerns on 1st Embodiment of this invention. It is a figure explaining the procedure of establishment of connection in the information processing system which concerns on 1st Embodiment of this invention. It is a figure explaining the role of the address management table implemented in the information processing system which concerns on 1st Embodiment of this invention. It is a figure which shows the comparison between the information processing system which concerns on 1st Embodiment of this invention, and the conventional information processing system. It is a figure which shows the comparison between the information processing system which concerns on 1st Embodiment of this invention, and the conventional information processing system. It is a block diagram which shows the information processing system which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the information processing system which concerns on 3rd Embodiment of this invention. It is a block diagram which shows the information processing system which concerns on 4th Embodiment of this invention. It is a block diagram which shows the information processing system which concerns on 5th Embodiment of this invention. It is a figure which shows the structure of the address management table implemented in the information processing system which concerns on 6th Embodiment of this invention. It is a block diagram which shows the conventional information processing system.

Hereinafter, the mobile terminal according to the embodiment of the present invention will be described in detail with reference to the drawings. The embodiments shown below are examples of the embodiments of the present invention, and the present invention is not limited to these embodiments. In the drawings referred to in the present embodiment, the same part or a part having a similar function is given the same code or a similar code (a code in which A, B, etc. are simply added after the numbers), and the process is repeated. The explanation of may be omitted. Further, the dimensional ratio of the drawing may differ from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

(First Embodiment)
<System configuration>
FIG. 1 is a configuration diagram showing an information processing system 100 according to the first embodiment of the present invention. In FIG. 1, 101 is a general-purpose network, and information processing devices 102 to 107 are connected via the general-purpose network. Here, the general-purpose network refers to a network whose destination can be specified by using an identifier, and refers to, for example, the Internet, LAN (Local Area Network), and WAN (Wide Area Network).

The information processing devices 102 to 107 can communicate with each other via the network 101 according to a predetermined protocol. The protocol differs depending on the general-purpose network, but in the information processing system according to the first embodiment, the information processing devices 102 to 107 do not need to be connected by the same general-purpose network. For example, the information processing device 102 and information processing are processed. The general-purpose network connecting the device 105 and the general-purpose network connecting the information processing device 105 and the information processing device 106 may be different.

FIG. 2 is a block diagram showing an information processing apparatus 200 according to the first embodiment of the present invention. The information processing devices 102 to 107 in FIG. 1 all have the same configuration as the information processing device 200.

In FIG. 2, 201 is a multi-core processor, which includes two CPU cores 202a and 202b. Each CPU core 202a and 202b has a built-in memory management unit (MMU) 203a and 203b, respectively. Although the multi-core processor is illustrated in FIG. 2, it may be a single-core processor or a multi-processor provided with a plurality of processors.

The memory management units 203a and 203b hold the address management tables 204a and 204b, respectively. The address management table associates an address that specifies a storage area of virtual memory space (hereinafter referred to as "virtual address") with an address that specifies a storage area of memory as a hardware resource (hereinafter referred to as "physical address"). It is a table for. In the information processing system of the first embodiment, a table different from the conventional address management table is used in that an identifier (a network address such as a MAC address) that specifies another information processing device is stored together with the physical address. Details will be described later.

Reference numeral 205 is a bus, which is a communication path connecting the multi-core processor 201 and each element described later. Reference numeral 206 is a RAM (Random Access Memory), which includes a work area 207 and a system memory area 208 used by the multi-core processor 201. The information processing apparatus 200 of the first embodiment holds control information 209 indicating the state (status) of the logical processor operating on the hypervisor in the system memory area 208. That is, the system memory area 208 corresponds to the "control information storage unit" of the present invention. There are as many control information 209s as there are logical processors operating on the hypervisor.

As such control information 209, VMCS (Virtual Machine Control Structure) used in the virtualization support function of Intel Corporation and VMCB (Virtual Machine Control Block) used in the virtualization support function of AMD are known. , Any control information may be used as long as it is information indicating the state of the logical processor (for example, at least one of a register value indicating the state of the logical processor, a program counter value, and a pointer to a memory). The operation using the control information 209 will be described later.

In FIG. 2, 210 is a ROM (Read Only Memory), and various programs such as BIOS are stored. Reference numeral 211 is an input / output unit (I / O unit) for input / output of various data. Reference numeral 212 denotes a communication unit, which communicates with other information processing devices via the general-purpose network 101 of FIG. The communication method may be a wireless method or a wired method, and may be provided with a mechanism for short-range wireless communication. Reference numeral 213 is a storage functioning as a database, and a large-capacity storage medium such as a hard disk can be used. Of course, other recording media may be used, or data may be held by using cloud computing without having a unique storage.

<Principle of system>
FIG. 3 is a conceptual diagram showing a principle in the information processing system of the first embodiment. Each of 301a to 301f is a hypervisor executed by a control unit (specifically, a multi-core processor) of an information processing apparatus. That is, by executing the hypervisor in each of the information processing devices shown in FIGS. 1 and 2, a plurality of hypervisors 301a to 301f are connected to each other via a general-purpose network to construct an information processing system.

302a to 302i are virtual machines (referred to as OS here) that operate on the hypervisor. The major difference from the conventional example shown in FIG. 14 is that in the information processing system of the first embodiment, the virtual machine operates across each hypervisor. For example, in FIG. 3, the OS 302c operates across four hypervisors 301a to 301d, and each hypervisor cooperates to operate one virtual machine.

As described above, in the information processing system of the first embodiment, the OS 302a to 302i operate seamlessly between the hypervisors 301a to 301f, and each hypervisor is a hardware resource (hardware resource) such as a CPU core and a memory. , Or just resources). That is, an information processing system is constructed in which hypervisors 301a to 301f cooperate with each other to share each other's hardware resources and enable dynamic scale-up of virtual machines.

Next, a specific implementation method for constructing such an information processing system will be described. FIG. 4 is a diagram illustrating a role of control information mounted on an information processing apparatus for constructing an information processing system according to the first embodiment. Here, a logical processor is shown transitioning between hypervisors.

In FIG. 4, 401a and 401b are hypervisors, respectively. Each hypervisor 401a and 401b has memories 402a and 402b, respectively, and holds various data. The memory 402a is a hardware resource provided in the information processing device executing the hypervisor 401a, and the memory 402b is a hardware resource provided in the information processing device executing the hypervisor 401b.

In the hypervisor 401a, three logic processors 403a to 403c are currently operating, and one new logic processor is about to be added. In the hypervisor 401b, two logic processors 403d and 403e are currently operating. Reference numeral 403f indicates a logic processor that has been operating for a time t before the time point in FIG.

Each of the logical processors 403a to 403e holds the control information 404a to 404e in the system memory area, respectively. Then, as shown in FIG. 4, the control information 404f indicating the state of the logic processor 403f that was operating before the time t in FIG. 4 is in the transition process from the hypervisor 401b to the hypervisor 401a. As described above, the control information 404f is transmitted via the general-purpose network. Then, in the hypervisor 401a, the logic processor 403f can be restarted based on the received control information 404f.

As described above, in the information processing system 100 of the first embodiment, the control information 404 is transmitted and received across the physical barrier between the hypervisors, so that the logic processor 403 is operated without depending on the hypervisor. As a result, the virtual machine (OS) 405 can be operated so as to straddle the hypervisors 401a and 401b.

Regarding which CPU of the hypervisor 401a processes the control information 404f, it is desirable to arbitrate between the hypervisor 401a and 401b in advance before transmitting the control information 404f. For example, the CPU of a hypervisor that lacks resources broadcasts a request instruction to search for a hypervisor that has surplus resources on the network, or sends it to a server that manages resource usage. , There may be a process of obtaining a transmission destination of control information.

Once the destination of the control information is determined, an instruction requesting permission to use the resource may be sent to the hypervisor for prior confirmation. Then, when the arbitration is completed, the control information is transmitted to the hypervisor that has given permission to use the resource, so that the resource of the hypervisor that has received the control information can be used. Such arbitration is performed by the CPU under the control of each hypervisor, and the CPU in this case corresponds to the "issuer" of the present invention.

For transmission / reception of control information via a general-purpose network, an appropriate protocol may be selected according to the network to be used. For example, FIG. 5 shows a case where an IP network is used as a general-purpose network and TCP / IP is used as a protocol.

As shown in FIG. 5, in the TCP protocol, a “3-way handshake” establishes a connection between the hypervisor 401a and the hypervisor 401b. After that, the control information 404f and the data 406 are transmitted from the hypervisor 401b to the hypervisor 401a. Further, after that, the control information 501 and the data 502 may be transmitted from the hypervisor 401a to the hypervisor 401b.

As described above, when the logical processor 403 is transitioned from the hypervisor 401b to the hypervisor 401a, the data cached in the logical processor (for example, the data stored in the L1 to L3 caches of the logical processor) and the logical processor are used. It is preferable that the frequently referenced data 406, such as the stack data of the process in charge of the executed CPU, is also transitioned together with the control information 404. As a result, even if the logical processor 403 makes a transition between hypervisors, the data 406 with a high reference frequency also makes a transition, so that processing can be continuously executed. Such frequently referred data 406 is data related to a logical processor that refers to the data 406, in other words, data related to control information indicating the state of the logical processor.

The address management table may be referred to in order to transmit the frequently referred data 406. For example, the hypervisor 401b can specify the data necessary for transmission by referring to its own address management table, read it from the memory under its control, and transmit it.

Further, as shown in FIG. 4, when the logic processor 403f processed by the hypervisor 401b transitions to the hypervisor 401a, most of the data processed before the transition is stored in the memory 402b. There is. Therefore, if the process is continued after the transition to the hypervisor 401a, it becomes necessary to refer to the memory 402b.

Therefore, the information processing system 100 of the first embodiment implements specific means for enabling each hypervisor to access the memory under the control of the other hypervisor via the general-purpose network. FIG. 6 is a diagram illustrating the role of the address management table mounted on the information processing apparatus for constructing the information processing system according to the first embodiment.

FIG. 6 shows the state after the transition of the logic processor 403f described with reference to FIG. 601 is an address management table, which is the same as the address management tables 204a and 204b shown in FIG. The address management table 601 is for associating a virtual address that specifies a storage area of a virtual memory space managed by OS405 with a physical address that specifies a storage area of an actual memory space (memory space composed of memories 402a and 402b). It is a table of.

The physical address of the address management table 601 includes two types of physical addresses. The first physical address specifies the physical address of the memory 402a provided in the information processing device (hypervisor 401a) in which the address management table 601 is stored (“55”, “56”, “57” in FIG. 6). , Etc.), and the second physical address specifies the physical address of the memory 402b provided in another information processing device (hypervisor 401b) (“identifier +81”, “identifier +83”, etc. in FIG. 6). ).

Here, the second physical address not only simply specifies the physical address, but also stores an identifier (network address) that designates another information processing device on the network. In the first embodiment, the expression is expressed as "identifier +81", but the present invention is not limited to this, and any embodiment may be used as long as the identifier and the physical address are combined. As the identifier, an identifier corresponding to the protocol of the general-purpose network connecting the hypervisors may be used. For example, a "MAC address", an "IP address", or the like can be used.

In order to reduce the overhead in memory reference between hypervisors over a general purpose network as shown in FIG. 6, it is desirable to use a general purpose network with low latency and wide bandwidth. For example, "infiniBand", "Converged Enhanced Ethernet (registered trademark)", and "Serial RapidIO" can be used. However, it is possible to select a general-purpose network in the right place according to the environment, budget, etc. to be used. For example, use "IP network" when importance is placed on low cost rather than low latency. , There are no particular restrictions on the general-purpose networks that can be used.

As described above, the information processing apparatus 200 that constructs the information processing system 100 of the first embodiment can transfer the logic processor between the hypervisors by transmitting and receiving the control information of each logic processor between the hypervisors. , One virtual machine (OS) can be operated across the hypervisors.

Further, by providing the address management table shown in FIG. 6 in the CPU under the control of each hypervisor, it is possible to refer to the memory between different hypervisors via a general-purpose network, and the hypervisor is physically isolated. It is possible to operate a virtual machine that straddles between hypervisors without being aware of. As a result, a plurality of CPUs under the control of different hypervisors can be integrated and controlled, and higher processing performance can be realized.

For example, in the past, in order to improve the performance of an application, it was necessary to adopt a scale-out approach as shown in FIG. 7 (a). That is, when the virtual machines (OS) 702a to 702d are independently operated in the plurality of hypervisors 701a to 701d and the performance of the application is improved, the number of the virtual machines, that is, the number of hypervisors is increased. I have responded by that.

However, in this case, for example, the virtual machine 701a is made to function as a control tower (host) and the virtual machines 702a to 702d are made to function as a processing node (slave) to perform application processing. It is necessary to perform requests and responses, data synchronization, processing timing adjustment, etc., and there is a problem that a lot of man-hours and high technical ability are required for development.

On the other hand, in the information processing system 100 of the first embodiment, as shown in FIG. 7B, a scale-up approach of operating the virtual machine 702a across the hypervisors 701a to 701d can be adopted. .. Therefore, it is possible to easily improve the application performance only by developing the program while paying attention only to multithreading without being aware of the overhead associated with network communication.

Further, by transitioning the logical processor to a hypervisor having a sufficient resource (for example, CPU core or memory), the resource of each hypervisor can be used efficiently. That is, the information processing system can be efficiently used by dynamically transitioning the logical processor (transitioning the control information) according to the resource usage status of each hypervisor.

For example, as shown in FIG. 7A, it is assumed that the virtual machine (OS1) 702a is operating in the hypervisor 701a and the CPU core 703a is insufficient. On the other hand, it is assumed that the virtual machine (OS2) 702b is operating in the hypervisor 701b and one of the CPU cores 703b is left over.

In this case, as shown in FIG. 7B, by expanding the virtual machine 702a operating on the hypervisor 701a to the hypervisor 701b, the surplus CPU core of the hypervisor 701b is allocated to the virtual machine 702a. Is possible. Therefore, it is possible to improve the inefficiency of having to procure extra resources required for desired processing and perform distributed processing, and to realize higher utilization efficiency of hardware resources.

In addition, it is assumed that the virtual machine (OS1) 702a is operating in the hypervisor 701a, and the memory (not shown) in the information processing device in which the hypervisor 701a is operating is insufficient. On the other hand, it is assumed that there is a free area in the memory in the information processing apparatus in which the hypervisor 701b operates, and there is a margin in the capacity.

In this case, by extending the virtual machine 702a operating on the hypervisor 701a to the hypervisor 701b, it is possible to allocate the free memory area managed by the hypervisor 701b to the virtual machine 702a.

(Second Embodiment)
The information processing system 900 of the second embodiment of the present invention will be described with reference to FIG. The information processing system 900 of the second embodiment adds a function of layering the CPU performance to be used inside one virtual machine to the information processing system 100 of the first embodiment.

Conventionally, only CPUs with the same performance can be used in one virtual machine, and for high-level processing, a virtual machine with appropriate processing power is operated, a backup virtual machine is operated, and so on. , I had to decide the processing level (processing amount) for each virtual machine. Therefore, it has been difficult to flexibly respond to a situation where the required processing changes dynamically.

However, the information processing system 900 of the second embodiment takes advantage of the fact that the virtual machine 903 can be operated across a plurality of different hypervisors, and has the CPU performance to be used according to the required processing level. It is characterized by changes that dynamically change the allocation.

In FIG. 9, the hypervisor 901a operates on an information processing device equipped with a CPU having the first performance (hereinafter referred to as “high-performance CPU”) 902a, and the hypervisor 901b is a CPU having the second performance. The hypervisor 901c is an information processing unit equipped with a CPU having a third performance (hereinafter referred to as a "low performance CPU") 902c, which operates on an information processing device equipped with a 902b (hereinafter referred to as a "medium performance CPU"). Operate. Here, the first performance is the highest, followed by the second performance, the third performance, and so on.

It should be noted that the high-performance CPU does not mean the absolute performance, but is merely a relative comparison of each CPU. That is, the CPU may have any performance as long as the relationship of first performance> second performance> third performance is satisfied.

Therefore, since the hypervisor 901a is equipped with a high-performance CPU 902a, it is possible to perform processing at a relatively higher level than the other hypervisors 901b and 901c. On the contrary, since the hypervisor 901a is equipped with a low-performance CPU 902c, it can perform processing at a relatively lower level than the other hypervisors 901a and 901b.

However, even when the low-performance CPU 902c is used, the processing capacity increases as the number of allocations increases. Therefore, even if the high-performance CPU 902a is allocated to another virtual machine and is in short supply, as shown in FIG. 9, for example, one high-performance CPU 902a is provided for one virtual machine 903. By allocating two medium-performance CPUs 902b and three low-performance CPUs 902c, it is possible to handle the required processing. Of course, if the high-performance CPU 902a becomes available, it is possible to dynamically change the allocation such as two high-performance CPUs and one medium-performance CPU to continue processing.

As described above, the information processing system 900 of the second embodiment constantly monitors the usage status of the CPUs 902a to 902c managed by the hypervisors 901a to 901c, and responds to the required processing level inside the virtual machine 903. Therefore, appropriate CPU allocation can be dynamically executed, and CPU performance can be teared (layered). Further, by allocating the minimum CPU performance, it is possible to further improve the efficiency of using the hardware resources managed by the hypervisors 901a to 901c.

(Third Embodiment)
The information processing system 1000 of the third embodiment of the present invention will be described with reference to FIG.
The information processing system 1000 of the third embodiment has a failover function added to the information processing system 100 of the first embodiment.

Conventionally, in order to realize a non-stop fail server when an information processing device used as a server or the like fails, as shown in FIG. 10 (a), a hypervisor for backup is a copy of the entire state of the hypervisor 1001a. It was necessary to provide 1001b. In this case, there is a problem that the cost for preparing the hypervisor 1001b and the network bandwidth for copying the entire hypervisor are consumed, which is not economical.

However, in the information processing system 1000 of the third embodiment, taking advantage of the fact that the memory can be shared between a plurality of different hypervisors, the parity data of the memory managed by each hypervisor can be transferred to another hypervisor. It is characterized by storing it in a memory managed by the information processing device (hypervisor) and using parity data to realize non-disruptive failover in the event of a failure of the information processing device (hypervisor).

In FIG. 10B, virtual machines 1002a and 1002b are operating on the hypervisor 1001a, and each of the virtual machines 1002a and 1002b occupies a predetermined memory area in the memory managed by the hypervisor 1001a, respectively. There is. On the other hand, in the hypervisor 1001b, in addition to the virtual machine 1002c, a memory area 1003 for storing parity data is secured. The virtual machine 1002c occupies a predetermined memory area in the memory managed by the hypervisor 1001b.

Then, all the parity data of the memory used by each virtual machine 1002a to 1002c is stored in the memory area 1003. As a result, even if the hypervisor 1001a is stopped due to some kind of failure, the virtual machines 1002a and 1002b can be repaired by another hypervisor using the parity data stored in the memory area 1003, and non-disruptive failover can be performed. It can be realized.

Here, the configuration is such that all the parity data of the memory area used by each virtual machine 1002a to 1002c is stored in the memory area 1003, but the parity data is distributed to the memories managed by a plurality of different hypervisors. Is also possible.

As described above, in the information processing system 1000 of the second embodiment, it is possible to add the failover function only in the memory area and the network bandwidth of the capacity of the parity data. This makes it possible to realize failover with excellent redundancy with a small number of information processing devices.

(Fourth Embodiment)
The information processing system 1100 according to the fourth embodiment of the present invention will be described with reference to FIG.
The information processing system 1100 of the fourth embodiment is characterized in that the processing of data stored in the memory managed by a specific hypervisor can be outsourced to another hypervisor. For example, there may be a case where a country that cannot take data out of the country due to various circumstances outsources only the processing using the data to another country.

In FIG. 11, the hypervisor 1101a located in country A manages the memory 1102a. Then, it is assumed that the data stored in the memory 1102a is prohibited from being taken out of the country due to the circumstances peculiar to country A.

On the other hand, the hypervisor 1101b located in country B manages the memory 1102b. Then, it is assumed that Country B provides outsourcing to hypervisors of other countries by using the information processing system according to the present invention.

In the information processing system 1100 of the fourth embodiment, the virtual machine (OS) 1103 on the hypervisor 1101a in country A operates a plurality of logical processors 1104a to 1104c to perform processing, and if necessary, for example, in country A. When the hardware resources (CPU core, etc.) are insufficient in computing power, as shown in FIG. 11, the control information 1105 and the cache data 1106 of a certain logical processor 1104c are transmitted to the hypervisor 1101b of country B via a general-purpose network. To transition to. Of course, other data with high reference frequency may be included in addition to the cache data.

As a result, the virtual machine 1103 can be operated across the hypervisor 1101a of country A and the hypervisor 1101b of country B, and the hypervisor 1101a of country A utilizes the hardware resources of country B. Can be done. In other words, country B allows country B to specify the hypervisor 1101b of country B as the destination of the control information of the logical processor 1104 operating on the hypervisor 1101a of country A, thereby allowing the hypervisor of country B to be specified. It enables outsourcing of visors (or hardware resources).

In order to construct the information processing system 1100 of the fourth embodiment, the hypervisor 1101a of country A may specify only the hypervisor 1101b of country B as the transmission destination of the control information of the logical processor 1104. desirable. This is because if the destination is not explicitly determined, control information may be transmitted to a hypervisor other than country B.

Further, it is desirable that both the hypervisor 1101a in country A and the hypervisor 1101b in country B specify the memory 1102a in country A as the data storage destination. This is because the processing data should not be stored in the memory 1102b of country B as long as the export of data from country A is prohibited.

Strictly speaking, data equivalent to cache data will flow from country A to country B. However, in the first place, the cache data has a very small amount of data, and the content differs depending on the processing at that time, and it is only fragmentary data with a high reference frequency. Therefore, although fragmentary data flows slightly at the time of processing, the cache data changes sequentially as the processing progresses, so unlike taking out the entire data of country A, it is practically seen from country B. It can be said that the data of country A is not acquired.

As described above, the information processing system 1100 of the fourth embodiment makes it possible to process only the data existing in the first country in the second country (other country) without substantially taking it out of the country. It is possible to utilize the hardware resources of other countries even if the hardware resources with high processing capacity do not exist in the home country.

(Fifth Embodiment)
From the first embodiment to the fourth embodiment, an example of sharing a virtual machine between two hypervisors is shown, but in the information processing system 1200 of the fifth embodiment, virtual machines are virtualized between three or more hypervisors. Here is an example of sharing a machine.

FIG. 12 is an information processing system 1200 of the fifth embodiment. The information processing system 1200 is composed of four hypervisors, hypervisors 1201a to 1201d, and each hypervisor manages the memories 1202a to 1202d. Then, the virtual machine (OS) 1203 operates across each hypervisor.

Control information 1204a to 1204d and frequently referred data (for example, cache data) 1205a to 1205d are transmitted and received between the hypervisors. As a result, each hypervisor can share the resources (hardware resources) of other hypervisors, and can dynamically provide the necessary resources to the virtual machine.

The transmission / reception sequences of the control information 1204a to 1204d may be performed simultaneously or sequentially. If the changes are made at the same time, the waiting time for processing can be reduced and the processing speed can be improved. In addition, if you go sequentially, the procedure for establishing a connection is simplified, so there is an advantage that less processing is required when extending the virtual machine to another hypervisor.

In this embodiment, an example of establishing a connection between the upper, lower, left, and right hypervisors is schematically shown, but the hypervisor 1202a and the hypervisor 1202d directly send and receive control information 1204 and frequently referred data 1205. Of course, it is possible to take such an aspect.

It is also possible to send and receive control information 1204 and frequently referred data 1205 to and from the target hypervisor via another hypervisor. For example, when the hypervisor 1202a shares the virtual machine 1203 with the hypervisor 1202d, the control information 1204 and the frequently referenced data 1205 may be transmitted and received via the hypervisor 1202b or the hypervisor 1202c.

Further, in the present embodiment, an example of sharing a virtual machine among four hypervisors is shown, but it is also possible to share a virtual machine among five or more hypervisors.

As described above, in the information processing system 1200 of the fifth embodiment, by operating the virtual machine across three or more hypervisors, the virtual machine can be shared among many hypervisors, and the application can be easily applied. It is possible to improve the scale-up type of performance.

(Sixth Embodiment)
The information processing system 1300 according to the sixth embodiment of the present invention will be described with reference to FIG.
The information processing system 1300 of the sixth embodiment has a different structure of the address management table from the information processing system 100 of the first embodiment.

In FIG. 13, the hypervisor A1301a and the hypervisor B1301b share a virtual machine (OS) 1302. The virtual machine 1302 has a unique address management table 1303 (referred to as an OS address management table), and the OS address management table 1303 is an MMU (not shown) in the CPU core that executes the hypervisor A1301a. ) Is stored.

The OS address management table 1303 has a function of converting a virtual address in the virtual memory space managed by the virtual machine 1302 into a virtual address (address in VM) allocated to each virtual machine.

Further, each hypervisor A1301a and hypervisor B1301b have hypervisor address management tables 1304a and 1304b, respectively. The hypervisor address management tables 1304a and 1304b each include a virtual machine ID (VMID), a virtual machine address (VM address), a hypervisor ID, a physical address, and an area for holding data.

The virtual machine ID is an ID (identifier) associated with the virtual machine 1302 operating on the hypervisor, and indicates which virtual machine holds the data associated with it. For example, when the virtual machine ID is "OS1", it means that each area of the line is associated with OS1.

The address in the virtual machine is an address assigned to each virtual machine, and is an address that can be referred to by the virtual machine indicated by the virtual machine ID.

The hypervisor ID is an identifier that points to the referenced hypervisor or the referencing hypervisor. For example, in the hypervisor address management table 1304a of FIG. 13, there is no effective data in the "physical address" or "data" column corresponding to the address "58" in the VM. That is, the target data does not exist in the memory managed by the hypervisor A1031a.

However, in the information processing system 1300 of the sixth embodiment, since the hypervisor ID indicates "B" as a reference destination, the hypervisor address management table 1304b stored in the hypervisor B1301b is referred to, and the VM in the table is referred to. By referring to the internal address "58", the target data "&&&" can be found at the physical address "83" of the memory managed by the hypervisor B1301b.

As described above, in the information processing system 1300 of the sixth embodiment, an address management table for a hypervisor is provided for each hypervisor, and by introducing the concept of a hypervisor ID into the management table, the hypervisor itself is used. Even when the target data does not exist, it is possible to easily refer to the memory of another hypervisor.

Then, if the target data exists in the memory in its own hypervisor, the corresponding physical address is referred to in the hypervisor address management table, and the target data exists in the memory in its own hypervisor. Otherwise, the hypervisor ID can be used to refer to the corresponding physical address in another hypervisor address management table.

100: Information processing system, 101 ... General-purpose network, 102 to 107 ... Information processing device, 301a to 301f ... Hypervisor, 302a to 302i ... Virtual machine (OS), 401a, 401b ... Hypervisor, 402a, 402b ... Memory, 403a ~ 403f ... Logical processor, 404a ~ 404f ... Control information, 405 ... Virtual machine (OS), 406 ... Frequently referred data, 601 ... Address management table

Claims (2)

For the first information processing device,
A virtual address that specifies a storage area of a virtual memory space managed by an OS that operates across a second information processing device connected to the first information processing device and the first information processing device via a general-purpose network, and the above . A control program for transmitting a processing command to the second information processing device by referring to a management table associated with a physical address that specifies a storage area of a real memory space in the second information processing device. The control program according to claim 1, wherein the management table further includes a physical address that specifies a storage area of the real memory space in the first information processing apparatus.

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