JP7009223B2 - Power switching control circuit - Google Patents

Description

The present invention relates to a power supply switching control circuit, particularly a power supply switching control circuit mounted on a semiconductor storage device such as a flash memory.

Flash memory is widely used as a non-volatile semiconductor storage device. In a flash memory, data is written, read, and erased by applying a voltage to a memory cell. At that time, since the voltages used for writing, reading, and erasing the data are different, the power supply voltage is switched (for example, Patent Document 1).

The power supply switching control circuit that controls voltage switching during data writing (hereinafter referred to as rewriting) and reading in the flash memory is, for example, a regulator provided between the first line and the second line and an intermediate line. It has a first switching circuit and a second switching circuit connected via the above.

The regulator receives the supply of the first voltage from the first line, steps down the voltage to generate a second voltage lower than the first voltage and higher than the power supply voltage, and outputs the second voltage to the second line.

The first switching circuit is provided between the second line and the intermediate line. The first switching circuit switches the connection so that the intermediate line is connected to the power supply when the data is rewritten and the intermediate line is connected to the second line when the data is read. As a result, the intermediate line becomes the voltage level of the power supply voltage at the time of rewriting the data and the voltage level of the second voltage at the time of reading.

The second switching circuit is connected to a third line which is a third voltage higher than the first voltage when the data is rewritten and a voltage level of the power supply voltage when reading the data. The second switching circuit switches the connection so that the voltage output line connected to the gate of the memory cell is connected to the third line when rewriting the data and to the intermediate line when reading the data. As a result, the voltage output line becomes the voltage level of the third voltage at the time of rewriting the data and the voltage level of the second voltage at the time of reading.

The second switching circuit has a P-channel type MOS transistor provided between the intermediate line and the voltage output line, and an N-channel type MOS transistor provided between the third line and the voltage output line. .. A signal that becomes the voltage level of the third line is applied to the gate terminals of these P-channel type MOS transistors and N-channel type MOS transistors when the data is rewritten.

Further, between the third line and the voltage output line, a transistor pair composed of two P-channel type MOS transistors connected in series is provided in parallel with the N-channel type MOS transistor. A signal that becomes a signal of the voltage level of the third line is applied to the gate terminal of one of the P-channel type MOS transistors constituting the transistor pair when data is read out. A backflow prevention control signal is applied to the gate terminal of the other P-channel type MOS transistor constituting the transistor pair.

The signal generation circuit that generates the backflow prevention control signal includes, for example, a first P-channel type MOS transistor in which a drain terminal is connected to a signal output line that outputs a backflow prevention control signal, a second P-channel type MOS transistor, and a second P-channel type MOS transistor. including. A voltage having a voltage level of the second voltage is applied to the source terminal of the first P-channel type MOS transistor. A power supply voltage is applied to the source terminal of the second P-channel type MOS transistor. A control signal for controlling the voltage level of the signal output line is applied to the gate terminal of the first P-channel type MOS transistor, and a signal in which the signal level of the control signal is inverted is applied to the gate terminal of the second P-channel type MOS transistor. Is applied. The control signal is a signal that becomes the voltage level of the second voltage at the time of rewriting the data and becomes the voltage level of the ground potential at the time of reading.

Japanese Unexamined Patent Publication No. 2010-97676

When the flash memory having the power supply switching control circuit as described above ends the data rewriting operation, the voltage output line is discharged via a transistor pair consisting of two P-channel type MOS transistors connected in series, and a third voltage output line is discharged. The voltage level of the line drops to a level higher than the power supply level by the threshold voltage of the P-channel type MOS transistor. On the other hand, the intermediate line is maintained at the same power supply voltage level as when the data was rewritten.

After that, when the flash memory starts the read operation, the intermediate line is connected to the second line. A ground potential level control signal is applied to the gate terminal of the first P-channel type MOS transistor of the signal generation circuit, and a voltage level of the second voltage is applied to the gate terminal of the second P-channel type MOS transistor. Will be done. As a result, the first P-channel type MOS transistor is turned on and the second P-channel type MOS transistor is turned off, so that the backflow prevention control signal becomes the voltage level of the second voltage.

Since the backflow prevention control signal is at the voltage level of the second voltage, the other P-channel type MOS transistor constituting the transistor pair of the second switching circuit is turned off, and the current is generated between the third line and the voltage output line. Not flowing. As a result, the intermediate line, which was the level of the power supply voltage before the start of the read operation, the voltage output line, which was the voltage level higher than the power supply voltage by the threshold voltage of the P-channel type MOS transistor, and the second, which is the output of the regulator. Will be connected to the line. At this time, the load capacity of the intermediate line is negligibly small, but the load capacity is large because the voltage output line is a line that supplies voltage to the gate of the memory cell. Therefore, the voltage level of the second line drops due to the coupling with the load capacity of the voltage output line. On the other hand, the voltage output line rises to the voltage level of the second line lowered by the coupling. After that, due to the drive capability of the regulator, the second line and the voltage output line return to the voltage level of the second voltage after a certain period of time. After the second line and the voltage output line have returned to the voltage level of the second voltage, the flash memory can perform a read operation.

In this way, the period from the end of the write operation to the start of the read operation of the flash memory is the period from when the voltage level of the second line drops once to when it returns to the voltage level of the second voltage, which is the so-called "wait". "Period" is required. Therefore, there is a problem that the read operation cannot be started immediately after the rewrite operation is completed.

Further, in a flash memory composed of two banks that commonly use the voltage of the first line and the voltage of the second line, both banks simultaneously operate to read data from the other bank while rewriting data in one bank. In that case, the decrease in the voltage level of the second line at the end of rewriting affects the bank during the read operation, and there is a possibility that erroneous data is read.

A method is also conceivable in which the backflow prevention control signal is always set to the voltage level of the second line so that the voltage output line during the rewriting end period is set to a voltage level higher than that of the second line by the threshold voltage of the P-channel type MOS transistor. However, in that case, the voltage level of the second line rises due to the coupling. During the read operation, if the voltage level of the second line is higher than the second voltage, the regulator is cut off, and the voltage level of the second line is significantly lowered by the subsequent read operation, which may read erroneous data.

The present invention has been made in view of the above problems, and provides a power supply switching control circuit capable of quickly shifting from a rewriting operation by a flash memory to a reading operation and suppressing reading of erroneous data. The purpose is.

The power supply switching control circuit according to the present invention is a power supply switching control circuit mounted on a semiconductor memory and performing switching control of a voltage applied to a memory cell during a rewriting period for rewriting data and a reading period for reading data. The second voltage is connected to a first line having a first voltage higher than the power supply voltage, steps down the first voltage, is lower than the first voltage, and is higher than the power supply voltage. Is generated, and the connection is switched between the regulator that outputs to the second line, one of the second line and the power supply line that supplies the power supply voltage, and the intermediate line, and the rewriting period and the rewriting period are described as described above. A first switching circuit that connects the intermediate line to the power supply line during the rewrite end period, which is a transition period to the read period, and connects the intermediate line to the second line during the read period, and the rewrite period. A third voltage having a third voltage higher than the first voltage, switching from the third voltage to the power supply voltage during the rewriting end period, and controlling the voltage level so as to be the power supply voltage during the read period. It has a second switching circuit which is connected to three lines and connects either one of the third line and the intermediate line to the voltage output line, and the second switching circuit has the same. It is turned on in the rewriting period, turned off in the rewriting end period and the reading period, and in the rewriting period, the first switch connecting the third line to the voltage output line and the first switch are connected in parallel to the rewriting. A backflow prevention circuit that connects the third line to the voltage output line during the period and the rewrite end period, and an intermediate line that is turned off during the rewrite period and the rewrite end period and turned on during the read period. The backflow prevention circuit includes a second switch connected to the voltage output line, and the backflow prevention circuit has a backflow prevention control signal having a voltage level between the second voltage and the power supply voltage during the rewriting period and the rewriting end period. It is characterized in that the voltage of the voltage output line during the rewriting end period is controlled to be the second voltage.

According to the power supply switching control circuit according to the present invention, the flash memory can quickly start the read operation after the rewrite operation is completed. In addition, it is possible to suppress reading of erroneous data.

It is a circuit diagram which shows the structure of the power supply switching control circuit of Example 1. FIG. It is a circuit diagram which shows the structure of the signal generation circuit of Example 1. FIG. It is a figure which shows the waveform of the voltage and the signal of each line at the time of the power-source switching operation of Example 1. FIG. It is a circuit diagram which shows the structure of the signal generation circuit of the comparative example. It is a figure which shows the waveform of the voltage and the signal of each line at the time of the power supply switching operation of the comparative example. It is a circuit diagram which shows the structure of the signal generation circuit of Example 2. It is a figure which shows the waveform of the voltage and the signal of each line at the time of the power-source switching operation of Example 2. FIG.

Hereinafter, examples of the present invention will be described with reference to the drawings. In the description and the accompanying drawings in each of the following examples, substantially the same or equivalent parts are designated by the same reference numerals.

FIG. 1 is a circuit diagram showing the configuration of the power supply switching control circuit 100 of this embodiment. The power supply switching control circuit 100 is mounted on a non-volatile semiconductor memory (for example, a flash memory). The power switching control circuit 100 is connected to a memory cell in the flash memory via a voltage output line Z VDDL, and supplies a gate voltage to the gate of the memory cell transistor (not shown).

The power supply switching control circuit 100 includes a regulator 10, a first switching circuit 11, and a second switching circuit 12. The first switching circuit 11 and the second switching circuit 12 are connected via the intermediate line Z VDDW.

In the regulator 10, the input terminal VIN is connected to the first line PWL. The first line PWL has a voltage level of a first voltage V1 that boosts the power supply voltage VDD. The regulator 10 outputs a voltage obtained by stepping down the voltage on the first line PWL to the second line VD25. The second line VD25 has a voltage level of a second voltage V2 that is higher than the power supply voltage VDD and lower than the first voltage V1.

The first switching circuit 11 is a switching circuit that switches the connection between the intermediate line Z VDDW, the second line VD25, and the power supply line that supplies the power supply voltage VDD. The first switching circuit 11 includes a transistor PM10 which is a P-channel type (first conductive type) MOS transistor, and a transistor NM10 which is an N-channel type (second conductive type opposite to the first conductive type) MOS transistor. The transistor NM11 which is an N-channel type MOS transistor and the transistor PM11 which is a P-channel type MOS transistor are included.

The source terminal of the transistor PM10 is connected to the second line VD25, and the drain terminal is connected to the intermediate line Z VDDW. The well (back gate) of the transistor PM10 is connected to the first line PWL. The control signal ENVD25 is supplied to the gate terminal of the transistor PM10. The control signal ENVD25 is a signal for controlling the level of the voltage output to the intermediate line Z VDDW. The control signal ENVD25 becomes the voltage level (high level) of the second line VD25 when the memory cell is rewritten. Further, the control signal ENVD25 becomes the voltage level (low level) of the ground potential VSS when the memory cell is read out.

In the transistor NM10, the drain terminal is connected to the source terminal of the transistor PM10 and the second line VD25, and the source terminal is connected to the drain terminal of the transistor PM10 and the intermediate line Z VDDW. The control signal ENVD25N is supplied to the gate terminal of the transistor NM10. The control signal ENVD25N is a signal for controlling the level of the voltage output to the intermediate line Z VDDW, and has a signal level in which the signal level of the control signal ENVD25 is inverted. That is, the control signal ENVD25N becomes the voltage level (low level) of the ground potential VSS when the memory cell is rewritten. Further, the control signal ENVD25N becomes the voltage level (high level) of the second line VD25 when the memory cell is read out.

The transistor NM11 has a drain terminal connected to a power supply line that supplies the power supply voltage VDD. The source terminal of the transistor NM11 is connected to the intermediate line Z VDDW, and is also connected to the source terminal of the transistor NM10 and the drain terminal of the transistor PM10. The control signal EN VDD is supplied to the gate terminal of the transistor NM11. The control signal EN VDD is a signal for controlling the level of the voltage output to the intermediate line Z VDDW. The control signal EN VDD becomes the voltage level (high level) of the second line VD25 when the memory cell is rewritten. Further, the control signal EN VDD becomes the voltage level (low level) of the ground potential VSS when the memory cell is read out.

The source terminal of the transistor PM11 is connected to a power supply line that supplies the power supply voltage VDD. The drain terminal of the transistor PM11 is connected to the source terminal of the transistor NM11, connected to the intermediate line Z VDDW, and connected to the source terminal of the transistor NM10 and the drain terminal of the transistor PM10. The well of the transistor PM11 is connected to the first line PWL. The control signal EN whether N is supplied to the gate terminal of the transistor PM11. The control signal EN VDDN is a signal for controlling the level of the voltage output to the intermediate line Z VDDW, and has a signal level in which the signal level of the control signal EN VDD is inverted. That is, the control signal EN VDDN becomes the voltage level (high level) of the second line VD25 when the memory cell is read out. Further, the control signal EN VDDN becomes the voltage level (low level) of the ground potential VSS at the time of rewriting the memory cell.

When the memory cell is rewritten, the transistors NM10 and PM10 are turned off, and the transistors NM11 and PM11 are turned on. As a result, the intermediate line Z VDDW is connected to the power supply line that supplies the power supply voltage VDD, and the intermediate line Z VDDW becomes the voltage level of the power supply voltage VDD.

On the other hand, when the memory cell is read out, the transistors NM10 and PM10 are turned on, and the transistors NM11 and PM11 are turned off. As a result, the intermediate line Z VDDW is connected to the second line VD25, and the intermediate line Z VDDW becomes the voltage level of the second line VD25.

The second switching circuit 12 is a switching circuit that switches the connection between the voltage output line Z VDDL and any one of the intermediate line Z VDDW and the third line VEP. The second switching circuit 12 includes a transistor PM12 which is a P-channel type MOS transistor and a transistor NM12 which is an N-channel type MOS transistor. Further, the second switching circuit 12 includes a transistor pair composed of transistors PM13 and PM14, which are P-channel type MOS transistors. The transistor pair consisting of the transistors PM13 and PM14 is connected in parallel to the transistor NM12.

The voltage level of the third line VEP is controlled so that it becomes the third voltage V3 at the time of rewriting the data and becomes the power supply voltage VDD at the time of reading. The third voltage V3 is sufficiently higher than the voltage level obtained by adding the first voltage V1 and the threshold voltage PVt of the P-channel type MOS transistor (hereinafter referred to as the threshold voltage PVt of the MOSFET).

The drain terminal of the transistor PM12 is connected to the intermediate line Z VDDW, and is connected to the source terminal of the transistor NM10, the drain terminal of the transistor PM10, the source terminal of the transistor NM11, and the drain terminal of the transistor PM11 via the intermediate line Z VDDW. The source terminal of the transistor PM12 is connected to the voltage output line Z VDDL. The source terminal and the well of the transistor PM12 are connected to each other. A control signal HVO is supplied to the gate terminal of the transistor PM12. The control signal HVO is a signal that controls the level of the voltage output to the voltage output line Z VDDL. The control signal HVO has a high level when the memory cell is rewritten and a low level when the memory cell is read. At high levels, the control signal HVO becomes the voltage level of the third line VEP.

The drain terminal of the transistor NM12 is connected to the third line VEP. The source terminal of the transistor NM12 is connected to the voltage output line Z VDDL, and is commonly connected to the source terminal and the well of the transistor PM12 via the voltage output line Z VDDL. A control signal HVO is supplied to the gate terminal of the transistor NM12.

The transistor NM12 is a first switch that is turned on when the memory cell is rewritten and connects the third line VEP to the voltage output line Z VDDL. The transistor PM12 is a second switch that is turned on when the memory cell is read out and connects the intermediate line Z VDDW to the voltage output line Z VDDL.

The drain terminals of the transistors PM13 and PM14 constituting the transistor pair are connected to each other. The source terminal of the transistor PM13 is connected to the third line VEP. The source terminal and the well of the transistor PM13 are connected to each other. A control signal HVON is supplied to the gate terminal of the transistor PM13. The control signal HVON is a signal whose signal level changes according to the logic opposite to that of the control signal HVO, and is a low level when the memory cell is rewritten and a high level when the memory cell is read. At high levels, the control signal HVON becomes the voltage level of the third line VEP.

The source terminal of the transistor PM14 is connected to the voltage output line Z VDDL, and is connected to the source terminal of the transistor NM12 and the source terminal of the transistor PM12. The source terminal and the well of the transistor PM14 are connected to each other. A backflow prevention control signal STP is supplied to the gate terminal of the transistor PM14.

The transistors PM13 and PM14 connect the third line VEP to the voltage output line Z VDDL and the current from the voltage output line Z VDDL to the third line VEP during the rewriting end period during the transition from the rewrite operation to the read operation of the flash memory. It has a function as a backflow prevention circuit to prevent backflow. In particular, the transistor PM14 applies the signal level (voltage level) of the backflow prevention signal STP to the gate terminal so that the voltage level of the voltage output line Z VDDL is the sum of the threshold voltage of the transistor PM14 and the signal level of the backflow prevention signal STP. After lowering to the corresponding voltage level, the backflow prevention function works.

FIG. 2 is a circuit diagram of a signal generation circuit 20 that generates a backflow prevention control signal STP. The signal generation circuit 20 includes transistors PM20, PM21 and PM22 which are P-channel type MOS transistors, and transistors NM20 and NM21 which are N-channel type MOS transistors.

The drain terminal and the gate terminal of the transistor NM20 are connected to a signal output line SL that outputs a backflow prevention control signal STP. The source terminal of the transistor NM20 is connected to the drain terminal of the transistor NM21.

The source terminal of the transistor NM21 is grounded. A control signal EN is supplied to the gate terminal of the transistor NM21. The control signal EN is a control signal that controls the voltage level of the signal output line SL. The control signal EN becomes the voltage level (high level) of the second line VD25 at the time of rewriting the memory cell, and becomes the voltage level (low level) of the ground potential VSS at the time of reading.

The drain terminal of the transistor PM20 is connected to the signal output line SL. The source terminal of the transistor PM20 is connected to the drain terminal of the transistor PM21. The well of the transistor PM20 is connected to the first line PWL. A control signal ENN is supplied to the gate terminal of the transistor PM20. The control signal ENN is a control signal that controls the voltage level of the signal output line SL, and the signal level changes according to the logic opposite to that of the control signal EN. The control signal ENN becomes the voltage level (low level) of the ground potential VSS at the time of rewriting the memory cell, and becomes the voltage level (high level) of the second line VD25 at the time of reading.

The source terminal of the transistor PM21 is connected to the second line VD25. Further, the source terminal and the well of the transistor PM21 are connected to each other. The gate terminal of the transistor PM21 is connected to the signal output line SL and is also connected to the gate terminal of the transistor NM20.

The source terminal of the transistor PM22 is connected to the second line VD25. The drain terminal of the transistor PM22 is connected to the signal output line SL. The well of the transistor PM22 is connected to the first line PWL. A control signal EN is supplied to the gate terminal of the transistor PM22.

The transistor PM21 and the transistor NM20 are diode-connected. When both the transistor PM20 and the transistor NM21 are on, the transistor PM21 and the transistor NM20 are in a state of passing a current. At this time, the transistors NM20, NM21, PM20 and so that the signal level of the backflow prevention control signal STP (that is, the voltage level of the signal output line SL) is lower than that of the second line VD25 by the threshold voltage PVt of the polyclonal. The dimension of PM21 is set.

Next, the power supply switching operation by the power supply switching control circuit 100 will be described with reference to FIGS. 1, 2, and 3. FIG. 3 is a waveform diagram showing the voltage level of each line and the time change of each signal during the power supply switching operation.

During the rewriting period in which the flash memory rewrites the memory cell, the third line VEP becomes the third voltage V3. The control signal HVO becomes the third voltage V3 (high level), which is the voltage level of the third line VEP. The control signal HVON has a low level.

The control signal ENVD25, the control signal EN VDD, and the control signal EN become the voltage level (high level) of the second line VD25. On the other hand, the control signal ENVD25N, the control signal EN VDDN, and the control signal ENN become the voltage level (low level) of the ground potential VSS.

In the first switching circuit 11, the transistors NM10 and PM10 are turned off, and the transistors NM11 and PM11 are turned on. As a result, the intermediate line Z VDDW is connected to the power supply line, and the intermediate line Z VDDW becomes the voltage level of the power supply voltage VDD.

In the signal generation circuit 20, the transistor PM22 is turned off, and the transistors PM20 and NM21 are turned on. The transistors PM21 and NM20 are in a state of passing a current. The backflow prevention control signal STP becomes a low level, and becomes a voltage level (VD25-PVt) lower than that of the second line VD25 by the threshold voltage PVt of the polyclonal.

In the second switching circuit 12, the transistor PM12 is turned off and the transistors NM12, PM13 and PM14 are turned on. As a result, the voltage output line Z VDDL has the same voltage level as the third line VEP.

Next, in the rewriting end period in which the flash memory ends the rewriting of the memory cell, the third line VEP is discharged from the third voltage V3 and becomes the voltage level of the power supply voltage VDD. Since the control signal HVO has the same voltage level as the third line VEP, it becomes the voltage level of the power supply voltage VDD.

The control signal HVON and the backflow prevention control signal STP maintain the same signal level as the rewriting period. The voltage output line Z VDDL is discharged through the transistors PM13 and PM14 in the ON state, and drops to a voltage level higher than the backflow prevention control signal STP by the threshold voltage PVt of the photoresist, that is, the voltage level of the second line VD25.

Since the signal level of the control signal HVO and the voltage level of the third line VEP and the voltage output line Z VDDL decrease at the same speed, both the transistors PM12 and NM12 are turned off.

The control signals ENVD25, EN VDD, ENVD25N and EN VDDN maintain the same signal level as the rewrite period. Therefore, the transistors NM10 and PM10 are off, the transistors NM11 and PM11 are on, and the intermediate line Z VDDW maintains the voltage level of the power supply voltage VDD.

Next, when the flash memory starts the read operation of the memory cell, the control signals ENVD25, EN VDD and HVO become the low level, and the control signals ENVD25N and EN VDDN become the voltage level (high level) of the second line VD25. Further, the signal level of the control signal HVON is the voltage level of the third line VEP, that is, the voltage level of the power supply voltage VDD. As a result, the transistors NM10, PM10 and PM12 are turned on, and the transistors NM11, PM11 and NM12 are turned off.

Further, the control signal EN is a low level, and the control signal ENN is a voltage level (high level) of the second line VD25. As a result, in the signal generation circuit 20, the transistor PM22 is turned on, and the transistors PM20 and NM21 are turned off. As a result, the backflow prevention control signal STP becomes the voltage level of the second line VD25.

In the second switching circuit 12, the transistor PM14 is turned off, and no current flows between the third line VEP and the voltage output line Z VDDL. As a result, the intermediate line Z VDDW, which was the voltage level of the power supply voltage VDD before the start of the read operation, the voltage output line Z VDDL, which was the voltage level of the second line VD25, and the second line VD25, which is the output line of the regulator 10, Be connected.

The load capacitance of the intermediate line Z VDDW is negligibly small, and the voltage output line Z VDDL and the output of the regulator 10 have the same voltage level (that is, the voltage level of the second line VD25). Therefore, as shown in FIG. 3, the voltage level of the second line VD25 does not decrease, and the output of the regulator 10, the intermediate line Z VDDW, and the voltage output line Z VDDL all have the same second voltage level V2. As a result, the flash memory can quickly start the read operation (that is, shift to the read period).

FIG. 4 is a circuit diagram showing a configuration of a signal generation circuit 30 in a power switching control circuit of a comparative example different from the power switching control circuit 100 of the present embodiment. The signal generation circuit 30 of the comparative example includes transistors PM30 and PM31 which are P-channel type MOS transistors.

The drain terminals of the transistors PM30 and PM31 are connected to a signal output line SL that outputs a backflow prevention control signal STP. The wells of the transistors PM30 and PM31 are connected to the first line PWL. The source terminal of the transistor PM30 is connected to a power supply line that supplies the power supply voltage VDD, and the source terminal of the transistor PM31 is connected to the second line VD25. The control signal ENN is supplied to the gate terminal of the transistor PM30, and the control signal EN is supplied to the gate terminal of the transistor PM31.

In the signal generation circuit 30 of the comparative example, the control signal EN of the voltage level (high level) of the second line VD25 is applied to the gate terminal of the transistor PM31 during the rewriting operation of the flash memory, and the control signal EN of the voltage level (high level) of the second line VD25 is applied to the gate terminal of the transistor PM30. A low level control signal ENN is applied. As a result, the transistor PM31 is turned off, the transistor PM30 is turned on, and as shown in FIG. 5, the backflow prevention control signal STP becomes the voltage level (high level) of the power supply voltage VDD.

When the flash memory finishes the rewriting operation, the third line VEP is discharged from the third voltage level to reach the voltage level of the power supply voltage VDD. Since the control signal HVO has the same voltage level as the third line VEP, it also has the voltage level of the power supply voltage VDD. Since the control signal HVO and the backflow prevention control signal STP are maintained at the same signal level (voltage level) as the rewriting period, the voltage output line Z VDDL is discharged via the transistors PM13 and PM14, and the threshold value of ProLiant is higher than that of the power supply voltage VDD. The voltage drops to a higher voltage level by the voltage PVt.

When the flash memory starts the read operation, the control signal EN becomes the low level, and the control signal ENN becomes the voltage level (high level) of the second line VD25. As a result, the transistor PM31 is turned on, the transistor PM30 is turned off, and the backflow prevention control signal STP becomes the voltage level (low level) of the second line VD25.

In the second switching circuit 12, the transistor PM14 is turned off by receiving the supply of the low-level backflow prevention control signal STP, and no current flows between the third line VEP and the voltage output line Z VDDL. As a result, the intermediate line Z VDDW, which was the voltage level of the power supply voltage VDD before the start of the read operation, the voltage output line Z VDDL, which was the voltage level higher than the power supply voltage VDD by the threshold voltage PVt of FIGURE, and the output line of the regulator 10. The second line VD25, which is the above, will be connected.

At this time, the load capacity of the intermediate line Z VDDW is negligibly small, but the voltage output line Z VDDL is a line that supplies voltage to the gate of the memory cell, so that the load capacity is large. Therefore, the voltage level of the second line VD25 drops as shown in FIG. 5 due to the coupling with the load capacity of the voltage output line Z VDDL. Therefore, the time until the voltage level of the second line VD25 returns to the voltage level of the second voltage V2 by driving the regulator 10 is required as the "wait period" until the start of the read operation.

On the other hand, as described above, in the power supply switching control circuit 100 of this embodiment, the voltage level of the voltage output line Z VDDL does not drop to the power supply voltage VDD during the rewriting end period and is maintained at the voltage level of the second line VD25. Will be done. Therefore, in the power supply switching control circuit 100 of this embodiment, the voltage level of the second line VD25 does not decrease due to the coupling with the load capacity of the voltage output line Z VDDL. Therefore, the flash memory equipped with the power supply switching control circuit 100 of this embodiment can start the read operation immediately after the completion of rewriting without the wait period.

Further, when the flash memory is composed of two banks and the first line PWL and the second line VD25 are used in common in both banks, both banks read data from the other bank while rewriting the data in one bank. In the simultaneous operation, the decrease in the voltage level of the second line VD25 at the end of rewriting as in the comparative example affects the bank during the reading operation, and there is a possibility that erroneous data reading occurs. On the other hand, in the power supply switching control circuit 100 of this embodiment, since the voltage level of the second line VD25 does not decrease, erroneous data reading does not occur.

As described above, according to the power supply switching control circuit 100 of this embodiment, the flash memory can quickly start the read operation after the rewrite operation is completed, and the read of erroneous data is suppressed. Therefore, it can be expected that the performance of the system using the flash memory will be improved.

The power supply switching control circuit of this embodiment is different from the first embodiment in the configuration of the signal generation circuit that generates the backflow prevention control signal STP, and the other configurations are the same as the power supply switching control circuit 100 of the first embodiment shown in FIG. Is.

FIG. 6 is a circuit diagram showing the configuration of the signal generation circuit 40 of this embodiment. The signal generation circuit 40 includes transistors PM40, PM41 and PM42 which are P-channel type MOS transistors and transistors NM40 and NM41 which are N-channel type MOS transistors.

The arrangement of the transistors PM40, PM41, NM40 and NM41 and the connection relationship of each terminal are the same as those of the transistors PM20, PM21, NM20 and NM21 of the signal generation circuit 20 of the first embodiment. On the other hand, unlike the transistor PM22 of the signal generation circuit 20 of the first embodiment, the transistor PM42 has a source terminal connected to the first line PWL.

In the transistors NM40, NM41, PM40 and PM41, when the transistor PM40 and the transistor NM41 are both on and a current is flowing, the backflow prevention control signal STP is lower than that of the second line VD25 by the threshold voltage PVt of the polyclonal. The dimensions are set to the voltage level. Therefore, during the rewriting period in which the flash memory rewrites the memory cell, the transistor receives the supply of the control signal EN which is the voltage level of the second line VD25 and the control signal ENN which is the voltage level of the ground potential VSS. PM42 is turned off, and transistors PM40 and NM41 are turned on. The backflow prevention control signal STP becomes a low level, and becomes a voltage level (VD25-PVt) lower than that of the second line VD25 by the threshold voltage PVt of the polyclonal.

During the rewrite end period, the backflow prevention control signal STP maintains the same signal level as the rewrite period. In the second switching circuit 12, the voltage output line Z VDDL is discharged via the transistors PM13 and PM14 in the ON state, and the voltage level is higher than the backflow prevention control signal STP by the threshold voltage PVt of the MIMO, that is, the second line VD25. The voltage level drops to.

When the flash memory starts the read operation of the memory cell, the control signal EN becomes the low level and the control signal ENN becomes the voltage level (high level) of the second line VD25. As a result, in the signal generation circuit 40, the transistor PM42 is turned on, and the transistors PM40 and NM41 are turned off. As a result, as shown in FIG. 7, the backflow prevention control signal STP becomes the voltage level of the first line PWL.

In the second switching circuit 12, since the backflow prevention control signal STP is at the voltage level of the first line PWL, the transistor PM14 is turned off, and no current flows between the third line VEP and the voltage output line Z VDDL. .. As a result, the intermediate line Z VDDW, which was the voltage level of the power supply voltage VDD before the start of the read operation, the voltage output line Z VDDL, which was the voltage level of the second line VD25, and the second line VD25, which is the output line of the regulator 10, Be connected.

The load capacitance of the intermediate line Z VDDW is negligibly small, and the voltage output line Z VDDL and the output of the regulator 10 have the same voltage level. Therefore, as shown in FIG. 7, the voltage level of the second line VD25 does not decrease, and the output of the regulator 10, the intermediate line Z VDDW, and the voltage output line Z VDDL all have the same voltage level of the second voltage V2. As a result, the flash memory can quickly start the read operation.

Further, when the flash memory is configured to consist of two banks that commonly use the first line PWL and the second line VD25, and both banks simultaneously operate to read data from the other bank while rewriting the data in one bank. Even so, since the voltage level of the second line VD25 does not decrease, erroneous data reading does not occur.

Further, in the power supply switching control circuit including the signal generation circuit 40 of the present embodiment, since the backflow prevention control signal STP is the voltage level of the first line PWL (that is, the first voltage V1) during the read operation, the voltage is output. Even if the voltage level of the line Z VDDL fluctuates greatly, the current does not flow back to the third line VEP unless the voltage level rises to a voltage level higher than the first voltage V1 by the threshold voltage PVt of the P channel type MOS transistor. Therefore, it is more resistant to noise than the power supply switching control circuit 100 of the first embodiment.

Therefore, according to the power supply switching control circuit of this embodiment, improvement in the performance of the system using the flash memory can be expected.

The present invention is not limited to the above embodiment. For example, in the first embodiment, as a means for switching the backflow prevention control signal STP between the voltage level of the second line VD25 and the voltage level lower than the threshold voltage PVt of the MOSFET by the threshold voltage PVt of the second line VD25, the P-channel type MOS transistor and A case where an N-channel type MOS transistor is used has been described. However, elements other than the P-channel type MOS transistor and the N-channel type MOS transistor may be used.

Further, in the first embodiment, by connecting the transistor PM21 which is a P-channel type MOS transistor and the transistor NM20 which is an N-channel type MOS transistor by a diode, the signal output line SL is connected to the threshold voltage PVt of the MOSFET rather than the second line VD25. The case where the voltage level is set to be lower by a minute has been described. However, the signal output line SL may be set to a voltage level depending on another circuit configuration.

Further, in the first embodiment, the backflow prevention control signal STP is switched between the voltage level of the second line VD25 and the voltage level lower than the second line VD25 by the threshold voltage PVt of the photoresist of the second line VD25. The case of suppressing the decrease in the voltage level has been described. However, for example, a configuration in which the voltage level is switched between the voltage level of the first line PWL and the voltage level which is lower than the threshold voltage PVt of the phage by the threshold voltage PVt of the first line PWL may be used in the power supply switching control circuit of the PWL.

Further, in Examples 1 and 2, the case of suppressing the decrease in the voltage level of the second line VD25 has been described. For example, the voltage level is set to the fourth voltage and the voltage is lower than the fourth voltage by the threshold voltage PVt of the photoresist. The configuration for switching to the level may be used for the power supply switching control circuit of the fourth voltage.

Further, in the first and second embodiments, the case where the power supply switching control circuit is mounted in the flash memory has been described, but it may be applied to a semiconductor memory other than the flash memory or other semiconductor integrated circuits.

100 Power supply switching control circuit 10 Regulator 11 First switching circuit 12 Second switching circuit 20, 30, 40 Signal generation circuit

Claims (6)

It is a power supply switching control circuit that is mounted on a semiconductor memory and controls switching of the voltage applied to the memory cell during the rewriting period for rewriting data and the reading period for reading data.
Connected to a first line having a first voltage higher than the power supply voltage, the first voltage is stepped down to generate a second voltage lower than the first voltage and higher than the power supply voltage. Then, the regulator that outputs to the second line and
The connection is switched between the second line and the power supply line that supplies the power supply voltage, and the intermediate line is performed, and the intermediate rewriting period and the rewriting end period, which is the transition period from the rewriting period to the reading period, are performed. A first switching circuit that connects the line to the power supply line and connects the intermediate line to the second line during the read period.
It has a third voltage higher than the first voltage during the rewriting period, switches from the third voltage to the power supply voltage during the rewriting end period, and becomes the power supply voltage during the read period. A second switching circuit that is connected to a third line to which is controlled and connects one of the third line and the intermediate line to the voltage output line, and a second switching circuit for performing connection switching.
Have,
The second switching circuit is
A first switch that is turned on during the rewriting period, turned off during the rewriting end period and the reading period, and connects the third line to the voltage output line during the rewriting period.
A backflow prevention circuit connected in parallel with the first switch and connecting the third line to the voltage output line during the rewriting period and the rewriting end period.
A second switch that turns off during the rewrite period and the rewrite end period, turns on during the read period, and connects the intermediate line to the voltage output line during the read period.
Including
The backflow prevention circuit includes a backflow prevention transistor connected in parallel with the first switch between the third line and the voltage output line, and the second voltage during the rewriting period and the rewriting end period . The backflow prevention control signal having a voltage level lower than the threshold voltage of the backflow prevention transistor is supplied, and the voltage of the voltage output line during the rewriting end period is controlled to be the second voltage. Characterized power switching control circuit. The backflow prevention transistor is turned on by receiving the supply of the backflow prevention control signal during the rewriting period and the rewriting end period, and applies the second voltage to the voltage output line during the rewrite end period. The power supply switching control circuit according to claim 1. It has a signal generation circuit that generates the backflow prevention control signal, and has a signal generation circuit.
The signal generation circuit is
A first conductive type first transistor having a first end connected to a signal output line that outputs a backflow prevention control signal and receiving a first control signal applied to the control end.
A second transistor of the second conductive type opposite to the first conductive type, in which the first end and the control end are connected by a diode via the signal output line, and
The first conductive type third transistor whose first end is connected to the second end of the first transistor, the second end is connected to the second line, and the control end is connected to the signal output line.
A second end is connected to the second end of the second transistor, the second end is connected to a ground potential, and a second control signal is applied to the control end by inverting the signal level of the first control signal. Conductive type 4th transistor and
The power supply switching control circuit according to claim 1 or 2, wherein the power switching control circuit comprises. In the signal generation circuit, the first end is connected to the signal output line, the second end is connected to the second line, and the second control signal is applied to the control end of the first conductive type fifth. The power supply switching control circuit according to claim 3, further comprising a transistor. In the signal generation circuit, the first end is connected to the signal output line, the second end is connected to the first line, and the second control signal is applied to the control end of the first conductive type fifth. The power supply switching control circuit according to claim 3, further comprising a transistor. The first, third, and fifth transistors are first-channel MOS transistors whose first end is a drain, whose second end is a source, and whose control end is a gate.
The second and fourth transistors are second channel type MOS transistors whose first end is a drain, the second end is a source, and the control end is a gate.
The first control signal is a signal having a ground potential during the rewriting period and the rewriting end period, and a voltage level of the second voltage during the reading period.
The second control signal is a signal having a voltage level of the second voltage during the rewriting period and the rewriting end period, and a voltage level of the ground potential during the reading period.
The power supply switching control circuit according to claim 4 or 5.

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