JP7010095B2 - Semiconductor device - Google Patents

Description

The techniques disclosed herein relate to semiconductor devices.

In order to promote the miniaturization of semiconductor devices, a technique for forming a contact trench on the surface layer of a semiconductor layer is known. The electrode filled in the contact trench can contact the semiconductor layer by utilizing the side surface of the contact trench. Therefore, the contact area of the electrodes in the in-plane direction of the semiconductor layer can be reduced, so that the semiconductor device can be miniaturized.

A technique for forming a p-type hole extraction region below such a contact trench is known in order to extract holes generated during avalanche breakdown. Patent Document 1 discloses a technique for deeply forming this hole extraction region in order to improve the avalanche withstand capability.

Japanese Unexamined Patent Publication No. 2009-43966

The hole extraction region disclosed in Patent Document 1 is formed so as to penetrate the drift region beyond the body region. Therefore, the hole extraction region is arranged adjacent to the pn junction between the drift region and the body region. For example, if a load short circuit occurs while the semiconductor device is on, a large voltage may be applied to the semiconductor device. At this time, there is a concern that the vicinity of the side surface of the hole extraction region adjacent to the pn junction between the drift region and the body region becomes a high electric field region, and avalanche breakdown occurs in this region. This high electric field region is close to a parasitic npn transistor (parasitic npn transistor composed of a drift region, a body region, and a source region) existing on the side surface of the trench gate portion. Therefore, the avalanche current generated by the avalanche breakdown in the high electric field region becomes the base current of the parasitic npn transistor, and the secondary breakdown in which the parasitic npn transistor operates is generated. As described above, the semiconductor device disclosed in Patent Document 1 has a problem that the on-resistance is low. It is an object of the present specification to provide a technique for improving the on-tolerance.

The type of the semiconductor device disclosed in the present specification is not particularly limited, and is, for example, a MOSFET or an IGBT. Further, the semiconductor material of the semiconductor device disclosed in the present specification is not particularly limited, and is, for example, a wide bandgap semiconductor. The wide bandgap semiconductor may be, for example, silicon carbide, a nitride semiconductor or an oxide semiconductor. One embodiment of the semiconductor device disclosed in the present specification is a first conductive type first semiconductor region, a second conductive type second semiconductor region provided on the first semiconductor region, and a second semiconductor region. A first conductive type third semiconductor region provided above, a surface electrode filled in a contact trench extending beyond the third semiconductor region to reach the second semiconductor region, and provided below the contact trench. A second conductive type carrier drawn region and a second conductive type provided below the carrier drawn region and adjacent to a pn junction between the first semiconductor region and the second semiconductor region. The electric field relaxation region, the lower region of the second conductive type provided below the electric power relaxation region, the third semiconductor region, and the gate trench extending beyond the second semiconductor region to reach the first semiconductor region. A trench gate portion facing the second semiconductor region located at a position separating the first semiconductor region and the third semiconductor region can be provided. The surface electrode filled in the contact trench is in contact with the third semiconductor region on the side surface thereof, and is in contact with the carrier extraction region on the bottom surface thereof. The impurity concentration in the carrier extraction region is higher than the impurity concentration in the second semiconductor region. The impurity concentration in the electric field relaxation region is lower than the impurity concentration in the second semiconductor region. The impurity concentration in the lower region is higher than the impurity concentration in the electric field relaxation region. In this semiconductor device, an electric field relaxation region is arranged at a position adjacent to the pn junction between the first semiconductor region and the second semiconductor region, and the impurity concentration in the electric field relaxation region is higher than the impurity concentration in the second semiconductor region. It is thinly formed. As a result, even if a large voltage is applied to the semiconductor device while the semiconductor device is on, the electric field near the side surface of the electric field relaxation region is relaxed, and the first semiconductor region, the second semiconductor region, and the third semiconductor region are relaxed. The operation of the parasitic transistor composed of is suppressed. This semiconductor device can have the characteristic of high on-resistance.

The semiconductor device of the above embodiment may further include an embedded plate portion arranged below the trench gate portion in the gate trench. The embedded plate portion can have an embedded insulating film and a plate electrode facing the first semiconductor region via the embedded insulating film. This semiconductor device can improve the withstand voltage and / or reduce the on-resistance based on the voltage applied to the plate electrode of the embedded plate portion.

In the semiconductor device of the above embodiment, the lower region may form a super junction structure with the adjacent first semiconductor region. This semiconductor device can have a characteristic of high withstand voltage.

The cross-sectional view of the main part of the semiconductor device is schematically shown.

As shown in FIG. 1, the semiconductor device 1 is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and is a semiconductor layer 10, a drain electrode 22 covering the back surface 10A of the semiconductor layer 10, and the surface of the semiconductor layer 10. It includes a source electrode 24 that covers 10B, a trench gate portion 30, and an embedded plate portion 40. The material of the semiconductor layer 10 is silicon. Instead of this example, the material of the semiconductor layer 10 may be, for example, silicon carbide or a nitride semiconductor. The semiconductor layer 10 has an n ⁺ type drain region 11, an n ^- type drift region 12, a p-type body region 13, an n ⁺ type source region 14, a p ⁺ type hole extraction region 15, and a p ^- type. It has an electric field relaxation region 16 and a p-type lower region 17.

A gate trench TR1 is formed so as to penetrate a part of the drift region 12 from the surface 10B of the semiconductor layer 10 through the source region 14 and the body region 13, and the trench gate portion 30 is formed in the gate trench TR1. And the buried plate portion 40 is provided. The trench gate portion 30 is arranged on the upper side in the gate trench TR1, and the embedded plate portion 40 is arranged on the lower side in the gate trench TR1. Further, a contact trench TR2 is formed so as to penetrate a part of the body region 13 from the surface 10B of the semiconductor layer 10 through the source region 14, and a part of the source electrode 24 is formed in the contact trench TR2. Is filled. The contact trench TR2 is arranged between adjacent gate trenches TR1.

The drain region 11 is provided on the back layer portion of the semiconductor layer 10 and is exposed on the back surface 10A of the semiconductor layer 10. The drain region 11 is in ohmic contact with the drain electrode 22.

The drift region 12 is provided on the drain region 11 and is arranged between the drain region 11 and the body region 13. The buried plate portion 40 is arranged at a depth corresponding to the drift region 12. The drift region 12 is in contact with the side surface of the buried plate portion 40. The drift region 12 is an example of the first semiconductor region.

The body region 13 is provided on the drift region 12 and is arranged between the drift region 12 and the source region 14. The trench gate portion 30 is arranged at a depth corresponding to the body region 13. The body region 13 is in contact with the side surface of the trench gate portion 30. The impurity concentration of the body region 13 is designed in consideration of the threshold voltage and the channel resistance, and is, for example, in the range of 5 × 10 ¹⁶ to 5 × 10 ¹⁷ cm ^-3 . The body region 13 is an example of the second semiconductor region.

The source region 14 is provided on the body region 13 and is exposed on the surface 10B of the semiconductor layer 10. The source region 14 is in ohmic contact with the source electrode 24. As shown in FIG. 1, the source electrode 24 filled in the contact trench TR2 is in contact with the source region 14 on its side surface. As described above, by using the contact trench TR2, it is possible to sufficiently secure the contact area between the source region 14 and the source electrode 24 without securing a wide area in the surface direction of the source region 14. Therefore, the distance (gate pitch) between adjacent gate trenches TR1 can be shortened. The source region 14 is an example of a third semiconductor region.

The hole extraction region 15 is arranged below the contact trench TR2. When observed from a direction orthogonal to the surface 10B of the semiconductor layer 10 (vertical direction on the paper surface) (hereinafter referred to as “when viewed in a plane”), the hole extraction region 15 falls within the existence range of the contact trench TR2. It may be arranged so as to exceed the existence range of the contact trench TR2. The source electrode 24 filled in the contact trench TR2 is in ohmic contact with the hole extraction region 15 at the bottom surface thereof. The hole extraction region 15 may be formed so as to cover the corner portion of the bottom surface of the contact trench TR2. The impurity concentration in the hole extraction region 15 is higher than the impurity concentration in the body region 13, for example, in the range of 5 × 10 ¹⁸ to 1 × 10 ²⁰ cm ^-3 . The hole extraction region 15 is an example of a carrier extraction region.

The electric field relaxation region 16 is arranged below the hole extraction region 15, is arranged between the hole extraction region 15 and the lower region 17, and is in contact with both the hole extraction region 15 and the lower region 17. There is. The electric field relaxation region 16 may be separated from the hole extraction region 15. In this case, a part of the body region 13 is arranged between the electric field relaxation region 16 and the hole extraction region 15. The electric field relaxation region 16 may be arranged so as to be within the existing range of the contact trench TR2 when viewed in a plan view, or may be arranged beyond the existing range of the contact trench TR2. Further, the electric field relaxation region 16 may be arranged so as to be within the existence range of the hole extraction region 15 when viewed in a plan view, or may be arranged beyond the existence range of the hole extraction region 15. good. The electric field relaxation region 16 is provided at a depth corresponding to the pn junction between the drift region 12 and the body region 13, and is arranged adjacent to the pn junction. The impurity concentration in the electric field relaxation region 16 is thinner than the impurity concentration in the body region 13, and is, for example, in the range of 5 × 10 ¹⁵ to 5 × 10 ¹⁶ cm ^-3 .

The lower region 17 is arranged below the electric field relaxation region 16. The lower region 17 may be arranged so as to be within the existing range of the contact trench TR2 when viewed in a plan view, or may be arranged beyond the existing range of the contact trench TR2. Further, the lower region 17 may be arranged so as to be within the existing range of the electric field relaxation region 16 when viewed in a plan view, or may be arranged beyond the existing range of the electric field relaxation region 16. The impurity concentration in the lower region 17 is higher than the impurity concentration in the electric field relaxation region 16, for example, in the range of 5 × 10 ¹⁶ to 5 × 10 ¹⁷ cm ^-3 . Further, the lower region 17 is arranged between adjacent gate trenches TR1, and a pair of drift partial regions 12a are arranged between the gate trench TR1 and the lower region 17. The lower region 17 and the pair of drift partial regions 12a are configured to have a super junction structure.

As described above, in the semiconductor device 1, the lower region 17, the electric field relaxation region 16, and the hole extraction region 15 are laminated in this order in the depth direction below the contact trench TR2. When the impurity concentration distribution in the depth direction below the contact trench TR2 is measured, the maximum value is located in the lower region 17 and the hole extraction region 15, and the minimum value is located in the electric field relaxation region 16. In other words, the region between the lower region and 17 and the hole extraction region 15 having an impurity concentration lower than that of the body region 13 can be referred to as an electric field relaxation region 16.

The trench gate portion 30 is arranged above the gate trench TR1 and has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 faces the body region 13 at a position separating the drift region 12 and the source region 14 via the gate insulating film 34. As a result, when the semiconductor device 1 is turned on, a channel (inversion layer) is formed in the body region 13 located at a position separating the drift region 12 and the source region 14.

The embedded plate portion 40 is arranged under the gate trench TR1 and has a plate electrode 42 and an embedded insulating film 44. The plate electrode 42 faces the drift region 12 via the embedded insulating film 44. The plate electrode 42 may be electrically connected to the source electrode 24 or may be electrically connected to the gate electrode 32. When the plate electrode 42 is electrically connected to the source electrode 24, when the semiconductor device 1 is turned off, a depletion layer is quickly formed in the drift region 12 in contact with the side surface of the embedded plate portion 40 due to the field plate effect. The withstand voltage of the semiconductor device 1 is improved. On the other hand, when the plate electrode 42 is electrically connected to the gate electrode 32, when the semiconductor device 1 is turned on, an accumulation layer is formed in the drift region 12 in contact with the side surface of the embedded plate portion 40, and the semiconductor device 1 is formed. On resistance decreases. In this example, the width of the gate trench TR1 is constant in the depth direction, but the width of the gate trench TR1 may change in the depth direction. The width of the gate trench TR1 may be tapered toward the deep part, and is buried so that a step is formed between the depth corresponding to the buried plate portion 40 and the depth corresponding to the trench gate portion 30. The width of the depth corresponding to the plate portion 40 may be smaller than the width of the depth corresponding to the trench gate portion 30.

Next, the operation of the semiconductor device 1 will be described. When a voltage higher than the source electrode 24 is applied to the drain electrode 22 and a voltage higher than the threshold voltage is applied to the gate electrode 32, the semiconductor device 1 is turned on. At this time, a channel (inverted layer) is formed in the body region 13 in contact with the side surface of the trench gate portion 30. The electrons injected from the source region 14 move to the drift region 12 via the channel formed in the body region 13, and the semiconductor device 1 is turned on. As described above, the lower region 17 and the pair of drift partial regions 12a are configured to have a super junction structure. Therefore, the impurity concentration in the drift partial region 12a is adjusted to be relatively high, and the drift resistance is low. The semiconductor device 1 can have a characteristic of low on-resistance.

When the voltage applied to the gate electrode 32 falls below the threshold voltage, the channel in the body region 13 disappears and the semiconductor device 1 is turned off. As described above, the lower region 17 and the pair of drift partial regions 12a are configured to have a super junction structure. Therefore, in this super junction structure, the electric field strength becomes uniform in the depth direction, and the semiconductor device 1 can have a high withstand voltage. Further, when a high voltage such as a surge is applied when the semiconductor device 1 is turned off, the avalanche breakdown can occur at the bottom of the gate trench TR1 or in the super junction structure. The holes generated by this avalanche breakdown are rapidly discharged to the source electrode 24 via the lower region 17, the electric field relaxation region 16, and the hole extraction region 15. As a result, the semiconductor device 1 can have a high avalanche withstand when off.

Next, the behavior of the semiconductor device 1 when the load is short-circuited will be described. If the load is short-circuited while the semiconductor device 1 is on, a high voltage (for example, 100 V) corresponding to the power supply voltage is applied between the drain electrode 22 and the source electrode 24. At this time, if the impurity concentration of the electric field relaxation region 16 is set to be higher than the impurity concentration of the body region 13, the vicinity of the side surface 16a of the electric field relaxation region 16 adjacent to the pn junction between the drift region 12 and the body region 13a. Becomes a high electric field region, and there is concern that avalanche breakdown will occur in this region. When the avalanche breakdown occurs in the vicinity of the side surface 16a, the avalanche current becomes the base current of the parasitic npn transistor (the parasitic npn transistor composed of the drift region 12, the body region 13 and the source region 14), and the secondary order in which the parasitic npn transistor operates becomes. Surrender will occur. In particular, as described above, in the semiconductor device 1 having the contact trench TR2, since the distance (gate pitch) between the adjacent gate trenches TR1 is short, the high electric field region and the parasitic npn transistor are close to each other and are secondary. Surrender is likely to occur.

On the other hand, in the semiconductor device 1, the impurity concentration in the electric field relaxation region 16 is formed to be thinner than the impurity concentration in the body region 13. As a result, even if a large voltage is applied to the semiconductor device 1 while the semiconductor device 1 is on, the electric field near the side surface 16a of the electric field relaxation region 16 is relaxed, and the operation of the parasitic npn transistor is suppressed. .. The semiconductor device 1 can have a characteristic of high on-resistance.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples exemplified above. Further, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in the present specification or the drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

1: Semiconductor device 10: Semiconductor layer 11: Drain region 12: Drift region 13: Body region 14: Source region 16: Electric field relaxation region 17: Lower region 22: Drain electrode 24: Source electrode 30: Trench gate portion 40: Embedded plate Part TR1: Gate trench TR2: Contact trench

Claims (3)

The first semiconductor region of the first conductive type and
The second conductive type second semiconductor region provided on the first semiconductor region and
The first conductive type third semiconductor region provided on the second semiconductor region and
A surface electrode filled in a contact trench that extends beyond the third semiconductor region and reaches the second semiconductor region.
A second conductive type carrier drawing region provided below the contact trench, and
A second conductive type electric field relaxation region provided below the carrier extraction region and adjacent to the pn junction between the first semiconductor region and the second semiconductor region.
The lower region of the second conductive type provided below the electric field relaxation region and
The second semiconductor region is arranged in a gate trench that extends beyond the third semiconductor region and the second semiconductor region and reaches the first semiconductor region, and is located at a position separating the first semiconductor region and the third semiconductor region. It is equipped with a trench gate section facing the semiconductor region.
The surface electrode filled in the contact trench is in contact with the third semiconductor region on its side surface and in contact with the carrier extraction region on its bottom surface.
The impurity concentration in the carrier extraction region is higher than the impurity concentration in the second semiconductor region.
The impurity concentration in the electric field relaxation region is thinner than the impurity concentration in the second semiconductor region.
A semiconductor device in which the impurity concentration in the lower region is higher than the impurity concentration in the electric field relaxation region. In the gate trench, a buried plate portion, which is arranged below the trench gate portion, is further provided.
The buried plate portion is
Buried insulating film and
The semiconductor device according to claim 1, further comprising a plate electrode facing the first semiconductor region via the embedded insulating film. The semiconductor device according to claim 2, wherein the lower region constitutes a super junction structure with the adjacent first semiconductor region.

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