JP7010100B2 - Motor drive circuits, semiconductor devices, and electronic devices - Google Patents

Description

The present invention relates to a motor drive circuit for driving a motor. Further, the present invention relates to a semiconductor device incorporating such a motor drive circuit, an electronic device using such a semiconductor device, and the like.

For example, in a motor driver IC, a DC motor is driven by using a motor drive circuit having a bridge circuit configured by connecting a high-side transistor and a low-side transistor in series. Generally, an H-bridge circuit (also referred to as a full-bridge circuit) is formed by combining two sets of high-side and low-side transistors, and the connection point of the first set of transistors and the connection point of the second set of transistors are connected to each other. Two terminals of the motor are connected between them. Thereby, the direction of the current flowing through the motor can be arbitrarily set.

In order to pass a large current to the motor, the high-side transistor may be composed of a P-channel ED (Extended Drain) MOS transistor, and the low-side transistor may be composed of an N-channel LD (Lateral Double-diffused) MOS transistor. In that case, the high-side transistor and the low-side transistor are arranged, for example, in the N-type first impurity region and the N-type second impurity region provided on the P-type semiconductor substrate, respectively. As a result, a parasitic NPN bipolar transistor is formed by using the N-type first impurity region as a collector, the P-type semiconductor substrate as a base, and the N-type second impurity region as an emitter.

A power supply potential on the high potential side (for example, + 42V) is supplied to the first impurity region, and a power supply potential on the low potential side (for example, 0V) is supplied to the semiconductor substrate. An N-type drain of a low-side transistor is arranged in the second impurity region, and one terminal of the motor is electrically connected to the drain. When a regenerative current flows in the high-speed decay mode, a negative potential (for example, about -1V) is applied from one terminal of the motor to the second impurity region.

As a result, a current flows from the base of the parasitic transistor to the emitter, and the parasitic transistor becomes conductive. When the hFE (DC current amplification factor) of the parasitic transistor is large, a large parasitic current exceeding the allowable limit may flow, causing structural destruction of the IC. In the prior art, measures have been taken to ensure a sufficient distance between a plurality of transistors in order to suppress the hFE of the parasitic transistor to a permissible value or less.

As a related technique, Patent Document 1 discloses a semiconductor device including an H-bridge circuit, which is composed of four power transistors per channel and is used for driving control of a motor. In FIG. 8 of Patent Document 1, the horizontal spacing and the vertical spacing of the cell portions 21, 22, 25, and 26 corresponding to the four power transistors constituting the H-bridge circuit are all equal and are represented as Z. There is.

Further, Patent Document 2 discloses a power supply device including a bridge rectifier circuit composed of four transistors, which rectifies an AC voltage and supplies DC power. In paragraphs 0069-0070 and FIG. 2 of Patent Document 2, as a countermeasure against the latch-up caused by the conduction of the parasitic transistor, the P channel transistors P1 and P2 are surrounded by the high potential side power supply wiring LVdd, and the N channel transistor N3 and It is described that the N4 is surrounded by the low potential side power supply wiring LVss, and the transistors P1, P2, N3, and N4 are separated sufficiently apart from each other.

Japanese Unexamined Patent Publication No. 2009-181996 (paragraphs 0001-0002, 0049-0050, FIG. 8). Japanese Unexamined Patent Publication No. 2003-309978 (paragraphs 0001-0003, 0069-0070, FIG. 2)

However, as described in Patent Document 2, if the plurality of transistors are sufficiently separated from each other and separated from each other, the latch-up caused by the conduction of the parasitic transistors can be prevented. , The circuit area (chip size) will increase. Further, Patent Documents 1 and 2 do not disclose that the high-side transistor and the low-side transistor are arranged in a plurality of impurity regions (wells, etc.) of the same conductive type.

Therefore, in view of the above points, the first object of the present invention is to have a plurality of impurities regions of the same conductive type in which a plurality of transistors constituting the H-bridge circuit are arranged or configured in the motor drive circuit, and the opposite conductivity. This is to suppress the increase in the circuit area while preventing the structural destruction caused by the conduction of the parasitic bipolar transistor formed by the semiconductor substrate of the mold. A second object of the present invention is to provide a semiconductor device incorporating such a motor drive circuit. Furthermore, a third object of the present invention is to provide an electronic device or the like using such a semiconductor device.

In order to solve at least a part of the above problems, the motor drive circuit according to the first aspect of the present invention is lower than the first node to which the first power supply potential is supplied and the first power supply potential. A first H bridge connected to a second node to which a second power potential of potential is supplied and a third node and a fourth node connected to two terminals of a motor to be driven, respectively. A first P having a circuit, the first H-bridge circuit being arranged in the N-type first impurity region in a P-type semiconductor substrate and connected between the first node and the third node. The channel MOS transistor and the N-type second impurity region on the semiconductor substrate, or directly arranged on the semiconductor substrate, have an N-type second impurity region, and the second node and the third. A first N-channel MOS transistor connected to the node of No. 1 and a second N-channel MOS transistor arranged in a third impurity region of the N type in the semiconductor substrate and connected between the first node and the fourth node. A second node having two P-channel MOS transistors and an N-type fourth impurity region located in the N-type fourth impurity region on the semiconductor substrate or directly arranged on the semiconductor substrate. The distance between the first impurity region and the third impurity region includes the second N-channel MOS transistor connected between the first impurity region and the third impurity region, and the first impurity region and the second impurity region are included. It is smaller than the distance between the impurity region, smaller than the distance between the third impurity region and the fourth impurity region, and smaller than the distance between the second impurity region and the fourth impurity region. ..

Here, the first P-channel MOS transistor is an EDMOS transistor, the second P-channel MOS transistor is an EDMOS transistor, the first N-channel MOS transistor is an LDMOS transistor, and the second N-channel. The MOS transistor may be an LDMOS transistor.

Further, in the motor drive circuit according to the second aspect of the present invention, the first node to which the first power supply potential is supplied and the second power supply potential lower than the first power supply potential are supplied. The first H-bridge circuit comprises a first H-bridge circuit connected to a second node and a third node and a fourth node connected to two terminals of a motor to be driven, respectively. , The first N-channel EDMOS transistor arranged in the first P-type impurity region on the N-type semiconductor substrate and connected between the second node and the third node, and the P-type on the semiconductor substrate. The first P-channel LDMOS transistor arranged in the second impurity region and connected between the first node and the third node, and the P-type third impurity region in the semiconductor substrate are arranged in the third impurity region. A second N-channel EDMOS transistor connected between the second node and the fourth node, and a P-type fourth impurity region in the semiconductor substrate, the first node and the fourth node. The distance between the first impurity region and the third impurity region is the distance between the first impurity region and the second impurity region, including the second P-channel LDMOS transistor connected between them. Less than, less than the distance between the third impurity region and the fourth impurity region, and less than the distance between the second impurity region and the fourth impurity region.

According to the first or second aspect of the present invention, in the motor drive circuit, a plurality of impurities regions of the same conductive type in which a plurality of transistors constituting the H-bridge circuit are arranged or configured, and a conductive semiconductor opposite to the region of impurities. The hFE (DC current amplification factor) of the parasitic bipolar transistor formed by the substrate is suppressed to the allowable value or less, and the possibility that the parasitic transistor conducts in the circuit operation while preventing the structural destruction caused by the conduction of the parasitic transistor. By reducing the distance between the first impurity region and the third impurity region, which have a low value, an increase in the circuit area can be suppressed and the cost can be suppressed.

Here, the distance between the first impurity region and the second impurity region, the distance between the third impurity region and the fourth impurity region, and the second impurity region and the fourth impurity region. The distances between and may be equal to each other. Thereby, between the first impurity region and the second impurity region, between the third impurity region and the fourth impurity region, and between the second impurity region and the fourth impurity region. The hFE of each of the parasitic transistors formed can be made substantially the same to improve the layout efficiency.

Further, in the semiconductor substrate, the motor drive circuit is located between the first impurity region and the second impurity region, the side of the first impurity region on the second impurity region side, and the second impurity region. At least one first guard region of the same conductive type as the semiconductor substrate extending along the side of the first impurity region, and the third impurity region and the fourth impurity region in the semiconductor substrate. At least of the same conductive type as the semiconductor substrate, extending along the side of the third impurity region on the side of the fourth impurity region and the side of the fourth impurity region on the side of the third impurity region. In the semiconductor substrate, between one second guard region and the second impurity region and the fourth impurity region, the side of the second impurity region on the fourth impurity region side, and the fourth impurity region. It may extend along the side of the region on the side of the second impurity region and further include at least one third guard region of the same conductive type as the semiconductor substrate. Thereby, between the first impurity region and the second impurity region, between the third impurity region and the fourth impurity region, and between the second impurity region and the fourth impurity region. , It is possible to prevent the depletion layer from spreading and punching through.

In that case, the motor drive circuit includes a plurality of first guard regions, a plurality of second guard regions, and a plurality of third guard regions, and also has a first impurity region and a first impurity region in the semiconductor substrate. It extends along the side of the first impurity region on the third impurity region side and the side of the third impurity region on the first impurity region side between the third impurity region and the semiconductor substrate. Further comprising at least one fourth guard region of the same conductive type, the number of fourth guard regions is less than the number of first guard regions, less than the number of second guard regions, third. It may be less than the number of guard areas in. As a result, the number of fourth guard regions provided between the first impurity region and the third impurity region, which are unlikely to cause punch-through in circuit operation, is reduced, and an increase in circuit area is suppressed. can do.

Alternatively, in the semiconductor substrate, the motor drive circuit is located between the first impurity region and the third impurity region, the side of the first impurity region on the third impurity region side, and the third impurity region. It extends along the side of the first impurity region and further includes a fourth guard region of the same conductive type as the semiconductor substrate, and the width of the fourth guard region is larger than the width of the first guard region. It may be small, smaller than the width of the second guard area, and smaller than the width of the third guard area. As a result, the width of the fourth guard region provided between the first impurity region and the third impurity region, which are unlikely to cause punch-through in circuit operation, is reduced to suppress the increase in circuit area. can do.

In the above, the motor drive circuit further includes a second H-bridge circuit having the same configuration as the first H-bridge circuit, and the first to fourth impurity regions and the second H of the first H-bridge circuit. The distance between the first to fourth impurity regions of the bridge circuit may be greater than or equal to the distance between the second impurity region and the fourth impurity region in the first or second H-bridge circuit. .. As a result, the parasitic bipolar transistor formed by a plurality of impurities regions of the same conductive type in which a plurality of transistors constituting the first and second H-bridge circuits are arranged or configured and a semiconductor substrate of the opposite conductive type. It is possible to suppress hFE to a permissible value or less and prevent structural destruction caused by conduction of the parasitic transistor.

Alternatively, the motor drive circuit extends between the second H-bridge circuit having the same configuration as the first H-bridge circuit and the first H-bridge circuit and the second H-bridge circuit in the semiconductor substrate. Further, a plurality of fifth guard regions of the same conductive type as the semiconductor substrate are further provided, and the number of the fifth guard regions is equal to or greater than the number of the first guard regions and equal to or greater than the number of the second guard regions. And may be greater than or equal to the number of third guard areas. Thereby, punch-through between the first H-bridge circuit and the second H-bridge circuit can be effectively prevented.

Alternatively, the motor drive circuit extends between the second H-bridge circuit having the same configuration as the first H-bridge circuit and the first H-bridge circuit and the second H-bridge circuit in the semiconductor substrate. Further, a fifth guard region of the same conductive type as the semiconductor substrate is further provided, and the width of the fifth guard region is equal to or greater than the width of the first guard region and equal to or greater than the width of the second guard region. , It may be equal to or larger than the width of the third guard area. Thereby, punch-through between the first H-bridge circuit and the second H-bridge circuit can be effectively prevented.

The semiconductor device according to the third aspect of the present invention is arranged in any of the above motor drive circuits and the fifth impurity region on the semiconductor substrate, or is directly arranged on the semiconductor substrate and has a fifth impurity region. A drive control circuit including a transistor having a sixth impurity region and a switching regulator control circuit including a transistor arranged in a sixth impurity region on the semiconductor substrate or directly arranged on the semiconductor substrate and having the sixth impurity region are provided. , The distance between the fifth impurity region and the first to fourth impurity regions is equal to or greater than the distance between the second impurity region and the fourth impurity region, and the sixth impurity region and the first The distance between the fourth impurity region and the fourth impurity region is equal to or greater than the distance between the second impurity region and the fourth impurity region.

According to the third aspect of the present invention, a parasitic bipolar formed by a plurality of impurities regions of the same conductive type in which a plurality of transistors constituting the H-bridge circuit are arranged or configured and a semiconductor substrate of the opposite conductive type. Built-in drive control circuit and switching regulator control circuit that are not easily affected by noise even if the motor drive circuit performs switching operation, along with a motor drive circuit that suppresses the increase in circuit area while preventing structural destruction caused by transistor conduction. Can provide the semiconductor device.

The electronic device according to the fourth aspect of the present invention includes any of the above motor drive circuits and a motor having two terminals connected to a third node and a fourth node, respectively.

According to the fourth aspect of the present invention, a parasitic bipolar formed by a plurality of impurities regions of the same conductive type in which a plurality of transistors constituting the H-bridge circuit are arranged or configured, and a semiconductor substrate of the opposite conductive type. It is possible to provide a highly reliable and compact electronic device by using a motor drive circuit that suppresses an increase in circuit area while preventing structural destruction caused by conduction of transistors.

The circuit diagram which shows the structural example of a part of the electronic device which concerns on 1st Embodiment of this invention. The circuit diagram for demonstrating the operation example of the motor drive circuit shown in FIG. FIG. 2 is a cross-sectional view showing a specific example of the motor drive circuit shown in FIG. The figure which shows the example of the change of hFE of a parasitic transistor. The plan view which shows the example of the layout of the motor drive circuit shown in FIG. The circuit diagram which shows the structural example of a part of the electronic device which concerns on 2nd Embodiment of this invention. FIG. 6 is a plan view showing a first example of the layout of the semiconductor device shown in FIG. FIG. 6 is a plan view showing a second example of the layout of the semiconductor device shown in FIG. FIG. 6 is a plan view showing a third example of the layout of the semiconductor device shown in FIG. FIG. 6 is a plan view showing a fourth example of the layout of the semiconductor device shown in FIG. The cross-sectional view which shows the specific example of the motor drive circuit in 3rd Embodiment. The cross-sectional view which shows the specific example of the motor drive circuit in 4th Embodiment. The cross-sectional view which shows the specific example of the motor drive circuit in 5th Embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same reference number is assigned to the same component, and duplicate description will be omitted.
<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration example of a part of an electronic device according to the first embodiment of the present invention. The electronic device corresponds to a printer equipped with a motor, a scanner, a projector, or the like, but in the following, a printer will be described as an example.

As shown in FIG. 1, this electronic device includes a motor 100, a semiconductor device (motor driver IC) 200 according to the first embodiment of the present invention, a SoC (System on a Chip) 300, and a resistor R1. Includes. In addition, a part of the component shown in FIG. 1 may be omitted or changed, or another component may be added to the component shown in FIG.

The motor 100 is a DC brush motor, a DC brushless motor, a stepping motor, or the like. For example, the motor 100 is used to move a carriage on which a print head of a printer is mounted, or to convey a print medium (paper or the like) to be printed using ink discharged from the print head.

The semiconductor device 200 includes a drive control circuit 201 and a motor drive circuit 202 that drives the motor 100 under the control of the drive control circuit 201. At least a part of the components of the drive control circuit 201 and the motor drive circuit 202 may be composed of discrete components.

For example, the semiconductor device 200 is configured by housing an IC chip in which a circuit is formed on a silicon substrate in a package. In that case, the first node N1 to the sixth node N6 of the semiconductor device 200 may be a pad (terminal) of the IC chip or a pin (terminal) provided in the package.

The resistance R1 is a resistance for measuring the drive current flowing through the motor drive circuit 202, and has a small resistance value of, for example, about 1Ω. Although the resistor R1 is shown as an external component of the semiconductor device 200 in FIG. 1, the resistor R1 may be built in the semiconductor device 200. Alternatively, if other means are used to measure the drive current, the resistor R1 may be omitted.

The SoC300 includes a processor, a memory, and the like, and controls each part of the electronic device. Note that the SoC is a semiconductor device in which a series of functions (systems) required for electronic devices and the like are integrated in one semiconductor chip. By communicating with the semiconductor device 200 by the serial interface method, the SoC 300 supplies the control data DATA necessary for driving the motor 100 to the semiconductor device 200 together with the clock signal CLK.

<Motor driver configuration>
The motor drive circuit 202 includes a first node N1 to which a first power potential VBB (for example, + 42V) is supplied, and a second power potential VSS (in FIG. 1) having a lower potential than the first power potential VBB. , Ground potential 0V) is supplied to the second node N2, and the H-bridge circuit connected to the third node N3 and the fourth node N4 connected to the two terminals of the motor 100 to be driven, respectively. It is equipped with.

The second power potential VSS is also supplied to the fifth node N5. As shown in FIG. 1, when the resistor R1 is connected between the fifth node N5 and the second node N2, the second power supply potential VSS is the second node N2 via the resistor R1. Is supplied to.

The H-bridge circuit is connected between the first P-channel MOS transistor QP1 connected between the first node N1 and the third node N3, and between the second node N2 and the third node N3. It also includes a first N-channel MOS transistor QN1. Further, the H-bridge circuit is formed between the second P-channel MOS transistor QP2 connected between the first node N1 and the fourth node N4, and between the second node N2 and the fourth node N4. It includes a second N-channel MOS transistor QN2 connected.

In the first embodiment, the first P-channel MOS transistor QP1 is an EDMOS transistor, the second P-channel MOS transistor QP2 is an EDMOS transistor, and the first N-channel MOS transistor QN1 is an LDMOS transistor. The second N-channel MOS transistor QN2 is an LDMOS transistor.

The high-side transistor QP1 has a source connected to the first node N1, a drain connected to the third node N3, and a gate to which the drive signal T11 is supplied. The low-side transistor QN1 has a drain connected to the third node N3, a source connected to the second node N2, and a gate to which the drive signal T12 is supplied.

Further, the high-side transistor QP2 has a source connected to the first node N1, a drain connected to the fourth node N4, and a gate to which the drive signal T21 is supplied. The low-side transistor QN2 has a drain connected to the fourth node N4, a source connected to the second node N2, and a gate to which the drive signal T22 is supplied.

The drive control circuit 201 has a high-side predriver 11 that generates a drive signal T11 according to the control signal S11, a low-side predriver 12 that generates a drive signal T12 according to the control signal S12, and a high-side predriver 12 that generates a drive signal T21 according to the control signal S21. It includes a side predriver 21 and a low side predriver 22 that generates a drive signal T22 according to the control signal S22.

Further, the drive control circuit 201 includes a comparator 30 and a switching control circuit 40. The comparator 30 compares the voltage generated between both ends of the resistor R1 when a current flows through the motor 100 with the set control voltage VC, and generates a comparison result signal COMP representing the comparison result.

The switching control circuit 40 is composed of, for example, a logic circuit including an RS type flip-flop or the like. The switching control circuit 40 operates according to the data DATA and the clock signal CLK supplied from the SoC 300, and the pulse width is modulated by performing pulse width modulation (PWM) based on the comparison result signal COMP output from the comparator 30. The control signals S11 to S22 are generated. Thereby, the current flowing through the motor 100 is controlled.

<Motor driver operation>
FIG. 2 is a circuit diagram for explaining an operation example of the motor drive circuit shown in FIG. Since the motor 100 has an inductance component, it is represented by an inductor symbol in FIG. The motor 100 has two terminals connected to the third node N3 and the fourth node N4, respectively.

In the charge mode shown in FIG. 2A, the transistors QP1 and QN2 are controlled to the ON state (ON), and the transistors QN1 and QP2 are controlled to the OFF state (OFF). As a result, a current flows from the first node N1 to the fifth node N5 via the transistor QP1, the motor 100, the transistor QN2, and the resistor R1, and the motor 100 rotates.

In the charge mode, the current flowing through the motor 100 gradually increases, and the voltage across the resistor R1 also gradually increases. In order to control the rotation speed or torque of the motor 100, the transistors QP1 and QN2 are intermittently turned on. When the voltage across the resistor R1 becomes larger than the control voltage VC, the comparison result signal COMP of the comparator 30 is activated to a high level. As a result, the switching control circuit 40 shifts from the charge mode to the high-speed attenuation mode.

In the high-speed attenuation mode shown in FIG. 2B, the transistors QP1 and QN2 are controlled to be in the off state, and the transistors QN1 and QP2 are controlled to be in the on state. Alternatively, if there is a parasitic diode in the forward direction from the source to the drain of the transistor QN1 and a parasitic diode in the forward direction from the drain to the source of the transistor QP2, the transistors QN1 and QP2 are controlled to be in the off state. May be done.

In the high-speed attenuation mode, the counter electromotive force of the motor 100 causes a current to flow from the fifth node N5 to the first node N1 via the resistor R1, the transistor QN1, the motor 100, and the transistor QP2. As a result, the speed of the motor 100 is adjusted and the electric power regeneration operation is performed. At that time, for example, the potential of the third node N3 drops to about -1V, and the potential of the fourth node N4 rises to about + 43V. In this way, a negative potential is applied to the drains of the transistors QP1 and QN1 electrically connected to the third node N3.

Since the energy stored in the motor 100 is released by the power regeneration operation, the current flowing through the motor 100 gradually decreases. For example, when the current flowing through the motor 100 approaches zero or a certain period of time has elapsed from the start of the high-speed attenuation mode, the switching control circuit 40 shifts from the high-speed attenuation mode to the low-speed attenuation mode. The switching control circuit 40 may omit the low-speed attenuation mode and restart the charge mode.

In the low-speed attenuation mode shown in FIG. 2C, the transistors QP1 and QP2 are controlled to be in the off state, and the transistors QN1 and QN2 are controlled to be in the on state. Alternatively, if there is a parasitic diode in the forward direction from the source of the transistor QN1 toward the drain, the transistor QN1 may be controlled to the off state.

In the low speed attenuation mode, the counter electromotive force of the motor 100 causes a current to flow from the fourth node N4 to the third node N3 via the transistors QN2 and QN1. As a result, the motor 100 is braked and the energy stored in the motor 100 is released, so that the current flowing through the motor 100 gradually decreases.

For example, when the current flowing through the motor 100 approaches zero or a certain period of time has elapsed from the start of the low-speed attenuation mode, the switching control circuit 40 shifts from the low-speed attenuation mode to the charge mode. After that, by repeating the charge mode and the attenuation mode to control the peak value of the current flowing through the motor 100 to be constant, the rotation speed or torque of the motor 100 is kept substantially constant.

On the other hand, by controlling the transistors QN1 and QP2 in the on state and controlling the transistors QP1 and QN2 in the off state, the transistor QP2, the motor 100, the transistor QN1 and the resistor R1 are controlled from the first node N1. A current flows through the fifth node N5, and the motor 100 reverses. Even when the motor 100 is reversed, the rotation speed or torque of the motor 100 can be kept substantially constant by performing the same control as when the motor 100 is rotated in the normal direction.

<Specific example of motor drive circuit>
FIG. 3 is a cross-sectional view showing a specific example of the motor drive circuit shown in FIG. In the specific example shown in FIG. 3, a P-type semiconductor substrate (for example, a silicon substrate containing P-type impurities such as boron) 210 is used. The first P-channel MOS transistor QP1 is an EDMOS transistor and is arranged in the N-type first impurity region 211 on the semiconductor substrate 210. Further, the first N-channel MOS transistor QN1 is an LDMOS transistor, and is arranged in the N-type second impurity region 212 on the semiconductor substrate 210.

Although not shown in FIG. 3, the second P-channel MOS transistor QP2 is an EDMOS transistor and is arranged in the N-type third impurity region on the semiconductor substrate 210. Further, the second N-channel MOS transistor QN2 is an LDMOS transistor and is arranged in the N-type fourth impurity region on the semiconductor substrate 210. In the following, the configurations of the transistors QP1 and QN1 will be described as an example, but the transistors QP2 and QN2 also have the same configurations.

The first impurity region 211 includes an N-type contact region 221, a P-type impurity region 222 that constitutes the source of the transistor QP1, a P-type impurity region 223 that constitutes the extended drain of the transistor QP1, and the transistor QP1. A P-type impurity region 224 constituting the drain of the above is arranged. The P-type impurity region 224 has a higher impurity concentration than the P-type impurity region 223.

In the second impurity region 212, a P-type body region 231 and an N-type impurity region 232 constituting the drain of the transistor QN1 are arranged. In the P-type body region 231, a P-type contact region 233 and an N-type impurity region 234 constituting the source of the transistor QN1 are arranged.

In the semiconductor substrate 210, a P-type impurity region (P ⁺ ) 217 having a higher impurity concentration than that of the semiconductor substrate 210 is arranged between the first impurity region 211 and the second impurity region 212, and P. A P-type contact region 218 is arranged in the impurity region 217 of the mold. The P-type impurity region 217 corresponds to a guard region for preventing the depletion layer from spreading between the first impurity region 211 and the second impurity region 212 to cause punch-through.

Further, a gate electrode 241 of the transistor QP1 and a gate electrode 242 of the transistor QN1 are arranged on the semiconductor substrate 210 via a gate insulating film. Further, on the semiconductor substrate 210 on which the gate electrodes 241 and 242 and the like are arranged, a wiring layer including a plurality of wirings is arranged via an interlayer insulating film. The interlayer insulating film and the wiring layer may have a multilayer structure, if necessary.

The N-type contact region 221 and the P-type impurity region 222 are connected to the first node N1 via wiring. The P-shaped contact region 218 is connected to the fifth node N5 via wiring. The P-type contact region 233 and the N-type impurity region 234 are connected to the second node N2 via wiring. The P-type impurity region 224 and the N-type impurity region 232 are connected to the third node N3 via wiring.

Here, as shown in FIG. 3, a parasitic NPN bipolar transistor is formed by using the N-type first impurity region 211 as a collector, the P-type semiconductor substrate 210 as a base, and the N-type second impurity region 212 as an emitter. Has been done. The first power supply potential VBB (for example, + 42V) is supplied from the first node N1 to the first impurity region 211 via the N-type contact region 221, and the fifth node N5 is supplied to the semiconductor substrate 210. A second power supply potential VSS (eg, 0V) is supplied from the P-type contact region 218 and the P-type impurity region 217.

In the high-speed attenuation mode shown in FIG. 2 (B), when a regenerative current flows from the fifth node N5 toward the first node N1 via the transistors QN1 and QP2, a negative potential (negative potential () to the third node N3. For example, about -1V) is applied. Therefore, a negative potential is applied to the second impurity region 212 from the third node N3 via the N-type impurity region 232.

As a result, the parasitic transistor conducts, and the parasitic current Ip flows from the first impurity region 211 toward the second impurity region 212 via the semiconductor substrate 210. When the hFE (DC current amplification factor) of the parasitic transistor is large, a large parasitic current Ip exceeding the allowable limit may flow, causing structural destruction of the IC.

FIG. 4 is a diagram showing an example of a change in hFE of a parasitic transistor with respect to the distance between the two transistors shown in FIG. In FIG. 4, the horizontal axis represents the distance Dw between the first impurity region 211 in which the transistor QP1 shown in FIG. 3 is arranged and the second impurity region 212 in which the transistor QN1 is arranged, and the vertical axis represents the distance Dw. Represents the hFE of the parasitic transistor.

As shown in FIG. 4, the smaller the distance Dw between the first impurity region 211 and the second impurity region 212, the larger the hFE of the parasitic transistor. Therefore, by setting the distance Dw between the first impurity region 211 and the second impurity region 212 to a predetermined distance or more, the hFE of the parasitic transistor is suppressed to a permissible value or less that does not cause structural destruction of the IC. Can be done. In the example shown in FIG. 4, if the distance Dw between the first impurity region 211 and the second impurity region 212 is set to about 40 μm or more, the hFE of the parasitic transistor can be suppressed to an allowable value or less.

<Layout>
FIG. 5 is a plan view showing an example of the layout of the motor drive circuit shown in FIG. FIG. 5 shows the layout area 210a of the H-bridge circuit in the semiconductor substrate 210. In the layout area 210a, a first impurity region 211 in which the transistor QP1 is arranged, a second impurity region 212 in which the transistor QN1 is arranged, a third impurity region 213 in which the transistor QP2 is arranged, and a transistor are included. A fourth impurity region 214 in which the QN2 is arranged is provided.

A second power supply potential VSS is supplied to the semiconductor substrate 210, and a first power supply potential VBB is supplied to the first impurity region 211 and the third impurity region 213. As a result, it is unlikely that the parasitic NPN bipolar transistor formed by the N-type first impurity region 211, the P-type semiconductor substrate 210, and the N-type third impurity region 213 will conduct.

Therefore, the distance A between the first impurity region 211 and the third impurity region 213 can be set to be smaller than a predetermined distance. The distance A is set based on various device characteristic values such as the withstand voltage of the PN junction. In the present application, the "distance" means the shortest distance between two regions.

On the other hand, in the high-speed attenuation mode shown in FIG. 2B, when a negative potential is applied to the second impurity region 212, the N-type first impurity region 211, the P-type semiconductor substrate 210, and N are used. The parasitic NPN bipolar transistor formed by the second impurity region 212 of the mold may conduct. Therefore, the distance B1 between the first impurity region 211 and the second impurity region 212 needs to be set to a predetermined distance or more.

Similarly, in the high-speed attenuation mode, when a negative potential is applied to the fourth impurity region 214, the N-type third impurity region 213, the P-type semiconductor substrate 210, and the N-type fourth impurity region are applied. The parasitic NPN bipolar transistor formed in the region 214 may conduct. Therefore, the distance B2 between the third impurity region 213 and the fourth impurity region 214 needs to be set to a predetermined distance or more.

Further, in the high-speed attenuation mode, when a negative potential is applied to the second impurity region 212 and a positive potential is applied to the fourth impurity region 214, and when a positive potential is applied to the second impurity region 212, a positive potential is applied to the second impurity region 212. When a negative potential is applied to the fourth impurity region 214 while the above is applied, the N-type second impurity region 212, the P-type semiconductor substrate 210, and the N-type fourth impurity region 214 There is a risk that the parasitic NPN bipolar transistor formed in will conduct. Therefore, the distance C between the second impurity region 212 and the fourth impurity region 214 needs to be set to a predetermined distance or more.

From the above, the following equations (1) to (3) are derived.
A <B1 ... (1)
A <B2 ... (2)
A <C ... (3)
That is, in the present embodiment, the distance A between the first impurity region 211 and the third impurity region 213 is larger than the distance B1 between the first impurity region 211 and the second impurity region 212. Smaller, smaller than the distance B2 between the third impurity region 213 and the fourth impurity region 214, and smaller than the distance C between the second impurity region 212 and the fourth impurity region 214. Set. For example, the distance A may be set to be 1/2 or less of the distance B1, 1/2 or less of the distance B2, and 1/2 or less of the distance C.

As a result, in the motor drive circuit 202, the hFE (DC current) of the parasitic NPN bipolar transistor formed by the N-type plurality of impurity regions in which the plurality of transistors constituting the H-bridge circuit are arranged and the P-type semiconductor substrate 210 The amplification factor) is suppressed to below the permissible value to prevent structural destruction caused by the conduction of the parasitic transistor, and the first impurity region 211 and the third impurity region where the possibility that the parasitic transistor is unlikely to conduct in the circuit operation are low. By reducing the distance between the 213 and the 213, an increase in the circuit area can be suppressed and the cost can be suppressed.

Further, the maximum voltage applied between the first impurity region 211 and the second impurity region 212, the maximum voltage applied between the third impurity region 213 and the fourth impurity region 214, and the maximum voltage applied. It is substantially equal to the maximum voltage applied between the second impurity region 212 and the fourth impurity region 214. Therefore, as represented by the following equation (4), the distance B1 between the first impurity region 211 and the second impurity region 212, and the third impurity region 213 and the fourth impurity region 214. The distance B2 between them and the distance C between the second impurity region 212 and the fourth impurity region 214 may be set to be equal to each other.
B1 = B2 = C ... (4)

As a result, between the first impurity region 211 and the second impurity region 212, between the third impurity region 213 and the fourth impurity region 214, and between the second impurity region 212 and the fourth impurity region 212. The hFE of the parasitic transistor formed between the region 214 and the region 214 can be made substantially the same to improve the layout efficiency.

Specifically, the distance A may be set to about 20 μm, and each of the distance B1, the distance B2, and the distance C may be set to about 60 μm. The boundary on the left side in the figure of the first impurity region 211 and the boundary on the left side in the figure of the second impurity region 212 do not have to be in a straight line, and the boundary on the right side in the figure of the third impurity region 213 does not have to be in line. The boundary and the boundary on the right side of the figure of the fourth impurity region 214 do not have to be in a straight line.

<Second embodiment>
FIG. 6 is a circuit diagram showing a configuration example of a part of the electronic device according to the second embodiment of the present invention. As shown in FIG. 6, this electronic device includes at least one motor 100a or 100b, a semiconductor device (motor driver IC) 200 according to a second embodiment of the present invention, a SoC300, an analog circuit IC400, and a power supply. Includes circuit 500. A part of the component shown in FIG. 6 may be omitted or changed, or another component may be added to the component shown in FIG.

The semiconductor device 200 includes at least one motor drive circuit 202a or 202b for driving at least one motor 100a or 100b, and a drive control circuit 203. FIG. 6 shows, as an example, a motor drive circuit 202a for driving a carriage motor 100a for moving a carriage on which a printer print head is mounted, and a print medium (paper) printed using ink discharged from the print head. Etc.) is shown as a motor drive circuit 202b for driving a paper feed motor 100b for transporting the paper feed motor 100b.

The motor drive circuits 202a and 202b include a first H-bridge circuit and a second H-bridge circuit similar to the H-bridge circuit of the motor drive circuit 202 in the first embodiment shown in FIG. 1, respectively. A resistor R1 (FIG. 1) may be externally attached to each of the motor drive circuits 202a and 202b. The drive control circuit 203 is composed of a logic circuit and an analog circuit, includes two drive control circuits 201 (FIG. 1) for controlling the motor drive circuits 202a and 202b, and further controls other parts of the electronic device. It may include a control circuit to be used.

Further, the semiconductor device 200 has a built-in switching regulator control circuit 204. The switching regulator control circuit 204 is composed of a logic circuit and an analog circuit, and peripheral parts such as a diode D1, an inductor L1, a capacitor C1, and resistors R2 and R3 are externally attached to form a switching regulator. The switching regulator steps down the power supply voltage (for example, 42V) supplied from the power supply circuit 500 to generate a power supply voltage (for example, 3.3V) supplied to the SoC300, the analog circuit IC400, and the like.

<Layout 1>
FIG. 7 is a plan view showing a first example of the layout of the semiconductor device shown in FIG. FIG. 7 shows a layout area 210a in which the first H-bridge circuit (Ch1) is arranged, a layout area 210b in which the second H-bridge circuit (Ch2) is arranged, and a drive control circuit 203 in the semiconductor substrate 210. The layout area 210c in which the switching regulator control circuit 204 is arranged and the layout area 210d in which the switching regulator control circuit 204 is arranged are shown.

Each of the layout regions 210a and 210b is provided with N-type first impurity regions 211 to fourth impurity regions 214. Further, the layout region 210c is provided with an N-type fifth impurity region 215, and the layout region 210d is provided with an N-type sixth impurity region 216. In FIG. 7, the layout area 210a and the layout area 210b are arranged on the left and right sides in the drawing, but the layout area 210a and the layout area 210b may be arranged on the upper and lower sides in the drawing. Further, the layout area 210c and the layout area 210d may be arranged in reverse, or may be arranged vertically in the figure.

Among the transistors constituting the first H-bridge circuit (Ch1), the first P-channel MOS transistor is arranged in the first impurity region 211 in the layout region 210a, and the first N-channel MOS transistor is laid out. It is arranged in the second impurity region 212 in the region 210a. Further, the second P-channel MOS transistor is arranged in the third impurity region 213 in the layout region 210a, and the second N-channel MOS transistor is arranged in the fourth impurity region 214 in the layout region 210a.

Among the transistors constituting the second H-bridge circuit (Ch2), the first P-channel MOS transistor is arranged in the first impurity region 211 in the layout region 210b, and the first N-channel MOS transistor is laid out. It is arranged in the second impurity region 212 in the region 210b. Further, the second P-channel MOS transistor is arranged in the third impurity region 213 in the layout region 210b, and the second N-channel MOS transistor is arranged in the fourth impurity region 214 in the layout region 210b.

The layout conditions of the first H-bridge circuit (Ch1) and the second H-bridge circuit (Ch2) are the same as the layout conditions of the H-bridge circuit in the first embodiment. In FIG. 7, the distance between the second impurity region 212 and the fourth impurity region 214 in the layout regions 210a and 210b is represented by “C”. Further, the first impurity region 211 to the fourth impurity region 214 of the first H-bridge circuit (Ch1) and the first impurity region 211 to the fourth impurity region 214 of the second H-bridge circuit (Ch2). The distance between them (the shortest distance) is represented by "D".

Since the motor drive circuit 202a and the motor drive circuit 202b operate asynchronously, in the example shown in FIG. 7, the second N-channel MOS transistor of the first H-bridge circuit (Ch1) is arranged in the layout area 210a. What is the relationship between the potential of the impurity region 214 of 4 and the potential of the second impurity region 212 in which the first N-channel MOS transistor of the second H-bridge circuit (Ch2) is arranged in the layout region 210b? It is uncertain whether it will be.

Therefore, in the present embodiment, the first impurity region 211 to the fourth impurity region 214 of the first H-bridge circuit (Ch1) and the first impurity region 211 to the second impurity region 211 to the second H-bridge circuit (Ch2). The distance D between the impurity region 214 of 4 is between the second impurity region 212 and the fourth impurity region 214 in the first H-bridge circuit (Ch1) or the second H-bridge circuit (Ch2). The distance is set to C or more.

As a result, it is formed by a plurality of N-type impurity regions in which a plurality of transistors constituting the first H-bridge circuit (Ch1) and the second H-bridge circuit (Ch2) are arranged, and a P-type semiconductor substrate 210. The hFE of the parasitic NPN bipolar transistor can be suppressed to a permissible value or less, and the structural destruction caused by the conduction of the parasitic transistor can be prevented.

Further, the drive control circuit 203 includes a P-channel MOS transistor arranged in the fifth impurity region 215 in the semiconductor substrate 210 or directly arranged in the semiconductor substrate 210 and having the fifth impurity region 215. .. In FIG. 7, when the fifth impurity region 215 is arranged closest to the layout region 210a or 210b in the layout region 210c, the fifth impurity region 215 and the first impurity regions 211 to the fourth impurity regions are shown. The distance to 214 is represented by "E".

Similarly, the switching regulator control circuit 204 is a P-channel MOS transistor (P) which is arranged in the sixth impurity region 216 in the semiconductor substrate 210 or is directly arranged in the semiconductor substrate 210 and has the sixth impurity region 216. It may be a channel EDMOS transistor). In FIG. 7, when the sixth impurity region 216 is arranged closest to the layout region 210a or 210b in the layout region 210d, the sixth impurity region 216 and the first impurity regions 211 to the fourth impurity regions are shown. The distance to 214 is represented by "F".

In the present embodiment, the distance E between the fifth impurity region 215 and the first impurity region 211 to the fourth impurity region 214 is between the second impurity region 212 and the fourth impurity region 214. The distance F between the sixth impurity region 216 and the first impurity region 211 to the fourth impurity region 214 is equal to or greater than the distance C between the second impurity region 212 and the fourth impurity region 214. The distance between them is C or more.

As a result, even if a plurality of transistors constituting the first H-bridge circuit (Ch1) or the second H-bridge circuit (Ch2) perform switching operations to generate noise, the drive control circuit 203 and the switching regulator control circuit The effect of noise on the 204 is reduced.

Therefore, it is formed by a plurality of N-type impurity regions in which a plurality of transistors constituting the first H-bridge circuit (Ch1) or the second H-bridge circuit (Ch2) are arranged, and a P-type semiconductor substrate 210. Drive control that is not easily affected by noise even if the motor drive circuit 202a or 202b performs switching operation together with the motor drive circuit 202a or 202b that suppresses the increase in circuit area while preventing the structural destruction caused by the conduction of the parasitic bipolar transistor. It is possible to provide a semiconductor device 200 having a built-in circuit 203 and a switching regulator control circuit 204.

<Layout 2>
FIG. 8 is a plan view showing a second example of the layout of the semiconductor device shown in FIG. FIG. 8 shows the first impurity region 211 to the fourth impurity region 214 of the first H-bridge circuit (Ch1), and the first impurity region 211 and the second impurity region 211 of the second H-bridge circuit (Ch2). Part of the impurity region 212 is shown.

In the second example, at least one guard region of the same conductive type as the semiconductor substrate is provided between two adjacent impurity regions. For example, when a P-type semiconductor substrate 210 is used, the guard region is composed of a P-type impurity region having a higher impurity concentration than the semiconductor substrate 210, and a terminal (pad) to which a second power supply potential VSS is supplied. ) It is electrically connected to P1 to P3. In other respects, the second example may be similar to the first example shown in FIG.

As shown in FIG. 8, since a layout area for arranging elements of other circuits is provided between or around the first impurity region 211 to the fourth impurity region 214, each impurity region is provided. The shape of is not limited to a rectangle. In such a case, for example, the distance between the first impurity region 211 and the second impurity region 212 is the side of the first impurity region 211 and the second impurity region 212 that are closest to each other. It means the distance between the sides.

In the semiconductor substrate 210, between the first impurity region 211 and the second impurity region 212, the side of the first impurity region 211 on the second impurity region 212 side, and the second impurity region 212 of the second impurity region 212. At least one first guard region 251 extending along the side of the impurity region 211 of 1 is provided.

Further, between the third impurity region 213 and the fourth impurity region 214, the side of the third impurity region 213 on the fourth impurity region 214 side and the third impurity region 214 of the fourth impurity region 214. At least one second guard area 252 extending along the side of the area 213 is provided.

Further, between the second impurity region 212 and the fourth impurity region 214, the side of the second impurity region 212 on the fourth impurity region 214 side and the second impurity region 214 of the fourth impurity region 214. At least one third guard region 253 extending along the side of the region 212 is provided.

As a result, between the first impurity region 211 and the second impurity region 212, between the third impurity region 213 and the fourth impurity region 214, and between the second impurity region 212 and the fourth impurity region 212. It is possible to prevent the depletion layer from spreading and punch-through with the region 214.

Further, in the semiconductor substrate 210, between the first impurity region 211 and the third impurity region 213, the side of the first impurity region 211 on the third impurity region 213 side and the third impurity region 213. At least one fourth guard region 254 may be provided extending along the side of the first impurity region 211.

Further, when the semiconductor substrate 210 is provided with the plurality of first guard regions 251, the plurality of second guard regions 252, and the plurality of third guard regions 253, the number of the fourth guard regions 254. However, it may be less than the number of the first guard area 251 and less than the number of the second guard area 252 and less than the number of the third guard area 253. For example, in FIG. 8, one fourth guard area 254, two first guard areas 251, two second guard areas 252, and two third guard areas 253 are provided. There is.

As a result, the number of the fourth guard areas 254 provided between the first impurity region 211 and the third impurity region 213, which are unlikely to cause punch-through in circuit operation, is the number of the first guard area 251 to the first guard area 251 to The increase in the circuit area can be suppressed by making the number smaller than the number of each of the third guard regions 253.

Alternatively, the semiconductor substrate 210 may be provided with a plurality of fifth guard regions 255 extending between the first H-bridge circuit (Ch1) and the second H-bridge circuit (Ch2). In that case, the number of the fifth guard area 255 is equal to or greater than the number of the first guard area 251, is equal to or greater than the number of the second guard area 252, and is greater than or equal to the number of the third guard area 253. Is also good.

For example, in FIG. 8, three fifth guard areas 255, two first guard areas 251, two second guard areas 252, and two third guard areas 253 are provided. There is. Thereby, punch-through between the first H-bridge circuit (Ch1) and the second H-bridge circuit (Ch1) can be effectively prevented.

Further, the layout area 210a or 210b in which the first H-bridge circuit (Ch1) or the second H-bridge circuit (Ch2) shown in FIG. 7 is arranged, and the layout area 210c or the switching regulator in which the drive control circuit 203 is arranged. A sixth guard area 256 or a seventh guard area 257 may be provided between the layout area 210d and the layout area 210d in which the control circuit 204 is arranged.

<Layout 3>
FIG. 9 is a plan view showing a third example of the layout of the semiconductor device shown in FIG. In the third example, in the semiconductor substrate 210, two fifth guard regions 255 extending between the first H-bridge circuit (Ch1) and the second H-bridge circuit (Ch2) are provided. There is. In other respects, the third example may be similar to the second example shown in FIG.

According to the third example, the distance C between the second impurity region 212 and the fourth impurity region 214 in the first H-bridge circuit (Ch1) and the second H-bridge circuit (Ch2) (FIG. 7). (See), the first impurity region 211 to the fourth impurity region 214 of the first H-bridge circuit (Ch1), and the first impurity region 211 to the fourth impurity region of the second H-bridge circuit (Ch2). It can be equal to the distance D (see FIG. 7) from 214.

<Layout 4>
FIG. 10 is a plan view showing a fourth example of the layout of the semiconductor device shown in FIG. In the fourth example, the shape and number of guard regions are different from those in the second example. In other respects, the fourth example may be similar to the second example shown in FIG.

As shown in FIG. 10, in the semiconductor substrate 210, a first guard region 251 extending between the first impurity region 211 and the second impurity region 212 is provided, and the third impurity region 213 and the third impurity region 213 are provided. A second guard region 252 extending between the impurity region 214 and the fourth impurity region 214 is provided, and a third guard region 253 extending between the second impurity region 212 and the fourth impurity region 214 is provided. Has been done.

Further, in the semiconductor substrate 210, a fourth guard region 254 extending between the first impurity region 211 and the third impurity region 213 may be provided. In that case, the width of the fourth guard area 254 is smaller than the width of the first guard area 251 and smaller than the width of the second guard area 252 and smaller than the width of the third guard area 253. Is also good.

As a result, the width of the fourth guard area 254 provided between the first impurity region 211 and the third impurity region 213, which is unlikely to cause punch-through in circuit operation, is set to the width of the first guard area 251 to It can be made smaller than the width of each of the third guard regions 253 to suppress an increase in the circuit area.

Alternatively, the semiconductor substrate 210 may be provided with a fifth guard region 255 extending between the first H-bridge circuit (Ch1) and the second H-bridge circuit (Ch2). In that case, the width of the fifth guard region 255 is equal to or greater than the width of the first guard region 251, equal to or greater than the width of the second guard region 252, and equal to or greater than the width of the third guard region 253. Is also good. Thereby, punch-through between the first H-bridge circuit (Ch1) and the second H-bridge circuit (Ch1) can be effectively prevented.

The fifth guard region 255 is a first one located between the third impurity region 213 of the first H-bridge circuit (Ch1) and the first impurity region 211 of the second H-bridge circuit (Ch2). A portion 255a and a second portion 255b located between the fourth impurity region 214 of the first H-bridge circuit (Ch1) and the second impurity region 212 of the second H-bridge circuit (Ch2). Have.

In FIG. 10, in order to facilitate the layout, the width of the first portion 255a and the width of the second portion 255b of the fifth guard region are made the same. However, the width of the first portion 255a of the fifth guard region may be equal to or greater than the width of the fourth guard region 254 and may be smaller than the width of the second portion 255b of the fifth guard region. .. Further, elements of another circuit may be arranged between the first H-bridge circuit (Ch1) and the second H-bridge circuit (Ch2).

<Third embodiment>
FIG. 11 is a cross-sectional view showing a specific example of the motor drive circuit according to the third embodiment. In the third embodiment, in the H-bridge circuit shown in FIG. 1, EDMOS transistors are used as the transistors QN1 and QN2. In other respects, the third embodiment may be the same as the first or second embodiment.

As shown in FIG. 11, the first P-channel MOS transistor QP1 is an EDMOS transistor and is arranged in the N-type first impurity region 211 on the semiconductor substrate 210. Further, the first N-channel MOS transistor QN1 is an EDMOS transistor and has an N-type second impurity region 235 in the semiconductor substrate 210.

Although not shown in FIG. 11, the second P-channel MOS transistor QP2 is an EDMOS transistor and is arranged in the N-type third impurity region on the semiconductor substrate 210. Further, the second N-channel MOS transistor QN2 is an EDMOS transistor and has an N-type fourth impurity region in the semiconductor substrate 210. In the following, the configurations of the transistors QP1 and QN1 will be described as an example, but the transistors QP2 and QN2 also have the same configurations.

The semiconductor substrate 210 has a second impurity region 235 constituting the extended drain of the transistor QN1, an N-type impurity region 236 constituting the drain of the transistor QN1, and an N-type impurity region 237 constituting the source of the transistor QN1. And a P-type contact area 238 are arranged. The N-type impurity region 236 has a higher impurity concentration than the second impurity region 235.

In the semiconductor substrate 210, a P-type impurity region (P ⁺ ) 217 having a higher impurity concentration than that of the semiconductor substrate 210 is arranged between the first impurity region 211 and the second impurity region 235, and P. A P-type contact region 218 is arranged in the impurity region 217 of the mold. The P-type impurity region 217 corresponds to a guard region for preventing the depletion layer from spreading between the first impurity region 211 and the second impurity region 235 to cause punch-through.

Further, a gate electrode 241 of the transistor QP1 and a gate electrode 243 of the transistor QN1 are arranged on the semiconductor substrate 210 via a gate insulating film. Further, on the semiconductor substrate 210 on which the gate electrodes 241 and 243 and the like are arranged, a wiring layer including a plurality of wirings is arranged via an interlayer insulating film. The interlayer insulating film and the wiring layer may have a multilayer structure, if necessary.

The N-type contact region 221 and the P-type impurity region 222 are connected to the first node N1 via wiring. The P-shaped contact region 218 is connected to the fifth node N5 via wiring. The N-type impurity region 237 and the P-type contact region 238 are connected to the second node N2 via wiring. The P-type impurity region 224 and the N-type impurity region 236 are connected to the third node N3 via wiring. Since the resistance value of the semiconductor substrate 210 between the P-type contact region 238 and the P-type impurity region 217 is sufficiently larger than the resistance value of the resistor R1, the P-type contact region 238 and the P-type contact region 238 and the P-type. Almost no current flows between the impurity region 217 and the impurity region 217.

Here, as shown in FIG. 11, a parasitic NPN bipolar transistor is formed by using the N-type first impurity region 211 as a collector, the P-type semiconductor substrate 210 as a base, and the N-type second impurity region 235 as an emitter. Has been done. The first power supply potential VBB (for example, + 42V) is supplied from the first node N1 to the first impurity region 211 via the N-type contact region 221, and the fifth node N5 is supplied to the semiconductor substrate 210. A second power supply potential VSS (eg, 0V) is supplied from the P-type contact region 218 and the P-type impurity region 217.

In the high-speed attenuation mode shown in FIG. 2 (B), when a regenerative current flows from the fifth node N5 toward the first node N1 via the transistors QN1 and QP2, a negative potential (negative potential () to the third node N3. For example, about -1V) is applied. Therefore, a negative potential is applied to the second impurity region 235 from the third node N3 via the N-type impurity region 236.

As a result, the parasitic transistor conducts, and the parasitic current Ip flows from the first impurity region 211 toward the second impurity region 235 via the semiconductor substrate 210. When the hFE (DC current amplification factor) of the parasitic transistor is large, a large parasitic current Ip exceeding the allowable limit may flow, causing structural destruction of the IC.

The smaller the distance Dw between the first impurity region 211 and the second impurity region 235, the larger the hFE of the parasitic transistor. Therefore, by setting the distance Dw between the first impurity region 211 and the second impurity region 235 to a predetermined distance or more, the hFE of the parasitic transistor is suppressed to a permissible value or less that does not cause structural destruction of the IC. Can be done.

Alternatively, in the third embodiment, general MOS transistors may be used as the transistors QN1 and QN2. In that case, an N-type offset region is provided in place of the extended drain of the transistor QN1 shown in FIG. 11, and the N-type offset region corresponds to the second impurity region. Further, an N-type offset region is provided in place of the extended drain of the transistor QN2, and the N-type offset region corresponds to the fourth impurity region.

<Fourth Embodiment>
FIG. 12 is a cross-sectional view showing a specific example of the motor drive circuit according to the fourth embodiment. In the fourth embodiment, in the H-bridge circuit shown in FIG. 1, general MOS transistors are used as the transistors QP1 and QP2. In other respects, the fourth embodiment may be the same as any of the first to third embodiments.

As shown in FIG. 12, the first P-channel MOS transistor QP1 is a general MOS transistor and is arranged in the N-type first impurity region 211 on the semiconductor substrate 210. Further, the first N-channel MOS transistor QN1 is an LDMOS transistor, and is arranged in the N-type second impurity region 212 on the semiconductor substrate 210.

Although not shown in FIG. 12, the second P-channel MOS transistor QP2 is a general MOS transistor and is arranged in the N-type third impurity region on the semiconductor substrate 210. Further, the second N-channel MOS transistor QN2 is an LDMOS transistor and is arranged in the N-type fourth impurity region on the semiconductor substrate 210. In the following, the configurations of the transistors QP1 and QN1 will be described as an example, but the transistors QP2 and QN2 also have the same configurations.

In the first impurity region 211, an N-type contact region 221, a P-type impurity region 222 constituting the source of the transistor QP1, a P-type offset region 225, and a P-type impurity region 226 are arranged. ing. The P-type impurity region 226 has a higher impurity concentration than the P-type offset region 225, and together with the P-type offset region 225, constitutes the drain of the transistor QP1.

In the semiconductor substrate 210, a P-type impurity region (P ⁺ ) 217 having a higher impurity concentration than that of the semiconductor substrate 210 is arranged between the first impurity region 211 and the second impurity region 212, and P. A P-type contact region 218 is arranged in the impurity region 217 of the mold. The P-type impurity region 217 corresponds to a guard region for preventing the depletion layer from spreading between the first impurity region 211 and the second impurity region 212 to cause punch-through.

Further, a gate electrode 244 of the transistor QP1 and a gate electrode 242 of the transistor QN1 are arranged on the semiconductor substrate 210 via a gate insulating film. Further, on the semiconductor substrate 210 on which the gate electrodes 244 and 242 and the like are arranged, a wiring layer including a plurality of wirings is arranged via an interlayer insulating film. The interlayer insulating film and the wiring layer may have a multilayer structure, if necessary.

The N-type contact region 221 and the P-type impurity region 222 are connected to the first node N1 via wiring. The P-shaped contact region 218 is connected to the fifth node N5 via wiring. The P-type contact region 233 and the N-type impurity region 234 are connected to the second node N2 via wiring. The P-type impurity region 226 and the N-type impurity region 232 are connected to the third node N3 via wiring.

Here, as shown in FIG. 12, a parasitic NPN bipolar transistor is formed by using the N-type first impurity region 211 as a collector, the P-type semiconductor substrate 210 as a base, and the N-type second impurity region 212 as an emitter. Has been done. The first power supply potential VBB (for example, + 42V) is supplied from the first node N1 to the first impurity region 211 via the N-type contact region 221, and the fifth node N5 is supplied to the semiconductor substrate 210. A second power supply potential VSS (eg, 0V) is supplied from the P-type contact region 218 and the P-type impurity region 217.

In the high-speed attenuation mode shown in FIG. 2 (B), when a regenerative current flows from the fifth node N5 toward the first node N1 via the transistors QN1 and QP2, a negative potential (negative potential () to the third node N3. For example, about -1V) is applied. Therefore, a negative potential is applied to the second impurity region 212 from the third node N3 via the N-type impurity region 232.

As a result, the parasitic transistor conducts, and the parasitic current Ip flows from the first impurity region 211 toward the second impurity region 212 via the semiconductor substrate 210. When the hFE (DC current amplification factor) of the parasitic transistor is large, a large parasitic current Ip exceeding the allowable limit may flow, causing structural destruction of the IC.

The smaller the distance Dw between the first impurity region 211 and the second impurity region 212, the larger the hFE of the parasitic transistor. Therefore, by setting the distance Dw between the first impurity region 211 and the second impurity region 212 to a predetermined distance or more, the hFE of the parasitic transistor is suppressed to a permissible value or less that does not cause structural destruction of the IC. Can be done.

<Fifth Embodiment>
FIG. 13 is a cross-sectional view showing a specific example of the motor drive circuit according to the fifth embodiment. In the fifth embodiment, instead of the P-type semiconductor substrate 210 shown in FIG. 3, an N-type semiconductor substrate (for example, a silicon substrate containing N-type impurities such as phosphorus or arsenic) 260 is used. Along with this, the P-type region and the N-type region in the semiconductor substrate are reversed, and the P-channel transistor and the N-channel transistor are reversed, and the connection relationship between the circuits is changed accordingly. In other respects, the fifth embodiment may be the same as any of the first to fourth embodiments.

The motor drive circuit in the fifth embodiment has a first node N1 to which a first power supply potential VBB (for example, 0V) is supplied, and a second power supply potential VSS having a lower potential than the first power supply potential VBB. The second node N2 to which (for example, -42V) is supplied, and the third node N3 and the fourth node N4 (see FIG. 1) connected to the two terminals of the motor 100 to be driven, respectively. It has a connected H-bridge circuit.

The first power supply potential VBB is also supplied to the seventh node N7. As shown in FIG. 13, when the resistor R1 is connected between the seventh node N7 and the first node N1, the first power supply potential VBB is the first node N1 via the resistor R1. Is supplied to.

The H-bridge circuit according to the fifth embodiment is the H-bridge circuit shown in FIG. 1, in which the P-channel EDMOS transistor is replaced with the P-channel LDMOS transistor and the N-channel LDMOS transistor is replaced with the N-channel EDMOS transistor.

Therefore, the first N-channel MOS transistor QN1 is an EDMOS transistor and is arranged in the P-type first impurity region 261 on the semiconductor substrate 260. Further, the first P-channel MOS transistor QP1 is an LDMOS transistor and is arranged in the P-type second impurity region 262 on the semiconductor substrate 260.

Although not shown in FIG. 13, the second N-channel MOS transistor QN2 is an EDMOS transistor and is arranged in a P-type third impurity region on the semiconductor substrate 260. Further, the second P-channel MOS transistor QP2 is an LDMOS transistor and is arranged in the P-type fourth impurity region on the semiconductor substrate 260. In the following, the configurations of the transistors QN1 and QP1 will be described as an example, but the transistors QN2 and QP2 also have the same configurations.

The first impurity region 261 includes a P-type contact region 271, an N-type impurity region 272 that constitutes the source of the transistor QN1, an N-type impurity region 273 that constitutes the extended drain of the transistor QN1, and a transistor QN1. An N-type impurity region 274 constituting the drain of the above is arranged. The N-type impurity region 274 has a higher impurity concentration than the N-type impurity region 273.

In the second impurity region 262, an N-type body region 281 and a P-type impurity region 282 constituting the drain of the transistor QP1 are arranged. In the N-type body region 281, an N-type contact region 283 and a P-type impurity region 284 constituting the source of the transistor QP1 are arranged.

In the semiconductor substrate 260, an N-type impurity region (N ⁺ ) 265 having a higher impurity concentration than the semiconductor substrate 260 is arranged between the first impurity region 261 and the second impurity region 262, and N An N-type contact region 266 is arranged in the mold impurity region 265. The N-type impurity region 265 corresponds to a guard region for preventing the depletion layer from spreading between the first impurity region 261 and the second impurity region 262 to cause punch-through.

Further, a gate electrode 291 of the transistor QN1 and a gate electrode 292 of the transistor QP1 are arranged on the semiconductor substrate 260 via a gate insulating film. Further, on the semiconductor substrate 260 on which the gate electrodes 291 and 292 are arranged, a wiring layer including a plurality of wirings is arranged via an interlayer insulating film.

The N-type contact region 283 and the P-type impurity region 284 are connected to the first node N1 via wiring. The N-shaped contact area 266 is connected to the seventh node N7 via wiring. The P-type contact region 271 and the N-type impurity region 272 are connected to the second node N2 via wiring. The P-type impurity region 282 and the N-type impurity region 274 are connected to the third node N3 via wiring.

Here, as shown in FIG. 13, a parasitic PNP bipolar transistor is formed by using the P-type second impurity region 262 as an emitter, the N-type semiconductor substrate 260 as a base, and the P-type first impurity region 261 as a collector. Has been done. A second power supply potential VSS (for example, −42V) is supplied from the second node N2 to the first impurity region 261 via the P-type contact region 271, and the semiconductor substrate 260 is supplied with the seventh node. The first power supply potential VBB (for example, 0V) is supplied from N7 through the N-type contact region 266 and the N-type impurity region 265.

In the high-speed attenuation mode, when a regenerative current flows from the second node N2 toward the seventh node N7 via the transistors QN2 and QP1, a positive potential (for example, about + 1V) is applied to the third node N3. Will be done. Therefore, a positive potential is supplied to the second impurity region 262 from the third node N3 via the P-type impurity region 282.

As a result, the parasitic transistor conducts, and the parasitic current Ip flows from the second impurity region 262 toward the first impurity region 261 via the semiconductor substrate 260. When the hFE (DC current amplification factor) of the parasitic transistor is large, a large parasitic current Ip exceeding the allowable limit may flow, causing structural destruction of the IC.

Therefore, by reversing the P-type region and the N-type region in the semiconductor substrate in FIGS. 4 to 12 and the description thereof, the first to fourth embodiments are also applied to the fifth embodiment. To. That is, the P-type first impurity region to the sixth impurity region is provided in place of the N-type first impurity region 211 to the sixth impurity region 216 shown in FIGS. 5 and 7 to 10.

For example, the distance A between the first impurity region and the third impurity region is smaller than the distance B1 between the first impurity region and the second impurity region, and the third impurity region and the fourth impurity region It is set to be smaller than the distance B2 between the impurities region and smaller than the distance C between the second impurity region and the fourth impurity region.

As a result, in the motor drive circuit, the hFE of the parasitic PNP bipolar transistor formed by the plurality of P-type impurity regions in which the plurality of transistors constituting the H-bridge circuit are arranged and the N-type semiconductor substrate 260 is less than the allowable value. The distance between the first impurity region and the third impurity region where the parasitic transistor is unlikely to conduct in circuit operation is reduced while preventing the structural destruction caused by the conduction of the parasitic transistor. As a result, it is possible to suppress an increase in the circuit area and reduce the cost.

Further, when the N-type semiconductor substrate 260 is used, the guard region is composed of an N-type impurity region having a higher impurity concentration than the semiconductor substrate 260, and a terminal (pad) to which the first power supply potential VBB is supplied. ) Is electrically connected. Therefore, instead of the P-shaped first guard region 251 to the seventh guard region 257 shown in FIGS. 8 to 10, an N-shaped first guard region to the seventh guard region is provided.

Further, according to the first to fifth embodiments of the present invention, a plurality of identical conductive type impurity regions in which a plurality of transistors constituting the H-bridge circuit are arranged or configured, and a conductive type semiconductor substrate opposite to the plurality of impurity regions. It is possible to provide a highly reliable and compact electronic device by using a motor drive circuit that suppresses an increase in the circuit area while preventing structural destruction caused by conduction of the parasitic bipolar transistor formed in the above.

The present invention is not limited to the embodiments described above, and many modifications can be made within the technical idea of the present invention by a person having ordinary knowledge in the art. For example, it is also possible to carry out a combination of a plurality of embodiments selected from the embodiments described above.

11, 21 ... High side predriver, 12, 22 ... Low side predriver, 30 ... Comparator, 40 ... Switching control circuit, 100 ... Motor, 100a ... Carriage motor, 100b ... Feeding motor, 200 ... Semiconductor device, 201, 203 ... Drive control circuit, 202, 202a, 202b ... Motor drive circuit, 204 ... Switching regulator control circuit, 210, 260 ... Semiconductor substrate, 210a to 210d ... Layout area, 211 to 216, 232, 234 to 237, 265, 272 274 ... N-type impurity region, 217, 222 to 224, 226, 261, 262, 282, 284 ... P-type impurity region, 218, 221, 233, 238, 266, 271, 283 ... Contact region, 225 ... Offset region, 231 and 281 ... Body region, 241-244, 291, 292 ... Gate electrode, 251 to 257 ... Guard region, 300 ... SoC, 400 ... Analog circuit IC, 500 ... Power supply circuit, QP1, QP2 ... P channel transistor , QN1, QN2 ... N channel transistor, R1 ... resistor, D1 ... diode, L1 ... inductor, C1 ... capacitor, P1 to P3 ... terminals

Claims (12)

Two terminals, a first node to which a first power supply potential is supplied, a second node to which a second power supply potential lower than the first power supply potential is supplied, and a motor to be driven. A motor drive circuit including a first H-bridge circuit connected to a third node and a fourth node, respectively, wherein the first H-bridge circuit is a motor drive circuit.
A first P-channel MOS transistor arranged in an N-type first impurity region on a P-type semiconductor substrate and connected between the first node and the third node, and a first P-channel MOS transistor.
The semiconductor substrate is located in the N-type second impurity region, or is directly disposed on the semiconductor substrate and has an N-type second impurity region, and the second node and the third. The first N-channel MOS transistor connected between the nodes and
A second P-channel MOS transistor arranged in an N-type third impurity region on the semiconductor substrate and connected between the first node and the fourth node, and a second P-channel MOS transistor.
The semiconductor substrate is located in the N-type fourth impurity region, or is directly disposed on the semiconductor substrate and has an N-type fourth impurity region, and the second node and the fourth impurity region. A second N-channel MOS transistor connected to the node,
Including
The distance between the first impurity region and the third impurity region is smaller than the distance between the first impurity region and the second impurity region, and the third impurity region and the said A motor drive circuit that is smaller than the distance between the fourth impurity region and smaller than the distance between the second impurity region and the fourth impurity region. The first P-channel MOS transistor is an EDMOS transistor.
The second P-channel MOS transistor is an EDMOS transistor.
The first N-channel MOS transistor is an LDMOS transistor.
The second N-channel MOS transistor is an LDMOS transistor.
The motor drive circuit according to claim 1. Two terminals, a first node to which a first power supply potential is supplied, a second node to which a second power supply potential lower than the first power supply potential is supplied, and a motor to be driven. A motor drive circuit including a first H-bridge circuit connected to a third node and a fourth node, respectively, wherein the first H-bridge circuit is a motor drive circuit.
A first N-channel EDMOS transistor arranged in a P-type first impurity region on an N-type semiconductor substrate and connected between the second node and the third node, and a first N-channel EDMOS transistor.
A first P-channel LDMOS transistor arranged in a P-type second impurity region on the semiconductor substrate and connected between the first node and the third node.
A second N-channel EDMOS transistor arranged in a P-type third impurity region on the semiconductor substrate and connected between the second node and the fourth node, and a second N-channel EDMOS transistor.
A second P-channel LDMOS transistor arranged in a P-type fourth impurity region on the semiconductor substrate and connected between the first node and the fourth node.
Including
The distance between the first impurity region and the third impurity region is smaller than the distance between the first impurity region and the second impurity region, and the third impurity region and the said A motor drive circuit that is smaller than the distance between the fourth impurity region and smaller than the distance between the second impurity region and the fourth impurity region. The distance between the first impurity region and the second impurity region, the distance between the third impurity region and the fourth impurity region, the second impurity region and the fourth impurity region. The motor drive circuit according to any one of claims 1 to 3, wherein the distances from the impurity regions of the above are equal to each other. In the semiconductor substrate, between the first impurity region and the second impurity region, the side of the first impurity region on the second impurity region side, and the second impurity region, said. At least one first guard region of the same conductive type as the semiconductor substrate, extending along the side of the first impurity region,
In the semiconductor substrate, between the third impurity region and the fourth impurity region, the side of the third impurity region on the fourth impurity region side, and the fourth impurity region. At least one second guard region of the same conductive type as the semiconductor substrate, extending along the side of the third impurity region,
In the semiconductor substrate, between the second impurity region and the fourth impurity region, the side of the second impurity region on the fourth impurity region side, and the fourth impurity region. At least one third guard region of the same conductive type as the semiconductor substrate, extending along the side of the second impurity region,
The motor drive circuit according to any one of claims 1 to 4, further comprising. A plurality of the first guard regions, a plurality of the second guard regions, and a plurality of the third guard regions are provided, and in the semiconductor substrate, the first impurity region and the third impurity region are provided. The semiconductor extends between the region and the side of the first impurity region on the side of the third impurity region and the side of the third impurity region on the side of the first impurity region. Further comprising at least one fourth guard region of the same conductive type as the substrate, the number of the fourth guard regions is less than the number of the first guard regions and more than the number of the second guard regions. 5. The motor drive circuit according to claim 5, which is less than the number of the third guard regions. In the semiconductor substrate, between the first impurity region and the third impurity region, the side of the first impurity region on the third impurity region side, and the third impurity region, said. It extends along the side of the first impurity region and further includes a fourth guard region of the same conductive type as the semiconductor substrate, and the width of the fourth guard region is the width of the first guard region. The motor drive circuit according to claim 5, which is smaller than the width, smaller than the width of the second guard region, and smaller than the width of the third guard region. A second H-bridge circuit having the same configuration as the first H-bridge circuit is further provided, and the first to fourth impurity regions of the first H-bridge circuit and the second H-bridge circuit are described. Claimed that the distance between the first to fourth impurity regions is equal to or greater than the distance between the second impurity region and the fourth impurity region in the first or second H-bridge circuit. The motor drive circuit according to any one of 1 to 7. A second H-bridge circuit having the same configuration as the first H-bridge circuit,
In the semiconductor substrate, a plurality of fifth guard regions of the same conductive type as the semiconductor substrate, extending between the first H-bridge circuit and the second H-bridge circuit,
The number of the fifth guard region is equal to or greater than the number of the first guard region, equal to or greater than the number of the second guard region, and equal to or greater than the number of the third guard region. The motor drive circuit according to claim 5 or 6. A second H-bridge circuit having the same configuration as the first H-bridge circuit,
In the semiconductor substrate, a fifth guard region of the same conductive type as the semiconductor substrate, which extends between the first H-bridge circuit and the second H-bridge circuit,
The width of the fifth guard region is equal to or greater than the width of the first guard region, equal to or greater than the width of the second guard region, and equal to or greater than the width of the third guard region. The motor drive circuit according to claim 5 or 7. The motor drive circuit according to any one of claims 1 to 10.
A drive control circuit including a transistor arranged in the fifth impurity region in the semiconductor substrate or directly arranged in the semiconductor substrate and having the fifth impurity region.
A switching regulator control circuit including a transistor arranged in the sixth impurity region on the semiconductor substrate or directly arranged on the semiconductor substrate and having the sixth impurity region.
The distance between the fifth impurity region and the first to fourth impurity regions is equal to or greater than the distance between the second impurity region and the fourth impurity region. The semiconductor device, wherein the distance between the sixth impurity region and the first to fourth impurity regions is equal to or greater than the distance between the second impurity region and the fourth impurity region. .. The motor drive circuit according to any one of claims 1 to 10.
The motor having the two terminals connected to the third node and the fourth node, respectively.
Electronic equipment equipped with.

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