JP7010784B2 - Measuring device and measuring method - Google Patents

Description

The present invention relates to a measuring device that measures a device to be measured that operates according to a standard such as LTE, and more particularly to a measuring device and a measuring method that receives a trigger signal and controls a signal processing start timing with the device to be measured. ..

With the increasing functionality of communication devices such as mobile terminals, the wireless communication speed with base stations has increased. In recent years, LTE Release 8 (downlink 300 Mbps, uplink 75 Mbps) and LTE Rel10 have been adopted in the 3GPP LTE standard. Various methods such as (downlink 1 Gbps, uplink 500 Mbps) are being put into practical use.

As the measuring device for measuring the various types of communication devices described above, a signal generator that transmits a test signal to the communication device that is the device to be measured, and a device that receives and analyzes the signal to be measured transmitted by the device to be measured. Signal analyzers are known.

Examples of conventional signal transmitters include a signal generator, a DAC that D / A-converts waveform data from the signal generator, and a smoothing filter that changes the cutoff frequency by variably controlling the gain of a variable gain amplifier. Patent Document 1 proposes a technique for blocking an image included in a sampling clock signal and an analog output waveform which is an output of the DAC, provided with a control means for controlling the gain according to the sampling frequency of the sampling clock signal with respect to the DAC. (See paragraph 0035, FIG. 4).

Japanese Unexamined Patent Publication No. 2001-136027

However, the one described in Patent Document 1 corresponds to the case where the transmission process of the test signal on the signal generation unit side is activated by an external trigger signal in order to ensure the reception of the test signal in the device under test. No consideration was given to the control function to delay the trigger signal appropriately. Moreover, Patent Document 1 does not suggest that the trigger signal is delayed in consideration of the speed difference between the operating clock of the signal generation unit and the sampling frequency of the DAC with respect to the control function.

Therefore, in the conventional signal generator described in Patent Document 1, when the operating clock of the signal generator is smaller than the sampling clock (sampling rate) of the DAC, the timing of output from the signal generator to the DAC is determined by the trigger signal. When the delay control is performed, the resolution of the delay control remains at the value corresponding to the operating clock of the signal generation unit, and there is a problem that the resolution corresponding to the sampling rate of the DAC cannot be achieved.

The same thing has happened with conventional signal analyzers. The signal analysis device receives the signal to be measured transmitted from the device to be measured, performs AD conversion by the ADC, and then detects the AD conversion output by the analysis processing unit. Here, when the operating clock of the analysis processing unit is smaller than the sampling rate of the ADC and the signal processing unit controls to delay the timing of capturing the signal from the ADC by the trigger signal, the resolution of the control is the signal processing unit. There is a problem that the value corresponding to the operating clock remains and the resolution corresponding to the sampling rate of the ADC cannot be achieved.

The present invention has been made to solve such a conventional problem, and has higher resolution in delay control of a trigger signal for controlling the processing start timing of a signal transmitted to and received from the device under test. It is an object of the present invention to provide an achievable measuring device and measuring method.

In order to solve the above problems, the measuring device according to claim 1 of the present invention executes a test signal transmission process to the measured device (5) or a measured signal reception process from the measured device. A measuring device (100, 200) that measures the device to be measured, and is a signal processing unit (11, 52) that performs a process of generating the test signal or waveform data corresponding to the signal to be measured at a predetermined operation clock. ), The signal conversion unit (13, 51) that samples the waveform data at a sampling rate faster than the operating clock of the signal processing unit and performs D / A conversion or A / D conversion processing, and the signal processing. The timing of inputting the waveform data generated by the unit as a plurality of columns of waveform data corresponding to the ratio of the operation clock to the sampling rate, and outputting the plurality of columns of waveform data to the signal conversion unit, or the signal. The timing control unit (12) that inputs the waveform data after signal conversion in the conversion unit as a plurality of columns of waveform data corresponding to the ratio and controls the timing of incorporating the waveform data of the plurality of columns into the signal processing unit. , 53), and the timing control unit delays the trigger signal input from the outside in the cycle of the operation clock based on the preset first adjustment value (aX). Second adjustment value set in advance at the timing when the delayed trigger signal is input to the unit (23, 64) and the waveform data of the plurality of columns input from the signal processing unit or the signal conversion unit. Based on (nY), it is characterized by having a delay fine adjustment unit (25, 66) that delays in the arrangement direction in the cycle of the sampling rate.

With this configuration, the measuring device according to claim 1 of the present invention not only delays the trigger signal by the cycle of the operating clock of the signal processing unit, but also delays it by the cycle of the sampling rate of the signal conversion unit, thereby delaying the sampling rate. Delay control of the trigger signal can be executed with the time resolution of.

The measuring device according to claim 2 of the present invention has a time resolution of trigger delay when the sampling rate is N [Hz], and the operation clock when the number of parallel processes is L (L is a positive integer). When the time resolution is X, M / N (M is a positive integer) is set as the trigger delay request value (32), and M is divided by L (M / L) after the decimal point. Adjustment value setting means for setting aX having the value a rounded down as a count as the first adjustment value and setting nY having the remainder value n of the (M / L) as the count as the second adjustment value. It is characterized by further having (33) and.

With this configuration, in the measuring device according to claim 2 of the present invention, the user simply sets the trigger delay request value, and the first adjustment value, the delay coarse adjustment based on the second adjustment value, and the delay fine adjustment. Adjustments can be made easily.

The measuring device according to claim 3 of the present invention uses a digital signal processor (26) and a waveform memory (40) as the signal processing unit to generate a signal to generate waveform data for generating the test signal. The signal conversion unit includes a D / A conversion unit (13) that performs D / A conversion processing of the waveform data generated by the signal generation unit, and the timing control unit includes the unit (11). A signal having an output control unit (12) that controls the timing of inputting the waveform data generated by the signal generation unit as the waveform data of the plurality of columns and outputting the waveform data of the plurality of columns to the D / A conversion unit. It is a generator (100).

With this configuration, the measuring device according to claim 3 of the present invention is in the case of outputting waveform data of a plurality of columns from the signal generating section to the D / A conversion section having a high sampling rate when applied to the signal generating device. When controlling the delay of the trigger signal, the time resolution of the sampling rate can be achieved.

The measuring device according to claim 4 of the present invention has an A / D conversion unit (51) as the signal conversion unit that performs A / D conversion processing of the measured signal after frequency conversion, and the signal processing. As a unit, the analysis processing unit (52) that captures the A / D converted processed signal to be measured as the waveform data of the plurality of columns and restores the base band signal is provided, and the A / A signal having an import control unit (53) that inputs the waveform data after signal conversion in the D conversion unit as the waveform data of the plurality of columns and controls the timing of importing the waveform data of the plurality of columns into the analysis processing unit. It is characterized by being an analyzer (200).

With this configuration, in the measuring device according to claim 4 of the present invention, when the signal analysis unit processes the waveform data output by the A / D conversion unit at a high sampling rate in parallel when applied to the signal analysis device. The time resolution of the sampling rate can be achieved in the delay control of the trigger signal.

In the measuring method according to claim 5 of the present invention, the measuring device according to claim 1 executes a test signal transmission process to the measured device or a measured signal reception process from the measured device. A measurement method for measuring the device under test, wherein the timing control unit delays a trigger signal input from the outside by the cycle of the operation clock based on a preset first adjustment value. The coarse adjustment step (S2) and the second adjustment value preset at the timing when the delayed trigger signal inputs the waveform data of the plurality of columns input from the signal processing unit or the signal conversion unit. Based on the above, it is characterized by including a delay fine adjustment step (S5) of delaying in the arrangement direction in the cycle of the sampling rate.

With this configuration, the measuring method according to claim 5 of the present invention uses the measuring device according to claim 1 and not only delays the trigger signal by the cycle of the operating clock of the signal processing unit, but also delays the sampling rate of the signal conversion unit. By delaying in the cycle of, the resolution of the sampling rate can be achieved in the delay control of the trigger signal.

INDUSTRIAL APPLICABILITY The present invention can provide a measuring device and a measuring method capable of achieving higher resolution in delay control of a trigger signal for controlling a processing start timing of a signal transmitted to and received from a measured device.

It is a conceptual diagram which shows the usage mode of the signal generator which concerns on 1st Embodiment of this invention. It is a block diagram which shows the structure of the signal generator which concerns on 1st Embodiment of this invention. It is a block diagram which shows the functional structure of the signal generation part and the output control part in FIG. It is a figure which shows the correspondence relationship between the operation clock of the output control part in FIG. 2 and the parallel data of an output timing control target. It is a block diagram which shows the functional structure of the delay coarse adjustment part in FIG. It is a block diagram which shows the functional structure of the delay fine adjustment part in FIG. It is a flowchart which shows the trigger signal delay control in the signal generator which concerns on 1st Embodiment of this invention. It is a figure which shows an example of the waveform data based on the trigger signal delay control in the signal generator which concerns on 1st Embodiment of this invention. It is a conceptual diagram which shows the usage mode of the signal analysis apparatus which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structure of the signal analysis apparatus which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the functional structure of the intake control part and the detection part of FIG. It is a flowchart which shows the trigger signal delay control in the signal analysis apparatus which concerns on 2nd Embodiment of this invention.

Hereinafter, an embodiment of the measuring device and the measuring method according to the present invention will be described with reference to the drawings.

The present invention relates to a measuring device that measures a measured device (DUT) 5 (see FIGS. 1 and 9) that operates according to various standards such as LTE, and is a signal generator that transmits a test signal to the DUT 5. It includes an SG: Signal Generator) 100 (see FIG. 1) and a signal analysis device (SA: Signal (Spectrum) Anaiyzer) that analyzes a measured signal transmitted from the DUT.

The DUT is, for example, a wireless terminal device such as a mobile phone, a network device such as a router, a switching hub, and a transmission device. The DUT also includes devices such as ICs (integrated circuits) and optical modules.

DUT communicates according to each communication standard such as SDH, Ethernet (registered trademark), OTN, WAN, or W-CDMA, GSM (registered trademark), LTE, CDMA2000, EV-DO, and TD-SCDMA. It is something to do.

In the measuring device according to the present invention, for example, when applied to a signal generator, an input of a trigger signal is received from the outside to control the start timing of a test signal transmission process to the DUT 5. Further, when applied to the signal analysis device, the start timing of the analysis processing of the measured signal from the DUT 5 is controlled. The trigger signal can be input from, for example, an external device connected to the measuring device.

The trigger signal is input to both the measuring device and the DUT5. At that time, depending on various delay factors, the two may arrive at different times, or the time from input to the measuring device to arrival at the output control unit 12 or the capture control unit 53 may differ. In this case, there may be a difference between the timing at which the measuring device starts signal processing and the timing at which the DUT 5 transmits or receives the signal. As a countermeasure, the measuring device according to the present invention implements a trigger signal delay control function that appropriately delays the input trigger signal in consideration of the above-mentioned delay factor.

Hereinafter, the measuring device according to the present invention and the signal measuring method based on the trigger signal delay control will be described with reference to each embodiment.

(First Embodiment)
First, the configuration of the signal generator 100 according to the first embodiment will be described with reference to FIGS. 1 to 6.

As shown in FIG. 1, the signal generator 100 according to the present embodiment starts the transmission processing of the test signal to the DUT 5 in response to the input of the trigger signal St1. At that time, the signal generator 100 appropriately delays the trigger signal St1 input from the outside and appropriately controls the start timing of the transmission process.

As shown in FIG. 2, the signal generator 100 includes a baseband unit 10, a modulation unit 14, an RF unit 15, a control unit 30, a RAM 35, a ROM 36, an operation unit 37, and a display unit 38.

The baseband unit 10 generates an I component baseband signal and a Q component baseband signal which is a orthogonal component signal whose phase is π / 2 out of phase with the I component baseband signal based on a predetermined operation clock.

The modulation unit 14 mixes a local signal with each of the I component baseband signal and the Q component baseband signal, further synthesizes the two, and outputs the modulation process as the frequency of digital modulation.

The RF unit 15 has a function as a frequency converter that converts the frequency of the digital modulation output from the modulation unit 14 into a desired value, and a test signal corresponding to the frequency of the digital modulation is used as the frequency of each communication standard. Generated and output the generated test signal toward DUT5.

The control unit 30 is composed of, for example, a computer device including a CPU 31, a RAM 35, a ROM 36, and various input / output interfaces. The CPU 31 performs predetermined information processing and control for realizing the function of the signal generator 100. The ROM 35 stores an OS for starting up the CPU 31, other programs, parameters for control, and the like. The RAM 36 stores execution codes, data, and the like of the OS and applications used by the CPU 31 for operation.

This computer device functions as a control unit 30 including a delay request value setting unit 32, an adjustment value setting unit 33, and a delay control unit 34 by the CPU 31 executing a program stored in the ROM 35 with the RAM 36 as a work area. The control unit 30 controls at least the baseband unit 10. The delay request value setting unit 32, for example, the operation unit 37, sets the trigger delay value required for delaying the trigger signal St1 according to the user operation. The adjustment value setting unit 33 sets the adjustment value of the trigger delay based on the trigger delay value set by the delay request value setting unit 32. The delay control unit 34 controls to delay the trigger signal St1 based on the adjustment value set by the adjustment value setting unit 33. The delay request value setting unit 32 and the adjustment value setting unit 33 constitute the setting means and the adjustment value setting means of the present invention, respectively.

The operation unit 37 and the display unit 38 are connected to the input / output interface of the computer device. The operation unit 37 is a functional unit for inputting various information such as commands, and the display unit 38 is a functional unit for displaying various information such as an input screen for the various information and measurement results.

In the signal generator 100 shown in FIG. 2, the baseband unit 10 includes a signal generation unit 11, an output control unit 12, and a DAC 13. The signal generation unit 11 generates an arbitrary reference waveform by a digital signal processor (DSP) 26, a waveform memory 40 (see FIG. 3), or the like, which will be described later. The DAC 13 has a function as a digital / analog converter (DAC) that converts waveform data having a reference waveform output from the signal generation unit 11 from a digital signal to an analog signal. The output control unit 12 processes the waveform data generated by the signal generation unit 11 in parallel, and controls the output timing of the waveform data with respect to the DAC 13. The signal generation unit 11, the output control unit 12, and the DAC 13 correspond to the signal processing unit, the timing control unit, and the signal conversion unit of the present invention, respectively.

In the configuration of the baseband 10 shown in FIG. 1, for example, the signal generation unit 11 and the output control unit 12 are realized by a field programmable gate array (hereinafter referred to as “FPGA”) 20 (see FIG. 3). The FPGA 20 can realize most of the functions particularly digitally processed in the measuring device. In the signal generator 100 according to the present embodiment, the program data stored in the storage means is read out and transferred to the FPGA 20 when the power is turned on. As a result, the circuit configuration based on the program data is determined, and a predetermined measurement function is realized.

In the FPGA 20, for example, as shown in FIG. 3, a DAC interface (I / F) unit 21, a trigger signal interface (Trigger I / F) unit 22, a delay coarse adjustment unit (Coarse Delay Adjustment) 23, and an output timing control unit ( Output Control) 24, delay fine adjustment unit (Fine Delay Adjustment) 25, DSP (Digital Signal Processing) 26, waveform memory interface (Wave Memory I / F) unit 27, CPU interface (I / F) unit 28 Has been realized.

In the FPGA 20, the DSP 26, the waveform memory I / F unit 27, and the CPU I / F unit 28 constitute the signal generation unit 11 in FIG. 1. Further, in the FPGA 20, the trigger signal I / F unit 22, the delay coarse adjustment unit 23, the output timing control unit 24, and the delay fine adjustment unit 25 constitute the output control unit 12 in FIG. 1.

In the portion corresponding to the signal generation unit 11 in the FPGA 20, the test signal generation command transmitted from the CPU 31 is given to the waveform memory I / F unit 27 via the CPU I / F unit 28. When the test signal generation command is given, the waveform memory I / F unit 27 reads the waveform data from the waveform memory (Wave Memory) 40 and sends it to the DSP 26. The waveform memory 40 stores waveform data according to a plurality of standards such as LTE, and the waveform memory I / F unit 27 conforms to the standard of the test signal to which the generation command is given. The waveform data is sent to the DSP 26.

The DSP 26 performs various digital signal processing such as interpolation processing on the waveform data transmitted from the waveform memory I / F unit 27, and transmits the waveform data to the output timing control unit 24.

The output control unit 12 controls the output timing of the waveform data transmitted from the DSP 26 by the delay control of the trigger signal St1 input from the outside. The delay control of the trigger signal St1 will be described in detail later. The DAC I / F unit 21 transmits the waveform data transmitted from the output control unit 12 to the DAC 13 by controlling the output timing.

The DAC 13 performs a D / A conversion process of converting the waveform data transmitted from the DAC I / F unit 21 from a digital signal to an analog signal.

Here, the clock for operating the signal generation unit 11 and the DAC 13 respectively and the parallel processing of the signals transmitted and received between them will be described.

Let the sampling rate of the DAC 13 be N [Hz]. At this time, the time resolution (hereinafter referred to as resolution) of the trigger delay that can be set by the user is 1 / N [s] (= Y). Further, when the number of parallel processes is L (L is a positive integer), the operating clock of the signal generation unit 11 is N / L [Hz]. The resolution in this case is L / N (= X).

From this, it can be seen that X, which is involved in the operation clock of the signal generation unit 11, and Y, which is involved in the sampling rate of the DAC 13, exist as factors that determine the resolution of the delay control of the waveform data in parallel with L. .. Based on this finding, in this embodiment,
aX + nY ・ ・ ・ (1)
In order to achieve the resolution represented by, the delay control of the trigger signal St1 is performed. In the above equation (1), X is a parameter related to the rough adjustment described later, and Y is a parameter related to the fine adjustment described later.

When the trigger delay set by the user is M / N [s] (M is a positive integer), a in the above equation (1) is a value obtained by rounding down the decimal point of M / L, a = Int (M ÷). It can be calculated as L). However, in reality, the bit width prepared by the hardware resource may be limited to the possible range. The range of a is any positive integer. Further, n is a value corresponding to the remainder of M / L (hereinafter, the remainder value), (n = Mod (M ÷ L)). The range of n is 0 to (L-1).

In the present embodiment, the signal generation unit 11 generates waveform data based on, for example, an operating clock of 100 MHz, while the DAC 13 receives the waveform data in 4 parallels (the number of parallel processes is 4), for example, 400 MHz. It is assumed that the D / A conversion process is performed at the sampling rate.

In FIG. 4, (a) shows the operation clock of the signal generation unit 11, and (b), (c), (d), and (e) show the waveform data of each column of the four parallels, respectively. There is. Here, the data in the first column are arranged in the time direction (D0, D4, D8, D12, ...). Similarly, the data in the second column is (D1, D5, D9, D13, ...), The data in the third column is (D2, D6, D10, D14, ...), And the data in the fourth column is. The data of is (D3, D7, D11, D17).

The output control unit 12 provided between the signal generation unit 11 and the DAC 13 controls the output timing of the four parallel waveform data (see FIG. 4) transmitted from the DSP 26 with respect to the DAC 13. This output timing control is realized by the control that delays the trigger signal St1.

In the present embodiment, the delay control of the trigger signal St1 is carried out by the delay coarse adjustment unit 23 and the delay fine adjustment unit 25 constituting the output control unit 12. The delay coarse adjustment unit 23 performs delay coarse adjustment of the trigger signal St1 based on the parameter X of the above equation (1), and the delay fine adjustment unit 25 performs delay fine adjustment based on the parameter Y of the above equation (1). It is supposed to do.

The delay coarse adjustment unit 23 has a counter 23a, for example, as shown in FIG. The counter 23a starts counting when a in the above equation (1) is given as a control signal and the trigger signal St1 is input, and when the counting of the above a is completed, the trigger signal St1 is used as the coarse adjustment trigger signal St1a. Output. As a result, the delay coarse adjustment of the trigger signal St1 based on the parameter of X in the above equation (1) is performed.

The delay fine adjustment unit 25 has, for example, a flip-flop (FFs) circuit unit 25a and a selector 25b, as shown in FIG. The FF circuit unit 25a is given n (0 to (L-1)) in the above equation (1) as a control signal. In the present embodiment, any value between 0 and 3 is input as the control signal n.

The delay fine adjustment unit 25 takes in the four parallel waveform data from the DSP 26 transmitted by the output control unit 12 in response to the input of the coarse adjustment trigger signal St1a described above, and inputs the four parallel waveform data to the selector 25b. Of the four parallel waveform data captured, the waveform data of each of the second to fourth columns (three parallels) is also input to the FF circuit unit 25a. The FF circuit unit 25a takes in the input three parallel waveform data, holds it for a time corresponding to the above a, and sends it to the selector 25b at the first clock after the holding time has elapsed.

The selector 25b collectively outputs the waveform data of the first column that does not pass through the FF circuit unit 25a and the waveform data of the remaining three columns that pass through the FF circuit unit 25a to the DAC 13 as four parallel waveform data. This output processing is performed at each clock timing of the operating clock until the four parallel data are exhausted.

Next, the trigger signal delay control in the signal generator 100 according to the present embodiment will be described with reference to FIGS. 7 and 8.

In executing the delay control of the trigger signal St1 in the signal generator 100, it is necessary to set in advance an adjustment value for adjusting the delay amount of the trigger signal St1. To achieve this, the user sets a trigger delay request value (trigger delay value). In this case, for example, the user operates the operation unit 37 to display the setting screen on the display unit 38, and inputs a desired trigger delay value (trigger signal delay amount) on the setting screen. As a result, the delay request value setting unit 32 stores the input trigger delay value in a storage area such as the RAM 36. Here, the user can set the value of M / N as the trigger delay value based on the sampling rate N [Hz] of the DAC 13.

When the trigger delay value is set, the adjustment value setting unit 33 sets a and n in the above equation (1) to the first adjustment value and the second adjustment value, respectively, based on the set trigger delay value. It is calculated as the adjustment value of, and both adjustment values are stored in, for example, the RAM 36.

The delay control unit 34 executes the delay control of the trigger signal St1 according to the flowchart shown in FIG. 7 based on the set first adjustment value and the second adjustment value. When this delay control is started, the delay control unit 34 first determines whether or not the trigger signal St1 is input (step S1).

Here, when it is determined that the trigger signal St1 has not been input (NO in step S1), the delay control unit 34 continues the process of step S1 and determines that the trigger signal St1 has been input (step S1). YES in S1), and the process proceeds to step S2.

In step S2, the delay control unit 34 uses the trigger signal St1 input from the trigger signal I / F unit 22 as the operation clock of the signal generation unit 11 based on the first adjustment value set by the adjustment value setting unit 33. The process of delay coarse adjustment that delays in the cycle of is executed. Specifically, the delay control unit 34 delays the trigger signal St1 by the time corresponding to the first adjustment value by the delay coarse adjustment unit 23 (see FIG. 5), and outputs it as the coarse adjustment trigger signal St1a.

Next, the delay control unit 34 controls to send the coarse adjustment trigger signal St1a to the output timing control unit 24 (step S3).

Further, the delay control unit 34 outputs the waveform data generated by the DSP 26 in parallel to the delay fine adjustment unit 25 in response to the input of the coarse adjustment trigger signal St1a from the delay coarse adjustment unit 23. The timing control unit 24 is controlled (step S4).

Subsequently, the delay control unit 34 performs a delay fine adjustment process of delaying the four parallel waveform data input from the output timing control unit 24 in the array direction in the sampling cycle of the DAC 13 based on the second adjustment value. (Step S5).

Specifically, the delay control unit 34 targets the delay fine adjustment unit 25 (see FIG. 6) as a control target, and has four parallel waveform data Data [0], Data [1], Data [2], and Data [2] in the first row. 3] is slid to the next column in order by the number of columns corresponding to the second adjustment value, and the rearrangement is controlled.

For example, when the second adjustment value is 0, as shown in FIG. 8A, any of the four parallel waveform data Data [0], Data [1], Data [2], and Data [3]. Do not rearrange. This state corresponds to a state in which there is no delay fine adjustment of the trigger signal St1.

When the second adjustment value is 1, as shown in FIG. 8B, the four parallel waveform data Data [0], Data [1], Data [2], and Data [3] are sequentially input. Control to slide to the next row. Similarly, when the second adjustment values are 2 and 3, as shown in FIGS. 8 (c) and 8 (d), the four parallel waveform data Data [0], Data [1], and Data [1], respectively. 2] and Data [3] are sequentially controlled to slide in the back row for two rows and three rows, respectively.

During the execution of the delay fine adjustment process in step S5, the delay control unit 34 determines whether or not the waveform data of a desired length has been output from the output timing control unit 24 (step S6). Here, if it is determined that the waveform data of a desired length is not output (NO in step S6), the delay control unit 34 returns to step S5 and continues the processing of the steps S5 and S6. During this period, if it is determined that the waveform data of a desired length has been output (YES in step S6), then the delay control unit 34 determines whether or not to output the next waveform data from the output timing control unit 24. (Step S7). Here, if it is determined that the next waveform data output is to be performed (YES in step S7), the delay control unit 34 returns to step S1 and continues the processing after that step S1. On the other hand, when it is determined that the next waveform data output is not performed (NO in step S7), the delay control unit 34 ends the series of trigger signal delay control in steps S1 to S7 described above.

As described above, in the present embodiment, the DSP 26 and the waveform memory 40 use the signal generation unit 11 for generating the waveform data for generating the test signal, and the waveform data generated by the signal generation unit 11 for D / A conversion processing. The DAC 13 to be used and the waveform data generated by the signal generation unit 11 are input to the output timing control unit 24 as waveform data of a plurality of columns, and the timing of outputting the waveform data of the plurality of columns from the output timing control unit 24 to the DAC 13 is controlled. The output control unit 12 is provided.

Then, the output control unit 12 is input from the delay coarse adjustment unit 23 that delays the trigger signal St1 input from the outside in the cycle of the operation clock based on the first adjustment value (aX), and the signal generation unit 11. It has a delay fine adjustment unit 25 that delays the waveform data of a plurality of columns in the array direction at a sampling rate cycle based on the second adjustment value (nY) at the timing when the delayed trigger signal St1a is input. is doing.

With this configuration, in the present embodiment, not only the trigger signal St1 is delayed by the cycle of the operation clock of the signal generation unit 11, but also the trigger signal St1 is delayed by the cycle of the sampling rate of the DAC13, so that the trigger signal St1 has the time resolution of the sampling rate. You will be able to perform delay control of.

Further, in the present embodiment, when the time resolution of the trigger delay when the sampling rate is N [Hz] is Y, and when the number of parallel processes is L (L is a positive integer), the time resolution by the operation clock is X. The delay request value setting unit 32, which sets M / N (M is a positive integer) as the trigger delay request value, and the value a obtained by dividing M by L (M / L), rounded down to the nearest whole number, are counted. Further, there is an adjustment value setting unit 33 in which aX to be set is set as the first adjustment value and nY having a remainder value n of (M / L) as a count is set as a second adjustment value.

With this configuration, in the present embodiment, the user can easily execute the first adjustment value, the delay coarse adjustment based on the second adjustment value, and the delay fine adjustment only by setting the trigger delay request value. Can be done.

(Second embodiment)
Next, the signal analysis device 200 according to the second embodiment will be described with reference to FIGS. 9 to 12.

The signal analysis device 200 according to the present embodiment constitutes the measuring device of the present invention, and for example, as shown in FIG. 9, measures the measured signal transmitted by the DUT 5 in response to the external trigger signal St2. Is. The trigger signal St2 is given to the DUT 5 and the signal analysis device 200, and is used in the signal analysis device 200 for control for adjusting the measurement timing of the signal to be measured transmitted by the DUT 5.

As shown in FIG. 10, the signal analysis device 200 includes an RF unit 50, an ADC 51, an analysis processing unit 52, and a control unit 30a.

The RF unit 50 receives the measured signal transmitted from the DUT 5, and converts the measured signal into an intermediate frequency band signal (IF signal) by mixing the measured signal with the local signal.

The ADC 51 functions as an analog-to-digital converter (ADC) that performs an A / D conversion process for converting an analog signal to a digital signal at a predetermined sampling rate from the signal to be measured converted into an IF signal by the RF unit 50. Have.

The analysis processing unit 52 includes an acquisition control unit 53 and a detection unit 54. The detection unit 54 captures the signal to be measured, which is a digital signal output by the ADC 51, via the control unit 53, and generates waveform data corresponding to the I component baseband signal and the Q component baseband signal by digital processing. .. Further, the analysis processing unit 52 performs a process of analyzing the I component baseband signal and the Q component baseband signal based on the waveform data.

The capture control unit 53 controls the input timing of the signal transmitted / received between the ADC 51 and the analysis processing unit 52, that is, the detection unit 54 of the signal to be measured output by the ADC 51. The ADC 51, the analysis processing unit 52, and the acquisition control unit 53 correspond to the signal conversion unit, the signal processing unit, and the timing control unit of the present invention, respectively.

The control unit 30a has the same configuration as the control unit 30 of the signal generator 100 according to the first embodiment. Further, although not shown, the signal analysis device 200 according to the present embodiment has an operation unit 37 and a display unit 38 equivalent to the signal generation device 100.

In the configuration of the signal analysis device 200 shown in FIG. 10, for example, the analysis processing unit 52 can be realized by, for example, the FPGA 60.

In the FPGA 60, for example, as shown in FIG. 11, the ADC I / F unit 61, the DSP (Digital Signal Processing 1) 62, the trigger signal I / F unit 63, the delay coarse adjustment unit 64, and the capture timing control unit (Capture Control) 65. , The delay fine adjustment unit 66, the waveform memory I / F unit 67, the waveform adjustment DSP (Digital Signal Processing2) 68, and the CPU I / F unit 69 are realized.

In the FPGA 60, the trigger signal I / F unit 63, the delay coarse adjustment unit 64, the acquisition timing control unit 65, and the delay fine adjustment unit 66 constitute the acquisition control unit 53 in FIG. 10, and the other functional units are in FIG. It constitutes a detection unit 54.

In the FPGA 60, the ADC I / F unit 61 takes in the measured signal output by the ADC 51 in the A / D conversion process and sends it to the DSP 62. The DSP 62 generates waveform data based on the input measured signal, for example, by a processing start command from the CPU 31a. The waveform data generated by the DSP 62 is taken into the waveform memory I / F unit 67 by the take-in timing control described later by the take-in timing control unit 65.

A waveform adjustment command is input from the CPU 31a to the waveform memory I / F unit 67. When the waveform adjustment command is input, the waveform memory I / F unit 67 reads the waveform data for adjustment from the waveform memory 40a and sends it to the DSP 68. The DSP 68 generates waveform data whose waveform has been adjusted based on the waveform data for adjustment. The CPU I / F unit 28 sends waveform-adjusted waveform data to the CPU 31a. The CPU 31a executes processing such as analysis of the signal to be measured based on the waveform data input from the CPU I / F unit 28.

In the above-mentioned series of processes relating to the analysis of the signal to be measured in the FPGA 60, the acquisition timing control unit 65 in the FPGA 60 receives the waveform data of a plurality of digital columns from the input side (ADC51 in this example), and the waveform data. Is shared with the output control unit 12 of the signal generator 100 according to the first embodiment with respect to the process of taking the data into the output side (in this example, the analysis processing unit 52). Further, the delay coarse adjustment unit 64 and the delay fine adjustment unit 66 each relate to the first embodiment with respect to a function of controlling the timing of transmitting and receiving digital waveform data of a plurality of columns between the input side and the output side. It has the same configuration as the delay coarse adjustment unit 23 and the delay fine adjustment unit 25 of the signal generator 100.

In the operation mode shown in FIG. 9, the signal analysis device 200 having the above configuration is a trigger signal input to the own device in order to measure and process the measured signal transmitted by the DUT 5 based on the trigger signal St2 at an appropriate timing. Control is performed to delay St2.

In the signal analysis device 200, the operation clock of the analysis processing unit 52 is set to 100 MHz, and the sampling frequency of the ADC 51 is set to 400 MHz. In this case, in the acquisition timing control unit 65, the delay coarse adjustment unit 64 performs rough adjustment control regarding the delay of the trigger signal St2 based on the operation clock of the analysis processing unit 52, and the delay fine adjustment unit 66 performs the sampling rate of the ADC 51. Fine adjustment control regarding the delay of the trigger signal St2 is performed based on.

The trigger signal delay control operation in the capture control unit 53 in the signal analysis device 200 will be described with reference to the flowchart shown in FIG. In this description, FIGS. 5, 6, and 8 used for explaining the trigger signal delay control operation in the signal generator 100 according to the first embodiment are also referred to. In this case, the delay coarse adjustment unit 23 shown in FIG. 5, the trigger signal St1, the coarse adjustment trigger signal St1a, and the delay fine adjustment unit 25 in FIG. 6 are the delay coarse adjustment unit 64, the trigger signal St2, and the coarse adjustment trigger, respectively. It shall be read as the signal St2a and the delay fine adjustment unit 66. In addition, the necessary replacement is done. Further, in the flowchart of FIG. 12, for the processes corresponding to the processes of S1 to S7 of the flowchart shown in FIG. 7, the same numbers as those of FIG. 7 are designated by the reference numeral “a”, and the signal transmission in FIG. 7 is performed. It is associated with the flow of the trigger signal delay control of the device 100.

In this embodiment as well, it is assumed that the trigger delay value, the first adjustment value, and the second adjustment value are set in advance as in the first embodiment.

In the signal analysis device 200, the delay control unit 34 of the control unit 30a controls the delay of the trigger signal St2 according to the flowchart shown in FIG. 12 based on the set first adjustment value and the second adjustment value. Execute. When this delay control is started, the delay control unit 34 first determines whether or not the trigger signal St2 is input (step S1a).

Here, when it is determined that the trigger signal St2 has not been input (NO in step S1a), the delay control unit 34 continues the processing of step S1a, and when it is determined that the trigger signal St2 has been input (step). YES in S1a), the process proceeds to step S2a.

In step S2a, the delay control unit 34 uses the trigger signal St2 input from the trigger signal I / F unit 63 as the operation clock of the analysis processing unit 52 based on the first adjustment value set by the adjustment value setting unit 33. The process of delay coarse adjustment that delays in the cycle of is executed. Specifically, the delay control unit 34 delays the trigger signal St2 by the time corresponding to the first adjustment value by the delay coarse adjustment unit 64 (see FIG. 5), and outputs it as the coarse adjustment trigger signal St2a.

Next, the delay control unit 34 controls to send the coarse adjustment trigger signal St2a to the capture timing control unit 65 (step S3a).

Further, the delay control unit 34 uses the delay adjustment trigger signal from the delay coarse adjustment unit 64 to generate waveform data generated by the DSP 62 based on the signal to be measured that has been A / D converted by the ADC 51 and arranged in four parallel directions. The acquisition timing control unit 65 is controlled so as to be output to the delay fine adjustment unit 66 in response to the input of St2a (step S4a).

Subsequently, the delay control unit 34 performs a delay fine adjustment process of delaying the four parallel waveform data input from the acquisition timing control unit 65 in the array direction at the period of the sampling rate of the ADC 51 based on the second adjustment value. (Step S5a).

Specifically, the delay control unit 34 has (a), (b), (c), and (d), respectively, depending on whether the second adjustment value is 0, 1, 2, or 3. Control is performed to rearrange the four parallel waveform data Data [0], Data [1], Data [2], and Data [3] so as to form an array of.

During the execution of the delay fine adjustment process in step S5a, the delay control unit 34 determines whether or not the acquisition timing control unit 65 has acquired waveform data of a desired length (step S6a). Here, if it is determined that the waveform data of a desired length has not been captured (NO in step S6a), the delay control unit 34 returns to step S5a and continues the processing of the steps S5a and S6a. During this time, if it is determined that the waveform data of a desired length has been captured (YES in step S6a), then the delay control unit 34 determines whether or not the capture timing control unit 65 captures the next waveform data. Determination (step S7a). Here, if it is determined that the next waveform data is to be captured (YES in step S7a), the delay control unit 34 returns to step S1a and continues the processing after that step S1a. On the other hand, when it is determined that the next waveform data is not fetched (NO in step S7a), the delay control unit 34 ends the series of trigger signal delay control in steps S1a to S7a described above.

As described above, in the present embodiment, the ADC 51 that performs A / D conversion processing on the measured signal after frequency conversion and the measured signal that has undergone A / D conversion processing are taken in as waveform data of a plurality of columns, and the base band signal is obtained. The analysis processing unit 52 restored to the above and the waveform data after the A / D conversion processing in the ADC 51 are input to the acquisition timing control unit 65 as the waveform data of a plurality of columns, and the waveform data of the plurality of columns is input by the acquisition timing control unit 65. It has an import control unit 53 that controls the timing of import to the analysis processing unit 52. Then, the capture control unit 53 delays the trigger signal St2 input from the outside in the cycle of the operation clock based on the first adjustment value (aX), and the delay coarse adjustment unit 64 and the plurality of rows input from the ADC 51. It has a delay fine adjustment unit 66 that delays the waveform data of the above in the array direction in the cycle of the sampling rate based on the second adjustment value (nY) at the timing when the delayed trigger signal St2a is input. ..

With this configuration, in the present embodiment, the trigger signal St2 is delayed not only by the cycle of the operation clock of the analysis processing unit 52 but also by the cycle of the sampling rate of the ADC 51, so that the trigger signal St2 has the time resolution of the sampling rate. You will be able to perform delay control of.

Further, also in this embodiment, the same delay request value setting unit 32 and adjustment value setting unit 33 as in the first embodiment are provided. With this configuration, also in the present embodiment, as in the first embodiment, the user simply sets the trigger delay request value, the first adjustment value, the delay rough adjustment based on the second adjustment value, and the delay coarse adjustment. Delay fine-tuning can be easily performed.

(Third embodiment)
The measuring device 1 according to the third embodiment has a configuration of a superordinate concept of the signal generator 100 according to the first embodiment and the signal analysis device 200 according to the second embodiment. In FIGS. 1 and 10, reference numerals “1” indicating that the signal generation device 100 and the signal analysis device 200 are the measuring devices 1 according to the present embodiment are also shown.

As described in the first and second embodiments, the signal generation unit 11 of the signal generation device 100 and the analysis processing unit 52 of the signal analysis device 200 respectively use a predetermined operating clock to generate a test signal or a signal to be measured. It has the function of a signal processing unit that performs processing to generate the corresponding waveform data. Further, the DAC 13 of the signal generator 100 and the ADC 51 of the signal analysis device 200 sample waveform data at a sampling rate faster than the operating clock of the signal processing unit including the DAC 13 or the ADC 51, respectively, and perform D / A conversion or A /. It has a function of a signal conversion unit that performs D conversion processing.

Further, the output control unit 12 of the signal generator 100 and the capture control unit 53 of the signal analysis device 200 each have a plurality of columns of waveform data generated by the signal processing unit, which correspond to the ratio of the operating clock and the sampling rate. The timing of inputting as waveform data and outputting the plurality of columns of waveform data to the signal conversion unit, or the waveform data after signal conversion by the signal conversion unit is input as the waveform data of the plurality of columns corresponding to the above ratio. It has a function of a timing control unit that controls the timing of importing the waveform data of the plurality of columns into the signal processing unit.

From the above, the measuring device 1 according to the present embodiment is a signal conversion unit that samples waveform data at a sampling rate faster than the operating clock of the signal processing unit and performs D / A conversion or A / D conversion processing. (13, 51) and the waveform data generated by the signal processing unit are input as a plurality of columns of waveform data corresponding to the ratio of the operating clock and the sampling rate, and the plurality of columns of waveform data are output to the signal conversion unit. Timing control that controls the timing at which the waveform data after signal conversion in the signal conversion unit is input as the waveform data in a plurality of columns corresponding to the above ratio and the waveform data in the plurality of columns is taken into the signal processing unit. It has a part (12, 53) and.

Further, the timing control unit delays the trigger signals (St1, St2) input from the outside in the cycle of the operation clock based on the preset first adjustment value (aX), and the delay coarse adjustment unit (23, 64) and a second adjustment value (nY) preset at the timing when the delayed trigger signals (St1a, St2a) input the waveform data of a plurality of columns input from the signal processing unit or the signal conversion unit. Based on the above, it has a delay fine adjustment unit (25, 66) that delays in the arrangement direction in the cycle of the sampling rate.

Then, according to the configuration of the measuring device 1 according to the present embodiment, the same operation and effect as the signal generating device 100 according to the first embodiment and the signal analysis device 200 according to the second embodiment can be expected.

(Other embodiments)
In the first and second embodiments, the configuration of the signal generator 100 and the signal analysis device 200 as independent measuring devices according to the present invention has been described, but the present invention is not limited to this, and the signal generator 100 and the signal analysis device are not limited to this. It may be a configuration in which both of 200 are provided. Further, the sampling rates of the DAC 13 and the ADC 51 and the operating clocks of the signal generation unit 11 and the analysis processing unit 52 described above can be arbitrarily set together with the number of parallel processing of the waveform data.

As described above, the measuring device and the measuring method according to the present invention have the effect that higher resolution can be achieved in the delay control of the trigger signal that controls the processing start timing of the signal sent to and received from the device under test. DAC, ADC, which measures mobile terminals such as various types of mobile phones such as LTE and mobile terminals, and has a faster sampling rate with respect to the operating clock of the signal generation unit and analysis processing unit. It is useful as a measurement device such as a signal generator or a signal analysis device and a measurement setting method.

1 Measuring device 11 Signal generation unit (signal processing unit)
12 Output control unit (timing control unit)
13 DAC (Signal Converter)
23, 64 Delay coarse adjustment unit 25, 66 Delay fine adjustment unit 26 DSP (Digital Signal Processor)
32 Delay request value setting unit (setting means)
33 Adjustment value setting unit (adjustment value setting means)
40, 40a Waveform memory 51 ADC (Signal converter)
52 Analysis processing unit (signal processing unit)
53 Import control unit (timing control unit)
100 Signal generator (measuring device)
200 Signal analysis device (measuring device)

Claims (5)

A measuring device (1, 100, 200) that performs measurement of the device to be measured by executing a process of transmitting a test signal to the device to be measured (5) or a process of receiving a signal to be measured from the device to be measured.
A signal processing unit (11, 52) that performs processing to generate waveform data corresponding to the test signal or the measured signal with a predetermined operating clock, and the signal processing unit (11, 52).
A signal conversion unit (13, 51) that samples the waveform data at a sampling rate faster than the operating clock of the signal processing unit and performs D / A conversion or A / D conversion processing.
Timing of inputting the waveform data generated by the signal processing unit as waveform data of a plurality of columns corresponding to the ratio of the operation clock to the sampling rate and outputting the waveform data of the plurality of columns to the signal conversion unit. Alternatively, timing control for inputting the waveform data after signal conversion in the signal conversion unit as waveform data in a plurality of columns corresponding to the ratio and controlling the timing of importing the waveform data in the plurality of columns into the signal processing unit. With parts (12, 53),
The timing control unit
A delay coarse adjustment unit (23, 64) that delays a trigger signal input from the outside in the cycle of the operation clock based on a preset first adjustment value (aX).
The sampling of the plurality of columns of waveform data input from the signal processing unit or the signal conversion unit based on a second adjustment value (nY) set in advance at the timing when the delayed trigger signal is input. A delay fine-tuning unit (25, 66) that delays in the array direction in the cycle of the rate,
A measuring device characterized by having. When the time resolution of the trigger delay when the sampling rate is N [Hz] is Y , and when the number of parallel processes is L (L is a positive integer), the time resolution by the operation clock is X, and M / Setting means (32) for setting N (M is a positive integer) as a trigger delay request value, and
The value a obtained by dividing M by L (M / L) rounded down to the nearest whole number is set as the first adjustment value, and the remainder value n of the (M / L) is used as the count. The measuring device according to claim 1, further comprising an adjustment value setting means (33) for setting nY as the second adjustment value. As the signal processing unit, the digital signal processor (26) and the waveform memory (40) have a signal generation unit (11) for generating waveform data for generating the test signal.
The signal conversion unit includes a D / A conversion unit (13) that performs D / A conversion processing on the waveform data generated by the signal generation unit.
As the timing control unit, output control for controlling the timing of inputting the waveform data generated by the signal generation unit as the waveform data of the plurality of columns and outputting the waveform data of the plurality of columns to the D / A conversion unit. The measuring device according to claim 1 or 2, wherein the signal generating device (100) has a unit (12). The signal conversion unit includes an A / D conversion unit (51) that performs A / D conversion processing on the signal to be measured after frequency conversion.
The signal processing unit includes an analysis processing unit (52) that captures the A / D-converted processed signal as waveform data of the plurality of columns and restores the baseband signal.
As the timing control unit, the waveform data after signal conversion in the A / D conversion unit is input as the waveform data of the plurality of columns, and the timing of importing the waveform data of the plurality of columns into the analysis processing unit is controlled. The measuring device according to claim 1 or 2, wherein the signal analysis device (200) has an capture control unit (53). A measuring method for measuring a measured device by executing a test signal transmission process to the measured device or a measured signal reception process from the measured device by the measuring device according to claim 1. hand,
In the timing control unit, a delay coarse adjustment step (S2) in which a trigger signal input from the outside is delayed in the cycle of the operation clock based on a preset first adjustment value, and
The period of the sampling rate of the waveform data of the plurality of columns input from the signal processing unit or the signal conversion unit based on the second adjustment value set in advance at the timing when the delayed trigger signal is input. Delay fine adjustment step (S5) to delay in the arrangement direction with
A measurement method comprising.

Images