JP7017016B2 - Normal off operation diamond power device and inverter using it - Google Patents

Description

The present invention relates to a normally-off operation diamond power device and an inverter using the same.

Diamond is expected as a semiconductor material suitable for power devices that are required to operate under high voltage and high current conditions. Various field effect transistors (FETs) using a diamond substrate have been proposed so far. In Patent Document 1, a two-dimensional hole gas (2DHG) layer is generated directly under the hydrogenated layer by hydrogenating the surface of the diamond substrate, and this is used as a channel layer of a field effect transistor. Diamond FETs to be used have been proposed.

Japanese Unexamined Patent Publication No. 2014-60377

By the way, since the 2DHG layer generated by hydrogenating the surface of the diamond substrate exists even when the gate voltage is not applied, the diamond FET proposed in Patent Document 1 operates in the normalion mode. From the viewpoint of reducing power consumption, safety, and applicability to existing circuits, it is preferable that the power device operates in the normal off mode, and a diamond power device that operates in the normal off mode is desired.
The present invention has been made in view of the above circumstances, and provides a diamond power device that operates in a normal off mode and an inverter using the same.

The first aspect of the present invention comprises a diamond field effect transistor and an enhancement type p-channel field effect transistor connected in series to the diamond field effect transistor, wherein the diamond field effect transistor is provided on a diamond substrate with a drain electrode and a drain electrode. A source electrode provided on the diamond substrate away from the transistor, a hydrogenated layer provided on the surface of the diamond substrate between the drain electrode and the source electrode and having a carbon hydrogen bond, a gate insulating film covering the hydrogenated layer, and a gate. Provided is a diamond power element including a gate electrode provided on an insulating film.

A second aspect of the present invention provides an inverter comprising the diamond power element of the first aspect and an n-channel field effect transistor connected in series with the diamond power element.

INDUSTRIAL APPLICABILITY According to the present invention, a diamond power device operating in a normal off mode and an inverter using the same are provided.

It is a circuit diagram of the diamond power element by 1st Embodiment of this invention. It is sectional drawing which shows typically the diamond field effect transistor of the diamond power element of this embodiment. It is an equivalent circuit diagram of the diamond field effect transistor when a gate voltage is applied. It is an equivalent circuit diagram of the diamond field effect transistor when the gate voltage is not applied. It is a graph which shows the current-voltage characteristic of the diamond power element of this embodiment. It is a graph which shows the other current-voltage characteristic of the diamond power element of this embodiment. For comparison, it is a graph which shows the current-voltage characteristic of the diamond field effect transistor in the diamond power element of this embodiment. It is a graph which shows the withstand voltage characteristic of the diamond power element of this embodiment. It is a circuit diagram which shows the inverter by the 2nd Embodiment of this invention. It is a graph which shows the operation characteristic of the inverter of this embodiment. It is a circuit diagram of the complementary type inverter of this invention which concerns on Example 1. FIG. It is a circuit diagram of the complementary type inverter of this invention which concerns on Example 2. FIG. (A) is a diagram showing an input voltage waveform input to the second stage circuit of the complementary inverter of the present invention, and (b) is input to the first stage circuit of the complementary inverter of the present invention. It is a figure which shows the input voltage waveform and the output voltage waveform output from the circuit of the 2nd stage.

Hereinafter, non-limiting exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In all the attached drawings, the same or corresponding members or parts are designated by the same or corresponding reference numerals, and duplicate description is omitted.

(First Embodiment)
Hereinafter, the diamond power device according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 8.

FIG. 1 is a circuit diagram of a diamond power device 1 according to the present embodiment. As shown in the figure, the diamond power element 1 has a diamond field effect transistor (hereinafter referred to as a diamond FET (Field Effect Transistor)) 10 and a p-channel field effect transistor (hereinafter referred to as a p-FET) 20. The diamond FET 10 and the p-FET 20 are connected in series with each other. That is, the source 10s of the diamond FET 10 is connected to the drain 20d of the p-FET 20. Further, the gate 10g of the diamond FET 10 is connected to the source 20s of the p-FET 20. That is, the diamond power element 1 of the present embodiment has a drain terminal D (corresponding to the drain terminal of the diamond FET 10), a source terminal S (corresponding to the source terminal of the p-FET 20), and a gate terminal G (corresponding to the gate terminal of the p-FET 20). It has a configuration like a three-terminal element having (corresponding to).

Next, the diamond FET 10 will be described. Referring to FIG. 2, the diamond FET 10 is a substrate 11 between the drain electrode 12 provided on the substrate 11, the source electrode 13 provided on the substrate 11 away from the drain electrode 12, and the drain electrode 12 and the source electrode 13. It includes a hydride layer 15 provided on the surface and having a carbon hydrogen (CH) bond, a gate insulating film 16 covering the hydride layer 15, and a gate electrode 14 provided on the gate insulating film 16. The gate insulating film 16 has a contact hole 17 above the drain electrode 12 and the source electrode 13, and the drain electrode 12 and the source electrode 13 are exposed upward through the contact hole 17. The gate electrode 14 is provided on the gate insulating film 16 between the drain electrode 12 and the source electrode 13.

The substrate 11 is made of diamond. In the present embodiment, the substrate 11 has a single crystal (Ib (001)) diamond substrate 11a and an undoped diamond layer 11b epitaxially grown on the surface thereof. The diamond layer 11b can be grown, for example, by microwave chemical vapor deposition (CVD). The thickness of the diamond layer 11b may be, for example, about 100 nm.

The drain electrode 12 has a titanium carbide (TiC) layer 12a, a titanium (Ti) layer 12b, and a gold (Au) layer 12c. The Ti layer 12b and the Au layer 12c can be formed, for example, by sequentially using a photolithography technique, a vapor deposition method, and a lift-off method. The TiC layer 12a can be formed, for example, by heating the substrate 11 after forming the Ti layer 12b and the Au layer 12c and diffusing the Ti constituting the Ti layer 12b into the diamond layer 11b immediately below the Ti layer 12b. The TiC layer 12a makes the drain electrode 12 ohmic contact with the diamond layer 11b.

The source electrode 13 has a TiC layer 13a, a Ti layer 13b, and an Au layer 13c. Since the layers 13a to 13c of the source electrode 13 are the same as the layers 12a to 12c of the drain electrode 12, detailed description thereof will be omitted.

The thicknesses of the Ti layers 12b and 13b and the Au layers 12c and 13c may be appropriately determined. For example, the thickness of the Ti layers 12b, 13b may be in the range of 3 nm to 50 nm, and the thickness of the Au layers 12c, 13c may be in the range of 50 nm to 1 μm. Specifically, the Ti layers 12b and 13b preferably have a thickness of about 30 nm, and the Au layers 12c and 13c preferably have a thickness of about 100 nm.

The hydrogenated layer 15 is formed on the surface of the diamond layer 11b between the drain electrode 12 and the source electrode 13. In the hydrogenated layer 15, the dangling bond of the carbon (C) atom forming the diamond layer 11b is terminated by the hydrogen (H) atom (that is, a CH bond is formed). The hydrogenated layer 15 induces a two-dimensional hole gas (2DHG) layer (not shown) in the diamond layer 11b immediately below the hydrogenated layer 15. The 2DHG layer functions as a p-type channel layer of the diamond FET 10. Since the 2DHG layer exists even when the gate voltage is not applied to the diamond FET 10, the diamond FET 10 functions as a depletion type element.

The hydrogenated layer 15 can be formed, for example, as follows. First, the surface of the diamond layer 11b is exposed to hydrogen plasma while heating the substrate 11 on which the drain electrode 12 and the source electrode 13 are formed to, for example, 600 ° C. As a result, the entire surface of the diamond layer 11b is hydrogen-terminated except for the portion covered by the drain electrode 12 and the source electrode 13. Next, after covering a predetermined range including the region between the drain electrode 12 and the source electrode 13 with a photoresist mask, the diamond layer 11b is exposed to oxygen plasma. The surface of the region exposed to the oxygen plasma is oxidized to eliminate the CH bond, and the hydrogenated layer 15 is removed from this region. On the other hand, CH bonds remain in the region covered with the photoresist mask, and when this photoresist mask is removed, a hydrogenated layer 15 having a predetermined size is obtained.

The gate insulating film 16 is made of alumina (Al ₂ O ₃ ). The gate insulating film 16 electrically insulates the gate electrode 14 from the hydrogenated layer 15, and also functions as a protective film for protecting the hydrogenated layer 15. The thickness of the gate insulating film 16 can be appropriately determined, but from the viewpoint of improving the withstand voltage of the diamond FET 10, it is preferably 50 nm or more, preferably 100 nm or more, and more preferably 400 nm or more.

The gate insulating film 16 can be formed by an atomic layer deposition (ALD) method using trimethylaluminum (TMA) and water ( _H2O ) in a vapor phase state as raw materials.

The gate electrode 14 is arranged on the gate insulating film 16 at a predetermined distance from each of the drain electrode 12 and the source electrode 13. The gate-drain spacing _LGD , gate-source spacing _LGS , and gate length _{LG can be determined as appropriate, but the gate-drain spacing LGD is} 1 to 30 μm, the gate-source spacing _LGS is 1 to 10 μm, and the gate. The length _LG is preferably in the range of 1 to 20 μm. The gate electrode 14 is made of, for example, aluminum (Al). The gate electrode 14 can be formed, for example, by sequentially using a photolithography technique, a vapor deposition method, and a lift-off method. The thickness of the gate electrode 14 may be, for example, about 0.5 μm.

The contact hole 17 is formed, for example, by forming a photoresist mask having an opening above the drain electrode 12 and the source electrode 13 and removing the gate insulating film 16 exposed to the opening with tetramethylammonium hydroxide (TMAH). Will be done. As a result, the drain electrode 12 and the source electrode 13 are exposed through the contact hole 17. The contact hole 17 is preferably formed before the gate electrode 14 is formed. According to this, when forming the gate electrode 14, Al is also deposited on the drain electrode 12 and the source electrode 13 exposed through the contact hole 17, and the deposited Al layer is used as a contact layer (not shown). can do.

The p-FET 20 (FIG. 1) is an enhancement type (normali-off type) p-channel FET made of silicon (Si) in the present embodiment. The p-FET 20 is not limited to these, and for example, the gate threshold voltage (Vth) is in the range of −0.8 V to -4 V, and the drain-source breakdown voltage (V _{(BR) DSS} ) is set. FETs in the range of −100V to −200V can be used. Specifically, for example, a commercially available FET such as 2SJ410 manufactured by Renesas Technology Corporation or 2SJ380 manufactured by Toshiba Corporation may be used.

Next, the operation of the diamond power element 1 will be described with reference to FIGS. 3 and 4. FIG. 3 shows an equivalent circuit of the diamond power element 1 when a gate voltage _VGS is applied. When the gate voltage _VGS (the gate terminal G has a negative potential with respect to the source terminal S) is applied, the p-FET 20 (enhancement type) of the diamond power element 1 is turned on, so that the voltage Vab between ab in the figure is It becomes 0V. Since the voltage Vab corresponds to the voltage between the gate and the source of the diamond FET 10 and becomes 0 V, the depletion type diamond FET 10 remains conductive. That is, when the gate voltage _VGS is applied, both the diamond FET 10 and the p-FET 20 are turned on, and the diamond power element 1 is turned on.

FIG. 4 shows an equivalent circuit of the diamond power element 1 when the gate voltage _VGS is not applied. In this case, the p-FET 20 is off and is equivalent to the capacitor 20c generated between the drain and the source. At this time, a current momentarily flows from the depletion type diamond FET 10 to the p-FET 20 by the drain voltage _VDS , and the capacitor 20c is charged. As a result, the voltage Vab becomes a positive voltage (based on b), and the gate-source voltage of the diamond FET 10 becomes −Vab. When this voltage exceeds the threshold voltage of the diamond FET 10, the diamond FET 10 is inverted to off. Therefore, when the gate voltage _VGS is not applied, the diamond power element 1 is turned off. That is, the diamond power element 1 operates in the normal off mode.

From the viewpoint of reducing power consumption, safety, and applicability to existing circuits, it is generally preferable that the power element operates in the normal off mode. However, the diamond FET 10 is a depletion type as described above, and the diamond FET 10 alone is a normalion. Works in mode. On the other hand, according to the diamond power element 1 according to the present embodiment, there is provided a power element that operates in the normal off mode while using the diamond FET 10.

Next, the measurement results of the electrical characteristics of the diamond power device 1 according to the present embodiment will be described. FIG. 5 is a graph showing an example of the current-voltage characteristic (gate voltage-drain current characteristic) of the diamond power element 1. The main specifications of the diamond FET 10 in the diamond power device 1 used for the measurement are as follows.
Thickness of diamond substrate 11a: 500 μm
Thickness of diamond layer 11b: 500 nm
Thickness of Ti layers 12b and 13b: 30 nm
Thickness of Au layers 12c and 13c: 100 nm
Thickness of gate electrode 14: 100 nm
Thickness of gate insulating film 16: 200 nm
Gate width (width of hydrogenated layer 15): 25 μm
Gate-drain distance _LGD : 5 μm
Gate length _LG : 4 μm
Gate-source spacing _LGS : 2 μm

Further, the above-mentioned FET (2SJ380) manufactured by Toshiba Corporation was used as the p-FET 20, and the diamond power element 1 was manufactured by connecting this FET to the diamond FET 10 as shown in FIG. A vacuum chamber equipped with a prober was used for the measurement of the electrical characteristics, and the diamond power element 1 was appropriately stored in this chamber for measurement.

With reference to FIG. 5, it can be seen that even if the drain voltage _VDS (-10V) is applied, no current flows when the gate voltage _VGS is 0V. That is, it was confirmed in the actual measurement that the diamond power element 1 operates in the normal off mode. Further, when the gate voltage V _GS becomes lower than about −0.9 V, the drain current I _DS rises sharply. That is, the threshold voltage of the diamond power element 1 is about −0.9V, and this value is almost the same as the standard value −0.8V to −1.0V of the p-FET 20 used. Even when the above SJ410 was used as the p-FET 20, the threshold voltage of the diamond power element 1 was within the range of the threshold voltage rated value of the 2SJ410. From this result, it can be seen that the threshold voltage of the diamond power element 1 is determined by the threshold voltage of the p-FET 20.

In the graph of FIG. 5, the drain current _IDS is saturated at about -13 mA / mm. This is because when the diamond power element 1 is on, the diamond FET 10 works as a constant current source, and even if the gate voltage of the p-FET 20 rises, the current flowing into the p-FET 20 becomes constant.

Next, the current-voltage characteristic (drain voltage-drain current characteristic) of the diamond power element 1 will be described with reference to FIG. FIG. 6 shows the result of measuring the drain current I _DS by changing the drain voltage V _DS from 0 V to -30 V. At this time, the gate voltage _VGS was used as a parameter and the voltage was changed to −1.2 V in increments of −0.02 V. As the drain voltage V _DS increases in the negative direction, the drain current I _DS also increases, and the drain current I _DS is about -20. When _VGS = -1.2V and V _DS = -30V. It became 8 mA / mm. As a result, it was confirmed that the diamond power element 1 can be used as a power element. In this graph as well, the drain current I _DS is saturated, and especially when the gate voltage _VGS is low, the drain current I _DS is saturated at a low value. This is because the current flowing through the p-FET 20 is limited by the gate voltage _VGS .

Next, for comparison, the current-voltage characteristics of the diamond FET 10 of the diamond power element 1 were measured. That is, while applying the drain voltage V _ds (-10V) between the drain (drain terminal D) of the diamond FET 10 and the source 10s in FIG. 1, the gate voltage V _gs applied between the gate 10 g and the source 10 s is changed. The drain current _Ids was measured. As shown in FIG. 7, even when the gate voltage V _gs is 0 V, a drain current of about -13 mA / mm is flowing. That is, it can be seen that the diamond FET 10 is operating in the normalion mode. By comparing this result with the result shown in FIG. 5, it can be seen that the diamond power device 1 according to the present embodiment operates in the normal off mode while using the diamond FET 10 operating in the normalion mode.

Subsequently, the withstand voltage characteristic of the diamond power element 1 will be described. FIG. 8 is a graph showing the current-voltage characteristics when the gate voltage _VGS is not applied (that is, when it is off). Both the drain current I _DS and the gate current I _GS are plotted in this graph. As shown in this graph, even if the drain voltage V _DS is changed from 0 V to about -1.5 kV, the drain current I _DS is generally within the extremely low range of ^10-8 A to ^10-9 A, and the gate. The current _IGS is generally within the very low range of ^10-12 A to ^10-10 A. Dielectric breakdown occurred when the drain voltage VDS was _-1735V , and from this result, it can be seen that the diamond power device 1 can be suitably used as a high voltage power device.

Further, when the drain voltage V _DS was −200 V (gate voltage V _GS = 0 V), the voltage (divided voltage) applied to each of the diamond FET 10 and the p-FET 20 was measured and found to be applied to the p-FET 20. The voltage was -24.2V. That is, the voltage applied to the p-FET 20 is only about 12% of the drain voltage _VDS . It was found that the diamond FET 10 plays a major role in the withstand voltage of the diamond power element 1.

It has been experimentally confirmed that the p-FET 20 operates normally without being destroyed even when 1.7 kV is applied as the drain voltage _VDS .

(Second embodiment)
Next, the inverter according to the second embodiment will be described with reference to FIG. 9. As shown in the figure, the inverter 100 is an n-channel field effect transistor (hereinafter, n-FET) 30 in which a drain is connected to the above-mentioned diamond power element 1 and a drain terminal D (FIG. 1) of the diamond power element 1. And have. In other words, the inverter 100 is an inverter composed of a diamond power element 1 as a p-channel FET and an n-FET 30 as an n-channel FET. As the n-FET 30, a commercially available high withstand voltage Si n-FET can be used. Here, TK20A60 (manufactured by Toshiba Corporation) was used.

Further, in the inverter 100, the input terminal V _in conducts to the gate terminal G (FIG. 1) of the diamond power element 1 and the gate of the n-FET 30, and the output terminal V _out is the diamond power element 1 and the n-FET 30. It is conducting to the drain.

When a predetermined voltage (referred to as voltage V for convenience of explanation) is applied to the terminal V _dd of the inverter 100 and the terminal V _ss is grounded, when the voltage V is applied to the input terminal _Vin , the diamond power element 1 is turned off. Then, the n-FET 30 is turned on. Therefore, the voltage of the output terminal V _out becomes 0V. When no input voltage is applied to the input terminal _Vin , the diamond power element 1 is turned on and the n-FET 30 is turned off. Therefore, the voltage V is output to the output terminal V _out .

FIG. 10 is a graph showing the operating characteristics of the inverter 100. In this graph, the solid line shows the input voltage and the broken line shows the output voltage. It can be seen that when the input voltage is "low" (0V), the output voltage is "high" (in this case, about 20V), and when the input voltage is "high", the output voltage is "low". That is, it was confirmed that the inverter 100 operates as an inverter.

The output voltage had a delay of about 215 ns when descending with respect to 1 ms per cycle. On the other hand, when rising, a delayed DL of about 290 μs is generated. It is presumed that this delay DL is caused by the fact that the gate length of the diamond FET 10 in the diamond power element 1 is smaller than the gate length of the n-FET 30. By adjusting these, it is expected that the delay DL will be reduced.

As described above, the diamond power device 1 functions as a high withstand voltage p-channel FET operating in the normal off mode. By using such a diamond power element 1 together with an n-FET 30 operating in a high withstand voltage normal off mode, an inverter 100 with a high withstand voltage is provided.

Although the present invention has been described above with reference to some embodiments, the present invention is not limited to these embodiments and can be variously modified or modified.

For example, in the above embodiment, the single crystal diamond substrate 11a is used, but a black polycrystalline diamond substrate may be used. In this case, a polycrystalline diamond layer may or may not be deposited on the surface.

Further, in the above embodiment, the Si FET is exemplified as the p-FET 20, but an enhancement type p-FET made of another material may be used. For example, a p-channel FET composed of germanium (Ge) (including an FET in which Ge or SiGe is adopted as a channel layer) can be used, and a p-channel FET composed of a III-V compound semiconductor can be used. -It may be used as FET 20. For example, a FET having an indium gallium arsenic (InGaAs) layer as a channel layer may be used.

In the diamond power device 1 according to the above embodiment, the gate 10g of the diamond FET 10 and the source 20s of the p-FET 20 are connected to each other, but each may be grounded.

Further, as the n-FET 30 in the inverter 100, not only the FET made of Si but also an n-FET made of other materials can be used. For example, as the n-FET 30, an element using an aluminum gallium nitride (AlGaN) / gallium nitride (GaN) -based n-FET may be used. Specifically, this element can have an AlGaN / GaN-based n-FET (depression type) and an enhancement type n-FET. The source of the AlGaN / GaN system n-FET and the drain of the enhancement type n-FET are connected, and the gate of the AlGaN / GaN system n-FET and the source of the enhancement type n-FET are connected. This allows the element to operate in normal off mode. According to this, a diamond power element 1, a first n-channel field-effect transistor composed of a semiconductor containing gallium and nitrogen, and an enhancement type first connected in series to the first n-channel field-effect transistor. Provided is an inverter comprising 2 n-channel field effect transistors and an element connected in series with the diamond power element 1.

When such an element is used, the AlGaN / GaN-based n-FET may be formed on the substrate 11 on which the diamond FET 10 is formed.

[Example 1]
The first embodiment of the present invention will be described with reference to FIG. In the drawing, the symbol D represents a drain, the symbol S represents a source, and the symbol G represents a gate.

The complementary inverter 200 of the first embodiment has a cascode p-FET 210 in which a depletion type diamond FET 211 and an enhancement type Si p-FET 212 are cascode connected, and a depletion type AlGaN / GaN system n-FET 221 and an enhancement type Si. It is composed of a circuit in which the drain of the cascode p-FET 210 and the drain of the cascode n-FET 220 are interconnected so that the cascode n-FET 220 having the n-FET 222 connected to the cascode constitutes a complementary inverter.

In the cascode p-FET 210, the drain of the Si p-FET 212 is connected to the source of the diamond FET 211, and the source of the Si p-FET 212 is connected to the gate of the diamond FET 211. The source of the Si p-FET 212 (corresponding to the source terminal of the cascode p-FET 210) is connected to the DC power supply 260a. The drain of the diamond FET 211 (corresponding to the drain terminal of the cascode p-FET 210) is connected to the drain of the AlGaN / GaN system n-FET 221 (corresponding to the drain terminal of the cascode n-FET 220).

On the other hand, in the cascode n-FET 220, the drain of the Si-made n-FET 222 is connected to the source of the AlGaN / GaN-based n-FET 221 and the source of the Si-made n-FET 222 is connected to the gate of the AlGaN / GaN-based n-FET 221. Has been done. The source of the Si p-FET 222 (corresponding to the source terminal of the cascode n-FET 220) is connected to the DC power supply 260b. The drain of the AlGaN / GaN system n-FET221 (corresponding to the drain terminal of the cascode n-FET 220) is connected to the drain electrode of the diamond FET 211 (corresponding to the drain terminal of the cascode p-FET 210).

The signal line extending from the signal source 250 is branched into two, and the gate of the Si p-FET 212 (corresponding to the gate terminal of the cascode p-FET 210) and the gate of the Si p-FET 222 (cascode p), respectively. -It is connected to (corresponding to the gate terminal of FET 220).

In this embodiment, the complementary inverter 200 configured as described above is used to apply a voltage + 10V from the DC power supply 260a to the source terminal of the cascode p-FET 210, and from the DC power supply 260b to the source terminal of the cascode n-FET 220. A voltage of -10V is applied, and a rectangular pulse with an input voltage level of 0V, an amplitude of 10V, a period of 1000Hz, and a duty ratio of 50% is input from the signal source 250 to the gate terminals of the cascode p-FET 210 and the cascode n-FET 220, and the cascode p- A rectangular pulse having an amplitude of 10 V whose waveform was inverted was obtained as an output from the midpoint connecting the drain terminal of the FET 210 and the drain terminal of the cascode n-FET 220.

[Example 2]
The second embodiment of the present invention will be described with reference to FIG. In the same drawing, the symbol D represents a drain, the symbol S represents a source, and the symbol G represents a gate.

The complementary inverter 300 of the second embodiment is composed of a first-stage circuit 330 that functions as a level shifter for an input voltage, and a second-stage circuit 340 that functions as a complementary inverter.

First, the circuit 340 in the second stage will be described. The circuit 340 in the second stage consists of a cascode p-FET 310 in which a depletion type diamond FET 311 and an enhancement type Si p-FET 312 are cascoded, and a depletion type AlGaN / GaN system n-FET 321 and an enhancement type Si p-FET 312. -The drain of the cascode p-FET 310 and the drain of the cascode n-FET 320 are connected to each other so that the cascode n-FET 320 having the cascode connected to the FET 322 constitutes a complementary inverter.

In the cascode p-FET 310, the drain of the Si p-FET 312 is connected to the source of the diamond FET 311 and the source of the Si p-FET 312 is connected to the gate of the diamond FET 311. The source of the Si p-FET 312 (corresponding to the source terminal of the cascode p-FET 310) is connected to the DC power supply 360a. The drain of the diamond FET 311 (corresponding to the drain terminal of the cascode p-FET 310) is connected to the drain of the AlGaN / GaN system n-FET 321 (corresponding to the drain terminal of the cascode n-FET 320).

On the other hand, in the cascode n-FET 320, the drain of the Si-made n-FET 322 is connected to the source of the AlGaN / GaN-based n-FET 321 and the source of the Si-made n-FET 322 is connected to the gate of the AlGaN / GaN-based n-FET 321. Has been done. The source of the Si p-FET 322 (corresponding to the source terminal of the cascode n-FET 320) is connected to the DC power supply 360b. The drain of the AlGaN / GaN system n-FET 321 (corresponding to the drain terminal of the cascode n-FET 320) is connected to the drain of the diamond FET 311 (corresponding to the drain terminal of the cascode p-FET 310).

Next, the circuit 330 of the first stage will be described. The circuit 330 of the first stage is the gate of the Si p-FET 312 of the second stage circuit 340 (corresponding to the gate terminal of the cascode p-FET 310) and the gate of the Si n-FET 322 (the gate of the cascode n-FET 320). This is a circuit for level-shifting the voltage level of the signal input from the signal source 350 so that the voltage level of the input signal input to (corresponding to the terminal) becomes a predetermined voltage level. A switch circuit that operates complementarily by connecting the source of the Si-made n-FET 331 and the source of the Si-made p-FET 332 is configured, and the source is grounded. Further, the signal line of the signal source 350 is branched into two and connected to the gates of the Si n-FET 331 and the Si p-FET 332, respectively.

A resistor 333 is connected to the drain of the Si n-FET 331, and a resistor 334 is connected in series to the tip of the resistor 333, and the resistor 333 and the resistor 334 form a resistance voltage divider. The end of the resistor 334 opposite to the end connected to the resistor 333 is connected to the DC power supply 360a. Further, the midpoint between the resistance 333 and the resistance 334 is connected to the gate of the Si p-FET 312, and the voltage divided by the resistance 333 and the resistance 334 and level-shifted to a predetermined voltage level is cascoded. A signal can be input to the gate terminal of the p-FET 310. In this embodiment, the resistance ratio of the resistance 333 and the resistance 334 is set to 4: 1.

On the other hand, a resistor 335 is connected to the drain of the Si p-FET 332, and a resistor 336 is connected in series to the tip of the resistor 335, and the resistor 335 and the resistor 336 form a resistance voltage divider. The end of the resistor 336 opposite to the end connected to the resistor 335 is connected to the DC power supply 360b. Further, the midpoint between the resistance 335 and the resistance 336 is connected to the gate of the Si n-FET 322, and the voltage divided by the resistance 335 and the resistance 336 and level-shifted to a predetermined voltage level is cascoded. A signal can be input to the gate terminal of the p-FET 320. In this embodiment, the resistance ratio of the resistance 335 and the resistance 336 is 4: 1.

In this embodiment, the complementary inverter 300 configured as described above is used to apply a voltage + 100V from the DC power supply 360a to the source terminal of the cascode p-FET 310, and from the DC power supply 360b to the source terminal of the cascode n-FET 320. A voltage of -100V was applied, and a rectangular pulse having an input voltage level of 0V and an amplitude of 5V was input to the gates of the Si n-FET 331 and the Si p-FET 332 of the circuit 330 in the first stage from the signal source 350.

Since the resistance ratio between the resistor 333 and the resistor 334 is set to 4: 1, when the Si-made n-FET 331 of the circuit 330 in the first stage is turned on, a current flows through the resistor 333 and the resistor 334, and the current flows from the signal source 350. Since the input input signal is level-shifted to a voltage level 20V lower than the power supply voltage + 100V of the DC power supply 360a by the resistance voltage division, the voltage between the gate and the source of the cascode p-FET 310 opens by 20V, and the cascode p-FET 310 opens. Turn on. On the contrary, when the Si-made n-FET 331 of the circuit 330 in the first stage is turned off, no current flows through the resistance 333 and the resistance 334, so that the gate of the cascode p-FET 310 is pulled up to the power supply voltage + 100V of the DC power supply 360a. , The voltage between the gate and the source of the cascode p-FET 310 becomes 0V, and the cascode p-FET 310 turns off.

On the other hand, since the resistance ratio of the resistor 335 and the resistor 336 is set to 4: 1, when the Si p-FET 332 of the circuit 330 in the first stage is turned on, a current flows through the resistor 335 and the resistor 336, and the signal source The input signal input from 350 is level-shifted to a voltage level 20V higher than the power supply voltage -100V of the DC power supply 360b by the resistance voltage division, the voltage between the gate and the source of the cascode n-FET 320 opens by 20V, and the cascode n-FET 320. Turns on. On the contrary, when the Si p-FET 332 of the first stage circuit 330 is turned off, no current flows through the resistance 335 and the resistance 336, so that the gate electrode of the cascode n-FET 320 is pulled down to the power supply voltage -100V of the DC power supply 360b. Then, the voltage between the gate and the source of the cascode n-FET 320 becomes 0V, and the cascode n-FET 320 is turned off.

Since the Si-made n-FET 331 and the Si-made p-FET 332 in the first-stage circuit 330 operate complementarily, the cascode p-FET 310 and the cascode n-FET 320 in the second-stage circuit 340 also operate complementarily. ..

FIG. 13A shows two output signals of the circuit 330 in the first stage when a rectangular pulse (INPUT1) having an input voltage level of 0 V, an amplitude of 5 V, a period of 1000 Hz, and a duty ratio of 50% is input from the signal source 350. That is, the gate input signal (INPUT2 ch1) of the cascode p-FET 310 and the gate input signal (INPUT2 ch2) of the cascode n-FET 320 are shown. As shown, the level is shifted to a predetermined voltage level. The lower part of FIG. 13B shows the input signal to the circuit 330 of the first stage, and the upper part of FIG. 13B shows the output waveform of the circuit 340 of the second stage. As shown, a rectangular pulse with a voltage level of 0 V and an amplitude of 100 V is output.

The withstand voltage of the complementary inverter 300 given as an example in the second embodiment is limited by the withstand voltage of the circuit 330 in the first stage. In the circuit 330 of the first stage, the Si-made n-FET 331 is a cascode n-FET in which an AlGaN / GaN-based n-FET and a Si-made n-FET are cascode-connected, and the Si-made p-FET 332 is made of a diamond FET and Si. The p-FET may be replaced with a cascoded p-FET connected by cascode. By doing so, the overall withstand voltage of the complementary inverter 300 can be significantly improved.

Further, the circuit 330 in the first stage is not limited to the circuit configuration of this embodiment as long as it is a circuit capable of level-shifting the input voltage level to a predetermined voltage level, and may be another circuit. It is particularly preferable that the circuit can output two signals having different voltage levels but being synchronized so that the cascode p-FET 310 and the cascode n-FET 320 constituting the circuit 340 of the stage are synchronized.

10 Diamond FET
11 Substrate 11a Diamond substrate 11b Diamond layer 12 Drain electrode 13 Source electrode 14 Gate electrode 15 Hydrogenated layer 16 Gate insulating film

Claims (7)

A diamond field effect transistor and an enhancement type p-channel field effect transistor connected in series with the diamond field effect transistor are provided.
The diamond field effect transistor
The drain electrode provided on the diamond substrate and
A source electrode provided on the diamond substrate away from the drain electrode and
A hydrogenated layer provided on the surface of the diamond substrate between the drain electrode and the source electrode and having a carbon-hydrogen bond,
The gate insulating film covering the hydrogenated layer and
Including a gate electrode provided on the gate insulating film
The gate electrode of the diamond field effect transistor is connected to the source of the p-channel field effect transistor.
Diamond power device. The diamond power device according to claim 1 , wherein the p-channel field effect transistor is made of silicon. The diamond power device according to claim 1 or 2 ,
An inverter including an n-channel field effect transistor connected in series with the diamond power element. The inverter according to claim 3 , wherein the n-channel field effect transistor is made of silicon. The inverter according to claim 3 , wherein the n-channel field effect transistor is composed of a III-V compound semiconductor. The inverter according to claim 5 , wherein the III-V compound semiconductor is a semiconductor containing gallium and nitrogen. The inverter according to claim 6 , wherein the n-channel field effect transistor composed of a semiconductor containing gallium and nitrogen is provided on the diamond substrate.

Images