JP7017035B2 - Manufacturing method of semiconductor device - Google Patents

Description

The techniques disclosed herein relate to methods of manufacturing semiconductor devices.

As disclosed in Patent Documents 1 and 2, semiconductor devices often include a patterned metal layer on an interlayer insulating film. As such a metal layer, for example, a field plate formed in a terminal region is known.

Japanese Unexamined Patent Publication No. 2013-33820 Japanese Unexamined Patent Publication No. 2013-172087

In order to reduce the chip size, it is desirable to reduce the distance between adjacent metal layers. In order to reduce the distance between adjacent metal layers, it is conceivable to process the side surfaces of the metal layers into a vertical shape. However, when the side surface of the metal layer is processed into a vertical shape, a steep surface reflecting the vertical shape of the side surface of the metal layer appears on the surface of the polyimide layer covering the metal layer. When such a steep surface appears, when the resist liquid is to be applied onto the polyimide layer in the subsequent manufacturing process, the resist liquid cannot exceed the steep surface, and poor application of the resist liquid occurs. It ends up. There is a need for a technique for avoiding such poor application of the resist liquid.

The method for manufacturing a semiconductor device disclosed in the present specification includes a metal layer forming step of forming a metal layer on an interlayer insulating film having a surface portion including a top surface and a side surface continuous from the top surface, and a polyimide for coating the metal layer. A polyimide layer forming step for forming a layer and a resist liquid applying step for applying a resist liquid on the polyimide layer can be provided. In the metal layer forming step, the metal layer is formed so as to cover the surface portion of the interlayer insulating film. Further, the surface of the metal layer facing the side surface of the surface portion of the interlayer insulating film is inclined. According to this manufacturing method, the metal layer covering the surface portion of the interlayer insulating film has a substantially inclined shape from the position above the top surface of the surface portion to the side position of the side surface of the surface portion. Therefore, the surface appearing on the polyimide layer covering the metal layer is a gentle surface reflecting the generally inclined shape of the metal layer. As a result, in the resist liquid application step, the resist liquid can spread beyond the gentle surface thereof, so that poor application of the resist liquid can be avoided.

The cross-sectional view of the main part in the manufacturing process of the semiconductor device of this embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the semiconductor device of this embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the semiconductor device of this embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the semiconductor device of this embodiment is schematically shown. The cross-sectional view of the main part in the manufacturing process of the semiconductor device of the comparative example is schematically shown. The cross-sectional view of the main part in the manufacturing process of the semiconductor device of the comparative example is schematically shown. The cross-sectional view of the main part in the manufacturing process of the semiconductor device of the comparative example is schematically shown. The cross-sectional view of the main part in the manufacturing process of the semiconductor device of the comparative example is schematically shown.

The cross-sectional view of the main part of FIGS. 1A-1D is an enlarged cross-sectional view of the vicinity of the surface of the terminal region of the semiconductor device 1. Here, the termination region is a region that goes around the active region in which the element structure exhibiting a specific function is formed, and is a region in which the termination withstand voltage structure for improving the withstand voltage of the semiconductor device 1 is formed. Is. Examples of the element structure include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), diodes and the like. As the terminal withstand voltage structure, an FLR (Field Limiting Ring) structure is exemplified. In this example as well, the FLR structure is formed in the semiconductor substrate 12, but the illustration is omitted. Hereinafter, a step of forming the metal layer 18 in the terminal region of the semiconductor device 1 will be described with reference to FIGS. 1A-1D.

First, as shown in FIG. 1A, a semiconductor substrate 12 whose surface is coated with the interlayer insulating film 14 is prepared. A polysilicon layer 16 is embedded in the interlayer insulating film 14. The interlayer insulating film 14 and the polysilicon layer 16 are formed on the surface of the semiconductor substrate 12 by utilizing the vapor deposition technique and the etching technique. The interlayer insulating film 14 has a surface portion 14a including a top surface 14t and a side surface 14s continuous from the top surface 14t. The surface portion 14a of the interlayer insulating film 14 is the remnant of the surface of the interlayer insulating film 14 when a part of the surface of the interlayer insulating film 14 is removed to expose the polysilicon layer 16. The top surface 14t is a surface parallel to the surface of the semiconductor substrate 12, and the side surface 14s is a surface perpendicular to the surface of the semiconductor substrate 12. The polysilicon layer 16 is arranged corresponding to each of a plurality of p-type regions constituting the FLR structure (not shown), and is configured to have the same potential as the p-type regions.

Next, the metal layer 18 of aluminum is formed so as to cover the entire surface of the interlayer insulating film 14 by utilizing the sputtering technique. The metal layer 18 covers the surface portion 14a of the interlayer insulating film 14 and comes into contact with the polysilicon layer 16 exposed around the surface portion 14a. The surface of the metal layer 18 has a curved surface portion 18a and a flat portion 18b that reflect the shape of the surface portion 14a of the interlayer insulating film 14. The curved surface portion 18a is formed at a position corresponding to the end portion of the surface portion 14a of the interlayer insulating film 14, and is a portion extending upward from the flat portion 18b. Next, the resist layer 22 is patterned on a part of the surface of the metal layer 18 by using a photolithography technique. The resist layer 22 is patterned so as to cover the curved surface portion 18a of the metal layer 18 in addition to the metal layer 18 existing above the surface portion 14a of the interlayer insulating film 14. More specifically, the resist is such that the end portion of the resist layer 22 (that is, the side surface 22s of the resist layer 22) is located within the range of the flat portion 18b around the curved surface portion 18a of the metal layer 18 when viewed in a plan view. The layer 22 is patterned.

Next, as shown in FIG. 1B, the metal layer 18 not covered with the resist layer 22 is removed by using a dry etching technique. As a result, the metal layer 18 is patterned so as to cover the surface portion 14a of the interlayer insulating film 14. The dry etching at this time is a condition in which the etched surface of the metal layer 18 (the surface facing the side surface 14a of the surface portion 14a of the interlayer insulating film 14) is inclined in a direction away from the side surface 14a of the surface portion 14a of the interlayer insulating film 14. It will be carried out at. As described above, the side surface 18s of the patterned metal layer 18 is composed of a curved surface portion 18a, a flat portion 18b, and an inclined portion 18c, and can have a substantially inclined shape. In other words, the side surface 18s of the metal layer 18 is formed in a stepped shape having a flat portion 18b between the curved surface portion 18a and the inclined portion 18c, whereby the top surface 14t of the surface portion 14a of the interlayer insulating film 14 is formed. The shape is substantially inclined from the upper position to the lateral position of the side surface 14s of the surface portion 14a. The metal layer 18 patterned in this way is arranged corresponding to each of the plurality of p-shaped regions constituting the FLR structure (not shown). The metal layer 18 and the polysilicon layer 16 function as field plates and can suppress the influence of mobile ions on the FLR structure.

Next, as shown in FIG. 1C, the polyimide layer 24 that covers the metal layer 18 is formed. Since the side surface 18s of the metal layer 18 is substantially inclined, the inclined surface 24s appearing on the polyimide layer 24 is gentle, reflecting the side surface 18a of the metal layer 18.

Next, as shown in FIG. 1D, the resist liquid 26 is applied onto the surface of the polyimide layer 24. This resist liquid 26 is created as a mask for removing the polyimide layer 24 in the range corresponding to the active region, and must be applied to the entire surface of the polyimide layer 24 in the range corresponding to the terminal region. As described above, in the semiconductor device 1, since the inclined surface 24s of the polyimide layer 24 in the terminal region is gently formed, the resist liquid 26 can spread beyond the inclined surface 24s. Therefore, in the semiconductor device 1, the resist liquid 26 is satisfactorily applied to the entire surface of the polyimide layer 24 in the terminal region.

Here, a step of forming the metal layer 118 in the terminal region of the semiconductor device 10 of the comparative example will be described with reference to FIGS. 2A-2D. Regarding the components common to the semiconductor device 1 of FIGS. 1A-1D, the last two digits of the reference numerals are matched, and the description of the components will be omitted.

As shown in FIG. 2A, in the semiconductor device 10, the end portion of the resist layer 122 (that is, the side surface 122s of the resist layer 122) is located within the range of the surface portion 114a of the interlayer insulating film 114 when viewed in a plan view. The resist layer 122 is patterned.

Next, as shown in FIG. 2B, a dry etching technique is used to remove the metal layer 118 that is not coated with the resist layer 122. The dry etching at this time is performed under the condition that the etched surface of the metal layer 118 is vertical. As a result, the area of the metal layer 118 can be reduced, and thus the chip area can be reduced.

Next, as shown in FIG. 2C, the polyimide layer 124 covering the metal layer 118 is formed. Since the side surface 118s of the metal layer 118 has a vertical shape, the inclined surface 124s appearing on the polyimide layer 124 is steep, reflecting the side surface 118s of the metal layer 118.

Next, as shown in FIG. 2D, the resist liquid 126 is applied onto the surface of the polyimide layer 124. As described above, in the semiconductor device 10, since the inclined surface 124s of the polyimide layer 124 in the terminal region is formed steeply, the resist liquid 126 cannot exceed the inclined surface 124s, and the surface of the polyimide layer 124 cannot be exceeded. A coating defect occurs in which a part of the resist liquid 126 is not applied. If the side surface 118s of the metal layer 118 is processed into a vertical shape in this way, poor application of the resist liquid 126 occurs.

On the other hand, in the semiconductor device 1 shown in FIGS. 1A-1D, since the side surface 18s of the metal layer 18 is formed so as to be substantially inclined, the inclined surface 24s of the polyimide layer 24 becomes gentle, and the resist liquid 26 has the inclined surface 24s. Can spread beyond. Therefore, in the semiconductor device 1, the resist liquid 26 is satisfactorily coated on the surface of the polyimide layer 24 in the terminal region, and coating defects are avoided.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples exemplified above. Further, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in the present specification or the drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

1: Semiconductor device 12: Semiconductor substrate 14: Interlayer insulating film 14a: Surface portion 16: Polysilicon layer 18: Metal layer 22: Resist layer 24: Polyimide layer 26: Resist liquid

Claims (1)

A method for manufacturing a semiconductor device including a semiconductor substrate having an active region in which an element structure is formed and a terminal region in which an FLR structure is formed while circulating around the active region .
A metal layer forming step of forming a metal layer on an interlayer insulating film having a top surface and a surface portion including a side surface continuous from the top surface in the terminal region of the semiconductor substrate , wherein the metal layer is the interlayer insulation. A metal layer forming step formed so as to cover the surface portion of the film, and
The polyimide layer forming step of forming the polyimide layer covering the metal layer, and
A resist liquid application step of applying a resist liquid on the polyimide layer is provided.
The surface of the metal layer facing the side surface of the surface portion of the interlayer insulating film is inclined .
The FLR structure is a plurality of p-type regions formed in the semiconductor substrate, and is a plurality of p-type regions.
A method for manufacturing a semiconductor device, wherein the metal layer is arranged corresponding to each of the plurality of p-shaped regions constituting the FLR structure .

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