JP7022093B2 - ESD protection circuit - Google Patents

Description

The present invention relates to an ESD protection circuit that protects the internal circuit of an IC (semiconductor integrated circuit) from being destroyed by an overcurrent (ESD current) and an overvoltage (ESD voltage) when an ESD (electrostatic discharge) event occurs.

The ESD protection circuit is responsible for protecting the IC from electrostatic discharge. Therefore, the ESD protection circuit is an important technology indispensable for the process of mounting an IC on a product board, and is installed in almost all IC products.

Testing of ESD protection circuits includes component-level ESD testing and system-level ESD testing.

The component level ESD test is an ESD test performed on a single component such as an IC, such as HBM (human body model) and CDM (charged device model).
In the component level ESD test, the component ESD test is performed when no power is applied (non-energized state). In other words, the component level ESD test assumes that a pulse of ESD current (ESD pulse) is applied to a component that is not normally operating.
Further, for example, in the HBM test, when an ESD pulse is applied using the power supply terminal of the component as a reference (hereinafter, also referred to as a power supply reference) as an external connection terminal for releasing the ESD current, and the ground terminal of the component as a reference (hereinafter, also referred to as a power supply reference). , Also referred to as ground reference), there are two cases where an ESD pulse is applied.

The system level ESD test is an ESD test performed in a system in which components such as ICs are built on the board.
System-level ESD tests include the Powered ESD test, which is performed when power is applied (energized state), and the Unpowered ESD test, which is performed when power is not applied (non-energized state). That is, system-level ESD testing assumes that ESD pulses are applied to both powered and operating systems and unpowered systems.
Also, in system-level ESD tests, the reference when an ESD pulse is applied is always the system ground terminal. That is, the ESD pulse is applied with reference to the ground.

FIG. 13 is a conceptual diagram of an example showing the configuration of the system used in the system level ESD test. In the system 90 shown in FIG. 13, two ICs 92 and 94 are connected to each other via differential signal line pairs 96 and 98. Each of the two noise filters 100, 102 is inserted into each of the differential signal line pairs 96, 98, and each of the two external ESD protection elements 104, 106 is grounded with each of the differential signal line pairs 96, 98. Is connected to. Further, inside each of the two ICs 92 and 94, each of the ESD protection circuits 108 and 110 is connected between each of the differential signal line pairs 96 and 98 and the ground (IC92 is not shown). ..

In the system level ESD test, an ESD pulse is applied to each of the application points 112 and 114 on each of the differential signal line pairs 96 and 98 using an ESD generator such as an ESD gun (ESDGUN).
In the Powered ESD test, an ESD pulse is applied to each of the application points 112 and 114 using an ESD gun during signal communication between the ICs 92 and 94 with the power applied. Communication may not be possible during the application of the ESD pulse, but it is required that communication can be performed by returning after the application is completed.
In the unpowered ESD test, an ESD pulse is similarly applied to each of the application points 112 and 114 using an ESD gun with no power applied. After that, when a power source is applied, it is required that communication can be performed normally.

FIG. 14 is an example graph showing an ESD pulse applied in the case of an ESD test. In the graph of FIG. 14, the vertical axis represents the current value I, and the horizontal axis represents the time t.
In a system level ESD test, for example, when the applied voltage is 8 kV, the first peak Ipeak of the current value of the ESD pulse applied using the ESD gun is about 30 A, as shown in the graph of FIG. 14 and Table 1. Subsequently, the ESD pulse drops once and then rises again, and the second peak I (30 ns) of the current value of the ESD pulse after 30 ns is about 16 A. Subsequently, the ESD pulse gradually decreases from there, and the current value I (60 ns) of the ESD pulse after 60 ns becomes about 8 A.
In the HBM test, for example, when the applied voltage is 2 kV, the peak Ipeak of the current value of the ESD pulse is 1.20-1.47 A, and the ESD pulse is there, as also shown in the graph of FIG. 14 and Table 1. It gradually decreases from. Further, when the applied voltage is 8 kV, the peak of the current value of the ESD pulse is 4.80-5.87 A, and the ESD pulse also gradually decreases from there.

Thus, in the system level ESD test, the current value of the ESD pulse applied using the ESD gun is much larger than the current value of the ESD pulse applied in the component level ESD test, and the external ESD protection element Even if there is, a considerable amount of residual current rushes into the IC. Therefore, in order to prevent the IC from being destroyed, an ESD protection circuit that can be clamped at a voltage sufficiently low for the ESD pulse applied using the ESD gun is required.

The ESD protection circuit is specified as one of various test items even in electronic devices in the in-vehicle field, for example, and its importance is increasing. In the normal technical field, passing the component level ESD test is sufficient for ESD resistance as an IC. However, in special technical fields such as in-vehicle fields, it is necessary to support both system-level ESD tests and noise immunity tests in addition to component-level ESD tests.

The noise immunity test is a test in which noise is applied during signal communication to evaluate the resistance of the ESD protection circuit to noise.
In the noise immunity test, for example, in the system 90 of FIG. 13, noise is applied to the differential signal line pairs 96 and 98 during signal communication between the ICs 92 and 94 with the power applied. During the noise immunity test, it is required that the ESD protection circuits 108 and 110 do not perform the protection operation and can communicate normally.

Here, as the prior art documents related to the present invention, there are Patent Documents 1 to 7 and the like.

Japanese Unexamined Patent Publication No. 2006-196808 Japanese Unexamined Patent Publication No. 2010-232606 Japanese Unexamined Patent Publication No. 2010-233140 Japanese Unexamined Patent Publication No. 2012-133924 JP-A-2015-12225 Japanese Unexamined Patent Publication No. 2017-130917 Japanese Unexamined Patent Publication No. 2018-128349

FIG. 15 is an example graph showing the IV (current-voltage) characteristics of the ESD protection circuit. In the graph of FIG. 15, the vertical axis represents the current value I, and the horizontal axis represents the voltage value V.
As shown in the graph of FIG. 15, the ESD protection circuit turns on when the ESD voltage reaches the turn-on voltage at the time of the occurrence of the ESD event, and releases the ESD current. In the system level ESD test, even if an ESD current of a much larger level than in the component level ESD test is applied, the system is required to return to normal after the application of the ESD pulse.

FIG. 16 is an example graph showing a signal waveform to which noise is applied. In the graph of FIG. 16, the vertical axis represents the voltage value V, and the horizontal axis represents the time t.
As shown in the graph of FIG. 16, in the noise immunity test, noise is applied to the signal waveform. Even in this case, the system is required to continue to operate normally.

In this way, the ESD protection circuit must perform a protective operation when an ESD event occurs, but do not perform a protective operation during a noise immunity test so as not to interfere with the normal operation of the IC.

FIG. 17 is a conceptual diagram showing a graph of a signal waveform to which noise is applied as shown in FIG. 16 superimposed on a graph of IV characteristics of the ESD protection circuit shown in FIG.
As shown in FIG. 17, the turn-on voltage of the ESD protection circuit needs to be set to a voltage higher than the maximum potential of the signal waveform to which noise is applied so as not to react to noise.
However, if the turn-on voltage of the ESD protection circuit is set too high with a margin, the risk of reacting to noise decreases, but the clamp voltage increases, so that the ability of the ESD protection circuit decreases.
In this way, resistance to noise and resistance to ESD pulses are contradictory requirements, so it is necessary to set an appropriate turn-on voltage.

FIG. 18 is an example circuit diagram showing the configuration of a conventional ESD protection circuit. The ESD protection circuit 120 shown in FIG. 18 is an active clamp type and includes a voltage detection circuit 130, an inverter 132, a clamp circuit 134, and a protection diode 136.
The voltage detection circuit 130 has a resistance element 144 and a capacitive element 146, the inverter 132 has a MOSFET (P-type MOS transistor) 148 and an OSPF (N-type MOS transistor) 150, and the clamp circuit 134 has a normal OSPF. The protection diode 136 has diodes 154 and 156, with a very large size MOSFETs 152 as compared to.

In the ESD protection circuit 120, when the power supply voltage VDD is supplied to the power supply node during normal operation, the capacitive element 146 is charged to the power supply voltage VDD. Therefore, the detection signal output from between the resistance element 144 and the capacitance element 146 of the voltage detection circuit 130 is at a high level, and the MIMO 148 and the MIMO 150 are in the off state and the on state, respectively, and the detection signal output from the inverter 132. The inverting signal of is low level, and the NMOS 152 of the clamp circuit 134 is in the off state.
Therefore, the ESD protection circuit 120 does not affect the operation of the internal circuit that operates at the power supply voltage VDD during normal operation.

On the other hand, when an ESD pulse is applied to the signal input terminal Sig when an ESD event occurs, the ESD current flows to the power supply node via the diode 154, and the voltage of the power supply node rises sharply, but the detection signal is a voltage. By the action of the low-pass filter of the detection circuit 130, the voltage rises more slowly than the power supply node. Therefore, the detection signal is obtained until the capacitance element 146 is charged to the ESD voltage via the resistance element 144, that is, when the resistance value R of the resistance element 144 of the voltage detection circuit 130 and the capacitance value C of the capacitance element 146 are used. The time corresponding to the constant RC, the low level, the inverted signal of the detection signal becomes the high level, and the MIMO 152 turns on.
Therefore, when an ESD event occurs, as shown by the broken line in FIG. 18, the ESD current applied to the signal input terminal Sig flows to the ground node via the diode 154, the power supply node, and the MIMO 152, and the voltage of the power supply node is clamped. By doing so, the internal circuit can be protected.

However, in the case of the conventional ESD protection circuit 120 shown in FIG. 18, the applied noise during the protection operation passes through the power supply node as it is and affects its potential. Therefore, there is a drawback that it affects the operation of the entire internal circuit that operates at the power supply voltage VDD.
For example, if a circuit having a holding circuit such as a flip-flop is included, the data of the holding circuit such as a flip-flop is destroyed when an ESD pulse is applied in the Powered ESD test, and the data is restored after the application is completed. Cannot perform normal communication.

Other conventional ESD protection circuits, such as thyristors, are generally used, but since thyristors are made of parasitic bipolar transistors, it is necessary to change the manufacturing process to adjust the turn-on voltage. Has the drawback of being difficult.

Therefore, the requirements required for the ESD protection circuit used in electronic devices in the in-vehicle field and the like are as follows (1) to (3).
(1) In the component level ESD test, the discharge path can be secured based on the power supply reference and the ground reference.
(2) In the system level ESD test, it is possible to secure a discharge path that does not pass through the power supply node.
(3) In the noise immunity test, the protection operation is not performed in response to noise.
Further, the ESD protection circuit can be manufactured by using a normal manufacturing process, and it is desirable that the ESD protection circuit is a small and compact circuit in order to avoid an increase in cost.

Therefore, it is an object of the present invention to provide an ESD protection circuit capable of supporting system level ESD test and noise immunity test in addition to component level ESD test.

In order to achieve the above object, the present invention is an ESD protection circuit that protects the internal circuit of the IC from being destroyed by the ESD current and the ESD voltage when an ESD event occurs.
The first protection circuit is provided, and the first protection circuit is
A bias circuit that generates a bias voltage, which is an intermediate voltage between the power supply voltage and the ground voltage, and outputs it to the first internal node.
A first voltage detection circuit that detects whether the voltage of the first internal node is the bias voltage or the ESD voltage and outputs the first detection signal to the second internal node.
It operates in the voltage range between the voltage of the first internal node and the ground voltage, inverts the first detection signal, and outputs the inverted signal of the first detection signal to the third internal node. With the first inverter
When it is detected that the voltage of the first internal node is the ESD voltage in response to the inverting signal of the first detection signal, the ESD current is passed from the first internal node to the ground node. The first clamping circuit that clamps the voltage of the first internal node,
When the ESD event occurs, the positive-polarity ESD current applied to each of the external connection terminals of the differential signal pair is passed from each of the external connection terminals of the differential signal pair to the first internal node. 1 protection diode and
When the ESD event occurs, a negative polarity ESD current applied to each of the external connection terminals of the differential signal pair flows from the ground terminal to each of the differential signal nodes corresponding to the differential signal pair in the reverse direction. Provides an ESD protection circuit, including a diode.

Here, the bias circuit includes two resistance elements connected in series between two differential signal nodes corresponding to the differential signal pair, and the first resistance element is provided between the two resistance elements. The bias voltage is output to the internal node,
The first voltage detection circuit includes a first resistance element and a first capacitive element connected in series between the first internal node and the ground node, and includes the first resistance element and the ground node. The first detection signal is output from between the first capacitive element and the second internal node.
The first inverter includes a first P-type MOS transistor and a first N-type MOS transistor connected in series between the first internal node and the ground node, and the first P-type is provided. The first detection signal is input to the gate of the MOS transistor and the first N-type MOS transistor, and the third inside is formed between the first P-type MOS transistor and the first N-type MOS transistor. The inverted signal of the first detection signal is output to the node, and the inverted signal is output.
The first clamp circuit comprises a third N-type MOS transistor connected between the first internal node and the ground node, and the first is at the gate of the third N-type MOS transistor. The inverted signal of the detection signal is input,
The first protection diode is the first diode connected in the forward direction from the differential signal node corresponding to one of the differential signal pairs toward the first internal node, and the differential signal pair. A second diode connected in the forward direction from the corresponding differential signal node to the first internal node.
The reverse diode is a third diode connected in the forward direction from the ground node toward the differential signal node corresponding to one of the differential signal pairs, and the other of the differential signal pairs from the ground node. It is preferred to include a fourth diode connected in the forward direction towards the corresponding differential signal node.

Further, it is preferable that the first capacitive element has a MOS gate capacitance.

Further, a second protection circuit is provided, and the second protection circuit is provided.
A second voltage detection circuit that detects whether the voltage of the power supply node is the power supply voltage or the ESD voltage and outputs a second detection signal to the fourth internal node.
With a second inverter that operates in a voltage range between the power supply voltage and the ground voltage, inverts the second detection signal, and outputs the inverted signal of the second detection signal to the fifth internal node. ,
When it is detected that the voltage of the power supply node is the ESD voltage in response to the inverting signal of the second detection signal, the ESD current is passed from the power supply node to the ground node of the power supply node. A second clamp circuit that clamps the voltage,
It is preferable to include a second protection diode that allows an ESD current having a negative polarity applied to the power supply terminal to flow from the ground terminal to the power supply node when the ESD event occurs.

Further, the second voltage detection circuit includes a second resistance element and a second capacitance element connected in series between the power supply node and the ground node, and the second resistance element and the second. The second detection signal is output from between the two capacitive elements to the fourth internal node.
The second inverter includes a second P-type MOS transistor and a second N-type MOS transistor connected in series between the power supply node and the ground node, and the second P-type MOS transistor and the second P-type MOS transistor. The second detection signal is input to the gate of the second N-type MOS transistor, and the second detection signal is input from between the second P-type MOS transistor and the second N-type MOS transistor to the fifth internal node. The inverted signal of the second detection signal is output,
The second clamp circuit includes a fourth N-type MOS transistor connected between the power supply node and the ground node, and the second detection signal is transmitted to the gate of the fourth N-type MOS transistor. An inverting signal is input and
The second protection diode preferably includes a fifth diode connected in the forward direction from the ground node to the power supply node.

Further, it is preferable that the second capacitive element has a MOS gate capacitance.

Further, it is preferable that the bias circuit outputs the common mode voltage of the differential signal pair to the first internal node as the bias voltage.

Further, it is preferable that the bias circuit outputs the bias voltage to the second internal node instead of the first internal node.

Further, the maximum potential of one of the differential signal pairs is equal to or lower than the power supply voltage, the minimum potential of the other of the differential signal pairs is equal to or higher than the ground voltage, and the operating voltage range of the differential signal pair is the power supply voltage. It is preferably in the voltage range between and the ground voltage.

Since the ESD protection circuit of the present invention can support system-level ESD tests and noise immunity tests in addition to component-level ESD tests, it can also be applied to electronic devices used in special fields such as in-vehicle fields. be. Further, the present invention can be manufactured by using a normal manufacturing process, and since it is a small-scale and compact circuit, it is possible to suppress an increase in cost.

It is a circuit diagram of one Embodiment which shows the structure of the ESD protection circuit of this invention. It is a conceptual diagram of one Embodiment which shows the waveform of the differential signal to which noise is applied. It is a conceptual diagram of one Embodiment which shows the state of the ESD protection circuit of this invention at the time of a noise immunity test. FIG. 3 is a conceptual diagram of an embodiment showing the state of the ESD protection circuit of the present invention when a positive polarity ESD pulse is applied in a Powered ESD test. FIG. 3 is a conceptual diagram of an embodiment showing the state of the ESD protection circuit of the present invention when an ESD pulse having a negative polarity is applied in a Powered ESD test. FIG. 3 is a conceptual diagram of an embodiment showing the state of the ESD protection circuit of the present invention when a positive polarity ESD pulse is applied in an unpowered ESD test. It is a conceptual diagram of one Embodiment which shows the state of the ESD protection circuit of this invention when the ESD pulse of a negative polarity is applied in the unpowered ESD test. It is a conceptual diagram of one Embodiment which shows the state of the ESD protection circuit of this invention when the ESD pulse of positive polarity is applied in the HBM test. FIG. 5 is a conceptual diagram of an embodiment showing the state of the ESD protection circuit of the present invention when an ESD pulse having a negative polarity is applied with reference to a power source in an HBM test. It is a conceptual diagram of one Embodiment which shows the state of the ESD protection circuit of this invention when the ESD pulse of positive polarity is applied by the ground reference in the HBM test. It is a conceptual diagram of one Embodiment which shows the state of the ESD protection circuit of this invention when the ESD pulse of the negative polarity is applied by the ground reference in the HBM test. It is a circuit diagram of one Embodiment which shows a part of the ESD protection circuit of this invention which the connection destination of a bias voltage was changed. It is a conceptual diagram of an example showing the configuration of the system used in the system level ESD test. It is an example graph which shows the ESD pulse applied in the case of an ESD test. It is an example graph which shows the IV (current-voltage) characteristic of an ESD protection circuit. It is an example graph which shows the signal waveform to which noise was applied. FIG. 5 is a conceptual diagram showing a graph of a signal waveform to which noise is applied shown in FIG. 16 superimposed on a graph of IV characteristics of the ESD protection circuit shown in FIG. It is an example circuit diagram which shows the structure of the conventional ESD protection circuit.

Hereinafter, the ESD protection circuit of the present invention will be described in detail based on the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a circuit diagram of an embodiment showing the configuration of the ESD protection circuit of the present invention. The ESD protection circuit 10 shown in FIG. 1 protects the internal circuit of the IC from being destroyed by the overcurrent (ESD current) and the overvoltage (ESD voltage) when an ESD event occurs, and is the first protection circuit. A second protection circuit 14 and a second protection circuit 14 are provided.

Note that FIG. 1 shows a differential circuit 16 that operates in the voltage range between the power supply voltage VDD and the ground voltage VSS as an example of an internal circuit that is a protected circuit protected by the ESD protection circuit 10. There is.
The differential circuit 16 includes a transmit buffer 16A and a receive buffer 16B, and each of the positive and negative output terminals of the transmit buffer 16A is connected to a differential signal node corresponding to each of the differential signal pair SigP and SigN. Has been done. Further, the differential signal node corresponding to each of the differential signal pair SigP and SigN is connected to each of the input terminals on the plus side and the minus side of the receive buffer 16B.
The maximum potential of each of the differential signal pairs SigP and SigN is below the power supply voltage VDD, and the minimum potential is above the ground voltage VSS. Any voltage range between.

The first protection circuit 12 includes a bias circuit 18, a first voltage detection circuit 20, a first inverter 22, a first clamp circuit 24, a first protection diode 26, and a reverse diode 28. , Is equipped.

The bias circuit 18 generates a bias voltage, which is an arbitrary voltage (intermediate voltage) between the power supply voltage VDD and the ground voltage VSS, and outputs the bias voltage to the first internal node, and the two resistance elements 30 and 32. It is equipped with. The resistance elements 30 and 32 are connected in series between two differential signal nodes corresponding to the differential signal pair SigP and SigN, and biased from between the two resistance elements 30 and 32 to the first internal node n1. The voltage is output.
In the case of the present embodiment, the resistance values of the resistance elements 30 and 32 are the same, and the voltage of one differential signal SigP and the voltage of the other differential signal SigN are used as the bias voltage between the resistance elements 30 and 32. The common mode voltage Vcm of the differential signal pair SigP, SigN having a voltage of 1/2 of that is output to the first internal node n1.

The first voltage detection circuit 20 detects whether the voltage of the first internal node n1 is a bias voltage during normal operation or an overvoltage (ESD voltage) when an ESD event occurs, and detects a first detection signal. Is output to the second internal node n2, and includes a first resistance element 34 and a first capacitive element 36. The first resistance element 34 and the first capacitive element 36 are connected in series between the first internal node n1 and the ground node. A first detection signal, which is an output signal thereof, is output from between the first resistance element 34 and the first capacitance element 36 to the second internal node n2.
In the case of the present embodiment, the first capacitive element 36 is the gate capacitance of the MOS, specifically, the gate capacitance of the MIMO in which the source and the drain are connected to the ground node, but the present invention is not limited to this, and various other types. Capacitive elements may be used.

The first inverter 22 operates in a voltage range between the voltage of the first internal node n1 and the ground voltage, inverts the first detection signal, and outputs the inverted signal to the third internal node n3. It includes a first PMOS 38 and a first NMOS 40. The first PMOS 38 and the first NMOS 40 are connected in series between the first internal node n1 and the ground node, and the first detection signal is input to the gate. An inverted signal of the first detection signal, which is an output signal thereof, is output to the third internal node n3 from between the first PMOS 38 and the first NMOS 40.

The first clamp circuit 24 sets the ESD current to the first internal node n1 when it is detected that the voltage of the first internal node n1 is the ESD voltage in response to the inverting signal of the first detection signal. The voltage of the first internal node n1 is clamped by flowing the voltage from the ground node to the ground node, and has a third MIMO 42 having a size much larger than that of a normal NOTES. The third MIMO 42 is connected between the first internal node n1 and the ground node, and an inverted signal of the first detection signal is input to the gate.

The first protection diode 26 applies a positive polarity ESD current applied to each of the external connection terminals of the differential signal pair SigP and SigN to the external connection terminals of the differential signal pair SigP and SigN when an ESD event occurs. It flows from each of them to the first internal node n1, and includes a first diode 44 and a second diode 46. The first diode 44 is forward connected from the differential signal node corresponding to one differential signal SigP toward the first internal node n1, and the second diode 46 is connected to the other differential signal SigN. The corresponding differential signal node is connected in the forward direction toward the first internal node n1.

The reverse diode 28 determines the difference in the negative polarity ESD current applied to each of the external connection terminals of the differential signal pair SigP and SigN1 from the ground terminal to the differential signal pair SigP and SigN when an ESD event occurs. It flows through each of the dynamic signal nodes, and includes a third diode 48 and a fourth diode 50. The third diode 48 is connected forward from the ground node to the differential signal node corresponding to one differential signal SigP, and the fourth diode 50 corresponds to the other differential signal SigN from the ground node. It is connected in the forward direction toward the differential signal node.

The second protection circuit 14 is an active clamp type and includes a second voltage detection circuit 60, a second inverter 62, a second clamp circuit 64, and a second protection diode 66. ing.

The second voltage detection circuit 60 detects whether the voltage of the power supply node is the power supply voltage VDD during normal operation or the overvoltage (ESD voltage) when an ESD event occurs, and outputs the second detection signal to the fourth. It outputs to the internal node of the above, and includes a second resistance element 74 and a second capacitance element 76. The second resistance element 74 and the second capacitance element 76 are connected in series between the power supply node and the ground node. A second detection signal, which is an output signal thereof, is output from between the second resistance element 74 and the second capacitance element 76 to the fourth internal node n4.
In the case of the present embodiment, the second capacitive element 76 is the gate capacitance of the MOS, specifically the gate capacitance of the MIMO in which the source and drain are connected to the ground node, but other various capacitive elements are used. You may.

The second inverter 62 operates in a voltage range between the power supply voltage VDD and the ground voltage VSS, inverts the second detection signal, and outputs the inverted signal to the fifth internal node n5. It includes a second MIMOS 78 and a second MIMOS 80. The second PMOS 78 and the second NMOS 80 are connected in series between the power supply node and the ground node, and the second detection signal is input to the gate. An inverted signal of the second detection signal, which is an output signal thereof, is output to the fifth internal node n5 from between the second PMOS 78 and the second NMOS 80.

The second clamp circuit 64 flows an ESD current from the power supply node to the ground node when it is detected that the voltage of the power supply node is the ESD voltage in response to the inverting signal of the second detection signal. It is intended to clamp the voltage of the above, and is equipped with a fourth MIMO 82 having a size much larger than that of a normal NOTES. The fourth MIMO 82 is connected between the power supply node and the ground node, and the inverted signal of the second detection signal is input to the gate.

The second protection diode 66 causes a negative polarity ESD current applied to the power supply terminal to flow from the ground terminal to the power supply node when an ESD event occurs, and includes a fifth diode 84. The fifth diode 84 is connected in the forward direction from the ground node to the power supply node.
The second protection diode 66 may utilize the parasitic diode of the fourth NMOS 82 of the second clamp circuit 64, or may provide a diode separately from the fourth NMOS 82.

Next, the operation of the ESD protection circuit 10 will be described.
Hereinafter, the differential signal SigP will be described as a representative.

First, the operation of the ESD protection circuit 10 during normal operation will be described.
In this case, it is required that the ESD protection circuit 10 does not perform a protective operation, that is, it does not affect the operation of the internal circuit.

In normal operation, the power supply voltage VDD is 3.3V and the ground voltage VSS is 0V. Further, it is assumed that the operating voltage range (minimum potential to maximum potential) of the differential signal pair SigP and SigN is 0V to 3V, and the common mode voltage Vcm thereof is 1.5V. It is assumed that the turn-on voltage Vth_dio of the first diode 44, the second diode 46, the third diode 48, the fourth diode 50, and the fifth diode 84 is 1V.

In the first protection circuit 12, the voltage of the first internal node n1 is always 1.5V, which is the common mode voltage Vcm. The first capacitive element 36 of the first voltage detection circuit 20 is charged to 1.5V of the common mode voltage Vcm, and the voltage Vrc of the first detection signal is also 1.5V.
In this case, the logic level of the input signal of the first inverter 22 is high level, the logic level of the output signal is low level, and the third MIMO 42 of the first clamp circuit 24 is in the off state.
Further, since the ground voltage VSS is 0V and the operating voltage range of the differential signal SigP is 0V to 3V, the third diode 48 of the reverse diode 28 is also in the off state.
Therefore, in the normal operation, the first protection circuit 12 does not perform the protection operation and does not affect the operation of the internal circuit at all.

In the second protection circuit 14, the second capacitive element 76 of the second voltage detection circuit 60 is charged to 3.3V of the power supply voltage VDD, and the voltage of the second detection signal is 3.3V.
In this case, the logic level of the input signal of the second inverter 62 is high level, the logic level of the output signal is low level, and the fourth MIMO 82 of the second clamp circuit 64 is in the off state.
Further, since the power supply voltage VDD is 3.3V and the ground voltage VSS is 0V, the fifth diode 84 of the second protection diode 66 is also in the off state.
Therefore, in the normal operation, the second protection circuit 14 does not perform the protection operation and does not affect the operation of the internal circuit at all.

Subsequently, the operation of the ESD protection circuit 10 during the noise immunity test will be described.
Also in this case, it is required that the ESD protection circuit 10 does not perform the protection operation.

In the noise immunity test, the operating voltage range of the differential signal pair SigP and SigN when ± 1V noise is applied is assumed to be -0.5V to 3.5V as shown in FIG. Other conditions are the same as in normal operation.

In the first protection circuit 12, the initial value of the voltage of the first internal node n1 before noise is applied is 1.5V, which is the same common mode voltage Vcm as in normal operation, as shown in FIG. The initial value of the voltage Vrc of the detection signal of 1 is also 1.5V.

Since the first voltage detection circuit 20 has a low-pass filter structure, the voltage Vrc of the first detection signal follows even if noise is applied to the differential signal pairs SigP and SigN and the common mode voltage Vcm fluctuates. It cannot be done and is 1.5V for a certain period of time. Therefore, unless the voltage of the first internal node n1 rises to 1.5V × 2 = 3V, which is twice the voltage Vrc of the first detection signal, due to noise, the logic of the input signal of the first inverter 22 The level remains high, the logic level of the output signal remains low, and the third MIMO42 of the first clamp circuit 24 is in the OFF state.

When viewed from the differential signal SigP side, the logic level of the input signal of the first inverter 22 becomes low level, the logic level of the output signal becomes high level, and the third MFPS 42 of the first clamp circuit 24 turns on. The minimum potential Vt1 on the positive side of the differential signal SigP at the time is 4V from the equation (1). That is, the minimum potential Vt1 on the positive side of the differential signal SigP is determined by adding the turn-on voltage Vth_dio of the first diode 44 and the initial value × 2 of the voltage Vrc of the first detection signal.

(Equation 1)
Minimum potential Vt1 on the positive side of the differential signal SigP
= Turn-on voltage of the first diode 44 Vth_dio + Initial value of voltage Vrc of the first detection signal x 2
= 1V + 1.5V x 2
= 1V + 3V
= 4V

On the other hand, the maximum potential on the positive side of the differential signal SigP when a noise of ± 1 V is applied is 3.5 V as shown in FIG. 2, so that the third MFPS 42 of the first clamp circuit 24 Does not turn on in response to noise.
Further, since the ground voltage VSS is 0V and the operating voltage range of the differential signal SigP is −0.5V to 3.5V, the third diode 48 of the reverse diode 28 is below the turn-on voltage, so that it is in the off state. Is.
Therefore, at the time of the noise immunity test, the first protection circuit 12 does not perform the protection operation in response to the noise.

There are various variations in how to give the initial value of the bias voltage. By setting the initial value of the bias voltage to an arbitrary voltage, the minimum potential Vt1 on the positive side of the differential signal SigP can be freely set. It can correspond to any noise amplitude.
For example, when the initial value of the bias voltage is set to 2V, the minimum potential Vt1 on the positive side of the differential signal SigP is Vt1 = 1V + 2V × 2 = 5V.
Further, by increasing the number of stages of the third diode 48, the maximum potential on the negative side of the differential signal SigP when the third MFPS 42 of the first clamp circuit 24 turns on can be easily adjusted.

Subsequently, in the Powered ESD test, which is one of the system level ESD tests, the operation of the ESD protection circuit 10 when a positive polarity ESD pulse is applied will be described.
In this case, the ESD protection circuit 10 is required to perform a protective operation.

In the Powered ESD test, since the power supply voltage VDD is applied, the initial value of the common mode voltage Vcm is 1.5V as shown in FIG. 4, and therefore the initial value of the voltage Vrc of the first detection signal is also 1. It is assumed to be 5.5V. Other conditions are the same as in normal operation.
In this case, in the first protection circuit 12, the logic level of the input signal of the first inverter 22 is high level, the logic level of the output signal is low level, and the third MFPS 42 of the first clamp circuit 24 is It is off.
Further, the third diode 48 of the reverse diode 28 is also in the off state.

When a positive polarity ESD pulse is applied to the external connection terminal of the differential signal SigP using an ESD gun, the first diode 44 turns on and the ESD current is transferred to the first internal node n1 via the first diode 44. After flowing in, the voltage of the first internal node n1 rises immediately.
On the other hand, since the first voltage detection circuit 20 has a low-pass filter structure, the voltage Vrc of the first detection signal cannot rise immediately, and by the time it rises, the first voltage detection circuit 20 A delay of about the time constant RC is required due to the resistance value R of the first resistance element 34 and the capacitance value C of the first capacitance element 36. Since the time constant RC is set larger than the pulse width of the ESD pulse, the logic level of the input signal of the first inverter 22 is low level and the logic level of the output signal is high level during the time constant RC period. , The third MFPS 42 of the first clamp circuit 24 turns on.
Therefore, as shown by the broken line in FIG. 4, the ESD current flows from the external connection terminal of the differential signal SigP to the ground node via the first diode 44 and the third MFPS 42 of the first clamp circuit 24. It can be released to the outside from the ground terminal.

The minimum potential Vt1 on the positive side of the differential signal SigP when the third NMOS 42 of the first clamp circuit 24 is turned on is also 4V from the equation (1). Since the maximum potential of the differential signal SigP becomes 4V or more due to the ESD pulse applied in the Powered ESD test, the third MIMO42 of the first clamp circuit 24 can be turned on and escape the ESD current as described above. can.

Subsequently, in the Powered ESD test, the operation of the ESD protection circuit 10 when an ESD pulse having a negative polarity is applied will be described.
In this case as well, the ESD protection circuit 10 is required to perform a protective operation.

As shown in FIG. 5, in the Powered ESD test, the initial value of the common mode voltage Vcm is 1.5V, and therefore the initial value of the voltage Vrc of the first detection signal is also 1.5V. Other conditions are the same as in normal operation.
In this case, in the first protection circuit 12, the logic level of the input signal of the first inverter 22 is high level, the logic level of the output signal is low level, and the third MFPS 42 of the first clamp circuit 24 is It is off. Further, the third diode 48 of the reverse diode is in the off state.

When a negative polarity ESD pulse is applied to the external connection terminal of the differential signal SigP using an ESD gun, the third diode 48 turns on and the ESD current is grounded from the ground terminal as shown by the broken line in FIG. It can flow through the node and the third diode 48 to the differential signal node corresponding to the differential signal SigP and escape to the outside from the external connection terminal of the differential signal SigP.

Subsequently, in the Unpowered ESD test, which is one of the system level ESD tests, the operation of the ESD protection circuit 10 when a positive polarity ESD pulse is applied will be described.
In this case, the ESD protection circuit 10 is required to perform a protective operation.

In the unpowered ESD test, the differential signal pairs SigP and SigN do not operate because the power supply voltage VDD is not applied, and as shown in FIG. 6, the initial value of the common mode voltage Vcm is 0V, and therefore the first detection signal. It is assumed that the initial value of the voltage Vrc of is also 0V. Other conditions are the same as in normal operation.
In this case, in the first protection circuit 12, the logic level of the input signal of the first inverter 22 is low level, but since the common mode voltage Vcm is also low level, the output signal is low level, and the second The third MIMO 42 of the clamp circuit 24 of 1 is in the off state.
Further, the third diode 48 of the reverse diode 28 is also in the off state.

In the Unpowered ESD test, the operation of the ESD protection circuit 10 when a positive polarity ESD pulse is applied to the external connection terminal of the differential signal SigP is as follows. In the Powered ESD test, the positive polarity ESD pulse is the differential signal SigP. The operation is the same as when applied to the external connection terminal of.
That is, the ESD current flows from the external connection terminal of the differential signal SigP to the ground node via the first diode 44 and the third MIMO42 of the first clamp circuit 24, as shown by the broken line in FIG. It can be released to the outside from the ground terminal.

Subsequently, in the Unpowered ESD test, the operation of the ESD protection circuit 10 when an ESD pulse having a negative polarity is applied will be described.
In this case as well, the ESD protection circuit 10 is required to perform a protective operation.

As shown in FIG. 7, even in the Unpowered ESD test, the differential signal pair SigP and SigN do not operate, and the initial value of the common mode voltage Vcm is 0V. Therefore, the initial value of the voltage Vrc of the first detection signal is also 0V. Suppose that Other conditions are the same as in normal operation.
In this case, in the first protection circuit 12, the logic level of the input signal of the first inverter 22 is low level, but since the common mode voltage Vcm is also low level, the output signal is low level, and the second The third MIMO 42 of the clamp circuit 24 of 1 is in the off state.
Further, the third diode 48 of the reverse diode 28 is also in the off state.

In the Unpowered ESD test, the operation of the ESD protection circuit 10 when a negative polarity ESD pulse is applied to the external connection terminal of the differential signal SigP is as follows. In the Powered ESD test, the negative polarity ESD pulse is the differential signal SigP. The operation is the same as when applied to the external connection terminal of.
That is, the ESD current flows from the ground terminal to the differential signal node corresponding to the differential signal SigP via the ground node and the third diode 48, as shown by the broken line in FIG. 7, and is outside the differential signal SigP. It can be released to the outside from the connection terminal.

As described above, in the ESD protection circuit 10, it is possible to secure a discharge path that does not pass through the power supply node in the system level ESD test. Since the power supply node is not included in the discharge path of the ESD current, the power supply voltage VDD-ground voltage VSS does not fluctuate, and the data of the holding circuit such as the flip-flop of the internal circuit that receives the power supply is not destroyed.

Subsequently, in the HBM test, which is one of the component level ESD tests, the operation of the ESD protection circuit 10 when the ESD pulse is applied based on the power supply reference will be described.
In this case, the ESD protection circuit 10 is required to perform a protective operation.
In the HBM test, the power supply voltage VDD is not applied, so all the conditions are the same as in the Unpowered ESD test.

In the HBM test, the operation of the first protection circuit 12 when a positive polarity ESD pulse is applied to the external connection terminal of the differential signal SigP in the power supply reference is that the positive polarity ESD pulse is differential in the Unpowered ESD test. This is the same as the operation of the first protection circuit 12 when applied to the external connection terminal of the signal SigP.
Therefore, the ESD current flows from the external connection terminal of the differential signal SigP to the ground node via the first diode 44 and the third MFPS 42 of the first clamp circuit 24, as shown by the broken line in FIG. Subsequently, the ESD current can further flow from the ground node to the power supply node via the fifth diode 84 and escape from the power supply terminal to the outside.

On the other hand, in the HBM test, when the negative polarity ESD pulse is applied to the external connection terminal of the differential signal SigP, the operation of the first protection circuit 12 is that the negative polarity ESD pulse is applied in the Unpowered ESD test. This is the same as the operation of the first protection circuit 12 when applied to the external connection terminal of the differential signal SigP.

That is, in the HBM test, when an ESD pulse having a negative polarity based on the power supply is applied to the external connection terminal of the differential signal SigP, the third diode 48 turns on and the voltage of the ground node drops immediately.
On the other hand, since the second voltage detection circuit 60 has a low-pass filter structure, the voltage Vrc of the second detection signal cannot rise immediately, and by the time it rises, the voltage Vrc of the second voltage detection circuit 60 A delay of about RC is required. Since the time constant RC is set larger than the pulse width of the ESD pulse, the logic level of the input signal of the second inverter 62 is low level and the logic level of the output signal is high level during the time constant RC period. , The fourth MIMO 82 of the second clamp circuit 64 turns on.
Therefore, as shown by the broken line in FIG. 9, the ESD current flows from the power supply terminal to the ground node via the power supply node, the fourth MIMO 82 of the second clamp circuit 64, and subsequently via the third diode 48. It can flow to the differential signal node corresponding to the differential signal SigP and escape to the outside from the external connection terminal of the differential signal SigP.
As described above, in the ESD protection circuit 10, in the HBM test, the discharge path when the ESD pulse having a negative polarity is applied with reference to the power supply is also secured without any problem.

Subsequently, in the HBM test, which is one of the component level ESD tests, the operation of the ESD protection circuit 10 when the ESD pulse is applied with reference to the ground will be described.
In this case as well, the ESD protection circuit 10 is required to perform a protective operation.

In the HBM test, the operation of the first protection circuit 12 when a positive polarity ESD pulse is applied to the external connection terminal of the differential signal SigP with respect to the ground is that the positive polarity ESD pulse is differential in the Unpowered ESD test. This is the same as the operation of the first protection circuit 12 when applied to the external connection terminal of the signal SigP.
Therefore, as shown by the broken line in FIG. 10, the ESD current flows from the external connection terminal of the differential signal SigP to the ground node via the first diode 44 and the third MFPS 42 of the first clamp circuit 24. It can be released to the outside from the ground terminal.

On the other hand, in the HBM test, when the negative polarity ESD pulse is applied to the external connection terminal of the differential signal SigP, the operation of the first protection circuit 12 is that the negative polarity ESD pulse is applied in the Unpowered ESD test. This is the same as the operation of the first protection circuit 12 when applied to the external connection terminal of the differential signal SigP.
Therefore, as shown by the broken line in FIG. 11, the ESD current flows from the ground terminal to the differential signal node corresponding to the differential signal SigP via the ground node and the third diode 48, and is outside the differential signal SigP. It can be released to the outside from the connection terminal.
As described above, in the ESD protection circuit 10, in the HBM test, the discharge path when the ESD pulse is applied with reference to the ground is also secured without any problem.

As described above, since the ESD protection circuit 10 can support system level ESD test and noise immunity test in addition to component level ESD test, it can be used in electronic devices used in special fields such as in-vehicle field. Applicable. Further, the ESD protection circuit 10 can be manufactured by using a normal manufacturing process, and since it is a small-scale and compact circuit, it is possible to suppress an increase in cost.

Although the differential signal SigP has been described as a representative, the differential signal SigN also operates in the same manner. In the case of the differential signal SigN, the second diode 46 and the fourth diode 50 operate in place of the first diode 44 and the third diode 48.

The bias voltage is not limited to the common mode voltage Vcm, and any intermediate voltage between the power supply voltage VDD and the ground voltage VSS can be used.
For example, the bias voltage can be changed by changing the resistance values of the resistance elements 30 and 32. Alternatively, the resistance elements 30 and 32 are connected in series between the power supply node and the ground node, and the resistance values of the resistance elements 30 and 32 are similarly changed to change the bias voltage between the power supply voltage VDD and the ground voltage VSS. It can be set to any intermediate voltage between.
As a result, the turn-on voltage of the ESD protection circuit can be set higher than the maximum voltage of the signal waveform to which noise is applied, and the risk of reacting to noise can be reduced. In addition, the turn-on voltage of the ESD protection circuit can be set to an appropriate voltage that can react quickly to the ESD pulse so that the capability of the ESD protection circuit can be maximized.

Common mode voltages are often used in differential circuits. Therefore, in the first protection circuit 12, the bias circuit 18 can be omitted and the circuit scale can be reduced by using the existing common mode voltage used in the differential circuit.
Further, as shown in FIG. 12, even if the bias voltage is output from the bias circuit 18 to the second internal node n2 instead of the first internal node n1, the first protection circuit 12 operates in the same manner. be able to.

The second protection circuit 14 has the same configuration as the conventional ESD protection circuit shown in FIG. 18, and the conventional ESD protection circuit may be provided in the IC on which the ESD protection circuit of the present invention is mounted. .. Therefore, in the ESD protection circuit 10, by using the conventional ESD protection circuit used in the IC as the second protection circuit 14, the second protection circuit 14 can be omitted and the circuit scale can be reduced. ..

The first and second protection circuits 12, 14, the bias circuit 18, the first and second voltage detection circuits 20, 60, the first and second inverters 22, 62, the first and second clamp circuits. 24, 64, the first and second protection diodes 26, 66, and the reverse diode 28 have been described with reference to specific circuits, but the present invention is not limited to this, and various configurations capable of realizing the same function can be realized. Circuit can be used.

Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and changes may be made without departing from the gist of the present invention.

10 ESD protection circuit 12 1st protection circuit 14 2nd protection circuit 16 Differential circuit 16A Transmit buffer 16B Receive buffer 18 Bias circuit 20 1st voltage detection circuit 22 1st inverter 24 1st clamp circuit 26 1st Protection diode 28 Reverse diode 30, 32 Resistance element 34 First resistance element 36 First capacitance element 38 First PCOS
40 First MIMO
42 Third NMOS
44 1st diode 46 2nd diode 48 3rd diode 50 4th diode 60 2nd voltage detection circuit 62 2nd inverter 64 2nd clamp circuit 66 2nd protection diode 74 2nd resistance element 76 Second capacitive element 78 Second cDNA
80 Second MFPS
82 Fourth MFPS
84 Fifth Diode 90 System 92,94 IC
96,98 Differential signal line pair 100,102 Noise filter 104,106 ESD protection element 108,110,120 ESD protection circuit 130 Voltage detection circuit 132 Inverter 134 Clamp circuit 136 Protection diode 144 Resistance element 146 Capacitive element 148 photoresist
150,152 SiO
154,156 diode

Claims (9)

It is an ESD protection circuit that protects the internal circuit of the IC from being destroyed by the ESD current and ESD voltage when an ESD event occurs.
The first protection circuit is provided, and the first protection circuit is
A bias circuit that generates a bias voltage, which is an intermediate voltage between the power supply voltage and the ground voltage, and outputs it to the first internal node.
A first voltage detection circuit that detects whether the voltage of the first internal node is the bias voltage or the ESD voltage and outputs the first detection signal to the second internal node.
It operates in the voltage range between the voltage of the first internal node and the ground voltage, inverts the first detection signal, and outputs the inverted signal of the first detection signal to the third internal node. With the first inverter
When it is detected that the voltage of the first internal node is the ESD voltage in response to the inverting signal of the first detection signal, the ESD current is passed from the first internal node to the ground node. The first clamping circuit that clamps the voltage of the first internal node,
When the ESD event occurs, the positive-polarity ESD current applied to each of the external connection terminals of the differential signal pair is passed from each of the external connection terminals of the differential signal pair to the first internal node. 1 protection diode and
When the ESD event occurs, a negative polarity ESD current applied to each of the external connection terminals of the differential signal pair flows from the ground terminal to each of the differential signal nodes corresponding to the differential signal pair in the reverse direction. An ESD protection circuit with a diode. The bias circuit comprises two resistance elements connected in series between two differential signal nodes corresponding to the differential signal pair, from between the two resistance elements to the first internal node. The bias voltage is output,
The first voltage detection circuit includes a first resistance element and a first capacitive element connected in series between the first internal node and the ground node, and includes the first resistance element and the ground node. The first detection signal is output from between the first capacitive element and the second internal node.
The first inverter includes a first P-type MOS transistor and a first N-type MOS transistor connected in series between the first internal node and the ground node, and the first P-type is provided. The first detection signal is input to the gate of the MOS transistor and the first N-type MOS transistor, and the third inside is formed between the first P-type MOS transistor and the first N-type MOS transistor. The inverted signal of the first detection signal is output to the node, and the inverted signal is output.
The first clamp circuit comprises a third N-type MOS transistor connected between the first internal node and the ground node, and the first is at the gate of the third N-type MOS transistor. The inverted signal of the detection signal is input,
The first protection diode includes a first diode connected in the forward direction from a differential signal node corresponding to one of the differential signal pairs toward the first internal node, and the differential signal pair. A second diode connected in the forward direction from the corresponding differential signal node to the first internal node.
The reverse diode is a third diode connected in the forward direction from the ground node toward the differential signal node corresponding to one of the differential signal pairs, and the other of the differential signal pairs from the ground node. The ESD protection circuit of claim 1, comprising a fourth diode forwardly connected towards the corresponding differential signal node. The ESD protection circuit according to claim 2, wherein the first capacitive element is a MOS gate capacitance. Further, a second protection circuit is provided, and the second protection circuit is provided.
A second voltage detection circuit that detects whether the voltage of the power supply node is the power supply voltage or the ESD voltage and outputs a second detection signal to the fourth internal node.
With a second inverter that operates in a voltage range between the power supply voltage and the ground voltage, inverts the second detection signal, and outputs the inverted signal of the second detection signal to the fifth internal node. ,
When it is detected that the voltage of the power supply node is the ESD voltage in response to the inverting signal of the second detection signal, the ESD current is passed from the power supply node to the ground node of the power supply node. A second clamp circuit that clamps the voltage,
The invention according to any one of claims 1 to 3, further comprising a second protection diode that allows a negative polarity ESD current applied to the power supply terminal to flow from the ground terminal to the power supply node when the ESD event occurs. The ESD protection circuit described. The second voltage detection circuit includes a second resistance element and a second capacitance element connected in series between the power supply node and the ground node, and the second resistance element and the second. The second detection signal is output from between the capacitive element and the fourth internal node.
The second inverter includes a second P-type MOS transistor and a second N-type MOS transistor connected in series between the power supply node and the ground node, and the second P-type MOS transistor and the second P-type MOS transistor. The second detection signal is input to the gate of the second N-type MOS transistor, and the second detection signal is input from between the second P-type MOS transistor and the second N-type MOS transistor to the fifth internal node. The inverted signal of the second detection signal is output,
The second clamp circuit includes a fourth N-type MOS transistor connected between the power supply node and the ground node, and the second detection signal is transmitted to the gate of the fourth N-type MOS transistor. An inverting signal is input and
The ESD protection circuit according to claim 4, wherein the second protection diode includes a fifth diode connected in the forward direction from the ground node to the power supply node. The ESD protection circuit according to claim 5, wherein the second capacitive element is the gate capacitance of the MOS. The ESD protection circuit according to any one of claims 1 to 6, wherein the bias circuit outputs a common mode voltage of the differential signal pair as the bias voltage to the first internal node. The ESD protection circuit according to any one of claims 1 to 7, wherein the bias circuit outputs the bias voltage to the second internal node instead of the first internal node. The maximum potential of one of the differential signal pairs is equal to or lower than the power supply voltage, the minimum potential of the other of the differential signal pairs is equal to or higher than the ground voltage, and the operating voltage range of the differential signal pair is the power supply voltage and the above. The ESD protection circuit according to any one of claims 1 to 8, which is a voltage range between the ground voltage and the ground voltage.

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