JP7027481B2 - Solid-state image sensor - Google Patents

Description

The present invention relates to the arrangement of drive lines of a solid-state image sensor.

In recent years, image pickup devices such as digital video cameras and digital cameras using CMOS image sensors suitable for low power consumption and high-speed readout have become widespread and generally used. In a CMOS image sensor in which a plurality of pixels including a photoelectric conversion unit are arranged in the row and column directions, a configuration called a global electronic shutter in which exposure start and exposure end are electronically controlled simultaneously by all pixels has been proposed (Patent Document). 1).

However, the present inventors have found that in order to suppress the deterioration of image quality that occurs when the global electronic shutter is adopted, it is necessary to consider even the arrangement of the drive lines of the pixel transistors.

International Publication No. 11/043432

An object of the present invention is to provide a solid-state image sensor capable of suppressing deterioration of image quality that may occur when performing a global electronic shutter operation.

In the photoelectric conversion device according to the present invention, a pixel array in which each pixel row composed of a plurality of pixels arranged along a second direction is arranged in a plurality of first directions orthogonal to the second direction. The pixel has a photoelectric conversion unit, a first transfer transistor that transfers the charge of the photoelectric conversion unit to the charge storage unit, and a second transfer transistor that transfers the charge of the charge storage unit to the FD. The photoelectric conversion device includes a reset transistor for resetting the potential of the FD, and the photoelectric conversion device is arranged so as to extend in the second direction. A gate drive line, a plurality of second gate drive lines for driving the second transfer transistor arranged so as to extend in the second direction, and a plurality of second gate drive lines extending in the second direction. The first gate drive line and the first pixel, which have a plurality of third gate drive lines for driving the reset transistor and are provided corresponding to the first pixel row. From the point where the first transfer transistor of the first pixel of the row is connected to the first gate drive line provided corresponding to the first pixel row and the second direction. The first pixel row corresponding to the first pixel row in the section up to the point where the first transfer transistor of the second pixel arranged adjacent to the first pixel is connected. The widest portion of the wiring width of the gate drive line in the first direction is the third gate drive line provided corresponding to the first pixel row and the reset transistor of the first pixel. In the section from the place where the first pixel row is connected to the place where the third gate drive line provided corresponding to the first pixel row and the reset transistor of the second pixel are connected. It is characterized in that it is wider than the widest portion of the wiring width in the first direction of the third gate drive line corresponding to the first pixel row.

According to the present invention, it is possible to provide a solid-state image sensor capable of suppressing deterioration of image quality that may occur when performing a global electronic shutter operation.

Pixel plan view in Embodiment 1 of the present invention Cross-sectional view of pixels in Embodiment 1 of the present invention Pixel circuit diagram in Embodiment 1 of the present invention Drive timing diagram in Embodiment 1 of the present invention Pixel plan view in Embodiment 2 of the present invention Cross-sectional view of pixels in embodiments 2, 3 and 4 of the present invention Pixel circuit diagram in Embodiments 2, 3 and 4 of the present invention Drive timing diagram in embodiments 2, 3 and 4 of the present invention Pixel plan view in Embodiment 3 of the present invention Pixel plan view in Embodiment 4 of the present invention Schematic diagram of an arrangement example of drive wiring according to the first embodiment of the present invention. Explanatory diagram of wiring distance Schematic diagram of an arrangement example of drive wiring according to the second embodiment of the present invention. Schematic diagram of an arrangement example of drive wiring according to the third embodiment of the present invention.

[Embodiment 1]
The first embodiment of the present invention will be described with reference to FIGS. 1 to 4 and 11. FIG. 1 is a plan view of a plurality of pixels arranged in a 3 × 3 matrix. FIG. 2 is a pixel cross-sectional view of a portion along points A to B in FIG. 1. FIG. 3 is an equivalent circuit diagram of pixels for 3 rows and 3 columns corresponding to FIG. 1. FIG. 4 is a drive timing diagram for operating the solid-state image sensor of the present embodiment. The same members are designated by the same reference numerals in each figure. In the following, a configuration in which electrons are used as signal charges will be illustrated, but holes can also be used as signal charges. When holes are used as signal charges, the conductive type of each semiconductor region may be changed to the opposite conductive type as opposed to the case where the signal charges are electrons.

In FIG. 3, the pixel P1 is provided with a first transfer transistor 14 that transfers the charge of the photoelectric conversion unit 1 and a charge storage unit 3 that stores the charge transferred by the first transfer transistor 14. Further, a second transfer transistor 15 for transferring charges from the charge storage unit 3 is provided. Further, a floating diffusion 6 (hereinafter referred to as “FD6”) for accumulating the electric charge transferred by the second transfer transistor 15, a reset transistor 16 for resetting the potential of the FD6, a source follower transistor 17, and a row selection transistor 18 are provided. Has been.

Each pixel P1 is connected to the vertical output line Vout via the pixel output unit 22. Reference numeral 20 is a power supply, and reference numeral 21 is grounding. In the present embodiment, the charge is discharged from the photoelectric conversion unit 1 to the semiconductor substrate 7 via the embedded layer 9, which is called a Vertical Overflow Drain (hereinafter referred to as VOFD).

FIG. 2 is a pixel cross-sectional view of a portion along points A to B in FIG. 1. A p-type embedded layer 9 and a p-type well 8 are provided on the n-type semiconductor substrate 7. A surface protective layer 2 is provided on the photoelectric conversion unit 1 composed of an n-type and a p-type, and a so-called embedded photodiode is configured. A p-type surface protective layer 4 is provided on the n-type charge storage unit 3.

Further, a p-type depletion suppressing section 5 is provided below the charge storage section 3, and the depletion suppressing section 5 is made of a semiconductor having a higher concentration than the well 8.

By supplying a pulse for turning on the first transfer transistor 14 to TX1 which is the gate of the first transfer transistor 14, the charge of the photoelectric conversion unit 1 is transferred to the charge storage unit 3.

Then, the charge stored in the charge storage unit 3 is transferred to the FD 6 by supplying a pulse on which the second transfer transistor 15 is turned on to the TX2 which is the gate of the second transfer transistor 15.

Next, the operation of the solid-state image pickup device according to the present embodiment will be described with reference to FIGS. 3 and 4. In FIG. 4, each transistor is in a non-conducting state at a low level (hereinafter, L level), and each transistor is in a conducting state at a high level (hereinafter, H level).

In FIGS. 3 and 4, pTX1 (n) is the gate drive line of the first transfer transistor 14 in the nth row, and pTX2 (n) is the gate drive line of the second transfer transistor 15 in the nth row. .. Further, pREL (n) is the gate drive line of the reset transistor 16 in the nth row, and pSEL (n) is the gate drive line of the row selection transistor 18 in the nth row. The parentheses after the name of each gate drive line mean the number of rows of pixels.

By setting the level of the substrate potential to the L level at time t0 in FIG. 4, the VOFD is turned off, and the photoelectric conversion electrons are started to be accumulated in the photoelectric conversion unit 1.

Next, at time t1, the levels of the gate drive lines pTX1 (n-1), pTX1 (n), and pTX1 (n + 1) of the first transfer transistor 14 are set to H level, and the first transfer transistor 14 is turned on. Then, the electron is transferred to the charge storage unit 3. After a predetermined time has elapsed, the first transfer transistor 14 is turned off to end the transfer of electrons to the charge storage unit 3.

Since the present embodiment has the charge storage unit 3, the signal charge of the photoelectric conversion unit 1 of all the pixels can be transferred to the charge storage unit 3 at the same time. This makes it possible to realize the operation of a global electronic shutter in which the start and end of exposure are controlled by an electronic switch at the same time for all pixels.

Next, at time t2, by setting the level of the substrate potential to the H level, the photoelectric conversion unit 1 and the semiconductor substrate 7 are punched through, and the electric charge is discharged to the semiconductor substrate 7.

By appropriately setting the period from turning off the VOFD at the time t0 to turning on the first transfer transistor 14 at the time t1, an image of an arbitrary accumulation time can be obtained.

The first transfer transistor may be turned on a plurality of times intermittently between the time t0 and the time t1. By turning it on a plurality of times, the signal charge handled per transfer operation is reduced, and the transfer operation can be facilitated. When it is turned on a plurality of times, the time t1 is the last on time of the above-mentioned multiple on operations.

Next, at times t3, t4, and t5, the level of the gate drive line pTX2 of the second transfer transistor 15 is set to H level in a row sequence, and the second transfer transistor 15 is turned on. As a result, the signal charge is transferred from the charge storage unit 3 to the FD6.

As the signal transfer method after FD6, the conventional CMOS image sensor method can be applied. That is, a signal is output to the vertical signal line via the source follower transistor 17, the row selection transistor 18, and the pixel output unit 22. The noise component signal may be output to the vertical signal line before the second transfer transistor 15 is turned on. Although the row selection transistor 18 is provided in FIG. 3, a configuration omitted may be adopted.

Here, each gate drive line is composed of a conductor in order to transmit each drive pulse shown in FIG. 4, and a parasitic capacitance is formed between the conductor and the conductor. Due to this parasitic capacitance and the electric resistance of the conductor, a propagation delay occurs in each drive pulse transmitted in the conductor. As the number of pixels of the solid-state image sensor increases, the image pickup area expands, so that there are places where the propagation delay is small and places where the propagation delay is large in the image pickup area. As a result, the operation timing of the drive pulse input to each gate of the pixel transistor is deviated in the image pickup region, and the timing at which the image signal is accumulated in the photoelectric conversion unit 1 is deviated. As a result, the image quality may deteriorate.

In the conventional row-sequential shutter method, which is not a global electronic shutter, the deviation of the accumulation timing in the screen is relatively large, and the deviation of the accumulation timing in the screen did not cause a big problem in image quality. .. However, in the global electronic shutter, the difference in the accumulation timing for each row is unlikely to occur, so that the deterioration of the image quality due to the difference in the accumulation timing caused by the propagation delay becomes conspicuous in the imaging region. In particular, the deviation of the accumulation timing becomes more conspicuous because the ratio of the deviation to the accumulation time becomes larger as the accumulation time is shorter, and it may be one of the factors that the accumulation time cannot be shortened.

The accumulation timing in the global electronic shutter is controlled by the first transfer transistor 14 as described above. Therefore, by reducing the parasitic capacitance of the gate drive line pTX1 of the first transfer transistor 14 and reducing the propagation delay, it is possible to reduce the deviation of the accumulation timing in the imaging region. The influence of such parasitic capacitance is a problem that occurs remarkably when the gate drive lines of a plurality of pixel transistors are provided in the same wiring layer and the gate drive lines are arranged in close proximity to each other.

(Arrangement of pTX1)
Next, with reference to FIG. 1, the arrangement of the drive line of the pixel transistor for reducing the parasitic capacitance of the gate drive line pTX1 will be described.

FIG. 1 shows a semiconductor region constituting the photoelectric conversion unit 1 and the like, a gate electrode of a pixel transistor, wiring for electrically connecting each semiconductor region and a gate electrode of each pixel transistor, and the like. In the solid-state imaging device, in addition to the drive lines of the pixel transistors, wirings such as a power supply line, a ground power supply line, and a vertical output line are appropriately arranged in a wiring layer composed of a plurality of layers. It is shown that the drive lines of the pixel transistors shown in FIG. 1 are arranged in the same wiring layer. For example, in the case of a wiring layer having a three-layer structure, the drive lines of the pixel transistors shown in FIG. 1 are arranged in the wiring layer of the second layer.

In FIG. 1, a first transfer transistor 14, a second transfer transistor 15, a gate drive line of the reset transistor 16 and the like are provided on the charge storage unit 3 so as to extend in the row direction of the imaging region. There is. Further, these gate drive lines are provided in a periodic arrangement pattern.

Only the gate drive line pRES (n) of the reset transistor 16 is arranged in the vicinity of the gate drive line pTX1 (n), and the gate drive line pTX2 (n + 1) of the second transfer transistor 15 is arranged far away. .. According to such an arrangement, the pTX1 (n) can reduce the parasitic capacitance as compared with the case where the gate drive lines of the pixel transistors are arranged close to each other on both sides of the pTX1 (n). ..

FIG. 11 is a diagram schematically showing the arrangement of the drive wiring shown in FIG. The distance between each drive wiring is expressed in Dx.

Here, regarding the drive wiring of the n-1 line, the n line, and the n + 1 line, the gate drive line of the first transfer transistor and the gate drive line of the pixel transistor arranged on both sides of the gate drive line of the first transfer transistor. Let the total wiring distance with and be _DTX1 Transistor.

Similarly, the total wiring distance between the gate drive lines of the pixel transistors other than the first transfer transistor and the gate drive lines of the pixel transistors arranged on both sides of the gate drive line is set as follows. That is, the second transfer transistor is DTX2 _Total , the reset transistor is DRES _Total , and the row selection transistor is DSEL _Total .

In this case, the DTX1 _Total has a larger value than any one of the DTX2 _Total , the DRES _Total , and the DSEL _Total .

In FIG. 11, the intervals between the drive wirings of the n-1 line, the n line, and the n + 1 line are set to D ₁ to D ₁₁ .

Here, for the drive wiring of the n-1 line, the n line, and the n + 1 line, the DTX1 _Total is D ₁ + D ₃ + D ₆ + D ₈ + D ₉ . On the other hand, the DRES _Total is D ₁ + D ₂ + D ₇ + D ₈ + D ₉ + D ₁₀ . The DSEL _Total is D ₂ + D ₄ + D ₅ + D ₇ + D ₁₀ + D ₁₁ .

Since D ₃ and D ₆ are, for example, three times or more larger than the spacing between other wires, the DTX1 _Total is larger than the DRES _Total and DSEL _Total in the n-1, n, and n + 1 rows. ing. In the specification of the present application, the wiring distance between the drive wirings is defined as, for example, the distance between the end portion of pTX1 (n) and the end portion of pRES (n), as shown in FIG.

According to the configuration described above, it is possible to reduce the deviation of the accumulation timing by reducing the parasitic capacitance generated in the gate drive line pTX1 and reducing the propagation delay.

Further, the arrangement of the drive lines described above can be applied not only to the front-illuminated type (FSI: Front Side Illumination) but also to the back-illuminated type (BSI: Bronto Side Illumination). That is, even in the back-illuminated type, it is assumed that the drive line of each pixel transistor is arranged corresponding to each line of the pixel. In that case, the example of arranging the drive line described above may be appropriately adopted. can.

By the way, FIG. 1 shows a surface-illuminated pixel plan view, and in the surface-illuminated type, each drive line of each pixel transistor is generally arranged in a region where a photoelectric conversion unit is not formed. For example, in FIG. 1, the gate drive line of each pixel transistor is arranged above the charge storage unit. Therefore, considering the layout of the drive lines for the purpose of reducing the parasitic capacitance of the gate drive line pTX1 of the first transfer transistor 14, the gate drive line pTX1 among the gate drive lines of the pixel transistor is connected to the photoelectric conversion unit 1. It will be placed in close proximity. As a result, the gate drive line pTX1 is arranged at the end of the drive line region, and the gate drive line pTX1 is configured such that the conductor is arranged only on one side in the drive line region.

(Arrangement of pTX1 and pTX2)
In the present embodiment, the gate drive line pTX1 and the gate drive line pTX2 are not brought close to each other. Here, "not in close proximity" means that pTX2 is not arranged on either side of pTX1. Alternatively, even if pTX2 is arranged on one side of pTX1, the distance between pTX1 and pTX2 is, for example, three times or more the distance from the drive line arranged on the other side of pTX1. say.

The problem when the gate drive line pTX1 and the gate drive line pTX2 are brought close to each other is shown below.

When the gate drive line pTX1 and the gate drive line pTX2 are capacitively coupled, the potential of the gate drive line pTX2 also fluctuates at the timing of changing the level of the gate drive line pTX1. For example, at the time t1 shown in FIG. 4, the level of the gate drive line pTX2 is originally the L level, but when the gate drive line pTX1 is changed from the L level to the H level, the potential of the gate drive line TX2 is changed. Also fluctuates from the L level to the H level. As a result, the potential barrier from the charge storage unit 3 to the FD6 is reduced, so that the saturation signal amount of the charge storage unit 3 is reduced. Since the influence of this potential fluctuation changes due to the variation in the parasitic capacitance in the imaging region, the saturation signal amount of the charge storage unit 3 becomes a factor that varies in the imaging region. This phenomenon becomes more remarkable when the operation of the gate drive line pTX1 is intermittently performed a plurality of times between the time t0 and the time t1.

By the way, for example, the gate drive line TX2 may be set to a negative potential during the period when the second transfer transistor 15, which is an MIMO, is off. As a result, the hole can be excited in the channel portion, so that even if an electron is generated, the dark current can be suppressed by the recombination between the electron and the hole. At this time, if the gate drive line pTX1 and the gate drive line pTX2 are capacitively coupled, the potential of the gate drive line pTX2 fluctuates in the direction of increasing at the timing when the level of the gate drive line pTX1 is changed from the L level to the H level. However, the excitation of the hole may be insufficient. As a result, the suppression of dark current may be insufficient.

Therefore, in the present embodiment, the gate drive line pTX1 and the gate drive line pTX2 are arranged so as not to be close to each other. In particular, in FIGS. 1 and 11, regarding the drive wiring of the n-1 line, the n line, and the n + 1 line, the gate drive line pTX1 has the largest wiring distance among the wiring distances between the gate drive lines of the pixel transistors. And the wiring distance between the gate drive line pTX2 and the gate drive line pTX2.

By the way, as can be understood from FIG. 4, at the timing when the first transfer transistor is turned on, the reset transistor is also turned on, and even if the potential fluctuation of the reset transistor occurs in the direction from the L level to the H level. Less likely to be affected. Therefore, the gate drive line pRES can be arranged close to the gate drive line pTX1.

Further, instead of the gate drive line pRES, the gate drive line pSEL can be arranged close to the gate drive line pTX1. Even if the row selection transistor is turned off at the timing when the first transfer transistor is turned on, if the constant current source is turned off, there is no signal charge transfer path and no signal variation occurs in the imaging region. Because.

Further, instead of the gate drive line pRES, a power supply line or a ground line can be arranged close to the gate drive line pTX1 to suppress potential fluctuation. This is because the power supply line and the ground line are not directly related to the signal charge transfer path and do not cause signal variation in the imaging region.

In the present embodiment, the configuration in which the FD 6 is individually provided for each pixel has been described, but a pixel configuration in which the FD 6 is shared by a plurality of pixels may be adopted. Even in this case, the same effect can be obtained by arranging the gate drive line pTX1 of the first transfer transistor as described above. Further, since it is possible to reduce the number of drive lines by sharing the FD6 with a plurality of pixels, the gate drive line pTX1 of the first transfer transistor can be kept away from other drive lines, and the parasitic capacitance can be reduced. It is also possible to reduce it.

[Embodiment 2]
Embodiment 2 of the present invention will be described with reference to FIGS. 5 to 8 and 13. The parts having the same functions as those of the previous embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. FIG. 5 is a pixel plan view of the solid-state image sensor of the present embodiment for 3 rows and 3 columns. FIG. 6 is a pixel cross-sectional view of a portion along points C to D in FIG. FIG. 7 is an equivalent circuit diagram of pixels for 3 rows and 3 columns corresponding to FIG. FIG. 8 is a drive timing diagram for operating the solid-state image sensor of the present embodiment.

The difference from the first embodiment is that the VOFD configuration is not adopted and an overflow transistor is separately provided. That is, as shown in FIGS. 6 and 7, an overflow transistor 19 is provided, and when the gate OFG of the overflow transistor is turned on, the electric charge is transferred to the power supply 20 through the plug 12.

FIG. 8 shows a timing chart. At time t0, the overflow transistor 19 is turned off by setting the level of the gate drive line pOFG of the overflow transistor 19 to the L level.

Next, at time t1, the level of the gate drive line pTX1 of the first transfer transistor 14 is set to H level, and the first transfer transistor 14 is turned on to transfer electrons to the charge storage unit 3. After a predetermined time has elapsed, the first transfer transistor 14 is turned off to end the transfer of electrons to the charge storage unit 3.

Next, at time t2, the overflow transistor 19 is turned on by setting the level of the gate drive line pOFG to H level. As a result, electric charges can be discharged from the photoelectric conversion unit 1 to the power supply 20 which is an overflow drain.

An image of an arbitrary accumulation time can be obtained by appropriately setting the period from when the level of the gate drive line pOFG is set to L level at time t0 until the first transfer transistor 14 is turned on at time t1. ..

FIG. 13 is a diagram schematically showing the arrangement of the drive wiring shown in FIG. The intervals between the drive wirings of the n-1 line, the n line, and the n + 1 line are set to D ₁ to D ₁₂ . Since the pOFG (n-2) is the drive wiring corresponding to the pixel in the n-2th row, the distance between the pOFG (n-2) and the adjacent drive line is not taken into consideration. Also, although not shown, pOFG (n + 1) is also not taken into account because it is located between pRES (n + 2) and pSEL (n + 2).

Here, in the n-1 line, the n line, and the n + 1 line, the DTX1 _Total is D ₁ + D ₃ + D ₈ + D ₁₀ + D ₁₁ . On the other hand, the DRES _Total is D ₁ + D ₂ + D ₉ + D ₁₀ + D ₁₁ . The DSEL _Total is D ₄ + D ₅ + D ₆ + D ₇ + D ₁₂ . Further, the DOFG _Total is D ₂ + D ₄ + D ₇ + D ₉ .

Since D ₃ and D ₈ are, for example, three times or more larger than the spacing between other wires, the DTX1 _Total is larger than the DRES _Total , DSEL _Total , and DOFG _Total in the n-1, n, and n + 1 rows. It becomes a value. According to such a configuration, the stray capacitance generated in the gate drive line pTX1 can be reduced, and the propagation delay can be reduced to reduce the deviation of the accumulation timing.

Further, it can be expressed that such a wiring arrangement is arranged so that the pTX1 and the pTX2 are not close to each other. Further, in the n-1 line, the n line, and the n + 1 line, the distance between pTX1 and pTX2 can be expressed as the maximum wiring distance among the wiring distances between the gate drive lines of the pixel transistors.

(Arrangement of pTX1 and pOFG)
Further, a problem may occur when the gate drive line pTX1 and the gate drive line pOFG are capacitively coupled. That is, at the time t1 in FIG. 8, at the timing when the level of the gate drive line pTX1 is changed from the L level to the H level, the level of the gate drive line pOFG is the L level. However, when the gate drive line pTX1 and the gate drive line pOFG are capacitively coupled, the potential of the gate drive line pOFG fluctuates in the direction from the L level to the H level at time t1. As a result, the potential barrier from the photoelectric conversion unit 1 to the power supply 20 which is an overflow drain may be lowered, and electrons may be transferred from the photoelectric conversion unit 1 to the power supply 20 to reduce the saturation signal amount of the photoelectric conversion unit 1. , Causes variation within the imaging region.

Therefore, as shown in FIGS. 5 and 13, in the present embodiment, a drive line pRES is provided between both drive lines so that the gate drive line TX1 and the gate drive line OFG do not come close to each other in the same drive wiring region. ing.

By the way, in the present embodiment, an overflow transistor is adopted, and in the first embodiment, a VOFD configuration is adopted. If the photoelectric conversion unit 1 having a deep depth is adopted for the purpose of increasing the sensitivity on the long wavelength side, it becomes difficult for the VOFD to discharge charges. However, even in such a case, if the overflow transistor is adopted, the charge can be discharged. Further, in the VOFD, the embedded layer 9 needs to have a low concentration to some extent in order to punch through the photoelectric conversion unit 1 and the semiconductor substrate 7. On the other hand, if an overflow transistor is adopted, it is possible to increase the density of the embedded layer 9. This makes it possible to improve the sensitivity of the photoelectric conversion unit 1 and the transfer efficiency to the charge storage unit 3.

On the other hand, by adopting the VOFD configuration, the gate OFG of the overflow transistor and the gate drive line pOFG are eliminated, so that the vacant region can be allocated to other components. For example, while maintaining the size of the photoelectric conversion unit 1, the interval in which each drive line is arranged can be widened, and the parasitic capacitance of the gate drive line pTX1 of the first transfer transistor can be further increased as compared with the first embodiment. It can be reduced. Further, by increasing the area of the photoelectric conversion unit 1, the saturated charge amount of the photoelectric conversion unit 1 can be increased or the sensitivity can be increased.

[Embodiment 3]
Embodiment 3 of the present invention will be described with reference to FIGS. 6, 7, 9, and 14. The parts having the same functions as those in the above embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 9 is a pixel plan view of the solid-state image sensor of the present embodiment for 3 rows and 3 columns. The difference from the second embodiment is the position where the gate drive line pOFG and the gate drive line pTX2 are provided.

In FIG. 9, of the wiring distances between the gate drive lines of the pixel transistors, the maximum wiring distance is the wiring distance between the gate drive line pTX1 and the gate drive line pOFG. With such an arrangement, it is possible to reduce not only the parasitic capacitance between the gate drive line pTX1 and the other gate drive lines but also the parasitic capacitance between the gate drive line pOFG and the other gate drive lines.

The accumulation timing in the global electronic shutter is also controlled by the input of the drive pulse to the gate OFG of the overflow transistor 19 as described above. Therefore, by reducing the parasitic capacitance of the gate drive line pOFG of the overflow transistor 19 and reducing the propagation delay, the deviation of the accumulation timing can be reduced.

In the present embodiment, the gate drive line pOFG and the gate drive line pTX2 are not brought close to each other. If they are arranged close to each other, the saturation signal amount of the charge storage unit 3 is reduced, which causes the saturation signal amount of the charge storage unit 3 to be dispersed in the imaging region.

Further, the gate drive line TX2 may be set to a negative potential during the period when the gate drive line TX2 of the second transfer transistor 15 which is an IGMP is off. As a result, holes can be excited in the channel portion, recombination of electrons and holes can occur, and dark current can be suppressed. At this time, if the gate drive line pOFG and the gate drive line pTX2 are capacitively coupled, the potential of the gate drive line TX2 fluctuates in the direction of increasing at the timing when the level of the gate drive line pOFG is changed from the L level to the H level. do. As a result, the suppression of dark current may be insufficient.

Therefore, in the same drive wiring region, the gate drive line pRES of the reset transistor is arranged between the gate drive line pOFG and the gate drive line pTX2. Instead of the gate drive line pRES, the gate drive line pSEL, the power supply line, the ground line, etc. of the row selection transistor may be arranged.

FIG. 14 is a diagram schematically showing the arrangement of the drive wiring shown in FIG.

Here, for the drive wiring of the n-1 line, the n line, and the n + 1 line, the DTX1 _Total is D ₁ + D ₃ + D ₈ + D ₁₀ + D ₁₁ + D ₁₃ . On the other hand, the DRES _Total is D ₁ + D ₂ + D ₉ + D ₁₀ + D ₁₁ + D ₁₂ . The DSEL _Total is D ₄ + D ₅ + D ₆ + D ₇ + D ₁₄ . Further, the DTX2 _Total is D ₂ + D ₄ + D ₇ + D ₉ + D ₁₂ + D ₁₄ .

Since D ₃ , D ₈ and D ₁₃ are, for example, three times or more larger than the spacing between other wires, in the n-1, n, and n + 1 rows, the DTX1 _Total is the DRES _Total , DSEL _Total , and DTX2 _Total . Will be a larger value than.

Further, for the above reason, in FIG. 14, pTX1 and pOFG are not arranged close to each other, pTX2 and pOFG are not arranged close to each other, and pTX1 and pTX2 are arranged close to each other. Not.

Further, the pOFG is arranged so as to be close to the photoelectric conversion unit 1.

In addition, as described above, the wiring distance between pTX1 and pOFG is configured to be the maximum wiring distance among the wiring distances between the gate drive lines of the pixel transistors.

[Embodiment 4]
Embodiment 4 of the present invention will be described with reference to FIGS. 6 to 8 and 10. The parts having the same functions as those in the above embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 10 is a pixel plan view of the solid-state image sensor of the present embodiment for 3 rows and 3 columns. The difference from the second and third embodiments is that the wiring width of the gate drive line pOFG and the wiring width of the gate drive line pTX1 are wider than the wiring width of the other drive lines. In addition, the location of each drive wiring is also changed as appropriate.

The propagation delay of each drive pulse transmitted through the conductor is expressed by the product of the parasitic capacitance and the electrical resistance of the conductor. Therefore, by reducing the electrical resistance, the same effect as reducing the parasitic capacitance can be obtained. That is, by widening the wiring width of the gate drive line pOFG and the wiring width of the gate drive line pTX1, the propagation delay can be reduced and the deviation of the accumulation timing can be reduced.

In the present embodiment, the wiring widths of the gate drive line pOFG and the gate drive line pTX1 are both widened, but only one of them may be widened. Further, one of them may be made wider.

When the wiring width is widened, it is necessary to reduce the width of the wiring opening portion where the drive lines are not arranged, or to maintain the width of the wiring opening portion and shorten the arrangement interval of each drive line. Therefore, it is preferable to take a configuration having a high effect in consideration of the effect of reducing the parasitic capacitance and the effect of reducing the electric resistance.

1 Photoelectric conversion unit 3 Charge storage unit 6 Floating diffusion 9 Embedded layer 14 First transfer transistor 15 Second transfer transistor 16 Reset transistor 17 Source follower transistor 18 Row selection transistor 19 Overflow transistor

Claims (19)

It is a photoelectric conversion device
Each pixel row composed of a plurality of pixels arranged along the second direction has a plurality of pixel arrays arranged in a first direction orthogonal to the second direction.
The pixel is
Photoconverter and
A first transfer transistor that transfers the charge of the photoelectric conversion unit to the charge storage unit, and
A second transfer transistor that transfers the charge of the charge storage unit to the FD,
A reset transistor for resetting the potential of the FD is provided.
The photoelectric conversion device is
A plurality of first gate drive lines for driving the first transfer transistor arranged so as to extend in the second direction.
A plurality of second gate drive lines for driving the second transfer transistor arranged so as to extend in the second direction.
It has a plurality of third gate drive lines for driving the reset transistor, which are arranged so as to extend in the second direction.
The first from the position where the first gate drive line provided corresponding to the first pixel row and the first transfer transistor of the first pixel of the first pixel row are connected. The first transfer transistor of the first gate drive line provided corresponding to the pixel row and the first transfer transistor of the second pixel arranged adjacent to the first pixel in the second direction. In the section up to the point where and is connected, the widest portion of the wiring width in the first direction of the first gate drive line corresponding to the first pixel row is
It is provided corresponding to the first pixel row from the position where the third gate drive line provided corresponding to the first pixel row and the reset transistor of the first pixel are connected. The third gate drive line corresponding to the first pixel row within the section up to the point where the third gate drive line and the reset transistor of the second pixel are connected. A photoelectric conversion device characterized in that it is wider than the widest portion of the wiring width in the first direction. The pixels are an overflow transistor that discharges the electric charge of the photoelectric conversion unit, and
It has a fourth gate drive line that drives the overflow transistor, which is arranged so as to extend in the second direction.
The first pixel from a position where the fourth gate drive line provided corresponding to the first pixel row and the overflow transistor of the first pixel of the first pixel row are connected. The first pixel row corresponding to the first pixel row in the section up to the point where the fourth gate drive line provided corresponding to the row and the overflow transistor of the second pixel are connected. The widest portion of the wiring width of the gate drive line 4 in the first direction is
It is provided corresponding to the first pixel row from the position where the third gate drive line provided corresponding to the first pixel row and the reset transistor of the first pixel are connected. The third gate drive line corresponding to the first pixel row within the section up to the point where the third gate drive line and the reset transistor of the second pixel are connected. The photoelectric conversion device according to claim 1, wherein the wiring width in the first direction is wider than the widest portion. It has a source follower transistor electrically connected to the FD of at least one pixel in the first pixel row.
The wiring connecting the FD and the gate of the source follower transistor extends in the first direction.
Corresponding to the first pixel row from the position where the first gate drive line provided corresponding to the first pixel row and the first transfer transistor of the first pixel are connected. The first pixel row corresponding to the first pixel row in the section up to the point where the first gate drive line and the first transfer transistor of the second pixel are connected to each other. The widest part of the wiring width of the gate drive line in the first direction is
The photoelectric conversion device according to claim 1 , wherein the wiring width is wider than the widest portion of the wiring width in the second direction. The pixels are an overflow transistor that discharges the electric charge of the photoelectric conversion unit, and
It has a fourth gate drive line that drives the overflow transistor, which is arranged so as to extend in the second direction.
It is provided corresponding to the first pixel row from the position where the fourth gate drive line provided corresponding to the first pixel row and the overflow transistor of the first pixel are connected. The fourth gate drive line corresponding to the first pixel row within the section up to the point where the fourth gate drive line and the overflow transistor of the second pixel are connected. The widest part of the wiring width in the first direction is
The photoelectric conversion device according to claim 3 , wherein the wiring width is wider than the widest portion of the wiring width in the second direction. It has a second pixel row adjacent to the first pixel row and has a second pixel row.
In a plan view, the second gate drive line corresponding to the first pixel row has a plurality of the second gate drive lines having more than the first gate drive line corresponding to the first pixel row. The photoelectric conversion device according to any one of claims 1 to 4, wherein the photoelectric conversion unit is provided near the photoelectric conversion unit. It has a second pixel row adjacent to the first pixel row and has a second pixel row.
The third gate drive line is provided between the plurality of photoelectric conversion units of the first pixel row and the plurality of photoelectric conversion units of the second pixel row in a plan view. The photoelectric conversion device according to any one of claims 1 to 4 , which is characterized. The pixels are an overflow transistor that discharges the electric charge of the photoelectric conversion unit, and
It has a fourth gate drive line that drives the overflow transistor, which is arranged so as to extend in the second direction.
The second pixel row adjacent to the first pixel row and
It has a third pixel row adjacent to the first pixel row and not adjacent to the second pixel row.
In a plan view, the first gate drive line corresponding to the first pixel row and the second gate drive line corresponding to the first pixel row have a plurality of the first pixel row. It is provided between the photoelectric conversion unit and the plurality of photoelectric conversion units of the second pixel row.
The fourth gate drive line corresponding to the first pixel row is between the plurality of photoelectric conversion units of the first pixel row and the plurality of photoelectric conversion units of the third pixel row. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion device is provided in the above. The pixels are an overflow transistor that discharges the electric charge of the photoelectric conversion unit, and
It has a fourth gate drive line that drives the overflow transistor, which is arranged so as to extend in the second direction.
The second pixel row adjacent to the first pixel row and
It has a second pixel row and a third pixel row adjacent to it.
In a plan view, the first pixel row corresponding to the first pixel row between the plurality of photoelectric conversion units of the first pixel row and the plurality of photoelectric conversion units of the second pixel row. A gate drive line and the second gate drive line corresponding to the first pixel row are provided.
In a plan view, the first pixel row corresponding to the second pixel row is located between the plurality of photoelectric conversion units of the second pixel row and the plurality of photoelectric conversion units of the third pixel row. The photoelectric conversion device according to claim 1, wherein the gate drive line and the second gate drive line corresponding to the second pixel row are provided. Each of the plurality of pixels of the first pixel row has a row selection transistor, and the fifth gate drive line provided corresponding to the first pixel row is the second gate drive line in a plan view. The fifth gate drive line extends in the direction of the above and drives the row selection transistor possessed by the plurality of pixels, and the fifth gate drive line is a plurality of photoelectric conversions possessed by the first pixel row in a plan view. The photoelectric conversion device according to claim 7 , wherein the unit is provided between the unit and a plurality of photoelectric conversion units included in the second pixel row. The plurality of pixel rows have a fourth pixel row adjacent to the second pixel row and not adjacent to the third pixel row.
In a plan view, the first gate drive line and the second gate drive line corresponding to the second pixel row have a plurality of photoelectric conversion units of the second pixel row and the fourth pixel row. The photoelectric conversion device according to any one of claims 7 to 9 , wherein the photoelectric conversion device is provided between the plurality of photoelectric conversion units. The first gate drive line corresponding to the first pixel row overlaps with at least a part of the charge storage portion of the plurality of pixels constituting the first pixel row in a plan view. The photoelectric conversion device according to any one of claims 1 to 10 . The fifth aspect of claim 9 , wherein the fifth gate drive line overlaps with at least a part of the charge storage portion of the plurality of pixels constituting the first pixel row in a plan view. Photoconverter . It is provided corresponding to the first pixel row from the position where the fourth gate drive line provided corresponding to the first pixel row and the overflow transistor of the first pixel are connected. The fourth gate drive line corresponding to the first pixel row in the section up to the point where the fourth gate drive line and the overflow transistor of the second pixel are connected. The widest part of the wiring width in the first direction is
It is provided corresponding to the first pixel row from the position where the third gate drive line provided corresponding to the first pixel row and the reset transistor of the first pixel are connected. The third gate drive line corresponding to the first pixel row within the section up to the point where the third gate drive line and the reset transistor of the second pixel are connected. The photoelectric conversion device according to claim 7 , wherein the wiring width in the first direction is wider than the widest portion. It has a source follower transistor electrically connected to the FD of at least one pixel in the first pixel row.
The wiring connecting the FD and the gate of the source follower transistor extends in the first direction.
Corresponding to the first pixel row from the position where the first gate drive line provided corresponding to the first pixel row and the first transfer transistor of the first pixel are connected. The first pixel row corresponding to the first pixel row in the section up to the point where the first gate drive line and the first transfer transistor of the second pixel are connected to each other. The widest part of the wiring width of the gate drive line in the first direction is
The photoelectric conversion device according to claim 7 , wherein the wiring width is wider than the widest portion of the wiring width in the second direction. It is provided corresponding to the first pixel row from the position where the fourth gate drive line provided corresponding to the first pixel row and the overflow transistor of the first pixel are connected. The fourth gate drive line corresponding to the first pixel row in the section up to the point where the fourth gate drive line and the overflow transistor of the second pixel are connected. The widest part of the wiring width in the first direction is
The photoelectric conversion device according to claim 14 , wherein the wiring width is wider than the widest portion of the wiring width in the second direction. In a plan view, the fourth pixel row corresponding to the first pixel row between the plurality of photoelectric conversion units of the first pixel row and the plurality of photoelectric conversion units of the second pixel row. The photoelectric conversion device according to claim 7 or 8 , wherein the gate drive line is not provided. In a plan view, the second gate drive line corresponding to the first pixel row has a plurality of the second gate drive lines having more than the first gate drive line corresponding to the first pixel row. The photoelectric conversion device according to claim 7 , wherein the photoelectric conversion device is provided near the photoelectric conversion unit of the above. The third gate drive line is provided between the plurality of photoelectric conversion units of the first pixel row and the plurality of photoelectric conversion units of the second pixel row in a plan view. The photoelectric conversion device according to claim 7 or 8 . The first gate drive line corresponding to the first pixel row overlaps with at least a part of the plurality of charge storage portions of the first pixel row in a plan view. 7. The photoelectric conversion device according to 7.

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