JP7029640B2 - Method of processing plate materials and method of manufacturing element chips - Google Patents

Description

The present invention relates to a method for processing a plate material and a method for manufacturing an element chip.

A method called plasma dicing is known in which a single substrate (plate material) is individually processed into a plurality of element chips. In plasma dicing, a substrate having a plurality of element regions defined by a divided region is plasma-etched from one surface of the substrate to the other surface, so that the substrate is individually formed into each element chip. Is made. In such plasma dicing, only the divided region is plasma-etched, and the device region needs to be protected from plasma etching. Therefore, before plasma etching, a resist mask is formed in the element region of the substrate, and the divided region is exposed. The resist mask is removed by ashing or the like after plasma dicing.

For example, Patent Document 1 discloses a method for manufacturing an element chip using such plasma dicing.

Japanese Patent No. 5023614

Element chips that are fragmented by plasma dicing generally have sharp angles. Sharp corners cause chipping.

An object of the present invention is to round the corners of a plate material or a substrate processed by plasma etching in a method for processing a plate material and a method for manufacturing an element chip to prevent defects such as chipping.

A first aspect of the present invention is a resist mask including a lower layer portion having a first end surface formed of an upwardly convex curved surface and an upper layer portion having a second end surface continuously extending upward from the first end surface. Is formed on the surface of the plate material so as to cover the first region and expose the second region, and by exposing the resist mask and the plate material to plasma, the upper layer portion remains and the lower layer portion is said. Provided is a method for processing a plate material, which comprises etching the resist mask so as to at least partially eliminate the first end face, and etching the second region of the plate material.

According to this method, since the resist mask is formed on the surface of the plate material and plasma-etched so as to cover the first region and expose the second region, only the second region can be etched. At this time, the resist mask is also etched together with the second region, but by etching so that the first end surface of the lower layer portion of the resist mask is at least partially erased, the curved surface shape of the first end surface becomes the first region of the plate material. Transferred to the edge of. Further, since the upper layer portion is etched so as to remain, the region other than the edge portion of the first region is not etched and is protected from the plasma. Therefore, the second region can be plasma-etched while protecting the first region of the plate material, and the corners of the plate material processed by plasma etching can be rounded to prevent defects such as chipping.

The lower layer portion includes a round portion having the first end surface formed of an upwardly convex curved surface and a non-round portion having a third end surface formed of a flat surface continuously extending downward from the first end surface. Have and
The etching amount of the resist mask may be greater than or equal to the thickness of the non-round portion and less than or equal to the total thickness of the non-round portion and the round portion.

According to this method, the lower layer portion has a round portion and a non-round portion, and the etching amount is defined to be equal to or larger than the thickness of the non-round portion, so that the curved surface shape of the first end surface is surely obtained in the first region of the plate material. Can be transferred to the edge. Specifically, when etching is started, the second region is first etched and the thickness of the non-round portion gradually decreases. At this time, the shape of the round portion is generally maintained. Therefore, when the resist mask is etched to the thickness of the non-round portion or more, the non-round portion disappears completely. Next, when further etching is performed, the thickness of the round portion gradually decreases. At this time, with the etching of the round portion, the curved surface shape of the first end surface of the round portion is transferred to the edge portion of the first region of the plate material. If the round portion disappears completely after further etching, the thickness of the upper layer portion is then reduced. However, in the above method, the etching amount is specified to be equal to or less than the total thickness of the non-round portion and the round portion. Therefore, it is possible to suppress the decrease in the thickness of the upper layer portion. Therefore, the first region of the plate material can be protected.

The resist mask may be formed by forming a resin layer on the surface of the plate material and pressing the resin layer with a mold.

According to this method, a resist mask having a specific shape can be easily formed by the so-called nanoimprint method.

A second aspect of the present invention is a method for manufacturing an element chip, wherein the plate material is a substrate, and the substrate is individualized by the method according to any one of claims 1 to 3 to manufacture an element chip. offer.

According to this method, since the above-mentioned method is used when the substrate is separated into individual pieces by plasma dicing to manufacture the element chip, the corners of the element chip can be rounded. Therefore, chipping of the element chip can be prevented.

According to the present invention, by optimizing the shape of the resist mask in the plate material processing method and the element chip manufacturing method, the corners of the plate material processed by plasma etching can be rounded and defects such as chipping can be prevented.

The cross-sectional view which shows the middle of the mask forming process of the plate material processing method which concerns on 1st Embodiment. The cross-sectional view which shows after the mask forming process of the plate material processing method which concerns on 1st Embodiment. The cross-sectional view which shows the middle of the etching process of the processing method of the plate material which concerns on 1st Embodiment. The cross-sectional view which shows after the etching process of the processing method of the plate material which concerns on 1st Embodiment. The cross-sectional view which shows after the ashing process of the processing method of the plate material which concerns on 1st Embodiment. Schematic diagram of a plasma etching apparatus. The cross-sectional view which shows the middle of the etching process of the processing method of the plate material which concerns on 2nd Embodiment. The cross-sectional view which shows the middle of the etching process of the processing method of the plate material which concerns on 2nd Embodiment. The cross-sectional view which shows after the etching process of the processing method of the plate material which concerns on 2nd Embodiment. The cross-sectional view which shows after the etching process of the modification of the processing method of a plate material. The cross-sectional view which shows after the etching process of the other modification of the processing method of a plate material.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The dimensions of each part in the attached drawings are shown schematically and may differ from the actual ones.

(First Embodiment)
1A to 1E show a part of the substrate 1 to which the plate material processing method according to the first embodiment of the present invention is applied. In the present embodiment, a plurality of element chips 1a (see FIG. 1E) are manufactured by individualizing the substrate 1 as a plate material. That is, the method for processing a plate material according to this embodiment is also a method for manufacturing an element chip.

1A and 1B show a mask forming step. In the mask forming step, a resist mask 10 having a specific shape is formed on the surface of the substrate 1.

The substrate 1 is also referred to as a semiconductor wafer and is made of, for example, a Si material. The substrate 1 has an element region (first region) 2 in which electrodes (not shown) and the like are arranged, and a divided region (second region) 3 adjacent to the periphery of each element region 2. In a plan view, a plurality of rectangular element regions 2 are partitioned by linear divided regions 3 arranged in a mesh pattern. For example, referring to FIG. 1B, the width W1 of the element region 2 is 100 to 7000 μm, and the width W2 of the divided region 3 is 5 to 60 μm. However, the shapes of the element region 2 and the divided region 3 are not particularly limited.

First, referring to FIG. 1A, in the mask forming step, a flat resin layer 11 is formed on the surface of the substrate 1. The resin layer 11 is made of, for example, an acrylic resin material having UV curability. Next, referring to FIG. 1B, the resin layer 11 is pressed with the mold 20 to form the resist mask 10 having a specific shape. After forming into a specific shape, the resist mask 10 is cured by irradiating with UV light to maintain the specific shape. That is, in the mask forming step, the resist mask 10 having a specific shape is formed by the so-called nanoimprint method.

The resist mask 10 having a specific shape has a lower layer portion 12 having a first end surface 13a formed of an upwardly convex curved surface, and an upper layer portion 15 having a flat second end surface 15a extending continuously upward from the first end surface 13a. And. Specifically, the lower layer portion 12 has a round portion 13 having a first end surface 13a formed of an upwardly convex curved surface, and a flat third end surface 14a extending downward continuously from the first end surface 13a. It consists of a round portion 14. The resist mask 10 is formed on the surface of the substrate 1 so as to cover the element region 2 and expose the divided region 3.

The mold 20 has convex portions 21 provided at intervals corresponding to the divided region 3. The side surface of the convex portion 21 is a curved surface, and the curved surface matches the shape of the curved surface of the round portion 13 of the resist mask 10. The tip surface of the convex portion 21 is a flat surface, and when the mold 20 is pressed against the resist mask 10, it comes into contact with the substrate 1.

FIGS. 1C and 1D show an etching process performed after the mask forming process. In detail, FIG. 1C shows the middle of the etching process, and FIG. 1D shows after the etching process. In the etching step, the substrate 1 is separated into pieces by plasma etching (plasma dicing).

FIG. 2 shows an example of the plasma etching apparatus 50 used in the etching process. A dielectric window is provided at the top of the chamber 52 of the plasma etching apparatus 50, and an antenna 54 as an upper electrode is arranged above the dielectric window. The antenna 54 is electrically connected to the first high frequency power supply unit 56. On the other hand, on the bottom side of the processing chamber 58 in the chamber 52, a stage 60 on which the substrate 1 is placed is provided. The stage 60 also functions as a lower electrode and is electrically connected to the second high frequency power supply unit 62. Further, the stage 60 is provided with an electrostatic adsorption electrode (ESC electrode) (not shown) so that the substrate 1 mounted on the stage 60 can be electrostatically adsorbed on the stage 60. Instead of this, a vacuum suction mechanism may be adopted to vacuum suction the substrate 1 mounted on the stage 60 to the stage 60. Further, the stage 60 is provided with a cooling gas hole (not shown) for supplying the cooling gas, and by supplying the cooling gas such as helium from the cooling gas hole, the stage 60 is electrostatically adsorbed. The substrate 1 can be cooled. The gas inlet 64 of the chamber 52 is fluidly connected to the etching gas source 66, and the exhaust port 68 is connected to a vacuum exhaust section 70 including a vacuum pump for evacuating the inside of the chamber 52.

In the etching process, the substrate 1 is placed on the stage 60, the inside of the processing chamber 58 is evacuated by the vacuum exhaust unit 70, and the processing is performed from the etching gas source 66, with reference to FIGS. 1C, 1D, and 2 together. Etching gas is supplied into the chamber 58. Then, the inside of the processing chamber 58 is maintained at a predetermined pressure, high-frequency power is supplied to the antenna 54 from the first high-frequency power supply unit 56, plasma is generated in the processing chamber 58, and the substrate 1 and the resist mask 10 are irradiated. .. At this time, the divided region 3 of the substrate 1 is gradually etched from the upper surface by the physicochemical action of radicals and ions in the plasma, and a groove 3a is formed in the divided region 3 (see FIG. 1C). At this time, the resist mask 10 is also slightly etched at the same time. Therefore, when FIG. 1B and FIG. 1C are compared, it can be seen that the thickness of the resist mask 10 is reduced and the corner portion 15b of the upper layer portion 15 is rounded, so-called shoulder drop occurs. Then, by further etching, the substrate 1 is fragmented and the element chip 1a is formed (see FIG. 1D).

Specifically, in the etching step of the present embodiment, the substrate 1 is divided into individual element chips 1a by plasma treatment called cycle etching in which the deposition step, the first etching step, and the second etching step are sequentially repeated.

The conditions for cycle etching are the amount of etching gas supplied to the processing chamber 58, the pressure in the processing chamber 58, the power input from the first high frequency power supply unit 56 to the antenna 54, and the power input from the second high frequency power supply unit 62 to the stage 60. It is defined by the input power and the time of each step. The conditions are illustrated below.

In the deposition step, for example, while supplying a gas containing CH ₂ F ₂ as an etching gas into the processing chamber 58 at 400 sccm, the pressure in the processing chamber 58 is adjusted to 10 Pa, and the pressure in the processing chamber 58 is adjusted from the first high frequency power supply unit 56 to the antenna 54. The processing for 2 seconds is performed under the condition that the input power of the second high frequency power supply unit 62 is 4800 W and the input power from the second high frequency power supply unit 62 to the stage 60 is 30 W.

In the first etching step, for example, while supplying a gas containing SF ₆ as an etching gas at 700 sccm, the pressure in the processing chamber 58 is adjusted to 15 Pa, and the power input from the first high frequency power supply unit 56 to the antenna 54 is 4800 W. Therefore, the processing for 4 seconds is performed under the condition that the input power from the second high frequency power supply unit 62 to the stage 60 is 250 W.

In the second etching step, for example, while supplying a gas containing SF ₆ as an etching gas at 700 sccm, the pressure in the processing chamber 58 is adjusted to 15 Pa, and the power input from the first high frequency power supply unit 56 to the antenna 54 is 4800 W. As a result, the processing for 6 seconds is performed under the condition that the input power from the second high frequency power supply unit 62 to the stage 60 is 30 W.

Actually, when switching between the deposition step and the first etching step and the second etching step, detailed condition changes such as providing a transition step between each step are involved, but detailed description here is omitted. ..

Under the above conditions, the substrate 1 is etched perpendicularly to the thickness direction in the divided region 3 by cycle etching in which the deposition step, the first etching step, and the second etching step are repeated a plurality of times, and the substrate 1 is divided into individual element chips 1a. Will be done. At this time, the resist mask 10 is also etched at the same time, and as shown in FIG. 1D, when the etching step is completed, the lower layer portion 12 is completely disappeared in the present embodiment. The upper layer portion 15 remains as it is.

With reference to FIGS. 1C and 1D, particularly when the round portion 13 of the lower layer portion 12 is etched and disappears, the first end surface 13a of the round portion 13 has a curved surface shape, so that the edge portion of the element region 2 of the substrate 1 is formed. 2a is also etched into a curved surface. As a result, when the substrate 1 is fragmented into the element chip 1a, the corners 2a of the element chip 1a can be formed round, so that chipping (chips) and the like can be prevented.

In order to etch the edge portion 2a of the element region 2 of the substrate 1 into a curved surface as described above, the non-round portion 14 of the lower layer portion 12 of the resist mask 10 is etched until it completely disappears, and the round portion 13 is at least It needs to be partially eliminated. Further, in order to protect the element region 2, the upper layer portion 15 of the resist mask 10 needs to remain. Further, it is necessary to secure the etching amount of the resist mask 10 and also secure the etching amount of the substrate 1 in order to separate the substrate 1 into individual pieces. In other words, by exposing the resist mask 10 and the substrate 1 to plasma, the resist mask 10 is etched so as to leave the upper layer portion 15 and at least partially eliminate the first end surface 13a of the lower layer portion 12, and also to etch the substrate. It is necessary to etch the divided region 3 of 1. Preferably, the etching amount of the resist mask 10 is equal to or greater than the thickness of the non-round portion 14 and equal to or less than the total thickness of the non-round portion 14 and the round portion 13. Hereinafter, the conditions for preferably performing such etching will be described.

The ratio indicating the etching amount of the substrate 1 to the etching amount of the resist mask 10 is defined as the selection ratio R. The selection ratio R includes the type of etching gas, the pressure in the processing chamber 58, the power input from the first high frequency power supply unit 56 to the antenna 54, the power input from the second high frequency power supply unit 62 to the stage 60, and the substrate 1. It varies depending on various conditions such as the material of the resist mask 10.

In the present embodiment, when etching is performed under the above cycle etching conditions, the Si processing speed is 6.8 μm / min, the resist processing speed is 0.12 μm / min, and the SiO ₂ processing speed is 0.05 μm / min. The performance that Si can be processed almost vertically was obtained. From this experimental result, the selection ratio R, which is the ratio between the Si processing speed and the resist processing speed, is about 56.7. From the selection ratio R, the thickness of each part of the resist mask 10 is calculated as follows.

Assuming that the thickness T of the substrate 1 and the thickness t3 of the non-round portion 14 of the lower layer portion 12 of the resist mask 10 are also referred to with reference to FIG. 1B, these relationships are expressed by the following equation (1).

The thickness of the non-round portion 14 required for completely etching the substrate 1 can be obtained from the term of the thickness T / selection ratio R of the substrate. However, in reality, it is conceivable that the etching amount may vary slightly depending on various conditions, so a margin value Δ is provided. The margin value Δ is for completely etching the substrate 1, and is, for example, a constant of about 0 to 2 μm.

The thickness t1 of the upper layer portion 15 of the resist mask 10 may be 1 μm or more in consideration of the above-mentioned shoulder drop. Further, the thickness t2 of the round portion 13 is a value arbitrarily set according to the transfer shape. For example, the radius of the round portion 13 may be about 3 μm. Alternatively, the thickness t2 of the round portion 13 may be set based on the selection ratio R. Specifically, the thickness may be 1/R of the selection ratio R with respect to the shape to be transferred so that the curved surface shape of the round portion 13 is accurately transferred to the substrate 1. For example, if the selection ratio R = 10, the thickness is 1/10 of the shape to be transferred. As a result, the shape to be transferred can be accurately transferred to the substrate 1. Alternatively, at the time of transfer, the etching conditions may be switched to lower the selection ratio R, and preferably the etching conditions may be switched to a selection ratio R = 1. As a result, the curved surface shape of the round portion 13 can be transferred to the substrate 1 as it is.

Etching conditions near R = 1 include, for example, SF ₆ flow rate of 100 sccm, O ₂ flow rate of 100 sccm, pressure of 5.0 Pa, power input from the first high frequency power supply unit 56 to the antenna 54 of 2500 W, and a second high frequency. The condition that the input power from the power supply unit 62 to the stage 60 is 200 W can be exemplified. Under these conditions, the Si processing speed is 1.8 μm / min, the resist processing speed is 1.2 μm / min, the SiO2 processing speed is 0.2 μm / min, and the selection ratio R is 1.5. Further, the selection ratio R can be adjusted in the range of about 0.8 to 1.5 by adjusting the gas ratio of SF ₆ and O ₂ and the input power to the antenna 54 and the input power to the stage 60.

To give specific examples of each numerical value, the selection ratio R = 56.7 is set under the above cycle etching conditions, the thickness t2 of the round portion 13 is set to 3 μm, and the margin value is set to Δ = 2 μm. Further, the thickness T of the substrate 1 is set to 100 μm. At this time, when the thickness t3 of the non-round portion 14 is obtained based on the above equation (1), t3 = 3.8 μm. When the thickness t1 of the upper layer portion 15 is set to 2 μm, the thickness t of the resist mask 10 is 8.8 μm (= t1 + t2 + t3).

In the present embodiment, by defining the dimensional relationship of each part in detail in this way, when the etching amount of the substrate 1 is the thickness T of the substrate 1, the etching amount of the resist mask 10 is the thickness t3 of the non-round portion 14. And the total thickness t2 + t3 of the thickness t2 of the round portion 13 is set. Therefore, when the divided region 3 of the substrate 1 is completely etched to separate the substrate 1, the curved surface shape of the round portion 13 is transferred to the element chip 1a, and the element region 2 of the substrate 1 is protected. ..

Further, the etching amount of the resist mask 10 does not necessarily have to be the total thickness t2 + t3 of the non-round portion 14 and the round portion 13. That is, the etching amount of the resist mask 10 may be such that the thickness of the non-round portion 14 is t3 or more and the total thickness of the non-round portion 14 and the round portion 13 is t2 + t3 or less. As a result, the resist mask 10 can be etched so that the first end surface 13a of the lower layer portion 12 disappears at least partially while the upper layer portion 15 remains, and the curved surface shape of the round portion 13 can be transferred to the element chip 1a.

When the shape of the round portion 13 is transferred to the substrate by plasma treatment, if cycle etching is used as the etching condition, a hangnail-like (columnar, needle-like) shape abnormality may occur on the processed side surface. In this case, it is desirable that at least the plasma treatment for transferring the shape of the round portion 13 to the substrate is performed by continuous etching. For example, the plasma treatment until the non-round portion 14 disappears may be performed by cycle etching, and then the plasma treatment condition may be switched to continuous etching to transfer the shape of the round portion 13 to the substrate 1.

FIG. 1E shows an ashing step executed after the plasma dicing is completed. More specifically, FIG. 1E shows after the ashing process is completed. In the ashing step, while introducing a process gas for ashing (for example, oxygen gas) into the processing chamber 58, the inside of the processing chamber 58 is maintained at a predetermined pressure. After that, high-frequency power is supplied from the first high-frequency power supply unit 56 to the antenna 54 to generate plasma in the processing chamber 58 to irradiate each element chip 1a. The resist mask 10 is removed from the surface of each element chip 1a by irradiation with plasma.

As described above, the element chip 1a can be manufactured by separating the substrate 1 into individual pieces. In particular, according to this embodiment, there are the following merits.

In the mask forming step, the resist mask 10 is formed on the surface of the substrate 1 so as to cover the element region 2 and expose the divided region 3. After that, since the substrate 1 is plasma-etched in the etching step, only the divided region 3 can be etched. At this time, the resist mask 10 is also etched together with the divided region 3, but the curved surface shape of the first end surface 13a is formed by etching so that the first end surface 13a of the lower layer portion 12 of the resist mask 10 is at least partially erased. It is transferred to the edge 2a of the element region 2 of the substrate 1. Further, since the upper layer portion 15 is etched so as to remain, the region other than the edge portion 2a of the element region 2 is not etched and is protected from the plasma. Therefore, the divided region 3 can be plasma-etched while protecting the element region 2 of the substrate 1, and the corners of the substrate 1 processed by plasma etching can be rounded to prevent defects such as chipping.

In the mask forming step, the lower layer portion 12 has the round portion 13 and the non-round portion 14, and the etching amount is defined to be the thickness t3 or more of the non-round portion 14, so that the curved surface shape of the first end surface 13a is surely formed on the substrate. It can be transferred to the edge portion 2a of the element region 2 of 1. Specifically, when the etching is started, the divided region 3 is first etched and the thickness t3 of the non-round portion 14 gradually decreases. At this time, the shape of the round portion 13 is generally maintained. Therefore, when the resist mask 10 is etched with the thickness t3 or more of the non-round portion 14, the non-round portion 14 disappears completely. Next, when further etching is performed, the thickness t2 of the round portion 13 gradually decreases. At this time, with the etching of the round portion 13, the curved surface shape of the first end surface 13a of the round portion 13 is transferred to the edge portion 2a of the element region 2 of the substrate 1. If the round portion 13 disappears completely after further etching, then the thickness t1 of the upper layer portion 15 decreases. However, in the method of the present embodiment, the etching amount is the total of the non-round portion 14 and the round portion 13. Since the thickness t2 + t3 or less is specified, it is possible to suppress the decrease in the thickness t1 of the upper layer portion 15. Therefore, the element region 2 of the substrate 1 can be protected.

Since the so-called nanoimprint method is used in the mask forming step, the resist mask 10 having a specific shape can be easily formed.

(Second Embodiment)
The method of processing the plate material according to the second embodiment will be described with reference to FIGS. 3A to 3C. The method of this embodiment is substantially the same as that of the first embodiment except for the etching step. Therefore, the description other than the etching process will be omitted.

In the etching step of the present embodiment, since the substrate 1 is individualized into a plurality of element chips 1a, the substrate 1 is not completely etched. That is, as shown in FIG. 3B, the substrate 1 is etched to a predetermined depth T1 to form a groove 3a in the divided region 3. After that, grinding is performed from the back surface side of the substrate 1 to the position of the depth T1 to separate the substrate 1 into individual pieces.

The thickness t3 of the non-round portion 14 of the resist mask 10 in the present embodiment can be obtained only by replacing the thickness T of the substrate 1 with a predetermined depth T1 in the formula (1) of the first embodiment. However, in the present embodiment, since it is not necessary to completely etch the substrate 1, the margin value Δ can be omitted in the above equation (1). That is, the thickness t3 of the non-round portion 14 of the resist mask 10 is calculated by the following equation (2). The other thicknesses t1 and t2 of the resist mask 10 are the same as those in the first embodiment.

As described above, when the substrate 1 is individualized, it is not necessary to individualize the substrate 1 only by etching, and the substrate 1 may be individualized by combining etching and grinding.

(Modification example)
With reference to FIG. 4A, in the first embodiment and the second embodiment described above, an example in which the substrate 1 is made of a Si material is shown, but the substrate 1 may include a plurality of layers. In this modification, the substrate 1 includes a semiconductor layer 4 and a wiring layer 5 formed on the semiconductor layer 4. The semiconductor layer 4 is made of, for example, a Si material. The wiring layer 5 is made of, for example, SiN, SiO ₂ , Low-k (low dielectric constant) material, or the like.

This modification is the same as that of the first embodiment except that the substrate 1 includes two layers, a semiconductor layer 4 and a wiring layer 5. In this modification, the resist mask 10 is formed on the surface of the wiring layer 5, and the substrate 1 is etched from the wiring layer 5 side.

When processing from the wiring layer 5 side, first, the wiring layer 5 is etched under the following conditions (first wiring layer etching step). Taking the case where the wiring layer 5 is SiO ₂ , the processing conditions for the wiring layer 5 are _C4 F ₈ flow rate of 10 sccm, Ar flow rate of 300 sccm, pressure of 1.0 Pa, and the first high frequency power supply unit 56. The condition that the input power to the antenna 54 is 1200 W and the input power from the second high frequency power supply unit 62 to the stage 60 is 300 W can be exemplified. The processing performance at this time is a ratio of the SiO 2 processing speed to the resist processing speed, with the Si processing speed being 0.05 μm / min, the resist processing speed being 0.21 μm / min, and the SiO ₂ processing speed being 0.39 μm / min. , SiO ₂ : The mask selection ratio is 1.86. When processed under these conditions, the wiring layer 5 (SiO ₂ ) can be processed substantially vertically.

Next, the semiconductor layer 4 (Si) is vertically processed by the above-mentioned cycle etching (semiconductor layer etching step). In this case, since the Si: mask selection ratio is 56.7 and the Si: SiO2 selection ratio is 136, Si can be processed vertically without retreating both the resist mask 10 and the wiring layer 5 (SiO ₂ ). ..

Next, in order to transfer the shape of the round portion of the resist mask 10 to the wiring layer 5 (SiO ₂ ) portion, the wiring layer 5 (SiO ₂ ) is etched again (second wiring layer etching step). In order to transfer the round portion to 1: 1 it is desirable to lower the resist selection ratio than the conditions used in the first wiring layer etching step. CF ₄ is added as an additive gas by 10 to 40 sccm to the conditions used in the first wiring layer etching step described above, and the power input from the second high frequency power supply unit 62 to the stage 60 is reduced to about 100 to 250 W. The SiO ₂ processing speed can be adjusted to 0.2 to 0.3 μm / min, and the SiO ₂ : resist selection ratio can be adjusted to about 0.9 to 1.3, and the shape of the round portion of the resist mask 10 can be accurately transferred. be able to.

The ratio indicating the etching amount of the wiring layer 5 (for example, SiO2) to the etching amount of the resist mask 10 in the first wiring layer etching step is set as the selection ratio R1, and the substrate 1 with respect to the etching amount of the resist mask 10 in the semiconductor layer etching step. The ratio indicating the etching amount of the semiconductor layer 4 (for example, Si material) is defined as the selection ratio R2.

The thickness of the resist mask 10 is calculated using the selection ratios R1 and R2. Assuming that the thickness of the wiring layer 5 is T2 and the thickness of the semiconductor layer 4 is T3, the thickness of the resist mask 10 is expressed by the following equation (3). The thickness t2 of the round portion 13 of the resist mask 10 and the thickness t1 of the upper layer portion 15 may be the same as those of the first embodiment.

Further, referring to FIG. 4B, the resist mask 10 may be formed on the surface of the semiconductor layer 4, or the substrate 1 may be etched from the semiconductor layer 4 side. In this case, first, the semiconductor layer 4 in the divided region 3 is etched by cycle etching or the like until it reaches the wiring layer 5, and then the wiring layer 5 is attached to the back surface of the substrate 1 using the conditions of the first wiring layer etching step described above. By etching until it reaches, the substrate 1 is divided into individual element chips 1a. As shown in FIG. 4B, the film thickness of the non-round portion of the resist mask 10 is preset so that the non-round portion disappears when the wiring layer 5 is etched. Then, by etching under the etching conditions near R = 1 for transferring the shape of the round portion of the resist mask described in the first embodiment, the semiconductor layer 4 at the corner portion on the upper surface side of the element chip 1a is formed into a curved surface shape. Can be processed into.

Although the specific embodiment of the present invention and the modification thereof have been described above, the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the present invention. For example, an embodiment of the present invention may be obtained by appropriately combining the contents of individual embodiments and modifications.

Further, in the present embodiment, the substrate 1 has been described as an example of the plate material to be processed, but the application target of the present invention is not limited to the substrate. That is, it can be widely applied to so-called MEMS (Micro Electro Mechanical Systems) in which a plate material is three-dimensionally microprocessed.

1 Substrate (element chip)
2 element area (1st area)
2a Edge (corner)
3 division area (second area)
3a Groove 4 Semiconductor layer 5 Wiring layer 10 Resist mask 11 Resin layer 12 Lower layer 13 Round part 13a First end surface 14 Non-round part 14a Third end surface 15 Upper layer part 15a Second end surface 20 type 50 Plasma etching equipment 52 Chamber 54 Antenna 56 1st high frequency power supply 58 Processing room 60 Stage 62 2nd high frequency power supply 64 Gas inlet 66 Etching gas source 68 Exhaust port 70 Vacuum exhaust

Claims (4)

A resist mask including a lower layer portion having a first end surface formed of an upwardly convex curved surface and an upper layer portion having a second end surface continuously extending upward from the first end surface covers the first region. Formed on the surface of the plate so as to expose the second region,
By exposing the resist mask and the plate material to plasma, the resist mask is etched so as to leave the upper layer portion and at least partially eliminate the first end surface of the lower layer portion, and the plate material is the first. A method for processing a plate material, including etching two regions. The lower layer portion includes a round portion having the first end surface formed of an upwardly convex curved surface and a non-round portion having a third end surface formed of a flat surface continuously extending downward from the first end surface. Have and
The method for processing a plate material according to claim 1, wherein the etching amount of the resist mask is equal to or greater than the thickness of the non-round portion and equal to or less than the total thickness of the non-round portion and the round portion. The method for processing a plate material according to claim 1 or 2, wherein the resist mask is formed by forming a resin layer on the surface of the plate material and pressing the resin layer with a mold. The plate material is a substrate and
A method for manufacturing an element chip, which comprises individualizing the substrate by the method according to any one of claims 1 to 3 to manufacture the element chip.

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