JP7032926B2 - Semiconductor device and encryption key control method - Google Patents

Description

The present invention relates to a semiconductor device, particularly a semiconductor device having a data encryption function using an encryption key, and a method for controlling an encryption key.

Currently, scrambled plain text data using a scramble key is stored in memory, and when data processing using the plain text data is performed, the scrambled plain text data is descrambled to restore the original plain text data. A data processing apparatus has been proposed (see, for example, Patent Document 1).

In this data processing device, when scrambling plaintext data, a CPU (central processing unit) scrambles the plaintext data with a scramble circuit. At this time, the scramble circuit reads out the scramble key held in the register and scrambles the plaintext data using this scramble key.

Further, when performing data processing using plaintext data, in this data processing device, the CPU descrambles the plaintext data scrambled as described above by a scramble circuit. At this time, the scramble circuit reads out the scramble key held in the register, and uses the scramble key to descramble the scrambled plaintext data to restore the original plaintext data. The CPU executes predetermined data processing using the plaintext data restored in this way.

Further, in the data processing device, in order to prevent leakage of the scramble key used in the scramble and descramble processing, the scramble key value is changed to another value after the CPU finishes the predetermined data processing as described above. .. That is, a new scramble key whose value of the scramble key held in the above-mentioned register is changed is overwritten in this register.

Japanese Unexamined Patent Publication No. 2010-9217

By the way, a data processing device having a CPU as described above may be equipped with a so-called DMAC (direct memory access controller) that controls data transfer with peripheral circuits without intervening a CPU.

At this time, even when data is transferred by DMAC, encryption (scramble) or decryption (discramble) using a scramble key as an encryption key is performed in order to prevent leakage of plaintext data.

Therefore, while the CPU is executing data processing based on the plaintext data decrypted (declambled) by the encryption key (scramble key), the DMAC may transfer other plaintext data to the peripheral circuit. At this time, it is necessary to read the encryption key (scramble key) from the register in order to restore the other plaintext data described above even at the time of data transfer by DMAC.

Therefore, in such a case, the encryption key (scramble key) having the same value is read from the register twice in succession, and there is a high possibility that the encryption key will be leaked. Therefore, there is a risk that the above-mentioned plaintext data will be leaked by the illegally acquired encryption key.

Therefore, an object of the present invention is to provide a semiconductor device capable of preventing data leakage due to unauthorized access, and a method for controlling an encryption key.

The semiconductor device according to the present invention has an encryption processing unit that encrypts plain text data using an encryption key received via a data bus, and a first read request or a first read request for the generated encryption key by generating the encryption key. The encryption key generation unit sent to the data bus in response to the second read request and the encryption key sent from the encryption key generation unit by supplying the first read request to the encryption key generation unit are used. The first transfer control unit that transfers to the encryption processing unit via the data bus and the encryption key that supplies the second read request to the encryption key generation unit and that is transmitted from the encryption key generation unit are used. The encryption key generation unit includes a second transfer control unit that transfers to the encryption processing unit via a data bus, and the encryption key generation unit is a read request of one of the first read request and the second read request. When received, the value of the encryption key is changed to another value.

Further, the semiconductor device according to the present invention has an encryption processing unit that encrypts plain text data using an encryption key received via a data bus, a generation of the encryption key, and a first reading of the generated encryption key. An encryption key generation unit to be transmitted to the data bus in response to a request or a second read request, and the encryption key to be supplied to the encryption key generation unit and transmitted from the encryption key generation unit. The first transfer control unit that transfers the data to the encryption processing unit via the data bus, and the encryption key that supplies the second read request to the encryption key generation unit and is transmitted from the encryption key generation unit. The encryption key generation unit receives the first read request within the predetermined period at each predetermined period, including a second transfer control unit that transfers the data to the encryption processing unit via the data bus. After that, when the second read request is received, an error response is sent to the data bus in place of the encryption key in response to the second read request.

Further, the method for controlling an encryption key according to the present invention is a method for controlling an encryption key performed by an encryption key generator that generates the encryption key when encrypting plain text data using an encryption key received via a data bus. The generated encryption key is sent to the data bus in response to the first read request or the second read request, and the value of the encryption key is changed to another value after the transmission .

Further, the method for controlling an encryption key according to the present invention is a method for controlling an encryption key performed by an encryption key generator that generates the encryption key when encrypting plain text data using an encryption key received via a data bus. Therefore, the encryption key is sent to the data bus in response to the first read request or the second read request while changing the value of the encryption key every predetermined period, and within each of the predetermined periods. When the second read request is received after the first read request is received, an error response is sent to the data bus in place of the encryption key in response to the second read request.

In the present invention, when the plain text data is encrypted by using the encryption key received via the data bus, the generated encryption key is sent to the data bus in response to the first or second read request, and the first and second When one of the second read requests is received, the value of the encryption key is changed to the other value.

Further, in the present invention, if a second read request is received after receiving the first read request within the predetermined period every predetermined period, the encryption key is replaced in response to the second read request. And send an error response to the data bus.

As a result, for example, even if a first read request for acquiring the encryption key is made from the CPU (or DMAC) and a second read request for acquiring the encryption key is subsequently made from the DMAC (or CPU), the same value is obtained. The encryption key is never sent to the data bus twice in a row.

Therefore, the possibility of leaking the encryption key is reduced, and it is possible to prevent the leakage of plaintext data due to unauthorized access.

It is a block diagram which shows the structure of the microcomputer 100 as an example of the semiconductor device which concerns on this invention. It is a block diagram which shows an example of the internal structure of the encryption key generation unit 13. It is a figure which shows the data transfer operation for the encryption key acquisition by the secure DMAC21. It is a figure which shows the data transfer operation for the encryption key acquisition by the CPU 14. It is a time chart which shows an example of the internal operation of the encryption key generation unit 13. It is a time chart which shows another example of the internal operation of the encryption key generation unit 13. It is a block diagram which shows the structure of the microcomputer 100 as another example of a semiconductor device. It is a block diagram which shows an example of the internal structure of the encryption key generation unit 13A. FIG. 7 is a diagram showing an example of a data transfer operation for acquiring an encryption key by the secure DMAC 21 in the microcomputer 100 shown in FIG. 7. FIG. 7 is a diagram showing an example of a data transfer operation for acquiring an encryption key by the CPU 14 in the microcomputer 100 shown in FIG. 7. It is a time chart which shows an example of the internal operation of the encryption key generation unit 13A. FIG. 7 is a diagram showing another example of a data transfer operation for acquiring an encryption key by the CPU 14 in the microcomputer 100 shown in FIG. 7. FIG. 7 is a diagram showing another example of a data transfer operation for acquiring an encryption key by the secure DMAC 21 in the microcomputer 100 shown in FIG. 7. It is a time chart which shows another example of the internal operation of the encryption key generation unit 13A. It is a block diagram which shows the modification of the microcomputer 100 shown in FIG. 7. It is a figure which shows an example of the data transfer operation for the encryption key acquisition by the secure DMAC21 in the microcomputer 100 shown in FIG. FIG. 15 is a diagram showing an example of a data transfer operation for acquiring an encryption key by the CPU 14 in the microcomputer 100 shown in FIG. 15. FIG. 15 is a diagram showing another example of a data transfer operation for acquiring an encryption key by the CPU 14 in the microcomputer 100 shown in FIG. 15. FIG. 15 is a diagram showing another example of a data transfer operation for acquiring an encryption key by the secure DMAC 21 in the microcomputer 100 shown in FIG.

FIG. 1 is a block diagram showing a configuration of a microcomputer 100 included in the semiconductor device according to the present invention.

The microcomputer 100 includes an encryption processing unit 12, an encryption key generation unit 13, a CPU (central processing unit) 14, a RAM (random access memory) 15, a ROM (read only memory) control unit 16, ROM 17, a secure RAM 19, and a secure ROM 20. It has a secure DMAC (direct memory access controller) 21 and a key storage 22.

Further, the microcomputer 100 includes two data buses BS1 and BS8. The microcomputer 100 is capable of data communication with an externally connected device, and transmits or receives various data via the data bus BS1.

An encryption processing unit 12, an encryption key generation unit 13, a CPU 14, a RAM 15, a ROM control unit 16, a ROM 17, a secure RAM 19, and a key storage 22 are connected to the data bus BS1.

The data bus BS8 is an independent bus that is not connected to the data bus BS1 and is inaccessible from the outside of the microcomputer 100. The data bus BS8 is connected to an encryption key generation unit 13, a secure RAM 19, a secure ROM 20, a secure DMAC 21, a key storage 22, and an encryption processing unit 12, which are required to be confidential.

The encryption processing unit 12 obtains an encrypted data piece by encrypting the unencrypted plaintext data piece received via the data bus BS1 with an encryption key, and sends the encrypted data piece to the data bus BS1. Further, the encryption processing unit 12 restores the plaintext data piece before encryption by decrypting the encrypted data piece received via the data bus BS1 using this encryption key. The encryption processing unit 12 acquires an encryption key from the key storage 22 before executing such an encryption or decryption process.

The encryption key generation unit 13 generates an encryption key and sends it to the data bus BS1 or BS8.

FIG. 2 is a block diagram showing an example of the internal configuration of the encryption key generation unit 13.

In the example shown in FIG. 2, the encryption key generation unit 13 includes a random number generation unit 131, a register 132, and an output control unit 133.

The random number generation unit 131 generates a random number RND whose random number value changes every predetermined period, and supplies this to the register 132. When the random number generation unit 131 receives the random number change signal CH, the random number generation unit 131 generates the random number value indicated by the random number RND at the time of receiving the random number change signal CH without waiting for the elapse of the above-mentioned predetermined period. Change to another random number value.

The register 132 supplies the encryption key CRK having the random number value represented by the random number RND to the output control unit 133 while holding the random number RND.

When the output control unit 133 receives the encryption key read request RQ1 via the data bus BS1, the output control unit 133 sends the encryption key CRK supplied from the register 132 to the data bus BS1 and subsequently generates a random number change signal CH. Supply to unit 131. Further, when the output control unit 133 receives the encryption key read request RQ2 via the data bus BS8, the output control unit 133 sends the encryption key CRK supplied from the register 132 to the data bus BS8.

The CPU 14 shown in FIG. 1 is a central processing unit of the microcomputer 100, and performs various controls for calculation or data transfer according to a program stored in the ROM 17.

The RAM 15 is a storage element capable of writing data, and the CPU 14 writes or reads data.

The ROM control unit 16 writes data to the ROM 17, verifies whether or not the data is correctly written, erases the written data, and the like.

Program data representing a program executed by the CPU 14 is written in the ROM 17.

The secure RAM 19 stores data received via the data bus BS8 in response to a data write access from the secure DMAC21. Further, the secure RAM 19 reads the data stored in itself in response to the data read access from the secure DMAC 21, and sends the data to the data bus BS8. Further, the secure RAM 19 stores the data received via the data bus BS1 in response to the data write access from the CPU 14. The secure RAM 19 does not accept data read access from the CPU 14.

The secure ROM 20 reads the data stored in the secure ROM 20 in response to the data read access from the secure DMAC 21, and sends the data to the data bus BS8. Further, the secure ROM 20 writes the data received via the data bus BS8 in response to the data write access from the ROM control unit 16 or the secure DMAC21.

The secure DMAC 21 transfers data between the encryption processing unit 12, the encryption key generation unit 13, the secure RAM 19, the secure ROM 20, and the key storage 22 via the data bus BS8.

The key storage 22 holds the encryption key received via the data bus BS8. Further, the key storage 22 reads the held encryption key in response to the encryption key read request and sends it to the data bus BS8.

With the above configuration, the microcomputer 100 performs various data processing including encryption of plaintext data using the above-mentioned encryption key or decryption processing of encrypted data according to the program stored in the ROM 17.

Hereinafter, the data transfer operation performed in the microcomputer 100 will be described by taking the case of encrypting the plaintext data piece on the data bus BS1 as an example.

First, the secure DMAC 21 supplies the encryption key read request RQ2 for acquiring the encryption key to the encryption key generation unit 13 via the data bus BS8 as shown by the thick line arrow in FIG. In response to the encryption key read request RQ2, the encryption key generation unit 13 supplies the encryption key CRK to the secure DMAC 21 via the data bus BS8 as shown by the thick line arrow in FIG.

The secure DMAC 21 transfers the acquired encryption key CRK to the key storage 22 via the data bus BS8, and holds the encryption key CRK in the key storage 22. Next, the secure DMAC 21 transfers the encryption key CRK held in the key storage 22 to each of the secure RAM 19 and the secure ROM 20, and causes the encryption key CRK to be written in the secure RAM 19 and the secure ROM 20. Then, the secure DMAC 21 supplies the encryption key CRK written in the secure RAM 19 to the encryption processing unit 12 via the data bus BS8.

As a result, the encryption processing unit 12 generates an encrypted data piece in which the plain text data piece on the data bus BS1 is encrypted by using the encryption key CRK acquired by the secure DMAC 21 via the data bus BS8 as described above. , This is sent to the data bus BS1. At this time, the CPU 14 supplies the encrypted data piece to the RAM 15 via the data bus BS1 and causes the RAM 15 to write the encrypted data piece.

Therefore, by the series of processes described above, an encrypted data piece obtained by encrypting the plaintext data piece is generated.

By the way, in the microcomputer 100, not only the secure DMAC 21 but also the CPU 14 can perform data transfer control for encrypting the plaintext data or decrypting the encrypted data as described above.

For example, when encrypting a plain data piece on the data bus BS1, first, the CPU 14 sends an encryption key read request RQ1 for acquiring an encryption key via the data bus BS1 as shown by a thick line arrow in FIG. It is supplied to the encryption key generation unit 13. In response to the encryption key read request RQ1, the encryption key generation unit 13 supplies the encryption key CRK to the CPU 14 via the data bus BS1 as shown by the thick line arrow in FIG.

The CPU 14 transfers the acquired encryption key CRK to the key storage 22 via the data bus BS1 and holds the encryption key CRK in the key storage 22. Next, the CPU 14 transfers the encryption key CRK held in the key storage 22 to the RAM 15, and causes the RAM 15 to write the encryption key CRK. Then, the CPU 14 supplies the encryption key CRK written in the RAM 15 to the encryption processing unit 12 via the data bus BS1.

As a result, the encryption processing unit 12 generates an encrypted data piece in which the plaintext data piece on the data bus BS1 is encrypted by using the encryption key CRK acquired by the CPU 14 via the data bus BS1 as shown in FIG. Then, this is sent to the data bus BS1. At this time, the CPU 14 supplies the encrypted data piece to the RAM 15 via the data bus BS1 and causes the RAM 15 to write the encrypted data piece.

As described above, in the microcomputer 100, both the secure DMAC 21 and the CPU 14 can perform data transfer for data encryption or decryption.

Therefore, after the data transfer for acquiring the encryption key as shown in FIG. 3 is completed by the secure DMAC21 and before the encryption processing by the encryption processing unit 12 using the encryption key is completed, the CPU 14 shows the figure 4 in FIG. Data transfer for acquiring the encryption key as shown may be performed.

The following shows the internal operation of the encryption key generation unit 13 when the data transfer for acquiring the encryption key by the secure DMAC21 (FIG. 3) and the data transfer for acquiring the encryption key by the CPU 14 (FIG. 4) are continuous. This will be described with reference to the time chart shown in 5.

First, it is assumed that the random number generation unit 131 of the encryption key generation unit 13 generates a random number RND indicating the random number value Q1 as shown in FIG. Therefore, the register 132 supplies the encryption key CRK having the random number value Q1 represented by the random number RND to the output control unit 133 while holding the random number RND.

First, the encryption key generation unit 13 receives the encryption key read request RQ2 transmitted from the secure DMAC 21 via the data bus BS8 as shown in FIG. Then, as shown in FIG. 5, the output control unit 133 of the encryption key generation unit 13 sends the encryption key CRK having the random number value Q1 to the data bus BS8. As a result, the encryption key CRK is supplied to the secure DMAC 21 via the data bus BS8 as shown in FIG.

Further, the output control unit 133 responds to the encryption key read request RQ2, and immediately after transmitting the encryption key CRK to the data bus BS8, transitions from the logic level 0 to the logic level 1 state as shown in FIG. A binary random number change signal CH is supplied to the random number generation unit 131. That is, the output control unit 133 supplies the random number change signal CH for prompting the change of the encryption key to the random number generation unit 131.

In response to the random number change signal CH, the random number generation unit 131 changes the random number value Q1 of the current random number RND to the random number value Q2, as shown in FIG.

As a result, the register 132 overwrites the held contents with the random number value Q2. That is, the register 132 deletes the random number value Q1 held until immediately before that, and holds the random number value Q2 in place of the random number value Q1. Therefore, at this time, the register 132 supplies the encryption key CPK having the random number value Q2 shown in FIG. 5 to the output control unit 133.

After that, the encryption key generation unit 13 receives the encryption key read request RQ1 sent from the CPU 14 via the data bus BS1 as shown in FIG. Then, as shown in FIG. 5, the output control unit 133 of the encryption key generation unit 13 sends the encryption key CRK having the random number value Q2 to the data bus BS1. As a result, the encryption key CRK is supplied to the CPU 14 via the data bus BS1 as shown in FIG.

Therefore, the value (Q2) of the encryption key CRK sent by the encryption key generation unit 13 in response to the encryption key read request RQ1 from the CPU 14 is immediately before that, the encryption key is generated in response to the encryption key read request RQ2 from the secure DMAC21. It is different from the value (Q1) of the encryption key CRK sent by the unit 13.

Therefore, even if the encryption key read request RQ2 from the secure DMAC21 as shown in FIG. 3 is followed by the encryption key read request RQ1 from the CPU 14 as shown in FIG. 4, the encryption key CRK having the same value is performed twice. It is not continuously transmitted from the encryption key generation unit 13. Therefore, the possibility that the encryption key CRK is leaked to the outside of the microcomputer 100 is reduced, and it is possible to prevent the leakage of plaintext data.

In the above example, the encryption key generation unit 13 changes the encryption key CRK value (Q1) to another value (Q2) in response to the encryption key read request RQ2 from the secure DMAC21. However, the value of the encryption key CRK may be changed to another value according to the encryption key read request RQ1 from the CPU 14. At this time, as the encryption key generation unit 13, an output control unit 133 that performs the following operations is adopted.

That is, when the output control unit 133 receives the encryption key read request RQ1 from the CPU 14 via the data bus BS1, the output control unit 133 sends the encryption key CRK supplied from the register 132 to the data bus BS1 and subsequently changes the random number. The signal CH is supplied to the random number generation unit 131. Further, when the output control unit 133 receives the encryption key read request RQ2 from the secure DMAC 21 via the data bus BS8, the output control unit 133 sends the encryption key CRK supplied from the register 132 to the data bus BS8.

FIG. 6 shows the internal operation of the encryption key generation unit 13 when the data transfer for the encryption key acquisition by the secure DMAC 21 (FIG. 3) is continuous immediately after the data transfer for the encryption key acquisition by the CPU 14 (FIG. 4). It is a time chart showing.

First, when the output control unit 133 of the encryption key generation unit 13 receives the encryption key read request RQ1 sent from the CPU 14 via the data bus BS1 as shown in FIG. 4, the random number value Q1 is as shown in FIG. The encryption key CRK having the above is sent to the data bus BS1. As a result, the encryption key CRK is supplied to the CPU 14 via the data bus BS1 as shown in FIG.

Further, the output control unit 133 responds to the encryption key read request RQ1 and immediately after sending the encryption key CRK to the data bus BS1, transitions from the logic level 0 to the logic level 1 state as shown in FIG. The binary random number change signal CH is supplied to the random number generation unit 131. In response to the random number change signal CH, the random number generation unit 131 changes the random number value Q1 of the current random number RND to the random number value Q2, as shown in FIG. As a result, the register 132 overwrites the held contents with the random number value Q2. That is, the register 132 deletes the random number value Q1 held until immediately before that, and holds the random number value Q2 in place of the random number value Q1. Therefore, at this time, the register 132 supplies the encryption key CPK having the random number value Q2 to the output control unit 133 as shown in FIG.

After that, when the output control unit 133 of the encryption key generation unit 13 receives the encryption key read request RQ2 sent from the secure DMAC 21 via the data bus BS8 as shown in FIG. 3, a random number value is obtained as shown in FIG. The encryption key CRK having Q2 is sent to the data bus BS8. As a result, the encryption key CRK is supplied to the secure DMAC 21 via the data bus BS8 as shown in FIG.

Therefore, the value (Q2) of the encryption key CRK sent by the encryption key generation unit 13 in response to the encryption key read request RQ2 from the secure DMAC 21 is immediately before that, the encryption key is generated in response to the encryption key read request RQ1 from the CPU 14. It is different from the value (Q1) of the encryption key CRK sent by the unit 13.

Therefore, even if the encryption key read request RQ1 from the CPU 14 as shown in FIG. 4 is followed by the encryption key read request RQ2 from the secure DMAC21 as shown in FIG. 3, the encryption key CRK having the same value is performed twice. It is not continuously transmitted from the encryption key generation unit 13. Therefore, the possibility that the encryption key CRK is leaked to the outside of the microcomputer 100 is reduced, and it is possible to prevent the leakage of plaintext data.

In the above embodiment, the CPU 14 and the DMAC 21 are transfer control units that read the encryption key CRK generated by the encryption key generation unit 13 and transfer it to the encryption processing unit 12 via the data bus (BS1, BS8). Is used. However, the transfer control unit is not limited to the CPU, DMAC, or the like as long as it can transfer data for acquiring the encryption key as described above.

Further, in the embodiment shown in FIGS. 1 and 2, the data transfer for acquiring the encryption key is performed using the two data buses BS1 and BS8, but the same can be performed by a single data bus. It is possible.

In short, the microcomputer 100 shown in FIG. 1 may include the following encryption processing unit, encryption key generation unit, and first and second transfer control units.

That is, the encryption processing unit (12) encrypts the plaintext data using the encryption key (CRK) received via the data bus (BS1, BS8). The encryption key generation unit (13) generates an encryption key (CRK), and the generated encryption key is sent to the data bus in response to a first read request (RQ1 or RQ2) or a second read request (RQ2 or RQ1). Send. The first transfer control unit (14 or 21) supplies the first read request to the encryption key generation unit, and transfers the encryption key sent from the encryption key generation unit to the encryption processing unit via the data bus. The second transfer control unit (21 or 14) supplies the second read request to the encryption key generation unit, and transfers the encryption key sent from the encryption key generation unit to the encryption processing unit via the data bus. Here, the encryption key generation unit changes the value of the encryption key to another value when one of the first read request and the second read request is received.

Further, the encryption key generation unit 13 shown in FIG. 2 may include the following random number generation unit, register, and output control unit.

That is, the random number generation unit (131) generates a random number (RND) whose random number value changes every predetermined period, and changes the random number value to another random number value when the random number change signal (CH) is received. The register (132) holds this random number and outputs the held random number as an encryption key (CRK). The output control unit (133) sends the encryption key output from the register (132) to the data bus when the first or second read request is received. Further, the output control unit supplies a random number change signal (CH) to the random number generation unit when one of the first and second read requests is received.

FIG. 7 is a block diagram showing another configuration of the microcomputer 100. The configuration shown in FIG. 7 is the same as that shown in FIG. 1 except that the encryption key generation unit 13A is used instead of the encryption key generation unit 13. Therefore, the internal operation of the microcomputer 100 in the configuration shown in FIG. 7 will be described below, focusing on the configuration of the encryption key generation unit 13A.

FIG. 8 is a block diagram showing an internal configuration of the encryption key generation unit 13A.

As shown in FIG. 8, the encryption key generation unit 13A includes a random number generation unit 131A, a register 132, an output control unit 133A, and a flag register 134.

The random number generation unit 131A generates a random number RND whose random number value changes every predetermined period, and supplies this to the register 132. The random number generation unit 131A supplies a random number change signal VA indicating that the random number value has changed to the output control unit 133A at the timing when the random number value of the random number RND changes.

The register 132 supplies the encryption key CRK having the random number value represented by the random number RND to the output control unit 133A while holding the random number RND.

The flag register 134 holds a flag FG indicating whether or not an encryption key read request has been received within the predetermined period for each of the predetermined periods described above. For example, a binary flag FG having a logic level 1 when the encryption key read request is received and a logic level 0 when the encryption key read request is not received is held in the flag register 134. When the power is turned on, the flag FG having the logic level 0 is held in the flag register 134.

When the output control unit 133A receives the encryption key read request RQ2 from the secure DMAC 21 via the data bus BS8, the output control unit 133A sends the encryption key CRK supplied from the register 132 to the data bus BS8. Further, the output control unit 133A rewrites the flag FG held in the flag register 134 to the logic level 1 indicating that the encryption key read request has been received, in response to the encryption key read request RQ2.

Further, when the output control unit 133A receives the encryption key read request RQ1 from the CPU 14 via the data bus BS1, first, the flag FG held in the flag register 134 is set to the logic level 0, or the flag FG is set to the logic level 0. It is determined whether the logic level is 1.

Here, when it is determined that the flag FG is the logic level 0, that is, when it is determined that the encryption key read request has not been received, the output control unit 133A uses the encryption key CRK supplied from the register 132 as the data bus. Send to BS1.

On the other hand, if it is determined that the flag FG is the logical level 1, that is, if it is determined that the encryption key read request has already been received, the output control unit 133A replaces the encryption key CRK with an error indicating an encryption key read error. The response ERR is sent to the data bus BS1. At this time, the error response ERR is supplied to the CPU 14 via the data bus BS1.

Further, when the output control unit 133A receives the random number change signal VA indicating that the random number value of the random number RND has changed, the output control unit 133A initializes the flag FG held in the flag register 134 to the state of logic level 0. ..

Below, in the configuration shown in FIGS. 7 and 8, the operation when the data transfer for the encryption key acquisition by the CPU 14 is performed following the data transfer for the encryption key acquisition by the secure DMAC21 will be described in FIG. This description will be given with reference to FIG.

Note that FIG. 9 shows a data transfer operation for acquiring the encryption key by the secure DMAC21, and FIG. 10 shows a data transfer operation for acquiring the encryption key by the CPU 14 performed immediately after the data transfer shown in FIG. It is a figure.

Further, FIG. 11 is a time chart showing the internal operation of the encryption key generation unit 13A when the data transfer shown in FIG. 10 is performed immediately after the data transfer shown in FIG. 9.

In the example shown in FIG. 11, the random number generation unit 131A of the encryption key generation unit 13A first supplies the random number RND indicating the random number value Q1 to the register 132 over a predetermined period TU, and is disturbed after the lapse of the predetermined period TU. It is assumed that a random number RND indicating the numerical value Q2 is supplied to the register 132. Therefore, the register 132 supplies the encryption key CRK having the random number value Q1 over the predetermined period TU to the output control unit 133A, and supplies the encryption key CRK having the random number value Q2 to the output control unit 133A after the elapse of the predetermined period TU. .. Further, the encryption key generation unit 131A transitions from the state of logic level 0 to the state of logic level 1 at the time when the random number value indicated by the random number RND changes, and is in the state of logic level 0, as shown in FIG. A binary random number change signal VA is supplied to the output control unit 133A.

First, the encryption key generation unit 13A receives the encryption key read request RQ2 transmitted from the secure DMAC 21 via the data bus BS8 as shown by the thick line arrow in FIG. Then, as shown in FIG. 11, the output control unit 133A of the encryption key generation unit 13A sends the encryption key CRK having the random number value Q1 to the data bus BS8. As a result, the encryption key CRK is supplied to the secure DMAC 21 via the data bus BS8 as shown by the thick arrow in FIG. Further, the output control unit 133A rewrites the flag FG held in the flag register 134 to the logic level 1 indicating that the encryption key read request has been received, as shown in FIG. 11, in response to the encryption key read request RQ2. ..

After that, the encryption key generation unit 13A receives the encryption key read request RQ1 sent from the CPU 14 via the data bus BS1 as shown by the thick line arrow in FIG. Then, as shown in FIG. 11, the output control unit 133A of the encryption key generation unit 13A sets the error response ERR to the data bus BS1 because the flag FG is at the logic level 1 when the encryption key read request RQ1 is received. Send out. At this time, the error response ERR sent from the encryption key generation unit 13A is supplied to the CPU 14 via the data bus BS1 as shown by the thick line arrow in FIG. Upon receiving the error response ERR, the CPU 14 determines that the reading of the encryption key from the encryption key generation unit 13A has failed. If the flag FG is at the logic level 1 when the encryption key read request RQ1 is received as described above, the output control unit 133A does not send the encryption key at that time.

In this way, the encryption key generation unit 13A sends the encryption key CRK to the data bus BS8 in response to the encryption key read request RQ2 from the secure DMAC21. At this time, if the encryption key read request RQ1 is continuously received from the CPU 14, the encryption key generation unit 13A sends an error response ERR to the data bus BS1 in place of the encryption key CRK in response to the encryption key read request RQ1. Send.

As a result, even if the encryption key read request RQ2 from the secure DMAC 21 as shown in FIG. 9 is followed by the encryption key read request RQ1 from the CPU 14 as shown in FIG. 10, the encryption key CRK having the same value is 2. It is not continuously transmitted from the encryption key generation unit 13A. Therefore, the possibility that the encryption key CRK is leaked to the outside of the microcomputer 100 is reduced, and it is possible to prevent the leakage of plaintext data.

After that, when the random number generation unit 131A changes the random number value indicated by the random number RND from Q1 to Q2 as shown in FIG. 11, the output control unit 133A logics the contents of the flag FG held in the flag register 134. Rewrite from level 1 to logical level 0.

Therefore, after that, when the encryption key generation unit 13A receives the encryption key read request RQ1 from the CPU 14 via the data bus BS1, the flag FG is set to the logical level when the encryption key read request RQ1 is received as shown in FIG. Since it is 0, the encryption key CRK having the random number value Q2 is sent to the data bus BS1.

At this time, the value (Q2) of the encryption key CRK sent by the encryption key generation unit 13A in response to the encryption key read request RQ1 from the CPU 14 is the encryption key in response to the encryption key read request RQ2 from the secure DMAC 21 immediately before that. It is different from the value (Q1) of the encryption key CRK sent by the generation unit 13A.

Therefore, since the encryption key CRK having the same value is not transmitted from the encryption key generation unit 13A twice in a row, the possibility that the encryption key CRK is leaked to the outside of the microcomputer 100 is reduced, and the plaintext is written. It is possible to prevent data leakage.

By the way, in the example shown in FIGS. 9 and 10, the encryption key generation unit 13A performs an error response ERR when the encryption key read request from the CPU 14 is received immediately after receiving the encryption key read request from the secure DMAC21. I am doing it. However, the encryption key generation unit 13A may perform an error response ERR when an encryption key read request is received from the secure DMAC 21 immediately after receiving the encryption key read request from the CPU 14.

At this time, as the encryption key generation unit 13A, the following output control unit 133A is adopted.

That is, when the output control unit 133A receives the encryption key read request RQ1 from the CPU 14, the output control unit 133A sends the encryption key CRK to the data bus BS1. Further, in response to the encryption key read request RQ1, the output control unit 133A rewrites the flag FG held in the flag register 134 to the logic level 1 indicating that the encryption key read request has been received.

Further, when the output control unit 133A receives the encryption key read request RQ2 from the secure DMAC21, first, the flag FG held in the flag register 134 is the logic level 1 or the logic level 0. Is determined. Here, when it is determined that the flag FG is the logic level 0, that is, when it is determined that the encryption key read request has not been received, the output control unit 133A sends the encryption key CRK to the data bus BS8.

On the other hand, if it is determined that the flag FG is at the logic level 1, that is, if it is determined that the encryption key read request has already been received, the output control unit 133A sets an error response ERR indicating an encryption key read error to the data bus BS8. Send to. At this time, the error response ERR is supplied to the secure DMAC 21 via the data bus BS8.

Further, when the random number change signal VA indicating that the random number value of the random number RND has changed is supplied from the random number generation unit 131A, the output control unit 133A sets the flag FG held in the flag register 134 to the logic level. Initialize to the state of 0.

Hereinafter, the operation in the case where the data transfer for the encryption key acquisition by the secure DMAC 21 is continuous immediately after the data transfer for the encryption key acquisition by the CPU 14 will be described with reference to FIGS. 12 to 14.

Note that FIG. 12 is a diagram showing a data transfer operation for acquiring an encryption key by the CPU 14, and FIG. 13 is a diagram showing a data transfer operation for acquiring an encryption key by the secure DMAC 21 performed immediately after the data transfer shown in FIG. Is.

Further, FIG. 14 is a time chart showing the internal operation of the encryption key generation unit 13A when the data transfer shown in FIG. 13 is performed immediately after the data transfer shown in FIG. 12.

First, the encryption key generation unit 13A receives the encryption key read request RQ1 sent from the CPU 14 via the data bus BS1 as shown by the thick line arrow in FIG. Then, as shown in FIG. 14, the output control unit 133A of the encryption key generation unit 13A sends the encryption key CRK having the random number value Q1 to the data bus BS1. As a result, the encryption key CRK is supplied to the CPU 14 via the data bus BS1 as shown by the thick arrow in FIG. Further, the output control unit 133A rewrites the flag FG held in the flag register 134 to the logic level 1 indicating that the encryption key read request has been received, as shown in FIG. 14, in response to the encryption key read request RQ1. ..

After that, the encryption key generation unit 13A receives the encryption key read request RQ2 transmitted from the secure DMAC 21 via the data bus BS8 as shown by the thick line arrow in FIG. Then, as shown in FIG. 14, the output control unit 133A of the encryption key generation unit 13A responds with an error instead of the encryption key CRK because the flag FG is at the logic level 1 when the encryption key read request RQ2 is received. ERR is sent to the data bus BS8. At this time, the error response ERR sent from the encryption key generation unit 13A is supplied to the secure DMAC 21 via the data bus BS8 as shown by the thick line arrow in FIG. Upon receiving this error response ERR, the secure DMAC 21 determines that the reading of the encryption key from the encryption key generation unit 13A has failed. If the flag FG is at the logic level 1 when the encryption key read request RQ2 is received as described above, the output control unit 133A does not send the encryption key at that time.

As described above, when the encryption key generation unit 13A receives the encryption key read request from the secure DMAC 21 immediately after transmitting the encryption key CRK in response to the encryption key read request from the CPU 14, the encryption key CRK is transmitted. Is not performed, and an error response ERR is sent.

As a result, even if the encryption key read request RQ1 from the CPU 14 as shown in FIG. 12 is followed by the encryption key read request RQ2 from the secure DMAC21 as shown in FIG. 13, the encryption key CRK having the same value is 2. It is not continuously transmitted from the encryption key generation unit 13A. Therefore, the possibility that the encryption key CRK is leaked to the outside of the microcomputer 100 is reduced, and it is possible to prevent the leakage of plaintext data.

After that, when the random number generation unit 131A changes the random number value indicated by the random number RND from Q1 to Q2 as shown in FIG. 14, the output control unit 133A logics the contents of the flag FG held in the flag register 134. Rewrite from level 1 to logical level 0.

Therefore, when the encryption key generation unit 13A subsequently receives the encryption key read request RQ2 from the secure DMAC21 via the data bus BS8, the flag FG is logical when the encryption key read request RQ2 is received as shown in FIG. Since the level is 0, the encryption key CRK having the random number value Q2 is sent to the data bus BS8.

At this time, the value (Q2) of the encryption key CRK sent by the encryption key generation unit 13A in response to the encryption key read request RQ2 from the secure DMAC 21 is the encryption key in response to the encryption key read request RQ1 from the CPU 14 immediately before that. It is different from the value (Q1) of the encryption key CRK sent by the generation unit 13A.

Therefore, since the encryption key CRK having the same value is not transmitted from the encryption key generation unit 13A twice in succession, the possibility that the encryption key CRK is leaked to the outside of the microcomputer 100 is reduced, and the plaintext is written. It is possible to prevent data leakage.

As described above, in the microcomputer 100 shown in FIG. 7, the encryption key generation unit 13A shown in FIG. 8 is adopted instead of the encryption key generation unit 13 shown in FIG. The encryption key generation unit (13A) receives a first read request (RQ1 or RQ2) and then a second read request (RQ2 or RQ1) for each predetermined period (TU). In this case, in response to this second read request, an error response (ERR) is sent to the data bus (BS1, BS8) instead of the encryption key (CRK).

Further, in the microcomputer 100, as the encryption key generation unit 13A shown in FIG. 8, a unit including the following random number generation unit, first and second registers, and an output control unit is adopted.

That is, the random number generation unit (131A) generates a random number (RND) whose random number value changes every predetermined period (TU). The first register (132) holds this random number and outputs the held random number as an encryption key (CRK). The second register (134) holds a flag (FG) indicating whether or not a read request (RQ1 or RQ2) has been received.

The output control unit (133A) sends the encryption key output from the first register when the first read request or the second read request is received to the data bus (BS1, BS8), and at the same time, for a predetermined period. For each (TU), the flag held in the second register is initialized to a state (for example, logic level 0) indicating that a read request has not been received. Here, when the output control unit receives the first read request, the output control unit rewrites the flag held in the second register to a state (for example, logic level 1) indicating that the read request has been received. Further, when the output control unit receives the second read request, the output control unit responds with an error (ERR instead of the encryption key) when the flag held in the second register indicates that the read request has been received. ) Is sent to the data bus.

FIG. 15 is a block diagram showing a modification of the microcomputer 100 shown in FIG. 7. In the configuration shown in FIG. 15, the configurations other than the addition of the reset control unit 23 are the same as those shown in FIG. 7.

In FIG. 15, when the reset control unit 23 receives the above-mentioned error response ERR via the data bus BS1 or BS8, the reset control unit 23 supplies the reset signal RS to the encryption key generation unit 13A, the CPU 14, and the key storage 22. The encryption key generation unit 13A, the CPU 14, and the key storage 22 reset their own states in response to the reset signal RS.

Below, in the configuration shown in FIG. 15, the operation when the data transfer for the encryption key acquisition by the CPU 14 is performed following the data transfer for the encryption key acquisition by the secure DMAC21 will be described in FIGS. 16 and 17. In addition, it will be described with reference to FIG. 11 described above.

Note that FIG. 16 shows a data transfer operation for acquiring an encryption key by the secure DMAC21, and FIG. 17 shows a data transfer for acquiring an encryption key by the CPU 14 which is continuously performed immediately after the data transfer shown in FIG. It is a figure which shows the operation.

First, the encryption key generation unit 13A receives the encryption key read request RQ2 transmitted from the secure DMAC 21 via the data bus BS8 as shown by the thick line arrow in FIG. Then, the output control unit 133A of the encryption key generation unit 13A sends the encryption key CRK having the random number value Q1 to the data bus BS8. As a result, the encryption key CRK is supplied to the secure DMAC 21 via the data bus BS8 as shown by the thick arrow in FIG. Further, the output control unit 133A rewrites the flag FG held in the flag register 134 to the logic level 1 indicating that the encryption key read request has been received, as shown in FIG. 11, in response to the encryption key read request RQ2. ..

After that, the encryption key generation unit 13A receives the encryption key read request RQ1 sent from the CPU 14 via the data bus BS1 as shown by the thick line arrow in FIG. Then, as shown in FIG. 11, the output control unit 133A of the encryption key generation unit 13A sets the error response ERR to the data bus BS1 because the flag FG is at the logic level 1 when the encryption key read request RQ1 is received. Send. At this time, the error response ERR sent from the encryption key generation unit 13A is supplied to the reset control unit 23 via the data bus BS1 as shown by the thick line arrow in FIG.

The reset control unit 23 that has received the error response ERR supplies the reset signal RS to the encryption key generation unit 13A, the CPU 14, and the key storage 22. The encryption key generation unit 13A, the CPU 14, and the key storage 22 reset their own states in response to the reset signal RS.

As described above, when the encryption key generation unit 13A receives the encryption key read request from the CPU 14 immediately after transmitting the encryption key CRK in response to the encryption key read request from the secure DMAC 21, the encryption key CRK is transmitted. Is not performed, and an error response ERR is sent. At this time, the reset control unit 23 that has received the error response ERR resets the states of the encryption key generation unit 13A, the CPU 14, and the key storage 22.

As a result, even if the encryption key read request RQ2 from the secure DMAC 21 as shown in FIG. 16 is followed by the encryption key read request RQ1 from the CPU 14 as shown in FIG. 17, the encryption key CRK having the same value is 2. It is not continuously transmitted from the encryption key generation unit 13A. Therefore, the possibility that the encryption key CRK is leaked to the outside of the microcomputer 100 is reduced, and it is possible to prevent the leakage of plaintext data.

In the example shown in FIGS. 16 and 17, when the encryption key generation unit 13A receives the encryption key read request from the CPU 14 immediately after receiving the encryption key read request from the secure DMAC 21, the reset control unit 23 The error response ERR is performed. However, the encryption key generation unit 13A performs an error response ERR to the reset control unit 23 when the encryption key read request is received from the secure DMAC 21 immediately after receiving the encryption key read request from the CPU 14. Is also good.

At this time, as the encryption key generation unit 13A, an output control unit 133A that performs the following operations is adopted.

That is, when the output control unit 133A receives the encryption key read request RQ1 from the CPU 14, the output control unit 133A sends the encryption key CRK to the data bus BS1. Further, in response to the encryption key read request RQ1, the output control unit 133A rewrites the flag FG held in the flag register 134 to the logic level 1 indicating that the encryption key read request has been received.

Further, when the output control unit 133A receives the encryption key read request RQ2 from the secure DMAC21, first, the flag FG held in the flag register 134 is the logic level 0 or the logic level 1. Is determined. Here, when it is determined that the flag FG is the logic level 0, that is, when it is determined that the encryption key read request has not been received, the output control unit 133A sends the encryption key CRK to the data bus BS8.

On the other hand, if it is determined that the flag FG is the logic level 1, that is, if it is determined that the encryption key read request has already been received, the output control unit 133A replaces the encryption key CRK with an error indicating an encryption key read error. The response ERR is sent to the data bus BS8. At this time, the error response ERR is supplied to the reset control unit 23 via the data bus BS8.

Below, in the configuration shown in FIG. 15, the operation when the data transfer for the encryption key acquisition by the CPU 14 is followed by the data transfer for the encryption key acquisition by the secure DMAC21 is described in FIGS. 18 and 19. In addition, it will be described with reference to FIG. 14 described above.

Note that FIG. 18 shows a data transfer operation for acquiring the encryption key by the CPU 14, and FIG. 19 shows a data transfer operation for acquiring the encryption key by the secure DMAC21, which is performed immediately after the data transfer shown in FIG. It is a figure.

First, the encryption key generation unit 13A receives the encryption key read request RQ1 sent from the CPU 14 via the data bus BS1 as shown by the thick line arrow in FIG. Then, the output control unit 133A of the encryption key generation unit 13A sends the encryption key CRK having the random number value Q1 to the data bus BS1. As a result, the encryption key CRK is supplied to the CPU 14 via the data bus BS1 as shown by the thick arrow in FIG. Further, the output control unit 133A sets the flag FG held in the flag register 134 to the logic level 1 indicating that the encryption key read request has been received, as shown in FIG. 14, in response to the encryption key read request RQ1. rewrite.

After that, the encryption key generation unit 13A receives the encryption key read request RQ2 transmitted from the secure DMAC 21 via the data bus BS8 as shown by the thick line arrow in FIG. Then, as shown in FIG. 14, the output control unit 133A of the encryption key generation unit 13A sets the error response ERR to the data bus BS8 because the flag FG is at the logic level 1 when the encryption key read request RQ2 is received. Send to. At this time, the error response ERR sent from the encryption key generation unit 13A is supplied to the reset control unit 23 via the data bus BS8 as shown by the thick line arrow in FIG.

The reset control unit 23 that has received the error response ERR supplies the reset signal RS to the encryption key generation unit 13A, the CPU 14, and the key storage 22. The encryption key generation unit 13A, the CPU 14, and the key storage 22 reset their own states in response to the reset signal RS.

As described above, when the encryption key generation unit 13A receives the encryption key read request from the secure DMAC 21 immediately after transmitting the encryption key CRK in response to the encryption key read request from the CPU 14, the encryption key CRK is transmitted. Is not performed, and an error response ERR is sent. At this time, the reset control unit 23 that has received the error response ERR resets the states of the encryption key generation unit 13A, the CPU 14, and the key storage 22.

As a result, even if the encryption key read request RQ1 from the CPU 14 as shown in FIG. 18 is followed by the encryption key read request RQ2 from the secure DMAC21 as shown in FIG. 19, the encryption key CRK having the same value is 2. It is not continuously transmitted from the encryption key generation unit 13A. Therefore, the possibility that the encryption key CRK is leaked to the outside of the microcomputer 100 is reduced, and it is possible to prevent the leakage of plaintext data.

12 Cryptographic processing unit 13, 13A Cryptographic key generation unit 14 CPU
21 Secure DMAC
131 Random number generator 133 Output control unit

Claims (7)

An encryption processing unit that encrypts plaintext data using the encryption key received via the data bus,
An encryption key generation unit that generates the encryption key and sends the generated encryption key to the data bus in response to a first read request or a second read request.
A first transfer control unit that supplies the first read request to the encryption key generation unit and transfers the encryption key sent from the encryption key generation unit to the encryption processing unit via the data bus.
A second transfer control unit that supplies the second read request to the encryption key generation unit and transfers the encryption key sent from the encryption key generation unit to the encryption processing unit via the data bus. Including
The encryption key generation unit is characterized in that when one of the first read request and the second read request is received, the value of the encryption key is changed to another value. Semiconductor device. The encryption key generator is
A random number generator that generates a random number whose random number value changes every predetermined period and changes the random number value to another random number value in response to a random number change signal.
A register that holds the random number and outputs the held random number as an encryption key,
When the first read request or the second read request is received, the encryption key output from the register is sent to the data bus, and the first read request and the second read request are sent. The semiconductor device according to claim 1, further comprising an output control unit that supplies the random number change signal to the random number generation unit when one of the read requests is received. The semiconductor device according to claim 1 or 2, wherein the first transfer control unit is a CPU, and the second transfer control unit is a DMAC (direct memory access controller). An encryption processing unit that encrypts plaintext data using the encryption key received via the data bus,
An encryption key generation unit that generates the encryption key and sends the generated encryption key to the data bus in response to a first read request or a second read request.
A first transfer control unit that supplies the first read request to the encryption key generation unit and transfers the encryption key sent from the encryption key generation unit to the encryption processing unit via the data bus.
A second transfer control unit that supplies the second read request to the encryption key generation unit and transfers the encryption key sent from the encryption key generation unit to the encryption processing unit via the data bus. Including
When the encryption key generation unit receives the second read request after receiving the first read request within the predetermined period, the encryption key generation unit responds to the second read request. A semiconductor device characterized in that an error response is sent to the data bus instead of an encryption key. The encryption key generator is
A random number generator that generates a random number whose random number value changes every predetermined period, and a random number generator.
A first register that holds the random number and outputs the held random number as an encryption key,
A second register holding a flag indicating whether or not the first read request or the second read request has been received, and
When the first read request or the second read request is received, the encryption key output from the first register is sent to the data bus, and the encryption key is sent to the second register every predetermined period. Includes an output control unit that initializes the held flag to a state indicating that neither the first read request nor the second read request has been received.
The output control unit
When the first read request is received, the flag held in the second register is rewritten to a state indicating that the first read request or the second read request has been received.
When the second read request is received, the cipher is used when the flag held in the second register indicates that the first read request or the second read request has been received. The semiconductor device according to claim 4, wherein the error response is sent to the data bus instead of the key. A key holder that holds the encryption key sent to the data bus,
It is characterized by including a key holding unit, a first transfer control unit, and a reset control unit that resets the second transfer control unit when the error response is received via the data bus. The semiconductor device according to claim 4 or 5. The present invention according to any one of claims 4 to 6, wherein one of the first transfer control unit and the second transfer control unit is a CPU and the other is a DMAC (direct memory access controller). The semiconductor device described .

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