JP7045149B2 - Differential circuit, adjustment method, program - Google Patents

Description

The present invention relates to a differential circuit, a method of adjusting the differential circuit, and a program.

Differential circuits such as operational amplifiers are used in various electronic devices. The operational amplifier produces an output voltage according to the difference between the input voltages supplied to the transistors of the differential pair. An offset voltage is generated due to variations in the characteristics of the transistors of the differential pair. Therefore, the differential circuit includes an offset voltage adjusting circuit that adjusts the offset voltage by blowing the fuse (see, for example, Patent Document 1). For example, the offset voltage adjustment circuit includes a reference current source and corrects the differential current flowing through the differential pair by the correction current generated by the blown fuse to adjust the offset voltage.

Japanese Unexamined Patent Publication No. 2006-318337

By the way, in the above-mentioned offset voltage adjustment circuit, the correction accuracy of the offset voltage may decrease due to variations in the reference current source for each chip. Therefore, in the repair process for adjusting the offset voltage, the offset voltage is measured before and after cutting the predetermined fuse, and the fuse to be blown is determined based on the direction (positive or negative) in which the offset voltage changes and the amount of change. A method of cutting the determined fuse is used. In such a method, the repair process for each chip takes a long time, and the productivity is lowered.

An object of the present invention is to provide a differential circuit, an adjustment method, and a program that enable easy adjustment of an offset voltage.

[1] The differential circuit according to one aspect of the present invention is a differential circuit tested by a test device, in which a first transistor to which a first input current is applied to a control terminal and a second input voltage are controlled. A differential pair including a second transistor applied to the terminal, a current source for supplying the first current to the differential pair, and an output that generates an output voltage according to the differential current flowing from the differential pair. The offset voltage adjusting circuit includes an offset voltage adjusting circuit for adjusting an offset voltage of the output voltage by adjusting a current flowing from the first transistor or the second transistor, and the offset voltage adjusting circuit is the first one. A current generator that generates a correction reference current according to the current, and a plurality of trimmable fuse elements are included, and the correction current of the amount of current according to the state of the plurality of fuse elements based on the correction reference current. The correction reference current is used as the correction current source according to the control signal provided between the correction current source and the current generation unit and the correction current source and supplied from the external input terminal. Alternatively, it has a first switch circuit that supplies the external terminal for detection, and a second switch circuit that connects the correction current source to the second terminal of the first transistor or the second terminal of the second transistor. However, the first switch circuit includes an analog switch connected between the current generating unit and the detection external terminal, and the correction reference current is the detection external via only the analog switch. The second switch circuit supplied to the terminal includes a plurality of trimmable fuse elements, and the correction current source is supplied to the first transistor and the second transistor depending on the state of the plurality of fuse elements. On the other hand, the state of being disconnected is switched to a state in which the correction current source is connected to the second terminal of the first transistor, or a state in which the correction current source is connected to the second terminal of the second transistor. In order for the test apparatus to generate correction instruction data including voltage adjustment data for trimming the fuse element included in the correction current source, the first transistor and the second transistor are in phase with each other. It is configured to output the offset voltage of the output voltage when the first input voltage and the second input voltage are applied, and the correction reference current.

According to this configuration, the first switch circuit switches the path of the correction reference current between the correction current source and the detection external terminal according to the control signal. By passing the correction reference current for generating the correction current by the first switch circuit to the detection external terminal, the correction reference current can be measured by the detection external terminal. The correction current generated based on the correction reference current and the first current supplied to the first transistor and the second transistor of the differential pair are designed to be correlated with each other. If the current value of the correction reference current varies due to manufacturing variation or the like, the offset voltage adjustment accuracy deteriorates due to the variation in the correction current. On the other hand, by generating the correction current based on the measured value of the correction reference current, the number of correction steps for adjusting the offset voltage can be determined without cutting the fuse element, and easy trimming can be performed. Can be possible. In addition, since the reference current for correction can be measured, the influence of manufacturing variations and the like can be reduced, and the offset voltage can be adjusted with high accuracy.

According to this configuration, the offset voltage and the correction reference current supplied to the correction current source are set by disconnecting the correction current source from the first transistor and the second transistor by the second switch circuit. Can be measured. Then, by connecting a correction current source to one of the first transistor and the second transistor according to the polarity of the offset voltage, one of the differential currents flowing through the first transistor and the second transistor is adjusted and the offset voltage is applied. Can be adjusted. As described above, it is sufficient to prepare one correction current source, and it is possible to suppress an increase in the area occupied by the differential circuit. Since it is sufficient to prepare one correction current source, the step of the correction current that can be generated by one correction current source is compared with the case where the correction current source is connected to each of the first transistor and the second transistor. Can be increased, and the adjustment range of the offset voltage can be widened.

[3] The differential circuit according to one aspect of the present invention is a differential circuit tested by a test device, in which a first transistor to which a first input voltage is applied to a control terminal and a second input voltage are controlled. A differential pair including a second transistor applied to the terminal, a current source that supplies the first current to the differential pair, and an output that generates an output voltage according to the differential current flowing from the differential pair. The offset voltage adjusting circuit includes an offset voltage adjusting circuit for adjusting an offset voltage of the output voltage by adjusting a current flowing from the first transistor or the second transistor, and the offset voltage adjusting circuit is the first transistor. It includes a current generator that generates a reference current for correction according to the current and a plurality of non-volatile storage elements, and corrects the amount of current according to the state of the plurality of non-volatile storage elements based on the reference current for correction. The correction current source or the detection external terminal provided between the correction current source for generating a current and the current generation unit and the correction current source, depending on the control signal supplied from the external input terminal. A first switch circuit for connecting the current generation unit and a second switch circuit for connecting the correction current source to the second terminal of the first transistor or the second terminal of the second transistor. However, the first switch circuit includes an analog switch connected between the current generation unit and the detection external terminal, and the correction reference current is the detection external via only the analog switch. The second switch circuit supplied to the terminal includes a plurality of trimmable fuse elements, and the correction current source is supplied to the first transistor and the second transistor depending on the state of the plurality of fuse elements. On the other hand, the state of being disconnected is switched to a state in which the correction current source is connected to the second terminal of the first transistor, or a state in which the correction current source is connected to the second terminal of the second transistor. The first transistor and the second transistor are in phase with each other in order to generate correction instruction data including voltage adjustment data written by the test apparatus to the non-volatile storage element included in the correction current source. It is configured to output the offset voltage of the output voltage when the first input voltage and the second input voltage are applied, and the correction reference current.

According to this configuration, the first switch circuit switches the path of the correction reference current between the correction current source and the detection external terminal according to the control signal. By passing the correction reference current for generating the correction current by the first switch circuit to the detection external terminal, the correction reference current can be measured by the detection external terminal. The correction current generated based on the correction reference current and the first current supplied to the first transistor and the second transistor of the differential pair are designed to be correlated with each other. If the current value of the correction reference current varies due to manufacturing variation or the like, the offset voltage adjustment accuracy deteriorates due to the variation in the correction current. On the other hand, by generating the correction current based on the measured value of the correction reference current, it is possible to determine the number of correction steps for adjusting the offset voltage without writing to the non-volatile storage element, which is easy. Can be set. In addition, since the reference current for correction can be measured, the influence of manufacturing variations and the like can be reduced, and the offset voltage can be adjusted with high accuracy.

According to this configuration, the offset voltage and the correction reference current supplied to the correction current source are set by disconnecting the correction current source from the first transistor and the second transistor by the second switch circuit. Can be measured. Then, by connecting a correction current source to one of the first transistor and the second transistor according to the polarity of the offset voltage, one of the differential currents flowing through the first transistor and the second transistor is adjusted and the offset voltage is applied. Can be adjusted. As described above, it is sufficient to prepare one correction current source, and it is possible to suppress an increase in the area occupied by the differential circuit. Since it is sufficient to prepare one correction current source, the step of the correction current that can be generated by one correction current source is compared with the case where the correction current source is connected to each of the first transistor and the second transistor. Can be increased, and the adjustment range of the offset voltage can be widened.

[5] In the above differential circuit, it is preferable that the first switch circuit includes a resistor that pulls down the external input terminal.
According to this configuration, when the control signal is not supplied, the correction reference current can be supplied to the correction current source by pulling down by the resistance.

[6] In the above differential circuit, the correction current source includes a plurality of adjustment transistors that carry a current corresponding to the correction reference current, and the plurality of adjustment transistors carry a binary-weighted current. It is preferably formed to flow.

According to this configuration, the number of fuse elements and non-volatile storage elements required for changing the correction current is small with respect to the number of correction steps of the offset voltage, and an increase in the circuit scale can be suppressed.
[7] In the above differential circuit, the offset voltage adjusting circuit includes a MOS transistor connected in series with the current generating unit and connected to a gate terminal and a drain terminal, and gates of the plurality of adjusting transistors. Is preferably connected to the gate terminal of the MOS transistor.

According to this configuration, the MOS transistor connected in series to the correction current source and the adjustment transistor allow a current corresponding to the correction reference current to flow through each adjustment transistor.

[8] In the above differential circuit, it is preferable that the fuse element can be trimmed by laser irradiation, overcurrent, or overvoltage.
According to this configuration, the fuse element can be easily trimmed.

[9] In the above differential circuit, it is preferable that the differential circuit is integrally integrated on one semiconductor substrate.
The "integrated integration" includes a case where all the components of the circuit are formed on one substrate and a case where the main components of the circuit are formed on one substrate. A part of the element used for adjusting the circuit constants such as a resistor and a capacitor may be provided outside the substrate.

[10] The adjustment method according to one aspect of the present invention is an adjustment method executed in a test device for testing a differential circuit formed in a semiconductor element, and the differential circuit is controlled by a first input voltage. The difference between a differential pair including a first transistor applied to the terminal and a second transistor to which a second input voltage is applied to the control terminal, and a current source for supplying the first current to the differential pair. An offset voltage adjustment circuit that adjusts the offset voltage of the output voltage by adjusting the output unit that generates the output voltage according to the differential current flowing from the dynamic pair and the current flowing from the first transistor or the second transistor. The offset voltage adjusting circuit includes a current generator that generates a correction reference current corresponding to the first current, and a plurality of trimmable fuse elements, and is based on the correction reference current. A control that is provided between the correction current source that generates a correction current of the amount of current according to the state of the plurality of fuse elements and the current generation unit and the correction current source, and is supplied from an external input terminal. A first switch circuit that supplies the correction reference current to the correction current source or the detection external terminal according to the signal, and the correction current source is the second terminal of the first transistor or the second transistor. The first switch circuit includes an analog switch connected between the current generator and the detection external terminal , and includes a second switch circuit connected to the second terminal of the above. The reference current is supplied to the detection external terminal only via the analog switch, and the second switch circuit includes a plurality of trimmable fuse elements, and depending on the state of the plurality of fuse elements, the reference current is described. From the state where the correction current source is not connected to the first transistor and the second transistor, the state where the correction current source is connected to the second terminal of the first transistor, or the correction current source. The state is switched to the state of being connected to the second terminal of the second transistor, and the test apparatus applies the first input voltage and the second input voltage of the same phase to the first transistor and the second transistor. Then, a step of measuring the offset voltage of the output voltage, a step of applying the control signal and measuring the correction reference current flowing from the detection external terminal, and a measured value of the offset voltage and the correction reference. A voltage adjustment transistor for trimming the fuse element included in the correction current source based on the measured value of the current. Perform steps to generate correction instruction data including data.

According to this configuration, the first switch circuit switches the path of the correction reference current between the correction current source and the detection external terminal according to the control signal. By passing the correction reference current for generating the correction current by the first switch circuit to the detection external terminal, the correction reference current can be measured by the detection external terminal. By disconnecting the correction current source from the first transistor and the second transistor by the second switch circuit, the offset voltage and the correction reference current supplied to the correction current source can be measured. The correction current generated based on the correction reference current and the first current supplied to the first transistor and the second transistor of the differential pair are designed to be correlated with each other. If the current value of the correction reference current varies due to manufacturing variation or the like, the offset voltage adjustment accuracy deteriorates due to the variation in the correction current. On the other hand, by generating the correction current based on the measured value of the correction reference current, the number of correction steps for adjusting the offset voltage can be determined without cutting the fuse element, and easy trimming can be performed. Can be possible. In addition, since the reference current for correction can be measured, the influence of manufacturing variations and the like can be reduced, and the offset voltage can be adjusted with high accuracy.

[11] In the above adjustment method, the test apparatus has the second terminal of the first transistor and the second terminal of the second transistor by the second switch circuit according to the measured offset voltage. It is preferable to generate the correction instruction data including the polarity data for trimming the fuse element included in the second switch circuit so as to connect the correction current source to any one of the above.

According to this configuration, by connecting a correction current source to one of the first transistor and the second transistor according to the polarity of the offset voltage, one of the differential currents flowing through the first transistor and the second transistor can be transferred. The offset voltage can be adjusted by adjusting. As described above, it is sufficient to prepare one correction current source, and it is possible to suppress an increase in the area occupied by the differential circuit. Since it is sufficient to prepare one correction current source, the step of the correction current that can be generated by one correction current source is compared with the case where the correction current source is connected to each of the first transistor and the second transistor. Can be increased, and the adjustment range of the offset voltage can be widened.

[12] The adjustment method according to one aspect of the present invention is an adjustment method executed in a test device for testing a differential circuit formed in a semiconductor element, and the differential circuit is controlled by a first input voltage. The difference between a differential pair including a first transistor applied to the terminal and a second transistor to which a second input voltage is applied to the control terminal, and a current source for supplying the first current to the differential pair. An offset voltage adjustment circuit that adjusts the offset voltage of the output voltage by adjusting the output unit that generates the output voltage according to the differential current flowing from the dynamic pair and the current flowing from the first transistor or the second transistor. The offset voltage adjusting circuit includes a current generating unit that generates a correction reference current corresponding to the first current, and a plurality of non-volatile storage elements, and is based on the correction reference current. A correction current source that generates a correction current of a current amount according to the state of the plurality of non-volatile storage elements is provided between the current generation unit and the correction current source, and is supplied from an external input terminal. Depending on the control signal, the first switch circuit that connects the current generation unit to the correction current source or the detection external terminal, and the correction current source are the second terminal of the first transistor or the second transistor. The first switch circuit includes an analog switch connected between the current generator and the detection external terminal , and includes a second switch circuit connected to the second terminal of the above. The reference current is supplied to the detection external terminal only via the analog switch, and the second switch circuit includes a plurality of trimmable fuse elements, and depending on the state of the plurality of fuse elements, the reference current is described. From the state where the correction current source is not connected to the first transistor and the second transistor, the state where the correction current source is connected to the second terminal of the first transistor, or the correction current source. The state is switched to the state of being connected to the second terminal of the second transistor, and the test apparatus applies the first input voltage and the second input voltage of the same phase to the first transistor and the second transistor. Then, a step of measuring the offset voltage of the output voltage, a step of applying the control signal and measuring the correction reference current flowing from the detection external terminal, and a measured value of the offset voltage and the correction reference. A correction instruction transistor including voltage adjustment data to be written to the non-volatile storage element included in the correction current source based on the measured value of the current. Perform the steps to generate the data and.

According to this configuration, the first switch circuit switches the path of the correction reference current between the correction current source and the detection external terminal according to the control signal. By passing the correction reference current for generating the correction current by the first switch circuit to the detection external terminal, the correction reference current can be measured by the detection external terminal. By disconnecting the correction current source from the first transistor and the second transistor by the second switch circuit, the offset voltage and the correction reference current supplied to the correction current source can be measured. The correction current generated based on the correction reference current and the first current supplied to the first transistor and the second transistor of the differential pair are designed to be correlated with each other. If the current value of the correction reference current varies due to manufacturing variation or the like, the offset voltage adjustment accuracy deteriorates due to the variation in the correction current. On the other hand, by generating the correction current based on the measured value of the correction reference current, it is possible to determine the number of correction steps for adjusting the offset voltage without writing to the non-volatile storage element, which is easy. Can be set. In addition, since the reference current for correction can be measured, the influence of manufacturing variations and the like can be reduced, and the offset voltage can be adjusted with high accuracy.

[13] In the above adjustment method, the test apparatus has the second terminal of the first transistor and the second terminal of the second transistor by the second switch circuit according to the measured offset voltage. It is preferable to generate the correction instruction data including the polarity data to be written in the non-volatile storage element included in the second switch circuit so as to connect the correction current source to any one of the above.

According to this configuration, by connecting a correction current source to one of the first transistor and the second transistor according to the polarity of the offset voltage, one of the differential currents flowing through the first transistor and the second transistor can be transferred. The offset voltage can be adjusted by adjusting. As described above, it is sufficient to prepare one correction current source, and it is possible to suppress an increase in the area occupied by the differential circuit. Since it is sufficient to prepare one correction current source, the step of the correction current that can be generated by one correction current source is compared with the case where the correction current source is connected to each of the first transistor and the second transistor. Can be increased, and the adjustment range of the offset voltage can be widened.

[14] In the above adjustment method, the test apparatus sets the standard one-step shift amount when the output voltage is shifted by the correction current source in the step of generating the correction instruction data. Then, the ratio between the standard value of the correction reference current and the measured value of the correction reference current is calculated, and the deviation amount of the voltage change in one step in the measurement target is calculated based on the calculated ratio. The deviation amount is added to the standard shift amount to calculate a one-step voltage shift amount in consideration of the deviation of the measured value with respect to the standard value, and the measured value of the offset voltage is divided by the voltage shift amount to obtain the voltage. It is preferable to calculate the number of correction steps of the adjustment data.

According to this configuration, the number of correction steps corresponding to the measured value is obtained by calculating the deviation of the shift amount of the offset voltage of one step according to the current deviation of the measured value with respect to the standard value of the correction reference current. Therefore, the offset voltage can be adjusted with high accuracy.

[15] In the above adjustment method, the standard shift amount is obtained by a statistical method based on the value obtained by the design value having no variation in the correction reference current or the measurement result of the manufactured semiconductor element. It is preferably a value.

[16] The program according to one aspect of the present invention is a program executed in a test device for testing a differential circuit formed in a semiconductor element, and in the differential circuit, a first input voltage is used as a control terminal. A differential pair including a first transistor to which a second input voltage is applied and a second transistor to which a second input voltage is applied to a control terminal, a current source for supplying a first current to the differential pair, and the differential pair. An output unit that generates an output voltage according to the differential current flowing from the transistor, an offset voltage adjusting circuit that adjusts the offset voltage of the output voltage by adjusting the current flowing from the first transistor or the second transistor, and an offset voltage adjusting circuit. The offset voltage adjusting circuit includes a current generator that generates a correction reference current corresponding to the first current, and a plurality of trimmable fuse elements, and is based on the correction reference current. A control signal provided between a correction current source that generates a correction current of a current amount according to the state of a plurality of fuse elements and the current generation unit and the correction current source, and supplied from an external input terminal. Correspondingly, the first switch circuit that supplies the correction reference current to the correction current source or the detection external terminal, and the correction current source is the second terminal of the first transistor or the second transistor of the second transistor. The first switch circuit includes a second switch circuit connected to two terminals, and the first switch circuit includes an analog switch connected between the current generating unit and the detection external terminal, and the correction reference current. Is supplied to the detection external terminal only via the analog switch, and the second switch circuit includes a plurality of trimmable fuse elements, and the correction is performed according to the state of the plurality of fuse elements. From the state where the current source is not connected to the first transistor and the second transistor, the state where the correction current source is connected to the second terminal of the first transistor, or the state where the correction current source is the first. It switches to the state of being connected to the second terminal of the two transistors, and the program executed by the test apparatus is the first input voltage and the second input voltage in phase with the first transistor and the second transistor. A step of applying the above to measure the offset voltage of the output voltage, a step of applying the control signal to measure the correction reference current flowing from the detection external terminal, and a step of measuring the offset voltage and the correction. Transistor the fuse element included in the correction current source based on the measured value of the reference current. Includes a step of generating correction instruction data, including voltage adjustment data for charging.

According to this configuration, the first switch circuit switches the path of the correction reference current between the correction current source and the detection external terminal according to the control signal. By passing the correction reference current for generating the correction current by the first switch circuit to the detection external terminal, the correction reference current can be measured by the detection external terminal. By disconnecting the correction current source from the first transistor and the second transistor by the second switch circuit, the offset voltage and the correction reference current supplied to the correction current source can be measured. The correction current generated based on the correction reference current and the first current supplied to the first transistor and the second transistor of the differential pair are designed to be correlated with each other. If the current value of the correction reference current varies due to manufacturing variation or the like, the offset voltage adjustment accuracy deteriorates due to the variation in the correction current. On the other hand, by generating the correction current based on the measured value of the correction reference current, the number of correction steps for adjusting the offset voltage can be determined without cutting the fuse element, and easy trimming can be performed. Can be possible. In addition, since the reference current for correction can be measured, the influence of manufacturing variations and the like can be reduced, and the offset voltage can be adjusted with high accuracy.

[17] In the above program, the program executed by the test apparatus is the second terminal of the first transistor and the second transistor by the second switch circuit according to the measured offset voltage. The step of generating the correction instruction data including the polarity data for trimming the fuse element included in the second switch circuit so as to connect the correction current source to any one of the second terminals may be included. preferable.

According to this configuration, by connecting a correction current source to one of the first transistor and the second transistor according to the polarity of the offset voltage, one of the differential currents flowing through the first transistor and the second transistor can be transferred. The offset voltage can be adjusted by adjusting. As described above, it is sufficient to prepare one correction current source, and it is possible to suppress an increase in the area occupied by the differential circuit. Since it is sufficient to prepare one correction current source, the step of the correction current that can be generated by one correction current source is compared with the case where the correction current source is connected to each of the first transistor and the second transistor. Can be increased, and the adjustment range of the offset voltage can be widened.

[18] The program according to one aspect of the present invention is a program executed in a test device for testing a differential circuit formed in a semiconductor element, and in the differential circuit, a first input voltage is used as a control terminal. A differential pair including a first transistor to which a second input voltage is applied and a second transistor to which a second input voltage is applied to a control terminal, a current source for supplying a first current to the differential pair, and the differential pair. An output unit that generates an output voltage according to the differential current flowing from the transistor, an offset voltage adjusting circuit that adjusts the offset voltage of the output voltage by adjusting the current flowing from the first transistor or the second transistor, and an offset voltage adjusting circuit. The offset voltage adjusting circuit includes a current generating unit that generates a correction reference current corresponding to the first current, and a plurality of non-volatile storage elements, and the plurality of the offset voltage adjusting circuits are based on the correction reference current. A control signal provided between the correction current source that generates a correction current of the amount of current according to the state of the non-volatile storage element and the current generation unit and the correction current source, and supplied from an external input terminal. A first switch circuit for connecting the current generation unit to the correction current source or the detection external terminal, and the correction current source being the second terminal of the first transistor or the second transistor of the second transistor. The first switch circuit includes a second switch circuit connected to two terminals, and the first switch circuit includes an analog switch connected between the current generating unit and the detection external terminal, and the correction reference current. Is supplied to the detection external terminal only via the analog switch, and the second switch circuit includes a plurality of trimmable fuse elements, and the correction is performed according to the state of the plurality of fuse elements. From the state where the current source is not connected to the first transistor and the second transistor, the state where the correction current source is connected to the second terminal of the first transistor, or the state where the correction current source is the first. It switches to the state of being connected to the second terminal of the two transistors, and the program executed by the test apparatus is the first input voltage and the second input voltage in phase with the first transistor and the second transistor. To measure the offset voltage of the output voltage, the step to apply the control signal and measure the correction reference current flowing from the detection external terminal, and the measured value of the offset voltage and the correction. Voltage adjustment to be written to the non-volatile storage element included in the correction current source based on the measured value of the reference current. Includes a step to generate correction instruction data, including section data.

According to this configuration, the first switch circuit switches the path of the correction reference current between the correction current source and the detection external terminal according to the control signal. By passing the correction reference current for generating the correction current by the first switch circuit to the detection external terminal, the correction reference current can be measured by the detection external terminal. By disconnecting the correction current source from the first transistor and the second transistor by the second switch circuit, the offset voltage and the correction reference current supplied to the correction current source can be measured. The correction current generated based on the correction reference current and the first current supplied to the first transistor and the second transistor of the differential pair are designed to be correlated with each other. If the current value of the correction reference current varies due to manufacturing variation or the like, the offset voltage adjustment accuracy deteriorates due to the variation in the correction current. On the other hand, by generating the correction current based on the measured value of the correction reference current, it is possible to determine the number of correction steps for adjusting the offset voltage without writing to the non-volatile storage element, which is easy. Can be set. In addition, since the reference current for correction can be measured, the influence of manufacturing variations and the like can be reduced, and the offset voltage can be adjusted with high accuracy.

[19] In the above program, the program executed by the test apparatus is the second terminal of the first transistor and the second transistor by the second switch circuit according to the measured offset voltage. It is preferable to include a step of generating the correction instruction data including the polarity data to be written to the non-volatile storage element included in the second switch circuit so as to connect the correction current source to any one of the second terminals. ..

According to this configuration, by connecting a correction current source to one of the first transistor and the second transistor according to the polarity of the offset voltage, one of the differential currents flowing through the first transistor and the second transistor can be transferred. The offset voltage can be adjusted by adjusting. As described above, it is sufficient to prepare one correction current source, and it is possible to suppress an increase in the area occupied by the differential circuit. Since it is sufficient to prepare one correction current source, the step of the correction current that can be generated by one correction current source is compared with the case where the correction current source is connected to each of the first transistor and the second transistor. Can be increased, and the adjustment range of the offset voltage can be widened.

[20] In the above program, in the step of generating the correction instruction data, the test apparatus sets the standard shift amount of one step when shifting the output voltage by the correction current source as the standard shift amount. , The ratio of the standard value of the correction reference current and the measured value of the correction reference current is calculated, and based on the calculated ratio, the deviation amount of the voltage change in one step in the measurement target is calculated, and the standard. The deviation amount is added to the shift amount to calculate a one-step voltage shift amount in consideration of the deviation of the measured value with respect to the standard value, and the measured value of the offset voltage is divided by the voltage shift amount to adjust the voltage. It is preferable to calculate the number of correction steps of the data.

According to this configuration, the number of correction steps corresponding to the measured value is obtained by calculating the deviation of the shift amount of the offset voltage of one step according to the current deviation of the measured value with respect to the standard value of the correction reference current. Therefore, the offset voltage can be adjusted with high accuracy.

[21] In the above program, the standard shift amount is a value obtained by a design value having no variation in the correction reference current, or a value obtained by a statistical method based on the measurement result of the manufactured semiconductor element. Is preferable.
[22] An adjustment method executed in a test device for testing a differential circuit formed in a semiconductor element, wherein the differential circuit includes a first transistor to which a first input voltage is applied to a control terminal and a first transistor. A differential pair including a second transistor in which two input voltages are applied to the control terminal, a current source for supplying the first current to the differential pair, and an output corresponding to the differential current flowing from the differential pair. The offset voltage adjusting circuit includes an output unit that generates a voltage and an offset voltage adjusting circuit that adjusts the offset voltage of the output voltage by adjusting the current flowing from the first transistor or the second transistor. A current generating unit that generates a correction reference current according to the first current, and a plurality of trimmable fuse elements are included, and the state of the plurality of fuse elements is adjusted based on the correction reference current. The correction reference current provided between the correction current source that generates the correction current of the amount of current and the current generation unit and the correction current source is provided according to the control signal supplied from the external input terminal. A first switch circuit that supplies the correction current source or an external terminal for detection, and a second switch that connects the correction current source to the second terminal of the first transistor or the second terminal of the second transistor. The second switch circuit includes a circuit and a plurality of trimmable fuse elements, and the correction current source is the first transistor and the second transistor depending on the state of the plurality of fuse elements. From a state in which the current source for correction is connected to the second terminal of the first transistor, or a state in which the current source for correction is connected to the second terminal of the second transistor. The test device switches between a step of applying the first input voltage and the second input voltage having the same phase to the first transistor and the second transistor to measure the offset voltage of the output voltage. The correction current source is based on the step of applying the control signal and measuring the correction reference current flowing from the detection external terminal, the measured value of the offset voltage, and the measured value of the correction reference current. In the step of generating the correction instruction data including the voltage adjustment data for trimming the fuse element included in the above and the step of generating the correction instruction data, the output voltage is shifted by the correction current source. The standard shift amount of one step is set as the standard shift amount, and the correction reference current is used. The ratio between the standard value of the flow and the measured value of the reference current for correction is calculated, and based on the calculated ratio, the deviation amount of the voltage change of one step in the measurement target is calculated, and the deviation amount is calculated with respect to the standard shift amount. The number of correction steps of the voltage adjustment data is calculated by adding the amounts to calculate the voltage shift amount of one step in consideration of the deviation of the measured value from the standard value, and dividing the measured value of the offset voltage by the voltage shift amount. Is calculated.
[23] An adjustment method executed in a test device for testing a differential circuit formed on a semiconductor element, wherein the differential circuit includes a first transistor to which a first input voltage is applied to a control terminal and a first transistor. A differential pair including a second transistor to which two input voltages are applied to the control terminal, a current source that supplies the first current to the differential pair, and an output corresponding to the differential current flowing from the differential pair. The offset voltage adjusting circuit includes an output unit that generates a voltage and an offset voltage adjusting circuit that adjusts the offset voltage of the output voltage by adjusting the current flowing from the first transistor or the second transistor. A current generating unit that generates a correction reference current according to the first current, and a plurality of non-volatile storage elements are included, and based on the correction reference current, depending on the state of the plurality of non-volatile storage elements. The correction current source provided between the correction current source for generating the correction current of the amount of the current amount and the current generation unit and the correction current source, and according to the control signal supplied from the external input terminal, the correction current source. Alternatively, a first switch circuit that connects the current generator to the detection external terminal and a second switch that connects the correction current source to the second terminal of the first transistor or the second terminal of the second transistor. The second switch circuit includes a circuit, and the second switch circuit includes a plurality of non-volatile storage elements, and the correction current source is the first transistor and the second, depending on the state of the plurality of non-volatile storage elements. From a state in which the correction current source is not connected to the transistor to a state in which the correction current source is connected to the second terminal of the first transistor, or a state in which the correction current source is connected to the second terminal of the second transistor. In the test apparatus, the first input voltage and the second input voltage having the same phase are applied to the first transistor and the second transistor to measure the offset voltage of the output voltage. , The correction current is based on the step of applying the control signal and measuring the correction reference current flowing from the detection external terminal, the measured value of the offset voltage, and the measured value of the correction reference current. In the step of generating the correction instruction data including the voltage adjustment data to be written to the non-volatile storage element included in the source and the step of generating the correction instruction data, the output voltage is shifted by the correction current source. The standard shift amount of one step is used as the standard shift amount, and the standard value of the correction reference current and the correction reference are used. The ratio of the current to the measured value is calculated, the deviation amount of the voltage change in one step in the measurement target is calculated based on the calculated ratio, and the deviation amount is added to the standard shift amount to obtain the standard value. The voltage shift amount of one step considering the deviation of the measured value is calculated, and the measured value of the offset voltage is divided by the voltage shift amount to calculate the number of correction steps of the voltage adjustment data.

According to the present invention, the offset voltage can be easily adjusted.

A circuit diagram showing an example of an operational amplifier. A circuit diagram showing an example of a trimming block. A circuit diagram showing an example of a selection switch. The schematic diagram which shows an example of the system which performs repair processing. Flow chart of repair data creation process in the test device. An explanatory diagram showing the relationship between the trimming data, the repair step, and the shift amount. An explanatory diagram showing an example of calculation of the number of repair steps. A waveform diagram showing a simulation result of offset correction processing. Explanatory drawing explaining the offset voltage. Explanatory drawing which shows the adjustment of an offset voltage.

Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are designated by the same reference numerals, and duplicate description may be omitted as appropriate. Further, the embodiment is not limited to the invention, but is an example, and all the features and combinations thereof described in the embodiment are not necessarily essential to the invention.

In the present specification, the "state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. It also includes the case of being indirectly connected via other members that do not affect the state.

Similarly, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, and also electrically. It also includes the case of being indirectly connected via other members that do not affect the connection state.

Further, "the signal A (voltage, current) corresponds to the signal B (voltage, current)" means that the signal A has a correlation with the signal B. Specifically, (i) when signal A is signal B, (ii) when signal A is proportional to signal B, (iii) when signal A is obtained by level-shifting signal B, (iv). When the signal A is obtained by amplifying the signal B, (v) when the signal A is obtained by inverting the signal B, (vi) or any combination thereof, etc. are meant. Those skilled in the art will understand that the range of "according to" is determined according to the types and uses of signals A and B.

As shown in FIG. 1, the operational amplifier 10 includes a reference current source 11, a differential pair 12, a current source 13, an output unit 14, and an offset voltage adjusting circuit 15, which are integrally integrated on one semiconductor substrate. There is. The operational amplifier 10 operates based on the high potential voltage VDD supplied from the power supply terminal T11 and the low potential voltage VSS supplied from the power supply terminal T12. The operational amplifier 10 amplifies the potential difference between the non-inverting input terminal INP and the inverting input terminal INN, and outputs the output voltage Vo from the output terminal T13.

The reference current source 11 includes a transistor M11 and a current source 21. The transistor M11 of this embodiment is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). For example, a P-channel MOSFET can be used as the transistor M11. The source terminal of the transistor M11 is connected to a power supply wiring (hereinafter referred to as power supply VDD) to which a high potential voltage VDD is supplied. The drain terminal of the transistor M11 is connected to the first terminal of the current source 21, and the second terminal of the current source 21 is connected to the power supply wiring (hereinafter, power supply wiring VSS) in which the low potential voltage VSS is made of steel balls. The gate terminal of the transistor M11 is connected to the drain terminal of the transistor M11. The gate voltage of the transistor M11 is supplied to the current source 13 and the output unit 14 as the bias voltage VB1.

The current source 13 includes a transistor M12. The transistor M12 of this embodiment is a MOSFET. For example, a P-channel MOSFET can be used as the transistor M12. The source terminal of the transistor M12 is connected to the power supply wiring VDD, and the drain terminal of the transistor M12 is connected to the differential pair 12. The gate terminal (control terminal) of the transistor M12 is connected to the gate terminal of the transistor M11 of the reference current source 11. The current source 13 supplies the differential pair 12 with a tail current ID corresponding to the bias voltage VB1 supplied to the gate terminal of the transistor M12.

The differential pair 12 includes a pair of transistors M1 and M2. The transistors M1 and M2 of this embodiment are MOSFETs. For example, P-channel MOSFETs can be used as the transistors M1 and M2. The gate terminal (control terminal) of the transistor M1 is connected to the non-inverting input terminal INP, and the gate terminal (control terminal) of the transistor M2 is connected to the inverting input terminal INN. The source terminal of the transistor M1 and the source terminal of the transistor M2 are connected to each other, and the connection point N1 is connected to the drain terminal of the transistor M12 included in the current source 13. The drain terminals of the transistors M1 and M2 are connected to the output unit 14. The input voltage VIP of the non-inverting input terminal INP is applied to the gate terminal of the transistor M1. The input voltage VIN of the inverting input terminal INN is applied to the gate terminal of the transistor M2. The differential pair 12 generates differential currents I1 and I2 according to the input voltages VIP and VIN.

The output unit 14 has a load circuit 31 and a reference current source 32.
The load circuit 31 is, for example, a cascode current mirror circuit. The load circuit 31 is an active load connected to the differential pair 12.

The load circuit 31 includes transistors M21 to M14. In this embodiment, the transistors M21 to M24 are MOSFETs. For example, N-channel MOSFETs can be used as the transistors M21 to M24.

The transistor M21 is connected in series with the transistor M2 of the differential pair 12. The drain terminal of the transistor M21 is connected to the drain terminal of the transistor M2, and the source terminal of the transistor M21 is connected to the power supply wiring VSS. The transistor M22 is connected in series with the transistor M1 of the differential pair 12. The drain terminal of the transistor M22 is connected to the drain terminal of the transistor M1, and the source terminal of the transistor M22 is connected to the power supply wiring VSS. The gate terminal of the transistor M21 and the gate terminal of the transistor M22 are connected to each other.

The drain terminal of the transistor M21 is connected to the source terminal of the transistor M23. The drain terminal of the transistor M22 is connected to the source terminal of the transistor M24. A bias voltage VB3 is supplied to the gate terminal of the transistor M23 and the gate terminal of the transistor M24 from a bias circuit (not shown). The gate terminals of the transistor M21 and the transistor M22 are connected to the drain terminal of the transistor M23.

The drain terminal of the transistor M23 and the drain terminal of the transistor M24 are connected to the reference current source 32.
The reference current source 32 is a constant current circuit and maintains an appropriate bias state of the load circuit 31. The reference current source 32 includes transistors M25 to M28. In this embodiment, the transistors M25 to M28 are MOSFETs. For example, P-channel MOSFETs can be used as the transistors M25 to M28. The source terminal of the transistor M25 and the source terminal of the transistor M26 are connected to the power supply wiring VDD. The drain terminal of the transistor M25 is connected to the source terminal of the transistor M27, and the drain terminal of the transistor M27 is connected to the drain terminal of the transistor M23 of the load circuit 31. The drain terminal of the transistor M36 is connected to the source terminal of the transistor M28, and the drain terminal of the transistor M28 is connected to the drain terminal of the transistor M24 of the load circuit 31.

The gate terminal of the transistor M25 and the gate terminal of the transistor M26 are connected to each other, and a bias voltage VB1 is supplied. The gate terminal of the transistor M27 and the gate terminal of the transistor M28 are connected to each other, and a bias voltage VB2 is supplied from a bias circuit (not shown).

The node between the load circuit 31 and the reference current source 32, specifically, the node N2 between the drain terminal of the transistor M24 and the drain terminal of the transistor M28, is connected to the output terminal T13. The output unit 14 outputs an output voltage Vo equal to the voltage of the node N2 from the output terminal T13.

The offset voltage adjusting circuit 15 is connected to the differential pair 12 and adjusts the differential current of the differential pair 12.
The offset voltage adjusting circuit 15 includes a current generating unit 41, switch circuits 42 and 43, a transistor M31, and a correction current source 44.

The current generation unit 41 includes the transistor M32. The transistor M32 is, for example, a MOSFET. As the transistor M32, for example, a P-channel MOSFET can be used. The source terminal of the transistor M32 is connected to the power supply wiring VDD. The gate terminal of the transistor M32 is connected to the gate terminal of the transistor M12. A bias voltage VB1 is applied to the gate terminal of the transistor M12. The transistor M32 passes a correction reference current Ia corresponding to the tail current ID supplied to the differential pair 12 by the transistor M12 of the current source 13.

The drain terminal of the transistor M32 is connected to the transistor M31 via the switch circuit 42.
The switch circuit 42 includes analog switches SW1 and SW2, an inverter circuit 51, and a resistor R1. The analog switches SW1 and SW2 include a P-channel MOSFET and an N-channel MOSFET connected in parallel. The first terminal of the analog switch SW1 is connected to the drain terminal of the transistor M32. The second terminal of the analog switch SW1 is connected to the external terminal T21.

The first terminal of the analog switch SW2 is connected to the drain terminal of the transistor M32. The second terminal of the analog switch SW2 is connected to the transistor M31. The transistor M31 is a MOSFET. As the transistor M31, for example, an N-channel MOSFET can be used. The drain terminal of the transistor M31 is connected to the analog switch SW2. The source terminal of the transistor M31 is connected to the power supply wiring VSS.

The input terminal of the inverter circuit 51 is connected to the external terminal T22. Further, the input terminal of the inverter circuit 51 is connected to the first terminal of the resistor R1, and the second terminal of the resistor R1 is connected to the power supply wiring VSS. The output terminal of the inverter circuit 51 is connected to the inverting control terminal of the analog switch SW1 and the non-inverting control terminal of the analog switch SW2. The inverting control terminal of the analog switch SW1 and the non-inverting control terminal of the analog switch SW2 are connected to the external terminal T22. The control signal SC is supplied to the external terminal T22. The control signal SC is supplied from the test device in the repair process described later. The inverter circuit 51 outputs an inverting control signal SCX in which the control signal SC is logically inverted. The control signal SC and the inverting control signal SCX are supplied to the analog switches SW1 and SW2.

The analog switch SW1 is turned on in response to the H level (for example, high potential voltage VDD level) control signal SC and the L level (for example, low potential voltage VSS level) inverting control signal SCX, and the L level control signal SC1 is turned on. And turns off in response to the H level inversion control signal SCX. The analog switch SW2 turns off in response to the H level control signal SC and the L level inversion control signal SCX, and turns on in response to the L level control signal SC and the H level inversion control signal SCX. That is, the analog switches SW1 and SW2 are complementarily turned on and off based on the control signal SC. When the analog switch SW1 is turned on and the analog switch SW2 is turned off, the correction reference current Ia of the transistor M32 flows toward the external terminal T21 via the turned on analog switch SW1. On the other hand, when the analog switch SW1 is turned off and the analog switch SW2 is turned on, the correction reference current Ia flows through the transistor M31 via the turned on analog switch SW2.

When the control signal SC is not supplied, the external terminal T22 is pulled down to the low potential voltage VSS by the resistance R1. Therefore, the inverter circuit 51 outputs the H level inverting control signal SCX. The analog switch SW1 is turned off and the analog switch SW2 is turned on by the pull-down by the inversion control signal SCX and the resistance R1. As a result, the correction reference current Ia flows through the transistor M31 via the turned on analog switch SW2.

As shown in FIG. 2, the correction current source 44 of the offset voltage adjusting circuit 15 has eight trimming blocks 61 to 68.
The trimming block 61 includes a current source 61a, transistors M41a, M41b, resistors R11a, R11b, and a fuse element F1. The transistors M41a and M41b are, for example, MOSFETs. In this embodiment, N-channel MOSFETs can be used as the transistors M41a and M41b.

The source terminal of the transistor M41a is connected to the power supply wiring VSS, the drain terminal of the transistor M41a is connected to the source terminal of the transistor M41b, and the drain terminal of the transistor M41b is connected to the switch circuit 43 shown in FIG. The gate terminal of the transistor M41a is connected to the gate terminal of the transistor M31.

The first terminal of the current source 61a is connected to the power supply wiring VDD, and the second terminal of the current source 61a is connected to the gate terminal of the transistor M41b. The gate terminal of the transistor M41b is connected to the first terminal of the resistor R11a, and the second terminal of the resistor R11a is connected to the first terminal of the fuse element F1. The second terminal of the fuse element F1 is connected to the first terminal of the resistor R11b, and the second terminal of the resistor R11b is connected to the power supply wiring VSS.

The fuse element F1 is a trimming element. In the present embodiment, the fuse element F1 is an element that can be cut by irradiation with a laser. When the fuse element F1 is not blown, the transistor M41b is turned off, so that no current flows through the transistor M41a. When the fuse element F1 is blown, the transistor M41b is turned on. As a result, the transistor M41a of the trimming block 61 passes the correction current Ib1 proportional to the correction reference current Ia flowing through the transistor M31.

The trimming blocks 62 to 68 have the same configuration as the trimming block 61. The trimming blocks 62 to 68 include current sources 62a to 68a, transistors M42a to M48a, M42b to M48b, resistors R12a to R18a, R12b to R18b, and fuse elements F2 to F8. When the fuse elements F2 to F8 are not blown, the transistors M42b to M48b are turned off, so that no current flows through the transistors M42a to M48a. When the fuse elements F2 to F8 are blown, the transistors M42b to M48b are turned on. As a result, the transistors M42a to M48a pass the correction currents Ib2 to Ib8 proportional to the correction reference current Ia flowing through the transistor M31.

In the present embodiment, the transistors M41a to M48a of the trimming blocks 61 to 68 are set to pass the correction currents Ib1 to Ib8 weighted by the binary. For example, the transistor M41a is set to pass a correction current Ib1 equal to (× 1) the correction reference current Ia. The transistor M42a is set to pass a correction current Ib2 that is twice (× 2) the correction reference current Ia. The transistor M43a is set to pass a correction current Ib3 that is four times (× 4) the correction reference current Ia. The transistor M44a is set to pass a correction current Ib4 that is eight times (× 8) the correction reference current Ia. The transistor M45a is set to pass a correction current Ib5 that is 16 times (× 16) the correction reference current Ia. The transistor M46a is set to pass a correction current Ib6 that is 32 times (× 32) the correction reference current Ia. The transistor M47a is set to pass a correction current Ib7 that is 64 times (× 64) the correction reference current Ia. The transistor M48a is set to pass a correction current Ib8 that is 128 times (× 128) the correction reference current Ia.

In the trimming blocks 61 to 68, the transistors M41a, M41b to M48a, and M48b are connected in parallel between the switch circuit 43 shown in FIG. 1 and the power supply wiring VSS. Therefore, the current obtained by synthesizing the current flowing through the transistor of the trimming block including the blown fuse flows from the switch circuit 43 toward the power supply wiring VDD as the correction current Ic. The transistors M41a to M48a of the trimming blocks 61 to 68 are set to pass a binary-weighted current. Therefore, the correction current source 44 changes from the correction current Ic equal to the correction reference current Ia (× 1) to 255 times the correction reference current Ia (× 255) by selectively cutting the fuse elements F1 to F8. ) Correction current Ic can be passed.

As shown in FIG. 1, the switch circuit 43 selectively connects the correction current source 44 to the transistor M1 or the transistor M2 of the differential pair 12. In the switch circuit 43, a transistor for connecting the correction current source 44 is set according to the polarity of the offset voltage of the operational amplifier 10.

FIG. 3 shows an example of the configuration of the switch circuit 43. The switch circuit 43 includes analog switches SW11, SW12, inverter circuits 71a, 71b, current sources 72a, 72b, fuse elements F11, F12, and resistors R21, R22.

The analog switch SW11 includes a P-channel MOSFET and an N-channel MOSFET connected in parallel. The analog switch SW11 is connected between the drain terminal of the transistor M1 shown in FIG. 1 and the correction current source 44.

The current source 72a, the fuse element F11, and the resistor R21 are connected in series between the power supply wiring VDD and the power supply wiring VSS in this order. That is, the first terminal of the current source 72a is connected to the power supply wiring VDD, and the second terminal of the current source 72a is connected to the first terminal of the fuse element F11. The second terminal of the fuse element F11 is connected to the first terminal of the resistor R21, and the second terminal of the resistor R21 is connected to the power supply wiring VSS. The node N11 between the fuse element F11 and the resistor R21 is connected to the input terminal of the inverter circuit 71a and the inverting input terminal of the analog switch SW11. The output terminal of the inverter circuit 71a is connected to the non-inverting input terminal of the analog switch SW11.

The fuse element F11 is a trimming element. In the present embodiment, the fuse element F11 is an element that can be cut by irradiation with a laser. When the fuse element F11 is not blown, the analog switch SW11 is off. When the fuse element F11 is blown, the analog switch SW11 is turned on. The correction current source 44 shown in FIG. 1 is connected to the drain terminal of the transistor M1 by the analog switch SW11 turned on.

The analog switch SW12 includes a P-channel MOSFET and an N-channel MOSFET connected in parallel. The analog switch SW12 is connected between the drain terminal of the transistor M2 shown in FIG. 1 and the correction current source 44.

The current source 72b, the fuse element F12, and the resistor R22 are connected in series between the power supply wiring VDD and the power supply wiring VSS in this order. That is, the first terminal of the current source 72b is connected to the power supply wiring VDD, and the second terminal of the current source 72b is connected to the first terminal of the fuse element F12. The second terminal of the fuse element F12 is connected to the first terminal of the resistor R22, and the second terminal of the resistor R22 is connected to the power supply wiring VSS. The node N12 between the fuse element F12 and the resistor R22 is connected to the input terminal of the inverter circuit 71b and the inverting input terminal of the analog switch SW12. The output terminal of the inverter circuit 71b is connected to the non-inverting input terminal of the analog switch SW12.

The fuse element F12 is a trimming element. In the present embodiment, the fuse element F12 is an element that can be cut by irradiation with a laser. When the fuse element F12 is not blown, the analog switch SW12 is off. When the fuse element F12 is blown, the analog switch SW12 is turned on. The correction current source 44 shown in FIG. 1 is connected to the drain terminal of the transistor M2 by the analog switch SW12 turned on.

Therefore, in this switch circuit 43, by disconnecting one of the fuse elements F11 and F12, the correction current source 44 shown in FIG. 1 is connected to the drain terminal of the transistor M1 or the drain terminal of the transistor M2.

Here, the outline of the offset voltage and the correction of the offset voltage will be described.
As shown in FIG. 9A, common-mode input voltages VIP and VIN are applied to the transistors M1 and M2 of the differential pair 12. When the characteristics of the transistors M1 and M2 vary, the current I-ΔI flows through the transistor M1 and the current flows through the transistor M2 due to the difference between the gate-source voltage Vgs1 of the transistor M1 and the gate-source voltage Vgs2 of the transistor M2. I + ΔI flows. The current I is ½ of the tail current ID supplied by the current source 13 to the differential pair 12.

As shown in FIG. 9B, in the correction current source 44, a correction current Ic equal to the difference (2ΔI) between the current I−ΔI of the transistor M1 and the current I + ΔI of the transistor M2 is generated. Then, the correction current source 44 is connected to the side where the current is increased by the switch circuit 43, that is, to the drain terminal of the transistor M2. As a result, the offset voltage is corrected by reducing the correction current Ic from the current I + ΔI flowing through the transistor M2.

Next, the repair process of the operational amplifier 10 described above will be described.
FIG. 4 shows an outline of a system that corrects (repairs) the offset voltage.
The system includes a test device 110 and a trimming device 120. The outline operation of the system will be described. The test device 110 measures the electrical characteristics of each semiconductor element 100 formed on the wafer W1. The test device 110 generates correction instruction data 130 corresponding to the semiconductor element 100 based on the measurement result. The trimming device 120 trims the fuse element of the semiconductor element 100 based on the correction instruction data 130.

A plurality of semiconductor elements 100 are formed on the wafer W1. Each semiconductor element 100 includes the above-mentioned operational amplifier 10. A plurality of pads 101 and a plurality of fuse elements 102 are formed in each semiconductor element 100. The plurality of pads 101 schematically show a part of the above-mentioned external terminals T11 to T13, T21, and T22. The fuse element 102 schematically shows a part of the fuse elements F1 to F8 shown in FIG. 2 and the fuse elements F11 and F12 shown in FIG. By cutting the wafer W1 along a solid line, a chip-shaped semiconductor element 100 can be obtained.

The test device 110 brings the probe 110a into contact with the pad 101 of the semiconductor element 100. Although one probe 110a is shown in FIG. 4, the test device 110 has a probe 110a necessary for an operation test of each semiconductor element 100 or the like.

The test device 110 stores the program 111 and various data 112. The program 111 includes a repair processing program for each semiconductor element 100. The various data 112 include data necessary for the repair process and fuse blown data determined by the repair process. The test device 110 carries out a repair process for each semiconductor element 100 of the wafer W1 according to the program 111.

In the repair process, the test device 110 refers to various data 112 and generates correction instruction data necessary for the repair process.
The correction instruction data includes voltage correction data for trimming the fuse elements F1 to F8 shown in FIG. 2 to adjust the offset voltage. Further, the correction instruction data includes polarity data in which the fuse elements F11 and F12 shown in FIG. 3 are trimmed and the correction current source 44 is connected to any one of the transistors M1 and M2.

The various data 112 include data of the operational amplifier 10 (see FIG. 1) formed in the semiconductor element 100 to be repaired. This data includes standard electrical characteristic values for op amp 10. The standard characteristic value includes a standard value I0 of the current flowing through the correction current source 44 shown in FIG. 1, and a standard value (standard shift amount) A of the voltage shift amount in the correction current source 44.

The standard value I0 of the current of the correction current source 44 is, for example, a value set at the time of circuit design (design value) or a measurement value of a plurality of (for example, several lots of wafers) semiconductor elements 100 by a statistical method. The obtained values (for example, intermediate values, mean values, peak values of a predetermined distribution, etc.) can be used.

The standard shift amount A is a change amount (shift amount) of the offset voltage per step of the fuse to be trimmed. The standard shift amount A is obtained by dividing the amount of change in the offset voltage (shift amount) when the fuse is trimmed by the number of steps of the trimmed fuse. The standard shift amount A is, for example, a value (design value) set at the time of circuit design, or a value obtained by a statistical method from the measured values of a plurality of (for example, several lots of wafers) semiconductor elements 100 (for example). , Median, mean, peak value of predetermined distribution, etc.) can be used.

The number of steps is a current value gradation value in the correction current source, and is the number of current amounts that can be set by trimming the fuse elements F1 to F8 in the correction current source 44. The correction current source 44 of the present embodiment has eight trimming blocks 61 to 68, and the transistors M41a to M48a of each trimming block 61 to 68 are configured to pass a binary weighted current. By trimming the fuse elements F1 to F8, the currents flowing through the transistors M41a to M48a are combined to generate the correction current Ic. When 1 bit of repair data is assigned to each of the fuse elements F1 to F8, the repair data for trimming the correction current source 44 becomes "8" bits. Therefore, the maximum value of the variable steps (number of steps) of the correction current Ic generated by the correction current source 44 is “256”.

Then, the data indicating the fuse required to adjust the offset voltage is used as the voltage correction data, and the value of the voltage correction data is used as the number of correction steps. The test device 110 measures the characteristics of the operational amplifier 10 and calculates the number of correction steps of the voltage correction data based on the measurement result. Then, the correction instruction data 130 including the voltage correction data is generated.

The correction step number Rs is data of the number of bits (8 bits in this embodiment) corresponding to the fuse included in the correction current source 44. The position of each bit in the correction step number Rs corresponds to the transistors M41a to M48a included in the correction current source 44 and weighted by the binary. As for the value of each bit, for example, "1" indicates a trimming instruction and "0" indicates no trimming. For example, when only the first bit (LSB) is "1", the fuse element F1 of the trimming block 61 shown in FIG. 2 is trimmed (cut). As a result, a current having a current amount that is once the correction reference current Ia flows through the transistor M41a. When only the 8th bit (MSB) is "1", the fuse element F8 of the trimming block 68 shown in FIG. 2 is trimmed (cut). As a result, a current having a current amount 128 times that of the correction reference current Ia flows through the transistor M48a.

FIG. 5 shows a schematic flow of the repair process executed by the test apparatus 110. The test device 110 executes the processes of steps 201 to 205 and generates correction instruction data 130. The processing of steps 201 to 205 will be described with reference to FIGS. 1 to 4.

In step 201, the test device 110 measures the offset voltage Voff. More specifically, the test device 110 supplies the high potential voltage VDD and the low potential voltage VSS to the power supply terminals T11 and T12 in FIG. Further, the test device 110 applies in-phase input voltages VIP and VIN to the input terminals INP and INN in FIG. 1. Then, the test device 110 acquires the voltage value of the output voltage Vo. The voltage value of the output voltage Vo with respect to the input voltages VIP and VIN of the same phase becomes the offset voltage Voff.

In step 202, the test device 110 measures the correction reference current Ia. More specifically, a predetermined level (for example, H level) control signal SC is supplied to the external terminal T22. The correction reference current Ia of the current generation unit 41 is output to the external terminal T21 via the analog switch SW1 turned on by the control signal SC. The test device 110 measures the current value of the correction reference current Ia.

By the processing of step 203 and step 204, the test apparatus 110 calculates the number of correction steps of the correction instruction data 130.
First, in step 203, the test device 110 calculates the voltage shift amount per step. More specifically, the test device 110 is a current of the measured value Is with respect to the standard value I0 based on the standard value I0 of the correction reference current Ia of the current generation unit 41 and the measured value Is of the measured correction reference current Ia. Calculate the ratio β. The current ratio β is
β = IS / I0
Is calculated by. Then, the test device 110 obtains the amount of fluctuation of the offset voltage with respect to the correction of one step from the current ratio β. The fluctuation amount of the offset voltage is a voltage value corresponding to the deviation of the current amount of the correction reference current Ia with respect to the standard shift amount A. This voltage value is obtained by multiplying the deviation ratio (β-1) of the correction reference current Ia with respect to the standard value I0 by “1” (μV / STEP). By adding this calculation result to the standard shift amount A per step, the change amount (voltage shift amount) (A + (β-1)) of the offset voltage per step in the operational amplifier 10 to be measured can be obtained. ..

Next, in step 204, the test device 110 calculates the number of correction steps Rs. More specifically, the test apparatus 110 obtains the correction step number Rs based on the voltage shift amount (A + (β-1)) per step calculated as described above and the measured offset voltage Voff. The number of correction steps Rs is
Rs = Voff / (A + (β-1))
Obtained by The value obtained by converting the calculation result into an integer (for example, rounding off to the nearest whole number) is defined as the correction step number Rs.

In step 205, the test device 110 generates the correction instruction data 130. In the present embodiment, the correction instruction data 130 includes the voltage correction data of the above-mentioned correction step number Rs and the polarity data corresponding to the polarity of the offset voltage Voff. The polarity data is data for selectively connecting the correction current source 44 to the transistor M1 and the transistor M2 in FIG. 1.

(Action)
Next, the operation of the operational amplifier 10 described above will be described.
For example, the offset voltage Voff is 600 (μV), the standard shift amount A of the offset voltage adjustment circuit 15 is 3.4 (μV / STEP), and the standard value I0 of the correction reference current Ia is 5.64 (μA). Further, the maximum value of the measured value Is of the reference current Ia for correction due to variation is 7.037 (μA), and the minimum value is 4.699 (μA).

FIG. 6 shows the relationship between the trimming data, the number of correction steps, and the shift amount (in the case of the standard shift amount). FIG. 7 shows the above-mentioned standard value I0, the maximum value, the current ratio β at the minimum value, (β-1), the voltage shift amount (A + (β-1)), and the number of correction steps Rs.

When the standard value I0 is set, the number of correction steps Rs is "176". On the other hand, the correction step number Rs for the maximum value (7.037 (μA)) is “164”, and the correction step number Rs for the minimum value (4.699 (μA)) is “186”.

FIG. 8 shows the result obtained by simulation of the offset voltage Voff that shifts according to the number of these correction steps. FIG. 8 shows the simulation results. This simulation shows the result of performing repair processing so as to give an offset voltage of 600 (μV) to an ideal operational amplifier (offset voltage is “0”) by the offset voltage adjusting circuit 15. Since the offset voltage Voff based on the standard value I0 is 600 (μV), it is not shown in FIG. 7.

In FIG. 7, the curves L1 and L2 show the offset voltage Voff with respect to the maximum value of the correction reference current Ia, and the curves L3 and L4 show the offset voltage Voff with respect to the minimum value of the correction reference current Ia. The curve L1 and the curve L2 show the difference in the polarity of the offset voltage Voff. That is, FIG. 1 shows a case where the current of the transistor M1 is larger than the current of the transistor M2 and a case where the current of the transistor M2 is larger than the current of the transistor M1. The same applies to the curves L3 and L4.

When the offset voltage Voff is trimmed by the number of correction steps Rs (164) for the maximum value, the offset voltage Voff becomes “615” (μV). Further, when trimming is performed by the number of correction steps Rs (186) with respect to the minimum value, the offset voltage Voff becomes "586" (μV). Therefore, in the present embodiment, the offset voltage Voff can be adjusted within the range of ± 15 μV. In the conventional method in which the correction reference current Ia is not measured, the accuracy of the offset voltage Voff is about ± 50 μV.

As described above, according to the present embodiment, the following effects are obtained.
(1) The operational amplifier (differential circuit) 10 includes a differential pair 12 including transistors M1 and M2, a current source 13 for supplying a tail current ID to the differential pair 12, and currents I1 and I2 flowing from the differential pair 12. It has an output unit 14 that generates an output voltage Vo according to the above. Further, the operational amplifier 10 has an offset voltage adjusting circuit 15 that adjusts the offset voltage Voff by adjusting the currents I1 and I2 flowing through the transistors M1 and M2. The offset voltage adjustment circuit 15 includes a current generation unit 41, a correction current source 44, and a switch circuit 42. The current generation unit 41 generates a correction reference current Ia according to the tail current ID. The correction current source 44 includes the fuse elements F1 to F8 that can be trimmed, and based on the correction reference current Ia, the correction current Ic of the amount of current according to the state (cut / uncut) of the fuse elements F1 to F8 is obtained. Generate. The switch circuit 42 is provided between the current generation unit 41 and the correction current source 44, and sets the current path of the correction reference current Ia according to the control signal SC input from the external terminal T22 to the correction current source. Switch between 44 and the external terminal T21.

Therefore, by passing the correction reference current Ia for generating the correction current Ic by the switch circuit 42 to the external terminal T21, the correction reference current Ia can be measured by the external terminal T21. The correction current Ic generated based on the correction reference current Ia and the tail current ID supplied to the transistor M1 and the transistor M2 of the differential pair 12 are designed to have a correlation. When the current value of the correction reference current Ia varies due to manufacturing variation or the like, the adjustment accuracy of the offset voltage Voff decreases due to the variation of the correction current Ic. On the other hand, the correction step number Rs for adjusting the offset voltage Voff is determined by generating the correction current based on the measured value Is of the correction reference current Ia. Therefore, the trimming process for the fuse elements F1 to F8 may be performed once, and easy trimming can be performed. Further, since the correction reference current Ia can be measured, the influence of manufacturing variations and the like can be reduced, and the offset voltage Voff can be adjusted with high accuracy.

(2) The operational amplifier 10 has a switch circuit 43 connected between the differential pair 12 and the correction current source 44. The switch circuit 43 includes the fuse elements F11 and F12 that can be trimmed. The switch circuit 43 differentially sets the correction current source 44 from the state in which the correction current source 44 is not connected to the differential pair 12 according to the state (cut / uncut) of the fuse elements F11 and F12. The state is switched to the state of being connected to one of the pair of transistors M1 and M2.

Therefore, by connecting the correction current source 44 to one of the transistor M1 and the transistor M2 according to the polarity of the offset voltage Voff, one of the differential currents I1 and I2 flowing through the transistor M1 and the transistor M2 is adjusted and offset. The voltage Voff can be adjusted. In the present embodiment, one correction current source 44 may be prepared, and an increase in the circuit area of the operational amplifier 10 can be suppressed.

Since it is sufficient to prepare one correction current source 44, if the circuit area is about the same as that in which the correction current source 44 is connected to each of the transistor M1 and the transistor M2, one correction current source 44 is used. It is possible to increase the number of trimming blocks included in the above, that is, to widen the adjustment range of the offset voltage Voff. Further, by reducing the correction current in each trimming block, the voltage shift amount can be reduced and the offset voltage Voff can be adjusted with a fine voltage shift amount.

<Modification example>
In addition, each of the above-mentioned embodiments may be carried out in the following embodiments.
In the above embodiment, a plurality of trimming blocks 61 to 68 are weighted with a binary to generate a correction current Ic. On the other hand, a plurality of trimming blocks in which a current having the same current value is passed may be provided, and the currents of the trimming blocks may be combined to generate the correction current Ic.

-In the above embodiment, the number of trimming blocks included in the offset voltage adjustment circuit 15 may be appropriately changed.
-In the above embodiment, the fuse elements F1 to F8 that can be trimmed by irradiation with a laser are used, but an element such as a fuse that can be blown by applying an overvoltage or an overcurrent may be used. In this case, as the trimming device 120 shown in FIG. 4, a power supply device that supplies an overvoltage or an overcurrent is used instead of the laser processing device.

Further, a non-volatile memory element may be used. As the non-volatile memory element, for example, a memory element of a memory circuit for writing data by serial communication can be used. In this case, as the trimming device 120 shown in FIG. 4, a writing device to the memory circuit is used instead of the laser processing device.

In the above embodiment, an operational amplifier (op amp) is shown as an example of a differential circuit including a differential pair 12, but as a circuit including a differential pair 12, for example, a voltage comparator (comparator) and a mixing circuit (mixer) are shown. ), Modulation circuit, etc.

-In the above embodiment, the analog switches SW1 and SW2 of the switch circuit 42 are complementarily turned on and off by the control signal SC, but the analog switches SW1 and SW2 may be turned on and off by separate control signals.

-Although MOSFET is used in the above embodiment, a differential circuit may be configured by using a bipolar transistor. Further, a differential circuit in which MOSFETs and bipolar transistors are mixed may be used.

In the above embodiment, the P-channel MOSFET is used for the differential pair 12, but an operational amplifier having a differential pair including an N-channel MOSFET may be used. Further, the operational amplifier may have a differential pair including a P-channel MOSFET and a differential pair including an N-channel MOSFET.

In the above embodiment, the correction current source 44 is connected to the transistor M1 or the transistor M2 by the switch circuit 43, but the correction current source 44 is connected to each of the transistor M1 and the transistor M2, depending on the polarity of the offset voltage Voff. On the other hand, the fuse element of the correction current source may be trimmed.

10 ... Operate (differential circuit), 12 ... Differential pair, 13 ... Current source, 14 ... Output unit, 15 ... Offset voltage adjustment circuit, 41 ... Current generator, 42 ... First switch circuit, 43 ... Second Switch circuit, 44 ... correction current source, M1 ... first transistor, M2 ... second transistor, I1, I2 ... differential current, Ia ... correction reference current, Ic ... correction current, ID ... tail current (first) Current), F1 to F8, F11, F12 ... Fuse element, T11, T12 ... Power supply terminal, T21 ... External terminal (external terminal for detection), T22 ... External terminal (external input terminal), VIP, VIN ... Input voltage, Voff ... Offset voltage.

Claims (21)

A differential circuit that is tested by a test device
A differential pair containing a first transistor in which a first input voltage is applied to the control terminal and a second transistor in which a second input voltage is applied to the control terminal.
A current source that supplies the first current to the differential pair,
An output unit that generates an output voltage according to the differential current flowing from the differential pair, and an output unit.
An offset voltage adjustment circuit that adjusts the offset voltage of the output voltage by adjusting the current flowing from the first transistor or the second transistor.
Including
The offset voltage adjustment circuit is
A current generator that generates a correction reference current according to the first current, and
A correction current source that includes a plurality of trimmable fuse elements and generates a correction current of a current amount according to the state of the plurality of fuse elements based on the correction reference current.
A first that is provided between the current generation unit and the correction current source and supplies the correction reference current to the correction current source or the detection external terminal according to a control signal supplied from the external input terminal. 1 switch circuit and
A second switch circuit that connects the correction current source to the second terminal of the first transistor or the second terminal of the second transistor.
Have,
The first switch circuit includes an analog switch connected between the current generation unit and the detection external terminal, and the correction reference current is transmitted to the detection external terminal via only the analog switch. Supplied,
The second switch circuit includes a plurality of trimmable fuse elements, and the correction current source is not connected to the first transistor and the second transistor depending on the state of the plurality of fuse elements. From a certain state, the correction current source is connected to the second terminal of the first transistor, or the correction current source is connected to the second terminal of the second transistor.
The first input having the same phase as the first transistor and the second transistor in order for the test apparatus to generate correction instruction data including voltage adjustment data for trimming a fuse element included in the correction current source. It is configured to output the offset voltage of the output voltage when the voltage and the second input voltage are applied, and the correction reference current.
Differential circuit. A differential circuit that is tested by a test device
A differential pair containing a first transistor in which a first input voltage is applied to the control terminal and a second transistor in which a second input voltage is applied to the control terminal.
A current source that supplies the first current to the differential pair,
An output unit that generates an output voltage according to the differential current flowing from the differential pair, and an output unit.
An offset voltage adjustment circuit that adjusts the offset voltage of the output voltage by adjusting the current flowing from the first transistor or the second transistor.
Including
The offset voltage adjustment circuit is
A current generator that generates a correction reference current according to the first current, and
A correction current source that includes a plurality of non-volatile storage elements and generates a correction current of a current amount according to the state of the plurality of non-volatile storage elements based on the correction reference current.
A first that is provided between the current generation unit and the correction current source and connects the current generation unit to the correction current source or the detection external terminal according to a control signal supplied from the external input terminal. Switch circuit and
A second switch circuit that connects the correction current source to the second terminal of the first transistor or the second terminal of the second transistor.
Have,
The first switch circuit includes an analog switch connected between the current generation unit and the detection external terminal, and the correction reference current is transmitted to the detection external terminal via only the analog switch. Supplied,
The second switch circuit includes a plurality of non-volatile storage elements, and the correction current source is not connected to the first transistor and the second transistor depending on the state of the plurality of non-volatile storage elements. From this state, the correction current source is connected to the second terminal of the first transistor, or the correction current source is connected to the second terminal of the second transistor.
The first input voltage having the same phase as the first transistor and the second transistor in order to generate correction instruction data including voltage adjustment data written by the test device to the non-volatile storage element included in the correction current source. And, it is configured to output the offset voltage of the output voltage when the second input voltage is applied and the correction reference current.
Differential circuit. The differential circuit according to claim 1 or 2 , wherein the first switch circuit includes a resistor that pulls down the external input terminal. The correction current source includes a plurality of adjusting transistors that carry a current corresponding to the correction reference current, and the plurality of adjusting transistors are formed so as to carry a binary weighted current. Item 5. The differential circuit according to any one of Items 1 to 3 . The offset voltage adjustment circuit is
A MOS transistor connected in series with the current generator and connected to a gate terminal and a drain terminal is included.
Each of the gates of the plurality of adjusting transistors is connected to the gate terminal of the MOS transistor.
The differential circuit according to claim 4 . The differential circuit according to claim 1 , wherein the fuse element can be trimmed by laser irradiation, overcurrent, or overvoltage. The differential circuit according to any one of claims 1 to 6 , which is integrally integrated on one semiconductor substrate. An adjustment method performed in a test device that tests a differential circuit formed in a semiconductor device.
The differential circuit is
A differential pair containing a first transistor in which a first input voltage is applied to the control terminal and a second transistor in which a second input voltage is applied to the control terminal.
A current source that supplies the first current to the differential pair,
An output unit that generates an output voltage according to the differential current flowing from the differential pair, and an output unit.
An offset voltage adjustment circuit that adjusts the offset voltage of the output voltage by adjusting the current flowing from the first transistor or the second transistor.
Including
The offset voltage adjustment circuit is
A current generator that generates a correction reference current according to the first current, and
A correction current source that includes a plurality of trimmable fuse elements and generates a correction current of a current amount according to the state of the plurality of fuse elements based on the correction reference current.
A first that is provided between the current generation unit and the correction current source and supplies the correction reference current to the correction current source or the detection external terminal according to a control signal supplied from the external input terminal. 1 switch circuit and
A second switch circuit that connects the correction current source to the second terminal of the first transistor or the second terminal of the second transistor.
Including
The first switch circuit includes an analog switch connected between the current generation unit and the detection external terminal, and the correction reference current is transmitted to the detection external terminal via only the analog switch. Supplied,
The second switch circuit includes a plurality of trimmable fuse elements, and the correction current source is not connected to the first transistor and the second transistor depending on the state of the plurality of fuse elements. From a certain state, the correction current source is connected to the second terminal of the first transistor, or the correction current source is connected to the second terminal of the second transistor.
The test device is
A step of applying the first input voltage and the second input voltage having the same phase to the first transistor and the second transistor to measure the offset voltage of the output voltage.
A step of applying the control signal and measuring the correction reference current flowing from the detection external terminal, and
A step of generating correction instruction data including voltage adjustment data for trimming a fuse element included in the correction current source based on the measured value of the offset voltage and the measured value of the correction reference current.
How to adjust, to perform. In the test apparatus, according to the measured offset voltage, the second switch circuit is used to make the correction on either the second terminal of the first transistor or the second terminal of the second transistor. The correction instruction data including the polarity data for trimming the fuse element included in the second switch circuit so as to connect the current source is generated.
The adjustment method according to claim 8 . An adjustment method performed in a test device that tests a differential circuit formed in a semiconductor device.
The differential circuit is
A differential pair containing a first transistor in which a first input voltage is applied to the control terminal and a second transistor in which a second input voltage is applied to the control terminal.
A current source that supplies the first current to the differential pair,
An output unit that generates an output voltage according to the differential current flowing from the differential pair, and an output unit.
An offset voltage adjustment circuit that adjusts the offset voltage of the output voltage by adjusting the current flowing from the first transistor or the second transistor.
Including
The offset voltage adjustment circuit is
A current generator that generates a correction reference current according to the first current, and
A correction current source that includes a plurality of non-volatile storage elements and generates a correction current of a current amount according to the state of the plurality of non-volatile storage elements based on the correction reference current.
A first that is provided between the current generation unit and the correction current source and connects the current generation unit to the correction current source or the detection external terminal according to a control signal supplied from the external input terminal. Switch circuit and
A second switch circuit that connects the correction current source to the second terminal of the first transistor or the second terminal of the second transistor.
Including
The first switch circuit includes an analog switch connected between the current generation unit and the detection external terminal, and the correction reference current is transmitted to the detection external terminal via only the analog switch. Supplied,
The second switch circuit includes a plurality of non-volatile storage elements, and the correction current source is not connected to the first transistor and the second transistor depending on the state of the plurality of non-volatile storage elements. From this state, the correction current source is connected to the second terminal of the first transistor, or the correction current source is connected to the second terminal of the second transistor.
The test device is
A step of applying the first input voltage and the second input voltage having the same phase to the first transistor and the second transistor to measure the offset voltage of the output voltage.
A step of applying the control signal and measuring the correction reference current flowing from the detection external terminal, and
A step of generating correction instruction data including voltage adjustment data to be written to the non-volatile storage element included in the correction current source based on the measured value of the offset voltage and the measured value of the correction reference current.
How to adjust, to perform. In the test apparatus, the correction current source is connected to either the second terminal of the first transistor or the second terminal of the second transistor by the second switch circuit according to the measured offset voltage. Generates the correction instruction data including the polarity data to be written to the non-volatile storage element included in the second switch circuit so as to connect.
The adjustment method according to claim 10 . The test device is in the step of generating the correction instruction data.
The standard shift amount of one step when shifting the output voltage by the correction current source is set as the standard shift amount.
The ratio between the standard value of the correction reference current and the measured value of the correction reference current is calculated, and based on the calculated ratio, the amount of deviation of the voltage change in one step in the measurement target is calculated, and the standard shift is performed. The deviation amount is added to the amount to calculate a one-step voltage shift amount in consideration of the deviation of the measured value with respect to the standard value, and the measured value of the offset voltage is divided by the voltage shift amount to obtain the voltage adjustment data. Calculate the number of correction steps for
The adjustment method according to any one of claims 8 to 11 . The 12th aspect of the present invention, wherein the standard shift amount is a value obtained by a design value having no variation in the correction reference current, or a value obtained by a statistical method based on the measurement result of the manufactured semiconductor element. How to adjust. A program executed in a test device that tests a differential circuit formed in a semiconductor device.
The differential circuit is
A differential pair containing a first transistor in which a first input voltage is applied to the control terminal and a second transistor in which a second input voltage is applied to the control terminal.
A current source that supplies the first current to the differential pair,
An output unit that generates an output voltage according to the differential current flowing from the differential pair, and an output unit.
An offset voltage adjustment circuit that adjusts the offset voltage of the output voltage by adjusting the current flowing from the first transistor or the second transistor.
Including
The offset voltage adjustment circuit is
A current generator that generates a correction reference current according to the first current, and
A correction current source that includes a plurality of trimmable fuse elements and generates a correction current of a current amount according to the state of the plurality of fuse elements based on the correction reference current.
A first that is provided between the current generation unit and the correction current source and supplies the correction reference current to the correction current source or the detection external terminal according to a control signal supplied from the external input terminal. 1 switch circuit and
A second switch circuit that connects the correction current source to the second terminal of the first transistor or the second terminal of the second transistor.
Including
The first switch circuit includes an analog switch connected between the current generation unit and the detection external terminal, and the correction reference current is transmitted to the detection external terminal via only the analog switch. Supplied,
The second switch circuit includes a plurality of trimmable fuse elements, and the correction current source is not connected to the first transistor and the second transistor depending on the state of the plurality of fuse elements. From a certain state, the correction current source is connected to the second terminal of the first transistor, or the correction current source is connected to the second terminal of the second transistor.
The program executed by the test device is
A step of applying the first input voltage and the second input voltage having the same phase to the first transistor and the second transistor to measure the offset voltage of the output voltage.
A step of applying the control signal and measuring the correction reference current flowing from the detection external terminal, and
A step of generating correction instruction data including voltage adjustment data for trimming a fuse element included in the correction current source based on the measured value of the offset voltage and the measured value of the correction reference current.
Including the program. The program executed by the test apparatus is described in either the second terminal of the first transistor or the second terminal of the second transistor by the second switch circuit according to the measured offset voltage. A step of generating the correction instruction data including the polarity data for trimming the fuse element included in the second switch circuit so as to connect the correction current source.
The program according to claim 14 . A program executed in a test device that tests a differential circuit formed in a semiconductor device.
The differential circuit is
A differential pair containing a first transistor in which a first input voltage is applied to the control terminal and a second transistor in which a second input voltage is applied to the control terminal.
A current source that supplies the first current to the differential pair,
An output unit that generates an output voltage according to the differential current flowing from the differential pair, and an output unit.
An offset voltage adjustment circuit that adjusts the offset voltage of the output voltage by adjusting the current flowing from the first transistor or the second transistor.
Including
The offset voltage adjustment circuit is
A current generator that generates a correction reference current according to the first current, and
A correction current source that includes a plurality of non-volatile storage elements and generates a correction current of a current amount according to the state of the plurality of non-volatile storage elements based on the correction reference current.
A first that is provided between the current generation unit and the correction current source and connects the current generation unit to the correction current source or the detection external terminal according to a control signal supplied from the external input terminal. Switch circuit and
A second switch circuit that connects the correction current source to the second terminal of the first transistor or the second terminal of the second transistor.
Including
The first switch circuit includes an analog switch connected between the current generation unit and the detection external terminal, and the correction reference current is transmitted to the detection external terminal via only the analog switch. Supplied,
The second switch circuit includes a plurality of non-volatile storage elements, and the correction current source is not connected to the first transistor and the second transistor depending on the state of the plurality of non-volatile storage elements. From this state, the correction current source is connected to the second terminal of the first transistor, or the correction current source is connected to the second terminal of the second transistor.
The program executed by the test device is
A step of applying the first input voltage and the second input voltage having the same phase to the first transistor and the second transistor to measure the offset voltage of the output voltage.
A step of applying the control signal and measuring the correction reference current flowing from the detection external terminal, and
A step of generating correction instruction data including voltage adjustment data to be written to the non-volatile storage element included in the correction current source based on the measured value of the offset voltage and the measured value of the correction reference current.
Including the program. The program executed by the test apparatus is either one of the second terminal of the first transistor and the second terminal of the second transistor by the second switch circuit according to the measured offset voltage. The step of generating the correction instruction data including the polarity data to be written to the non-volatile storage element included in the second switch circuit so as to connect the correction current source to the second switch circuit.
The program according to claim 16 . The test device is in the step of generating the correction instruction data.
The standard shift amount of one step when shifting the output voltage by the correction current source is set as the standard shift amount.
The ratio between the standard value of the correction reference current and the measured value of the correction reference current is calculated, and based on the calculated ratio, the amount of deviation of the voltage change in one step in the measurement target is calculated, and the standard shift is performed. The deviation amount is added to the amount to calculate a one-step voltage shift amount in consideration of the deviation of the measured value with respect to the standard value, and the measured value of the offset voltage is divided by the voltage shift amount to obtain the voltage adjustment data. Calculate the number of correction steps for
The program according to any one of claims 14 to 17 . The 18th aspect of the present invention, wherein the standard shift amount is a value obtained by a design value having no variation in the correction reference current, or a value obtained by a statistical method based on the measurement result of the manufactured semiconductor element. Program. An adjustment method performed in a test device that tests a differential circuit formed in a semiconductor device.
The differential circuit is
A differential pair containing a first transistor in which a first input voltage is applied to the control terminal and a second transistor in which a second input voltage is applied to the control terminal.
A current source that supplies the first current to the differential pair,
An output unit that generates an output voltage according to the differential current flowing from the differential pair, and an output unit.
An offset voltage adjustment circuit that adjusts the offset voltage of the output voltage by adjusting the current flowing from the first transistor or the second transistor.
Including
The offset voltage adjustment circuit is
A current generator that generates a correction reference current according to the first current, and
A correction current source that includes a plurality of trimmable fuse elements and generates a correction current of a current amount according to the state of the plurality of fuse elements based on the correction reference current.
A first that is provided between the current generation unit and the correction current source and supplies the correction reference current to the correction current source or the detection external terminal according to a control signal supplied from the external input terminal. 1 switch circuit and
A second switch circuit that connects the correction current source to the second terminal of the first transistor or the second terminal of the second transistor.
Including
The second switch circuit includes a plurality of trimmable fuse elements, and the correction current source is not connected to the first transistor and the second transistor depending on the state of the plurality of fuse elements. From a certain state, the correction current source is connected to the second terminal of the first transistor, or the correction current source is connected to the second terminal of the second transistor.
The test device is
A step of applying the first input voltage and the second input voltage having the same phase to the first transistor and the second transistor to measure the offset voltage of the output voltage.
A step of applying the control signal and measuring the correction reference current flowing from the detection external terminal, and
Based on the measured value of the offset voltage and the measured value of the correction reference current, a step of generating correction instruction data including voltage adjustment data for trimming the fuse element included in the correction current source. Run and
In the step of generating the correction instruction data,
The standard shift amount of one step when shifting the output voltage by the correction current source is set as the standard shift amount.
The ratio between the standard value of the correction reference current and the measured value of the correction reference current is calculated, and based on the calculated ratio, the amount of deviation of the voltage change in one step in the measurement target is calculated, and the standard shift is performed. The deviation amount is added to the amount to calculate a one-step voltage shift amount in consideration of the deviation of the measured value with respect to the standard value, and the measured value of the offset voltage is divided by the voltage shift amount to obtain the voltage adjustment data. Calculate the number of correction steps for
Adjustment method. An adjustment method performed in a test device that tests a differential circuit formed in a semiconductor device.
The differential circuit is
A differential pair containing a first transistor in which a first input voltage is applied to the control terminal and a second transistor in which a second input voltage is applied to the control terminal.
A current source that supplies the first current to the differential pair,
An output unit that generates an output voltage according to the differential current flowing from the differential pair, and an output unit.
An offset voltage adjustment circuit that adjusts the offset voltage of the output voltage by adjusting the current flowing from the first transistor or the second transistor.
Including
The offset voltage adjustment circuit is
A current generator that generates a correction reference current according to the first current, and
A correction current source that includes a plurality of non-volatile storage elements and generates a correction current of a current amount according to the state of the plurality of non-volatile storage elements based on the correction reference current.
A first that is provided between the current generation unit and the correction current source and connects the current generation unit to the correction current source or the detection external terminal according to a control signal supplied from the external input terminal. Switch circuit and
A second switch circuit that connects the correction current source to the second terminal of the first transistor or the second terminal of the second transistor.
Including
The second switch circuit includes a plurality of non-volatile storage elements, and the correction current source is not connected to the first transistor and the second transistor depending on the state of the plurality of non-volatile storage elements. From this state, the correction current source is connected to the second terminal of the first transistor, or the correction current source is connected to the second terminal of the second transistor.
The test device is
A step of applying the first input voltage and the second input voltage having the same phase to the first transistor and the second transistor to measure the offset voltage of the output voltage.
A step of applying the control signal and measuring the correction reference current flowing from the detection external terminal, and
Based on the measured value of the offset voltage and the measured value of the correction reference current, a step of generating correction instruction data including voltage adjustment data to be written to the non-volatile storage element included in the correction current source is executed. death,
In the step of generating the correction instruction data,
The standard shift amount of one step when shifting the output voltage by the correction current source is set as the standard shift amount.
The ratio between the standard value of the correction reference current and the measured value of the correction reference current is calculated, and based on the calculated ratio, the amount of deviation of the voltage change in one step in the measurement target is calculated, and the standard shift is performed. The deviation amount is added to the amount to calculate a one-step voltage shift amount in consideration of the deviation of the measured value with respect to the standard value, and the measured value of the offset voltage is divided by the voltage shift amount to obtain the voltage adjustment data. Calculate the number of correction steps for
Adjustment method.

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