JP7054791B2 - Semiconductor devices and devices - Google Patents

Description

The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a plurality of switching elements and a device used in the semiconductor device.

As a conventional example, the semiconductor device described in Patent Document 1 will be illustrated. The semiconductor device described in Patent Document 1 includes an inverter circuit, a conductive path including a conductor connected to an output of the inverter circuit, and a clamp circuit. The inverter circuit is configured to include a plurality of first switching elements connected in a full bridge. The clamp circuit is configured to include a second switching element and is connected to the conductive path. The inverter circuit, the conductive path, and the clamp circuit are contained in one package.

Japanese Unexamined Patent Publication No. 2015-033217

However, in the semiconductor device described in Patent Document 1, since the inverter circuit, the conductive path, and the clamp circuit are contained in one package, the types of circuits that can be formed by using the semiconductor device are limited.

It is an object of the present disclosure to provide a semiconductor device having improved versatility and a device used in the semiconductor device.

The semiconductor device according to the first aspect of the present disclosure performs at least one of an operation of converting DC power into AC power and an operation of converting AC power into DC power. The semiconductor device includes a first series circuit of a plurality of first switching elements, a second series circuit of the plurality of second switching elements, and a third series circuit of the plurality of third switching elements. A fourth series circuit of the plurality of fourth switching elements, a fifth series circuit of the plurality of fifth switching elements, and a sixth series circuit of the plurality of sixth switching elements are provided. The second series circuit is connected in series with the first series circuit. The fourth series circuit is connected in series with the third series circuit. The fifth series circuit is connected between the first connection point and the second connection point. The first connection point is a connection point of two first switching elements among the plurality of first switching elements. The second connection point is a connection point of two second switching elements among the plurality of second switching elements. The sixth series circuit is connected between the third connection point and the fourth connection point. The third connection point is a connection point of two third switching elements among the plurality of third switching elements. The fourth connection point is a connection point of two fourth switching elements among the plurality of fourth switching elements. The end of the first series circuit opposite to the second series circuit side is connected to the end of the third series circuit opposite to the fourth series circuit side. The end of the second series circuit opposite to the first series circuit side is connected to the end of the fourth series circuit opposite to the third series circuit side. The connection point between the first series circuit and the second series circuit is connected to the connection point between the third series circuit and the fourth series circuit. The semiconductor device includes a plurality of modules. The plurality of modules include a group of switching elements and a package. The switching element group includes the plurality of first switching elements, the plurality of second switching elements, the plurality of third switching elements, the plurality of fourth switching elements, and the plurality of fifth switching elements. And at least two switching elements, which are less than half of the plurality of sixth switching elements. The package houses the switching element group. The number of switching elements in each of the plurality of modules is the same among the plurality of modules. The connection relationship of the switching element group in each of the plurality of modules is the same among the plurality of modules. The semiconductor device includes a first capacitor connected in parallel with a series circuit of at least two first switching elements of the plurality of first switching elements, and at least two of the plurality of second switching elements. A second capacitor connected in parallel with the series circuit of the two second switching elements, and a third connected in parallel with the series circuit of at least two third switching elements among the plurality of third switching elements. The capacitor is further provided with a fourth capacitor connected in parallel with a series circuit of at least two fourth switching elements among the plurality of fourth switching elements. The first module among the plurality of modules includes the first series circuit, the second series circuit, the fifth series circuit, the first capacitor, and the second capacitor. including. The second module other than the first module among the plurality of modules includes the third series circuit, the fourth series circuit, the sixth series circuit, and the third capacitor. And the fourth capacitor.
The semiconductor device according to the second aspect of the present disclosure performs at least one of an operation of converting DC power into AC power and an operation of converting AC power into DC power. The semiconductor device includes a first series circuit of a plurality of first switching elements, a second series circuit of the plurality of second switching elements, and a third series circuit of the plurality of third switching elements. A fourth series circuit of the plurality of fourth switching elements, a fifth series circuit of the plurality of fifth switching elements, and a sixth series circuit of the plurality of sixth switching elements are provided. The second series circuit is connected in series with the first series circuit. The fourth series circuit is connected in series with the third series circuit. The fifth series circuit is connected between the first connection point and the second connection point. The first connection point is a connection point of two first switching elements among the plurality of first switching elements. The second connection point is a connection point of two second switching elements among the plurality of second switching elements. The sixth series circuit is connected between the third connection point and the fourth connection point. The third connection point is a connection point of two third switching elements among the plurality of third switching elements. The fourth connection point is a connection point of two fourth switching elements among the plurality of fourth switching elements. The end of the first series circuit opposite to the second series circuit side is connected to the end of the third series circuit opposite to the fourth series circuit side. The end of the second series circuit opposite to the first series circuit side is connected to the end of the fourth series circuit opposite to the third series circuit side. The connection point between the first series circuit and the second series circuit is connected to the connection point between the third series circuit and the fourth series circuit. The semiconductor device includes a plurality of modules. The plurality of modules include a group of switching elements and a package. The switching element group includes the plurality of first switching elements, the plurality of second switching elements, the plurality of third switching elements, the plurality of fourth switching elements, and the plurality of fifth switching elements. And at least two switching elements, which are less than half of the plurality of sixth switching elements. The package houses the switching element group. The number of switching elements in each of the plurality of modules is the same among the plurality of modules. The connection relationship of the switching element group in each of the plurality of modules is the same among the plurality of modules. The six modules as the plurality of modules have a one-to-one correspondence with the first to sixth series circuits. Each of the six modules includes the corresponding series circuit of the first to sixth series circuits.
The semiconductor device according to the third aspect of the present disclosure performs at least one of an operation of converting DC power into AC power and an operation of converting AC power into DC power. The semiconductor device includes a first series circuit of a plurality of first switching elements, a second series circuit of the plurality of second switching elements, and a third series circuit of the plurality of third switching elements. A fourth series circuit of the plurality of fourth switching elements, a fifth series circuit of the plurality of fifth switching elements, and a sixth series circuit of the plurality of sixth switching elements are provided. The second series circuit is connected in series with the first series circuit. The fourth series circuit is connected in series with the third series circuit. The fifth series circuit is connected between the first connection point and the second connection point. The first connection point is a connection point of two first switching elements among the plurality of first switching elements. The second connection point is a connection point of two second switching elements among the plurality of second switching elements. The sixth series circuit is connected between the third connection point and the fourth connection point. The third connection point is a connection point of two third switching elements among the plurality of third switching elements. The fourth connection point is a connection point of two fourth switching elements among the plurality of fourth switching elements. The end of the first series circuit opposite to the second series circuit side is connected to the end of the third series circuit opposite to the fourth series circuit side. The end of the second series circuit opposite to the first series circuit side is connected to the end of the fourth series circuit opposite to the third series circuit side. The connection point between the first series circuit and the second series circuit is connected to the connection point between the third series circuit and the fourth series circuit. The semiconductor device includes a plurality of modules. The plurality of modules include a group of switching elements and a package. The switching element group includes the plurality of first switching elements, the plurality of second switching elements, the plurality of third switching elements, the plurality of fourth switching elements, and the plurality of fifth switching elements. And at least two switching elements, which are less than half of the plurality of sixth switching elements. The package houses the switching element group. The number of switching elements in each of the plurality of modules is the same among the plurality of modules. The connection relationship of the switching element group in each of the plurality of modules is the same among the plurality of modules. The plurality of first switching elements include a switching element included in the first module and a switching element included in the second module among the plurality of modules. The plurality of third switching elements include a switching element included in the first module and a switching element included in the third module among the plurality of modules. The plurality of fifth switching elements include a switching element included in the second module and a switching element included in the fourth module among the plurality of modules. The plurality of sixth switching elements include a switching element included in the third module and a switching element included in the fifth module among the plurality of modules. The plurality of second switching elements include a switching element included in the fourth module and a switching element included in the sixth module among the plurality of modules. The plurality of fourth switching elements include a switching element included in the fifth module and a switching element included in the sixth module among the plurality of modules.

The device according to one aspect of the present disclosure is used as the first module or the second module in the semiconductor device according to the first aspect .
The device according to another aspect of the present disclosure is used as one of the six modules in the semiconductor device according to the second aspect.
The device according to still another aspect of the present disclosure is used as one of the first to sixth modules in the semiconductor device according to the third aspect.

According to the semiconductor device and device according to one aspect of the present disclosure, versatility can be improved.

FIG. 1 is a circuit diagram showing a first configuration example of the semiconductor device according to the first embodiment. FIG. 2 is a circuit diagram showing a second configuration example of the same semiconductor device. 3A to 3D show a switching pattern when an output voltage having a polarity in which the U phase is + and the W phase is − in the first example of the switching pattern in the control method of the semiconductor device of the second configuration example. It is a figure which shows. 4A to 4D show a switching pattern in the first example of the switching pattern in the control method of the semiconductor device of the second configuration example, when the output voltage having a polarity in which the U phase is − and the W phase is + is output. It is a figure which shows. 5A to 5D show a switching pattern when an output voltage having a polarity in which the U phase is + and the W phase is − in the second example of the switching pattern in the control method of the semiconductor device of the second configuration example. It is a figure which shows. 6A to 6D show a switching pattern when an output voltage having a polarity in which the U phase is − and the W phase is + is output in the second example of the switching pattern in the control method of the semiconductor device of the second configuration example. It is a figure which shows. 7A to 7D are diagrams showing an example of a switching pattern in the control method of the semiconductor device of the second configuration example. FIG. 8 is a diagram showing a first example of a control method for a semiconductor device of the second configuration example. FIG. 9 is a diagram showing a second example of the control method of the semiconductor device of the second configuration example. FIG. 10 is a diagram showing a third example of the control method of the semiconductor device of the second configuration example. FIG. 11 is a diagram showing a flying capacitor circuit in a third configuration example of the semiconductor device according to the first embodiment. FIG. 12 is a circuit diagram showing that the semiconductor device of the second configuration example is composed of a plurality of modules. FIG. 13 is a plan view of the module of the semiconductor device of the second configuration example. FIG. 14 is a schematic view of the inside of one of the plurality of packages of the semiconductor device of the second configuration example. FIG. 15 is a circuit diagram of the semiconductor device according to the second embodiment. FIG. 16 is a schematic diagram of the inside of one of the plurality of packages of the same semiconductor device. FIG. 17 is a circuit diagram of the semiconductor device according to the third embodiment. FIG. 18 is a schematic diagram of the inside of one of the plurality of packages of the same semiconductor device. FIG. 19 is a circuit diagram of the semiconductor device according to the fourth embodiment. FIG. 20 is a schematic view of the inside of one of the plurality of packages of the same semiconductor device. FIG. 21 is a circuit diagram of the semiconductor device according to the fifth embodiment. FIG. 22 is a circuit diagram of the semiconductor device according to the sixth embodiment.

Hereinafter, the semiconductor device according to the embodiment and the device used for the semiconductor device will be described with reference to the drawings. However, each of the following embodiments is only part of the various embodiments of the present disclosure. Each of the following embodiments can be variously modified according to the design and the like as long as the object of the present disclosure can be achieved.

(Embodiment 1)
FIG. 1 is a circuit diagram of the semiconductor device 10 according to the first embodiment. The semiconductor device 10 includes a first input end IN1 and a second input end IN2 for inputting a DC power supply voltage. The semiconductor device 10 includes a first flying capacitor circuit 11 and a second flying capacitor circuit 12 connected in series with a DC power supply, and a first flying capacitor circuit 11 and a second flying capacitor circuit 11 and a second flying capacitor circuit 11 and a second flying capacitor circuit 12 connected in series with a DC power supply. A third flying capacitor circuit 13 and a fourth flying capacitor circuit 14 connected in series with the capacitor circuit 12 are further provided. That is, the series circuit of the first flying capacitor circuit 11 and the second flying capacitor circuit 12 and the series circuit of the third flying capacitor circuit 13 and the fourth flying capacitor circuit 14 are connected in parallel with the DC power supply. To. The semiconductor device 10 includes a switching element S1 and a switching element S2 connected in series between the output terminals of the first flying capacitor circuit 11 and the second flying capacitor circuit 12, and the third flying capacitor circuit 13 and the fourth flying. The switching element S3 and the switching element S4 connected in series between the output terminals of the capacitor circuit 14 and the first output end OUT1 provided in the electric circuit between the switching element S1 and the switching element S2 connected in series are connected in series. Further, a second output end OUT2 provided in an electric circuit between the switching element S3 and the switching element S4 is provided. The semiconductor device 10 is a power conversion device that performs at least one of an operation of converting DC power into AC power and an operation of converting AC power into DC power (both in the present embodiment). More specifically, the semiconductor device 10 is a 5-level inverter capable of outputting a 5-level output voltage from the first output terminal OUT1 and the second output terminal OUT2.

In the following description, the operation when the DC power supply voltage is input from the first input terminal IN1 and the second input end IN2 and the AC power is output from the first output terminal OUT1 and the second output end OUT2 will be mainly described. , This semiconductor device 10 has bidirectionality, that is, AC power is input to the first output terminal OUT1 and the second output end OUT2, and DC power is input from the first input terminal IN1 and the second input end IN2. It is possible to output. In other words, in the semiconductor device 10, it is also possible to send electric power from the AC side (first output end OUT1 and second output end OUT2) to the DC side (first input end IN1 and second input end IN2). In this case, the input and the output are reversed, the first output end OUT1 and the second output end OUT2 become the first input end IN1 and the second input end IN2, and the first input end IN1 and the second input end IN2 become the first. It becomes an output end OUT1 and a second output end OUT2. That is, the first input end IN1 and the second input end IN2 are connection ends that function as at least one of the input end and the output end of the DC power, and the first output end OUT1 and the second output end OUT2 are AC. A connection end that functions as at least one of an input end and an output end of power. Here, each connection end is, for example, a part of a conductor constituting an electric circuit.

In the semiconductor device 10 shown in FIG. 1, a three-level converter circuit capable of outputting a three-level voltage is used as the first to fourth flying capacitor circuits 11 to 14, but as will be described later, the first As the fourth flying capacitor circuits 11 to 14, a multi-level converter circuit capable of outputting a voltage of (2N + 3) level may be used (where N is a natural number).

Two capacitors C1 and C2 having the same capacitance value are connected in series between the first input end IN1 and the second input end IN2. Since the two capacitors C1 and C2 have the same capacitance value, the voltage between the terminals of the two capacitors C1 and C2 is equal to half (E / 2) of the DC power supply voltage E. Therefore, assuming that the potential of the first input end IN1 is E [V] and the potential of the second input end IN2 is 0 [V], the potential of the connection point between the capacitor C1 and the capacitor C2 is E / 2 [V]. .. As described above, in the semiconductor device 10 shown in FIG. 1, the DC power supply voltage is divided by the two capacitors C1 and C2, but in another example, the DC power supply voltage may be divided by the two resistors. .. Alternatively, even if two DC power supplies having a power supply voltage of E / 2 [V] are connected between the first input terminal IN1 and the second input terminal IN2 instead of the two capacitors C1 and C2. good. The connection point between the first flying capacitor circuit 11 and the second flying capacitor circuit 12 and the connection point between the third flying capacitor circuit 13 and the fourth flying capacitor circuit 14 are separated by two capacitors C1 and C2. It is connected to the midpoint of the compressed DC power supply voltage. In other words, the connection point between the first flying capacitor circuit 11 and the second flying capacitor circuit 12 and the connection point between the third flying capacitor circuit 13 and the fourth flying capacitor circuit 14 are the two capacitors C1 and It is connected to the electric circuit between C2 where the potential becomes E / 2 [V].

It should be noted that the fact that the capacitance values of the two capacitors C1 and C2 are the same is not limited to being exactly the same, and may be different within an allowable error range. The same capacitance value of the two capacitors C1 and C2 includes, for example, a case where there is an error of 10% or 20%.

The first to fourth flying capacitor circuits 11 to 14 are all flying capacitor type three-level converter circuits. Hereinafter, each capacitor of the first to fourth flying capacitor circuits 11 to 14 will be referred to as a flying capacitor. The first to fourth flying capacitor circuits 11 to 14 have four switching elements (switching elements S5a to S5d, S6a to S6d, S7a to S7d, or S8a to S8d) connected in series, respectively, as described later. It is composed of one flying capacitor (flying capacitor FC1, FC2, FC3, or FC4). In another example, instead of the first to fourth flying capacitor circuits 11 to 14, a three-level converter circuit other than the flying capacitor type may be used, or a multi-level converter having a number of levels greater than three. Circuits may be used.

The first flying capacitor circuit 11 is composed of four switching elements S5a, S5b, S5c, S5d and one flying capacitor FC1. The four switching elements S5a to S5d are composed of N-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and a diode is connected between the source and drain of each MOSFET. This diode is a body diode as part of the MOSFET configuration. The four switching elements S5a to S5d are connected in series in the order of S5a, S5b, S5c, S5d, the switching element S5a is connected to the first input terminal IN1, and the switching element S5d is connected to the connection point between the capacitor C1 and the capacitor C2. Will be done. One end of the flying capacitor FC1 is connected to the connection point between the switching element S5a and the switching element S5b, and the other end of the flying capacitor FC1 is connected to the connection point between the switching element S5c and the switching element S5d. Therefore, the potential of the output end provided at the connection point between the switching element S5b and the switching element S5c is in the range between the potential E [V] in the switching element S5a and the potential E / 2 [V] in the switching element S5d. It becomes the potential of. The flying capacitor FC1 is precharged so as to have a voltage of E / 4 [V], and charging / discharging is repeated centering on the voltage of E / 4 [V]. As will be described later, the potential at the output end of the first flying capacitor circuit 11 is approximately three levels of potentials, E [V], 3E / 4 [V], and E / 2 [V].

The second flying capacitor circuit 12 is composed of four switching elements S6a, S6b, S6c, S6d and one flying capacitor FC2. The four switching elements S6a to S6d are composed of N-channel MOSFETs, and a diode is connected between the source and drain of each MOSFET. This diode is a body diode as part of the MOSFET configuration. The four switching elements S6a to S6d are connected in series in the order of S6a, S6b, S6c, S6d, the switching element S6a is connected to the connection point between the capacitor C1 and the capacitor C2, and the switching element S6d is connected to the second input terminal IN2. Will be done. One end of the flying capacitor FC2 is connected to the connection point between the switching element S6a and the switching element S6b, and the other end of the flying capacitor FC2 is connected to the connection point between the switching element S6c and the switching element S6d. Therefore, the potential of the output end provided at the connection point between the switching element S6b and the switching element S6c is in the range between the potential E / 2 [V] in the switching element S6a and the potential 0 [V] in the switching element S6d. It becomes the potential of. The flying capacitor FC2 is precharged so as to have a voltage of E / 4 [V], and charging / discharging is repeated centering on the voltage of E / 4 [V]. As will be described later, the potential at the output end of the second flying capacitor circuit 12 is approximately three levels of potentials of E / 2 [V], E / 4 [V], and 0 [V].

The third flying capacitor circuit 13 is composed of four switching elements S7a, S7b, S7c, S7d and one flying capacitor FC3. The four switching elements S7a to S7d are composed of N-channel MOSFETs, and a diode is connected between the source and drain of each MOSFET. This diode is a body diode as part of the MOSFET configuration. The four switching elements S7a to S7d are connected in series in the order of S7a, S7b, S7c, S7d, the switching element S7a is connected to the first input terminal IN1, and the switching element S7d is connected to the connection point between the capacitor C1 and the capacitor C2. Will be done. One end of the flying capacitor FC3 is connected to the connection point between the switching element S7a and the switching element S7b, and the other end of the flying capacitor FC3 is connected to the connection point between the switching element S7c and the switching element S7d. Therefore, the potential of the output end provided at the connection point between the switching element S7b and the switching element S7c is in the range between the potential E [V] in the switching element S7a and the potential E / 2 [V] in the switching element S7d. It becomes the potential of. The flying capacitor FC3 is precharged so as to have a voltage of E / 4 [V], and charging / discharging is repeated centering on the voltage of E / 4 [V]. As will be described later, the potential at the output end of the third flying capacitor circuit 13 is approximately three levels of potentials, E [V], 3E / 4 [V], and E / 2 [V].

The fourth flying capacitor circuit 14 is composed of four switching elements S8a, S8b, S8c, S8d and one flying capacitor FC4. The four switching elements S8a to S8d are composed of N-channel MOSFETs, and a diode is connected between the source and drain of each MOSFET. This diode is a body diode as part of the MOSFET configuration. The four switching elements S8a to S8d are connected in series in the order of S8a, S8b, S8c, and S8d, the switching element S8a is connected to the connection point between the capacitor C1 and the capacitor C2, and the switching element S8d is connected to the second input terminal IN2. Will be done. One end of the flying capacitor FC4 is connected to the connection point between the switching element S8a and the switching element S8b, and the other end of the flying capacitor FC4 is connected to the connection point between the switching element S8c and the switching element S8d. Therefore, the potential of the output end provided at the connection point between the switching element S8b and the switching element S8c is in the range between the potential E / 2 [V] in the switching element S8a and the potential 0 [V] in the switching element S8d. It becomes the potential of. The flying capacitor FC4 is precharged so as to have a voltage of E / 4 [V], and charging / discharging is repeated centering on the voltage of E / 4 [V]. As will be described later, the potential of the output end of the fourth flying capacitor circuit 14 is approximately three levels of potentials of E / 2 [V], E / 4 [V], and 0 [V].

In the semiconductor device 10 according to the present embodiment, since all four three-level circuits are composed of flying capacitor type three-level circuits, the withstand voltage of all the switching elements constituting the four flying capacitor circuits 11 to 14 is E /. It can be 4 [V]. This makes it possible to use a switching element such as a MOSFET. In another example, a part or all of the switching elements constituting the four flying capacitor circuits 11 to 14 may be configured by other switching elements such as an IGBT (Insulated Gate Bipolar Transistor). A diode may be connected between the collector and the emitter of the IGBT.

The control method of the semiconductor device 10 according to the present embodiment is realized by a control circuit configured by a microcontroller or the like. As will be described later, in the control method of the semiconductor device 10 according to the present embodiment, the difference between the output voltages of the two flying capacitor circuits 11 and 12 connected in series is E/2 [V] or less. It controls two flying capacitor circuits 11 and 12. Further, the two flying capacitor circuits 13 and 14 are controlled so that the difference between the output voltages of the two flying capacitor circuits 13 and 14 connected in series is also E / 2 [V] or less. Therefore, as the switching elements S1 to S4 in the output stage of the semiconductor device 10, switching elements having a withstand voltage of E / 2 [V] can be used. As a result, switching elements such as MOSFETs can also be used in the output stage. Further, by using a switching element having a withstand voltage of E / 2 [V], the recovery current generated when the switching element is switched can be reduced as compared with the case where the withstand voltage of the switching element is higher. , It is possible to suppress damage to the element due to the recovery current.

Further, as will be described later, in the control method of the semiconductor device 10 according to the present embodiment, the control circuit controls the switching elements S1 to S4 of the output stage so as to operate only when the polarity of the output voltage is switched. do. Therefore, the frequency of the duty control of the switching elements S1 to S4 is lower than the frequency of the duty control of the switching elements constituting the four flying capacitor circuits 11 to 14. Therefore, instead of the respective switching elements S1 to S4, a plurality of switching elements having a lower withstand voltage can be connected in series. In the semiconductor device 10 according to the present embodiment, in the switching element of the output stage, the rising or falling timing of the control signal input to the plurality of switching elements connected in series is deviated, and the characteristics of the switching element are different. This is because even if there is a slight deviation in the on / off timing of the plurality of switching elements due to the above, a snubber circuit or the like connected to the semiconductor device 10 can suppress a sudden rise in voltage and appropriately protect the voltage. In the switching pattern in the second example of the control method described later, the switching elements S1 to S4 can be switched in a state where the voltage is zero, so that a timing shift is further allowed.

FIG. 2 is a circuit diagram showing a configuration example of the semiconductor device 10 different from that of FIG. In the semiconductor device 10 shown in FIG. 2, the switching elements S1 to S4 in the output stage of the semiconductor device 10 shown in FIG. 1 are replaced with two switching elements connected in series, respectively. That is, the switching element S1 in FIG. 1 is replaced by two switching elements S1a and S1b, the switching element S2 in FIG. 1 is replaced by two switching elements S2a and S2b, and the switching element S3 in FIG. 1 is replaced by two. The switching elements S3a and S3b have been replaced, and the switching element S4 in FIG. 1 has been replaced by two switching elements S4a and S4b. Other than that, the configuration is the same as in FIG.

According to such a configuration, the withstand voltage of the switching element of the output stage can be further halved as compared with the semiconductor device 10 shown in FIG. 1, so that the withstand voltage of the switching elements S1a to S4b of the output stage are all E. It becomes / 4 [V]. Therefore, as all the switching elements constituting the semiconductor device 10 shown in FIG. 2, a switching element having a withstand voltage of E / 4 [V] can be used. For example, when the DC power supply voltage is 600 [V], all the switching elements can be configured by cheaper and higher performance switching elements having a withstand voltage of 150 [V], so that they are cheaper and have higher performance. The semiconductor device 10 can be provided.

Hereinafter, the control method of the semiconductor device 10 according to the embodiment of the present invention will be described using the circuit of the semiconductor device 10 shown in FIG. It is assumed that all the switching elements constituting the semiconductor device 10 shown in FIG. 2 are composed of MOSFETs, and a gate signal is supplied from a control circuit to the gate terminal of each switching element to control on / off. That is, the voltage between the gate terminal and the source terminal of each switching element is switched between the low level and the high level, and the on / off of each switching element is controlled. Each switching element may be a normal-off type switching element or a normal-on type switching element.

Hereinafter, the electric circuit connected to the first output terminal OUT1 is referred to as a U phase. Further, in the following, the electric path connected to the second output terminal OUT2 will be referred to as a W phase. 3A to 3D show a switching pattern when an output voltage having a polarity in which the U phase is + and the W phase is − in the first example of the switching pattern in the control method of the semiconductor device 10 according to the embodiment. show. In FIGS. 3A to 3D, the switching element is simplified and shown in order to make the figure easier to see. In FIGS. 3A to 7D, the letters and numbers enclosed in square brackets [] represent the voltage at the position in brackets [] when the voltage of the second input end IN2 is 0 [V].

In the following description, the voltage may be represented by + or − in order to clearly indicate the polarity of the output voltage of the semiconductor device 10. When the potential of the first output terminal OUT1 is larger than the potential of the second output end OUT2, the polarity of the output voltage of the semiconductor device 10 is positive (+), and the potential of the first output terminal OUT1 is the potential of the second output end OUT2. When it is smaller than the potential, the polarity of the output voltage of the semiconductor device 10 is negative (−). However, when neither the + sign nor the-sign is attached to the voltage, it represents a + voltage unless otherwise specified.

FIG. 3A shows a switching pattern (1) for outputting an output voltage of + E [V]. In other words, FIG. 3A shows a switching pattern (1) for setting the U-phase voltage to + E [V] when the W-phase voltage is set to 0 [V]. In the switching pattern (1), the switching elements S5a and S5b of the first flying capacitor circuit 11 are turned on, S5c and S5d are turned off, and the voltage of E [V] is output from the first flying capacitor circuit 11. , The switching elements S1a and S1b of the output stage are turned on, S2a and S2b are turned off, and the voltage of E [V] output from the first flying capacitor circuit 11 is output from the first output terminal OUT1. The voltage output from the first flying capacitor circuit 11 is, in other words, an electric circuit between the switching elements S5b and S5c of the first flying capacitor circuit 11 when the voltage of the second input terminal IN2 is 0 [V]. The voltage of. The voltage output from the first output terminal OUT1 is, in other words, the voltage of the first output end OUT1 when the voltage of the second input terminal IN2 is 0 [V].

Further, in the switching pattern (1), the switching elements S8c and S8d of the fourth flying capacitor circuit 14 are turned on, S8a and S8b are turned off, and the voltage of 0 [V] is output from the fourth flying capacitor circuit 14. (That is, power is not output from the fourth flying capacitor circuit 14), the switching elements S4a and S4b of the output stage are turned on, S3a and S3b are turned off, and 0 is output from the fourth flying capacitor circuit 14. The voltage of [V] is output from the second output terminal OUT2. As a result, the output voltage of + E [V] is output from the first output terminal OUT1 and the second output end OUT2. The voltage output from the fourth flying capacitor circuit 14 is, in other words, an electric circuit between the switching elements S8b and S8c of the fourth flying capacitor circuit 14 when the voltage of the second input terminal IN2 is 0 [V]. The voltage of. The voltage output from the second output end OUT2 is, in other words, the voltage of the second output end OUT2 when the voltage of the second input end IN2 is 0 [V].

The voltage output from the second flying capacitor circuit 12 is, in other words, an electric circuit between the switching elements S6b and S6c of the second flying capacitor circuit 12 when the voltage of the second input terminal IN2 is 0 [V]. The voltage of. The voltage output from the third flying capacitor circuit 13 is, in other words, an electric circuit between the switching elements S7b and S7c of the third flying capacitor circuit 13 when the voltage of the second input terminal IN2 is 0 [V]. The voltage of.

In the switching pattern (1), when the second flying capacitor circuit 12 connected in series with the first flying capacitor circuit 11 is controlled in the same switching pattern in conjunction with the first flying capacitor circuit 11, the first flying capacitor circuit 12 is controlled. The difference between the voltage output from the capacitor circuit 11 and the voltage output from the second flying capacitor circuit 12 can be set to E / 2 [V]. Specifically, when the switching elements S6a and S6b of the second flying capacitor circuit 12 are turned on, S6c and S6d are turned off, and E / 2 [V] is output from the second flying capacitor circuit 12, the first The difference between the voltage E [V] output from the flying capacitor circuit 11 and the voltage E / 2 [V] output from the second flying capacitor circuit 12 is E / 2 [V].

Similarly, when the third flying capacitor circuit 13 connected in series with the fourth flying capacitor circuit 14 is controlled in the same switching pattern in conjunction with the fourth flying capacitor circuit 14, the third flying capacitor circuit 13 can be used. The difference between the output voltage and the voltage output from the fourth flying capacitor circuit 14 can be set to E / 2 [V]. Specifically, when the switching elements S7c and S7d of the third flying capacitor circuit 13 are turned on, S7a and S7b are turned off, and E / 2 [V] is output from the third flying capacitor circuit 13, the third flying capacitor circuit 13 is output. The difference between the voltage E / 2 [V] output from the flying capacitor circuit 13 and the voltage 0 [V] output from the fourth flying capacitor circuit 14 is E / 2 [V].

In the switching pattern (1), the four flying capacitors FC1 to FC4 are neither charged nor discharged, and the electric charge is maintained.

FIG. 3B shows a switching pattern (2) for outputting an output voltage of + E / 2 [V]. In other words, FIG. 3B shows a switching pattern (2) for setting the U-phase voltage to + E / 2 [V] when the W-phase voltage is set to 0 [V]. In the switching pattern (2), the switching elements S5a and S5c of the first flying capacitor circuit 11 are turned on, S5b and S5d are turned off, and 3E / 4 [V] is output from the first flying capacitor circuit 11. , The switching elements S1a and S1b of the output stage are turned on, S2a and S2b are turned off, and 3E / 4 [V] output from the first flying capacitor circuit 11 is output from the first output terminal OUT1. Further, the switching elements S8b and S8d of the fourth flying capacitor circuit 14 are turned on, S8a and S8c are turned off, E / 4 [V] is output from the fourth flying capacitor circuit 14, and the switching element of the output stage is output. S4a and S4b are turned on, S3a and S3b are turned off, and E / 4 [V] output from the fourth flying capacitor circuit 14 is output from the second output terminal OUT2. As a result, the output voltage of + E / 2 [V] is output from the first output terminal OUT1 and the second output end OUT2.

At this time, when the switching elements S6a and S6c of the second flying capacitor circuit 12 are turned on, S6b and S6d are turned off, and E / 4 [V] is output from the second flying capacitor circuit 12, the first flying is performed. The difference between the voltage 3E / 4 [V] output from the capacitor circuit 11 and the voltage E / 4 [V] output from the second flying capacitor circuit 12 is E / 2 [V].

Similarly, when the switching elements S7b and S7d of the third flying capacitor circuit 13 are turned on, S7a and S7c are turned off, and 3E / 4 [V] is output from the third flying capacitor circuit 13, the third flying is performed. The difference between the voltage 3E / 4 [V] output from the capacitor circuit 13 and the voltage E / 4 [V] output from the fourth flying capacitor circuit 14 is E / 2 [V].

In the switching pattern (2), the flying capacitor FC1 is charged, the flying capacitor FC4 is discharged, and the flying capacitors FC2 and FC3 are not charged / discharged.

FIG. 3C shows a switching pattern (3) for outputting an output voltage of + E / 2 [V]. In other words, FIG. 3C shows a switching pattern (3) for setting the U-phase voltage to + E / 2 [V] when the W-phase voltage is set to 0 [V]. In the switching pattern (3), the switching elements S5b and S5d of the first flying capacitor circuit 11 are turned on, S5a and S5c are turned off, and 3E / 4 [V] is output from the first flying capacitor circuit 11. , The switching elements S1a and S1b of the output stage are turned on, S2a and S2b are turned off, and 3E / 4 [V] output from the first flying capacitor circuit 11 is output from the first output terminal OUT1. Further, the switching elements S8a and S8c of the fourth flying capacitor circuit 14 are turned on, S8b and S8d are turned off, E / 4 [V] is output from the fourth flying capacitor circuit 14, and the switching element of the output stage is output. S4a and S4b are turned on, S3a and S3b are turned off, and E / 4 [V] output from the fourth flying capacitor circuit 14 is output from the second output terminal OUT2. As a result, the output voltage of + E / 2 [V] is output from the first output terminal OUT1 and the second output end OUT2.

At this time, when the switching elements S6b and S6d of the second flying capacitor circuit 12 are turned on, S6a and S6c are turned off, and E / 4 [V] is output from the second flying capacitor circuit 12, the first flying is performed. The difference between the voltage 3E / 4 [V] output from the capacitor circuit 11 and the voltage E / 4 [V] output from the second flying capacitor circuit 12 is E / 2 [V].

Similarly, when the switching elements S7a and S7c of the third flying capacitor circuit 13 are turned on, S7b and S7d are turned off, and 3E / 4 [V] is output from the third flying capacitor circuit 13, the third flying is performed. The difference between the voltage 3E / 4 [V] output from the capacitor circuit 13 and the voltage E / 4 [V] output from the fourth flying capacitor circuit 14 is E / 2 [V].

In the switching pattern (3), the flying capacitor FC1 is discharged, the flying capacitor FC4 is charged, and the flying capacitors FC2 and FC3 are not charged / discharged.

FIG. 3D shows a switching pattern (4) for outputting an output voltage of + E / 2 [V]. In other words, FIG. 3D shows a switching pattern (4) for setting the U-phase voltage to + E / 2 [V] when the W-phase voltage is set to 0 [V]. In the switching pattern (4), the switching elements S5c and S5d of the first flying capacitor circuit 11 are turned on, S5a and S5b are turned off, and E / 2 [V] is output from the first flying capacitor circuit 11. , The switching elements S1a and S1b of the output stage are turned on, S2a and S2b are turned off, and E / 2 [V] output from the first flying capacitor circuit 11 is output from the first output terminal OUT1. Further, the switching elements S8a and S8b of the fourth flying capacitor circuit 14 are turned on, S8c and S8d are turned off, E / 2 [V] is output from the fourth flying capacitor circuit 14, and the switching element of the output stage is output. S4a and S4b are turned on, S3a and S3b are turned off, and E / 2 [V] output from the fourth flying capacitor circuit 14 is output from the second output terminal OUT2. As a result, an output voltage of 0 [V] is output from the first output terminal OUT1 and the second output end OUT2 (that is, power is not output from the first output end OUT1 and the second output end OUT2).

At this time, when the switching elements S6c and S6d of the second flying capacitor circuit 12 are turned on, S6a and S6b are turned off, and 0 [V] is output from the second flying capacitor circuit 12, the first flying capacitor circuit The difference between the voltage E / 2 [V] output from 11 and the voltage 0 [V] output from the second flying capacitor circuit 12 is E / 2 [V].

Similarly, when the switching elements S7a and S7b of the third flying capacitor circuit 13 are turned on, S7c and S7d are turned off, and E [V] is output from the third flying capacitor circuit 13, the third flying capacitor circuit The difference between the voltage E [V] output from 13 and the voltage E / 2 [V] output from the fourth flying capacitor circuit 14 is E / 2 [V].

In the switching pattern (4), the four flying capacitors FC1 to FC4 are neither charged nor discharged, and the electric charge is maintained.

4A to 4D show a switching pattern in the first example of the switching pattern in the control method of the semiconductor device 10 according to the embodiment, when an output voltage having a polarity in which the U phase is − and the W phase is + is output. Is shown. Also in FIGS. 4A to 4D, the switching element is simplified and shown in order to make the figure easier to see.

FIG. 4A shows a switching pattern (1) for outputting an output voltage of −E [V]. In the switching pattern (1), the switching elements S6c and S6d of the second flying capacitor circuit 12 are turned on, S6a and S6b are turned off, and 0 [V] is output from the second flying capacitor circuit 12 and is output. The switching elements S2a and S2b of the stage are turned on, S1a and S1b are turned off, and 0 [V] output from the second flying capacitor circuit 12 is output from the first output terminal OUT1. Further, the switching elements S7a and S7b of the third flying capacitor circuit 13 are turned on, S7c and S7d are turned off, E [V] is output from the third flying capacitor circuit 13, and the switching elements S3a and the switching element S3a and the output stage are output. S3b is turned on, S4a and S4b are turned off, and E [V] output from the third flying capacitor circuit 13 is output from the second output terminal OUT2. As a result, the output voltage of −E [V] is output from the first output terminal OUT1 and the second output terminal OUT2.

At this time, when the switching elements S5c and S5d of the first flying capacitor circuit 11 are turned on, S5a and S5b are turned off, and E / 2 [V] is output from the first flying capacitor circuit 11, the first flying is performed. The difference between the voltage E / 2 [V] output from the capacitor circuit 11 and the voltage 0 [V] output from the second flying capacitor circuit 12 is E / 2 [V].

Similarly, when the switching elements S8a and S8b of the fourth flying capacitor circuit 14 are turned on, S8c and S8d are turned off, and E / 2 [V] is output from the fourth flying capacitor circuit 14, the third flying The difference between the voltage E [V] output from the capacitor circuit 13 and the voltage E / 2 [V] output from the fourth flying capacitor circuit 14 is E / 2 [V].

In the switching pattern (1), the four flying capacitors FC1 to FC4 are neither charged nor discharged, and the electric charge is maintained.

FIG. 4B shows a switching pattern (2) for outputting an output voltage of −E / 2 [V]. In the switching pattern (2), the switching elements S6b and S6d of the second flying capacitor circuit 12 are turned on, S6a and S6c are turned off, and E / 4 [V] is output from the second flying capacitor circuit 12. , The switching elements S2a and S2b of the output stage are turned on, S1a and S1b are turned off, and E / 4 [V] output from the second flying capacitor circuit 12 is output from the first output terminal OUT1. Further, the switching elements S7a and S7c of the third flying capacitor circuit 13 are turned on, S7b and S7d are turned off, 3E / 4 [V] is output from the third flying capacitor circuit 13, and the switching element of the output stage is output. S3a and S3b are turned on, S4a and S4b are turned off, and 3E / 4 [V] output from the third flying capacitor circuit 13 is output from the second output terminal OUT2. As a result, the output voltage of −E / 2 [V] is output from the first output terminal OUT1 and the second output end OUT2.

At this time, when the switching elements S5b and S5d of the first flying capacitor circuit 11 are turned on, S5a and S5c are turned off, and 3E / 4 [V] is output from the first flying capacitor circuit 11, the first flying is performed. The difference between the voltage 3E / 4 [V] output from the capacitor circuit 11 and the voltage E / 4 [V] output from the second flying capacitor circuit 12 is E / 2 [V].

Similarly, when the switching elements S8a and S8c of the fourth flying capacitor circuit 14 are turned on, S8b and S8d are turned off, and E / 4 [V] is output from the fourth flying capacitor circuit 14, the third flying The difference between the voltage 3E / 4 [V] output from the capacitor circuit 13 and the voltage E / 4 [V] output from the fourth flying capacitor circuit 14 is E / 2 [V].

In the switching pattern (2), the flying capacitor FC2 is discharged, the flying capacitor FC3 is charged, and the flying capacitors FC1 and FC4 are not charged / discharged.

FIG. 4C shows a switching pattern (3) for outputting an output voltage of −E / 2 [V]. In the switching pattern (3), the switching elements S6a and S6c of the second flying capacitor circuit 12 are turned on, S6b and S6d are turned off, and E / 4 [V] is output from the second flying capacitor circuit 12. , The switching elements S2a and S2b of the output stage are turned on, S1a and S1b are turned off, and E / 4 [V] output from the second flying capacitor circuit 12 is output from the first output terminal OUT1. Further, the switching elements S7b and S7d of the third flying capacitor circuit 13 are turned on, S7a and S7c are turned off, 3E / 4 [V] is output from the third flying capacitor circuit 13, and the switching element of the output stage is output. S3a and S3b are turned on, S4a and S4b are turned off, and 3E / 4 [V] output from the third flying capacitor circuit 13 is output from the second output terminal OUT2. As a result, the output voltage of −E / 2 [V] is output from the first output terminal OUT1 and the second output end OUT2.

At this time, when the switching elements S5a and S5c of the first flying capacitor circuit 11 are turned on, S5b and S5d are turned off, and 3E / 4 [V] is output from the first flying capacitor circuit 11, the first flying is performed. The difference between the voltage 3E / 4 [V] output from the capacitor circuit 11 and the voltage E / 4 [V] output from the second flying capacitor circuit 12 is E / 2 [V].

Similarly, when the switching elements S8b and S8d of the fourth flying capacitor circuit 14 are turned on, S8a and S8c are turned off, and E / 4 [V] is output from the fourth flying capacitor circuit 14, the third flying The difference between the voltage 3E / 4 [V] output from the capacitor circuit 13 and the voltage E / 4 [V] output from the fourth flying capacitor circuit 14 is E / 2 [V].

In the switching pattern (3), the flying capacitor FC2 is charged, the flying capacitor FC3 is discharged, and the flying capacitors FC1 and FC4 are not charged / discharged.

FIG. 4D shows a switching pattern (4) for outputting an output voltage of 0 [V] (that is, the semiconductor device 10 does not output power). In the switching pattern (4), the switching elements S6a and S6b of the second flying capacitor circuit 12 are turned on, S6c and S6d are turned off, and E / 2 [V] is output from the second flying capacitor circuit 12. , The switching elements S2a and S2b of the output stage are turned on, S1a and S1b are turned off, and E / 2 [V] output from the second flying capacitor circuit 12 is output from the first output terminal OUT1. Further, the switching elements S7c and S7d of the third flying capacitor circuit 13 are turned on, S7a and S7b are turned off, E / 2 [V] is output from the third flying capacitor circuit 13, and the switching element of the output stage is output. S3a and S3b are turned on, S4a and S4b are turned off, and E / 2 [V] output from the third flying capacitor circuit 13 is output from the second output terminal OUT2. As a result, an output voltage of 0 [V] is output from the first output terminal OUT1 and the second output end OUT2 (that is, power is not output from the first output end OUT1 and the second output end OUT2).

At this time, when the switching elements S5a and S5b of the first flying capacitor circuit 11 are turned on, S5c and S5d are turned off, and E [V] is output from the first flying capacitor circuit 11, the first flying capacitor circuit The difference between the voltage E [V] output from 11 and the voltage E / 2 [V] output from the second flying capacitor circuit 12 is E / 2 [V].

Similarly, when the switching elements S8c and S8d of the fourth flying capacitor circuit 14 are turned on, S8a and S8b are turned off, and 0 [V] is output from the fourth flying capacitor circuit 14, the third flying capacitor circuit The difference between the voltage E / 2 [V] output from 13 and the voltage 0 [V] output from the fourth flying capacitor circuit 14 is E / 2 [V].

In the switching pattern (4), the four flying capacitors FC1 to FC4 are neither charged nor discharged, and the electric charge is maintained.

As described above, the capacitor 10 according to the present embodiment can output a voltage in five stages of −E, −E / 2, 0, + E / 2, and + E, and FIGS. 3A to 4D show. In all the switching patterns in the first example shown, the difference between the output voltage of the first flying capacitor circuit 11 and the output voltage of the second flying capacitor circuit 12 is E / 2 [V] or less, and the third The difference between the output voltage of the flying capacitor circuit 13 and the output voltage of the fourth flying capacitor circuit 14 is also E / 2 [V] or less. Further, in order to generate a half wave of AC power, while outputting an output voltage having a polarity in which the U phase is + and the W phase is −, as shown in FIGS. 3A to 3D, the switching element S1a in the output stage, S1b, S4a, and S4b are on, and S2a, S2b, S3a, and S3b are off. Further, as shown in FIGS. 4A to 4D, the switching of the output stage is performed while the output voltage having the polarity in which the U phase is − and the W phase is + is output in order to generate a half wave of the opposite polarity of the AC power. The elements S2a, S2b, S3a, S3b are on, and S1a, S1b, S4a, S4b are off. In this way, the switching element of the output stage is switched on and off only when the polarity of the output voltage of the semiconductor device 10 is switched.

5A to 5D show a switching pattern when an output voltage having a polarity in which the U phase is + and the W phase is − in the second example of the switching pattern in the control method of the semiconductor device 10 according to the embodiment. show. In the switching patterns (1) to (4) shown in FIGS. 5A to 5D, the switching pattern between the switching element constituting the first flying capacitor circuit 11 and the fourth flying capacitor circuit 14 and the switching element of the output stage is It is the same as the switching patterns (1) to (4) in the first example shown in FIGS. 3A to 3D, respectively. Therefore, the voltage output from the first flying capacitor circuit 11 and the fourth flying capacitor circuit 14 and the charge / discharge state of the flying capacitors FC1 and FC4 are switched in the first example shown in FIGS. 3A to 3D. This is the same as in the cases of patterns (1) to (4).

In the switching patterns (1) to (4) shown in FIGS. 5A to 5D, the switching patterns of the switching elements constituting the second flying capacitor circuit 12 and the third flying capacitor circuit 13 are all the same, and the switching elements S6a, S6b, S7c, and S7d remain on all the time, and switching elements S6c, S6d, S7a, and S7b remain off all the time. Therefore, both the output voltage of the second flying capacitor circuit 12 and the output voltage of the third flying capacitor circuit 13 remain E / 2 [V].

Then, the difference between the output voltage of the first flying capacitor circuit 11 and the output voltage of the second flying capacitor circuit 12 is E / 2 [V] in the switching pattern (1), and the switching patterns (2) and (3). Then, it becomes E / 4 [V], and in the switching pattern (4), it becomes 0 [V]. Further, the difference between the output voltage of the third flying capacitor circuit 13 and the output voltage of the fourth flying capacitor circuit 14 is also E / 2 [V] in the switching pattern (1), and the switching patterns (2) and (3). Then, it becomes E / 4 [V], and in the switching pattern (4), it becomes 0 [V]. Therefore, also in the second example, the difference between the output voltage of the first flying capacitor circuit 11 and the output voltage of the second flying capacitor circuit 12, and the output voltage of the third flying capacitor circuit 13 and the fourth The difference from the output voltage of the flying capacitor circuit 14 can be controlled to be E / 2 [V] or less.

6A to 6D show a switching pattern when an output voltage having a polarity in which the U phase is − and the W phase is + is output in the second example of the switching pattern in the control method of the semiconductor device 10 according to the embodiment. show. In the switching patterns (1) to (4) shown in FIGS. 6A to 6D, the switching patterns of the switching elements constituting the second flying capacitor circuit 12 and the third flying capacitor circuit 13 and the switching elements of the output stage are shown in FIGS. It is the same as the switching patterns (1) to (4) in the first example shown in 4A to 4D, respectively. Therefore, the voltage output from the second flying capacitor circuit 12 and the third flying capacitor circuit 13 and the charge / discharge states of the flying capacitors FC2 and FC3 are also the switching patterns in the first example shown in FIGS. 4A to 4D. It is the same as the case of (1) to (4) respectively.

In the switching patterns (1) to (4) shown in FIGS. 6A to 6D, the switching patterns of the switching elements constituting the first flying capacitor circuit 11 and the fourth flying capacitor circuit 14 are all the same, and the switching elements S5c, S5d, S8a, and S8b remain on all the time, and switching elements S5a, S5b, S8c, and S8d remain off all the time. Therefore, both the output voltage of the first flying capacitor circuit 11 and the output voltage of the fourth flying capacitor circuit 14 remain E / 2 [V].

Then, the difference between the output voltage of the first flying capacitor circuit 11 and the output voltage of the second flying capacitor circuit 12 is E / 2 [V] in the switching pattern (1), and the switching patterns (2) and (3). Then, it becomes E / 4 [V], and in the switching pattern (4), it becomes 0 [V]. Further, the difference between the output voltage of the third flying capacitor circuit 13 and the output voltage of the fourth flying capacitor circuit 14 is also E / 2 [V] in the switching pattern (1), and the switching patterns (2) and (3). Then, it becomes E / 4 [V], and in the switching pattern (4), it becomes 0 [V]. Therefore, also in the second example, the difference between the output voltage of the first flying capacitor circuit 11 and the output voltage of the second flying capacitor circuit 12, and the output voltage of the third flying capacitor circuit 13 and the fourth The difference from the output voltage of the flying capacitor circuit 14 can be controlled to be E / 2 [V] or less.

In the second example, when the polarity of the output voltage is switched, that is, in the switching pattern (4), the difference between the output voltage of the first flying capacitor circuit 11 and the output voltage of the second flying capacitor circuit 12 is also The difference between the output voltage of the third flying capacitor circuit 13 and the output voltage of the fourth flying capacitor circuit 14 is also 0 [V]. Therefore, since the switching element of the output stage can be controlled by zero voltage switching (ZVS), the loss and load generated during switching can be reduced.

The switching pattern of the semiconductor device 10 is switched between, for example, switching patterns (1) to (4) during a constant switching cycle. In the control method of the semiconductor device 10 according to the present embodiment, as shown in FIGS. 3B and 3C, FIGS. 5B and 5C, the same voltage + E / 2 [V] is applied to different switching patterns (2) and (3). In the switching pattern (2), the flying capacitor FC1 is charged while the flying capacitor FC4 is discharged. In the switching pattern (3), the flying capacitor FC1 is discharged while the flying capacitor FC4 is charged. Therefore, when the output voltage of + E / 2 [V] is output, the ratio of the time length for executing the switching pattern (2) in the switching cycle to the time length for executing the switching pattern (3) in the switching cycle. By controlling the ratio, the voltages of the flying capacitors FC1 and FC4 can be kept constant. Similarly, as shown in FIGS. 4B and 4C, FIGS. 6B and 6C, the same voltage −E / 2 [V] can be output by different switching patterns (2) and (3), but the switching pattern ( In 2), the flying capacitor FC2 is discharged while the flying capacitor FC3 is charged. In the switching pattern (3), the flying capacitor FC2 is charged while the flying capacitor FC3 is discharged. Therefore, when the output voltage of −E / 2 [V] is output, the ratio of the time length for executing the switching pattern (2) in the switching cycle and the time length for executing the switching pattern (3) in the switching cycle. By controlling the ratio of, the voltages of the flying capacitors FC2 and FC3 can be kept constant. Thereby, the output voltage of the semiconductor device 10 can be controlled more accurately and efficiently.

In the switching pattern shown in FIGS. 3B, 3C, 4B, 4C, 5B, 5C, 6B, and 6C, one of the two flying capacitors is charged and the other is discharged. As described, it is also possible to control both to be charged or discharged.

7B and 7D show another example of the switching pattern (2) shown in FIG. 3B and the switching pattern (3) shown in FIG. 3C. The switching pattern shown in FIG. 7A is the same as the switching pattern (2) shown in FIG. 3B, and the switching pattern shown in FIG. 7C is the same as the switching pattern (3) shown in FIG. 3C, but for comparison. It is shown again in. In the switching pattern (5) shown in FIG. 7B, the switching patterns of the switching elements constituting the two flying capacitor circuits 11 and 12 on the U phase side are the same as the switching pattern (2), but the two on the W phase side. Since the switching pattern of the switching element constituting the flying capacitor circuits 13 and 14 is the same as the switching pattern (3), the flying capacitor FC1 and the flying capacitor FC4 are charged. In the switching pattern (6) shown in FIG. 7D, the switching patterns of the switching elements constituting the two flying capacitor circuits 11 and 12 on the U phase side are the same as the switching pattern (3), but the two on the W phase side. Since the switching pattern of the switching elements constituting the flying capacitor circuits 13 and 14 is the same as the switching pattern (2), the flying capacitor FC1 and the flying capacitor FC4 are discharged. Similarly, for the switching pattern (2) shown in FIGS. 4B, 5B, and 6B and the switching pattern (3) shown in FIGS. 4C, 5C, and 6C, the switching patterns (2) and (3) are used. By combining, it is possible to control both of the two flying capacitors to be charged or discharged.

In the first example of the switching pattern in the control method of the semiconductor device 10 according to the present embodiment, when only the switching patterns (2) and (3) are used and the switching patterns (5) and (6) are not used, In all the switching patterns shown in FIGS. 3A to 3D and FIGS. 4A to 4D, the switching patterns of the switching elements constituting the two flying capacitor circuits connected in series are interlocked with each other and face each other connected in parallel. The switching pattern of the switching elements constituting the two flying capacitor circuits connected in series of the arms is inverted. That is, the first flying capacitor circuit 11 and the second flying capacitor circuit 12 are interlocked and controlled, the third flying capacitor circuit 13 and the fourth flying capacitor circuit 14 are also interlocked and controlled, and the first flying capacitor circuit 11 The second flying capacitor circuit 12, the third flying capacitor circuit 13, and the fourth flying capacitor circuit 14 are inverting controlled (the switching pattern is inverting). Further, the switching elements S1a and S1b and S4a and S4b of the output stage are interlocked and controlled, and the switching elements S2a and S2b and S3a and S3b are also interlocked and controlled. Inversion control is performed with S2b, S3a, and S3b (the switching pattern is inverted). Therefore, the control lines for supplying the gate signal from the control circuit to the gate terminal of each switching element constituting the semiconductor device 10 are four lines for controlling the switching elements constituting the flying capacitor circuits 11 to 14 and an output. A total of six, two for controlling the polarity of the output voltage by the switching element of the stage, may be used. The switching elements constituting the third flying capacitor circuit 13 and the fourth flying capacitor circuit 14 include control signals of control signals supplied to the switching elements constituting the first flying capacitor circuit 11 and the second flying capacitor circuit 12. An inverting signal is supplied. As described above, according to the semiconductor device 10 according to the present embodiment, the number of control lines can be suppressed to six, so that an inexpensive and compact semiconductor device 10 can be provided. Moreover, since the control can be simplified, the occurrence of malfunctions and failures can be reduced.

In the first example of the switching pattern in the control method of the semiconductor device 10 according to the present embodiment, when not only the switching patterns (2) and (3) but also the switching patterns (5) and (6) are used together. Even if the voltage of the flying capacitor FC1 and the flying capacitor FC4 or the voltage of the flying capacitor FC2 and the flying capacitor FC3 deviates, each flying capacitor can be charged and discharged independently, so that the flying capacitor can be finely flown. The voltage of the capacitor can be adjusted and kept constant. In this case as well, the first flying capacitor circuit 11 and the second flying capacitor circuit 12 are interlocked and controlled, and the third flying capacitor circuit 13 and the fourth flying capacitor circuit 14 are interlocked and controlled. The control lines for supplying the gate signal to the gate terminal of each switching element constituting the semiconductor device 10 are four for controlling the switching elements constituting the flying capacitor circuits 11 and 12, the flying capacitor circuit 13 and the control line. A total of 10 units may be used, 4 for controlling the switching elements constituting the 14 and 2 for controlling the polarity of the output voltage by the switching element of the output stage.

The switching patterns described above are all switching patterns in which electric power is sent from the DC side to the AC side, but as described above, the semiconductor device 10 according to the present embodiment transfers electric power from the AC side to the DC side. It is also possible to send. In this case, the direction of the current is reversed, so that charging and discharging of the flying capacitor are opposite.

Hereinafter, in the method for controlling the semiconductor device according to the present embodiment, a technique for keeping the voltage of the flying capacitor constant will be described.

FIG. 8 shows a first example of the control method of the semiconductor device 10 according to the embodiment. In the first example, the duty ratio of the switching element is controlled by using two carrier waves. As shown in the uppermost stage, in the control circuit, the gate signals Gu2 and Gu3 are generated by comparing the first carrier wave (solid line) which is a triangular wave with the reference signal (thick line rectangular wave) for duty control. The gate signals Gu1 and Gu4 are generated by comparing the second carrier wave (broken line) in which the phase of the first carrier wave is inverted with the reference signal for duty control. The generated gate signals Gu1 to Gu4 are shown in the second to fifth stages. The reference signal for duty control is adjusted according to the voltage to be output by the semiconductor device 10.

The generated gate signals Gu1 to Gu4 are supplied to the respective switching elements via the control line. In the first example, the switching patterns (5) and (6) are not used, but the switching patterns (2) and (3) are used. Therefore, the gate signal Gu1 is supplied to the switching elements S5a and S6a, the inverting signal of the gate signal Gu1 is supplied to the switching elements S7a and S8a, the gate signal Gu2 is supplied to the switching elements S5b and S6b, and the switching elements S7b and S8b are supplied. The inverting signal of the gate signal Gu2 is supplied, the gate signal Gu3 is supplied to the switching elements S5c and S6c, the inverting signal of the gate signal Gu3 is supplied to the switching elements S7c and S8c, and the gate signal Gu4 is supplied to S5d and S6d. The inverted signal of the gate signal Gu4 is supplied to S7d and S8d. The switching pattern realized by the gate signals Gu1 to Gu4 is shown in the sixth stage, and the charging / discharging state of the flying capacitor FC1 is shown in the seventh stage.

In the first example, a gate signal is generated using two carriers whose phases are inverted, and the duty ratio of the switching element is controlled by the generated gate signal. Therefore, as shown in the seventh stage, each switching period. In the switching pattern (2), the period in which the flying capacitor FC1 (FC3) is charged can always be equal to the period in which the flying capacitor FC1 (FC3) is discharged in the switching pattern (3). Further, in each switching cycle, the period during which the flying capacitor FC4 (FC2) is discharged in the switching pattern (2) and the period during which the flying capacitor FC4 (FC2) is charged in the switching pattern (3) may always be equal. can. Thereby, the charging / discharging period of the flying capacitor can be balanced and the voltage of the flying capacitor can be kept constant by a simple configuration and control.

FIG. 9 shows a second example of the control method of the semiconductor device 10 according to the embodiment. In the second example, the duty ratio of the switching element is controlled by using two carrier waves as in the first example, but in the second example, the level of the carrier wave is adjusted according to the voltage of the flying capacitor. Allows the duty ratio to be adjusted. Even if the duty is controlled so that the charging period and the discharging period of the flying capacitor are always equal as in the first example, it is caused by the variation in the characteristics of the flying capacitor itself, the switching element, and the load condition. As a result, the voltage of the flying capacitor may vary and deviate from a predetermined voltage. According to the second example, even if the voltage of the flying capacitor deviates from a predetermined value, for example, E / 4 [V], the voltage of the flying capacitor can be adjusted by adjusting the charging period and the discharging period of the flying capacitor. Can be kept at a predetermined voltage.

As shown in the uppermost stage, in the first switching cycle, the two carriers whose phases are inverted are at the same level, but in the second switching cycle, the level of the first carrier wave shown by the solid line is the first. It is adjusted to be lower than the level of the first carrier wave in the switching cycle. As a result, in the second switching cycle, the period during which the gate signal Gu2 generated by the first carrier wave becomes high level becomes longer than that in the first switching cycle, and the gate signal Gu3 generated by the first carrier wave becomes low level. Since the period of becoming is longer than the first switching cycle, the period of the switching pattern (3) is longer than the period of the switching pattern (2). Therefore, the period in which the flying capacitor FC4 (FC2) is charged is longer than the period in which it is discharged, and as a result, the flying capacitor FC4 (FC2) is charged and the voltage rises.

Also in the second example of the control method of the semiconductor device 10 according to the embodiment, the switching patterns (2) and (3) are used without using the switching patterns (5) and (6) as in the first example. It may be used to control the switching element by six control lines. Rather than using only the switching patterns (5) and (6), using the switching patterns (2) and (3) together makes the voltages of the flying capacitor on the U-phase side and the voltage of the flying capacitor on the W-phase side independent. Since it can be adjusted, the fluctuation of the voltage of the flying capacitor can be smoothed more finely and kept at a predetermined voltage. When controlling to the switching patterns (5) and (6), the gate signals Gu1 to Gu4 are not inverted, and the switching element constituting the third flying capacitor circuit 13 and the fourth flying capacitor circuit 14 on the W phase side is used. Supply.

In this case, the semiconductor device 10 is a first comparison circuit that compares the voltage of the flying capacitor FC1 constituting the first flying capacitor circuit 11 or the flying capacitor FC2 constituting the second flying capacitor circuit 12 with a predetermined voltage. Further, a second comparison circuit for comparing the voltage of the flying capacitor FC3 constituting the third flying capacitor circuit 13 or the flying capacitor FC4 constituting the fourth flying capacitor circuit 14 with a predetermined voltage is provided.

When the voltage of the flying capacitor FC1 or FC2 is lower than E / 4 [V], the carrier level is adjusted so that the charging period of the flying capacitor FC1 or FC2 is longer than the discharging period in the switching cycle from the next time onward. , The gate signal generated by the level-adjusted carrier is supplied to the switching elements constituting the first flying capacitor circuit 11 and the second flying capacitor circuit 12. That is, when the control circuit determines that the voltage of the flying capacitor FC1 or FC2 is lower than E / 4 [V] based on the comparison result in the first comparison circuit, in the subsequent switching cycle, the control circuit sets the flying capacitor. The level of the carrier is adjusted so that the charging period of FC1 or FC2 is longer than the discharging period. When the voltage of the flying capacitor FC1 or FC2 is higher than E / 4 [V], the carrier level is adjusted so that the charging period of the flying capacitor FC1 or FC2 is shorter than the discharging period in the switching cycle from the next time onward. , The gate signal generated by the level-adjusted carrier is supplied to the switching elements constituting the first flying capacitor circuit 11 and the second flying capacitor circuit 12. That is, when the control circuit determines that the voltage of the flying capacitor FC1 or FC2 is higher than E / 4 [V] based on the comparison result in the first comparison circuit, in the subsequent switching cycle, the control circuit sets the flying capacitor. The level of the carrier is adjusted so that the charging period of FC1 or FC2 is shorter than the discharging period.

If the voltage of the flying capacitor FC3 or FC4 is lower than E / 4 [V], adjust the carrier level so that the charging period of the flying capacitor FC3 or FC4 is longer than the discharging period in the switching cycle from the next time onward. , The gate signal generated by the level-adjusted carrier is supplied to the switching elements constituting the third flying capacitor circuit 13 and the fourth flying capacitor circuit 14. That is, when the control circuit determines that the voltage of the flying capacitor FC3 or FC4 is lower than E / 4 [V] based on the comparison result in the second comparison circuit, in the subsequent switching cycle, the control circuit sets the flying capacitor. The level of the carrier is adjusted so that the charging period of FC3 or FC4 is longer than the discharging period. When the voltage of the flying capacitor FC3 or FC4 is higher than E / 4 [V], the carrier level is adjusted so that the charging period of the flying capacitor FC3 or FC4 is shorter than the discharging period in the switching cycle from the next time onward. , The gate signal generated by the level-adjusted carrier is supplied to the switching elements constituting the third flying capacitor circuit 13 and the fourth flying capacitor circuit 14. That is, when the control circuit determines that the voltage of the flying capacitor FC3 or FC4 is higher than E / 4 [V] based on the comparison result in the second comparison circuit, in the subsequent switching cycle, the control circuit sets the flying capacitor. The level of the carrier is adjusted so that the charging period of FC3 or FC4 is shorter than the discharging period.

In the first comparison circuit, the voltage of the flying capacitor constituting the flying capacitor circuit of the switching element S1a, S1b, S2a, and S2b of the U-phase output stage connected to the on switching element is predetermined. In the second comparison circuit, the flying capacitor circuit of the switching elements S3a, S3b, S4a, and S4b of the output stage of the W phase, which is connected to the on switching element, is configured. The voltage of the flying capacitor may be compared to a given voltage. For example, when the switching elements S1a and S1b, or S3a and S3b are on, the voltage of the flying capacitors FC1 or FC3 constituting the first flying capacitor circuit 11 or the third flying capacitor circuit 13 is predetermined. Compared to the voltage, the voltage of the flying capacitors FC2 or FC4 constituting the second flying capacitor circuit 12 or the fourth flying capacitor circuit 14 when the switching elements S2a and S2b, or S4a and S4b are turned on. May be compared to a given voltage. This makes it possible to control the charging and discharging of the flying capacitor based on the voltage of the flying capacitor on the side where a large current is flowing (the one connected to the switching element that is on) and where the voltage change is large. Therefore, the voltage of the flying capacitor can be more accurately balanced and kept constant.

Four comparison circuits for comparing the respective voltages of the flying capacitors FC1 to FC4 with a predetermined voltage may be provided, and the voltage of each flying capacitor may be independently adjustable. Further, only a comparison circuit for comparing the voltage of one of the flying capacitors FC1 to FC4 with a predetermined voltage may be provided, and the voltages of all the flying capacitors may be adjusted based on the voltage of the flying capacitors.

FIG. 10 shows a third example of the control method of the semiconductor device 10 according to the embodiment. In the third example, unlike the first and second examples, a single carrier wave is used to control the duty ratio of the switching element.

The carrier wave shown in the uppermost stage and the reference signal for duty control generate the control signal A shown in the second stage and the control signal B shown in the third stage. The control signal B is an inverted signal of the control signal A. In the third example, as in the second example, a comparison circuit for comparing the voltage of the flying capacitor with a predetermined voltage is provided, and the output of the comparison circuit is used as the charge / discharge control signal shown in the fourth stage. Will be done. If the voltage of the flying capacitor is lower than the specified voltage, a high level signal indicating charging is output in the next switching cycle, and if the voltage of the flying capacitor is higher than the specified voltage, it is discharged in the next switching cycle. A low level signal indicating is output.

Either the control signal A or the control signal B is assigned to the gate signals Gu1 to Gu4 shown in the fifth to eighth stages according to the state of the charge / discharge control signal. In other words, each of the gate signals Gu1 to Gu4 shown in the 5th to 8th stages is either a control signal A or a control signal B depending on the state of the charge / discharge control signal. Specifically, when the charge / discharge control signal is at a high level indicating charging, a gate signal that becomes a switching pattern for charging the flying capacitor is generated, and the charge / discharge control signal is at a low level indicating discharge. If, a gate signal is generated that serves as a switching pattern for discharging the flying capacitor. The switching pattern realized by the gate signals Gu1 to Gu4 is shown in the 9th stage, and the charging / discharging state of the flying capacitor is shown in the 10th stage.

Also in the third example, as in the second example, the first to fourth flying capacitor circuits are formed with reference to the voltage of any of the flying capacitors FC1 to FC4 without using the switching patterns (5) and (6). All the switching elements constituting it may be controlled in conjunction with each other, or the switching patterns (5) and (6) may be used in combination to form the first or second flying capacitor circuit on the U-phase side. Alternatively, the flying capacitors FC3 or FC4 constituting the third or fourth flying capacitor circuit on the W phase side are controlled in conjunction with the switching elements constituting the first and second flying capacitor circuits with reference to the voltage of FC2. The switching elements constituting the third and fourth flying capacitor circuits may be interlocked and controlled based on the voltage of. Further, four comparison circuits for comparing the respective voltages of the flying capacitors FC1 to FC4 with a predetermined voltage may be provided in the semiconductor device 10, and the voltage of each flying capacitor may be independently adjustable, or the flying capacitor may be adjusted independently. Only a comparison circuit for comparing the voltage of one of the capacitors FC1 to FC4 with a predetermined voltage may be provided in the semiconductor device 10, and the voltages of all the flying capacitors may be adjusted based on the voltage of the flying capacitors.

FIG. 11 shows another example of the flying capacitor circuit of the semiconductor device 10 according to the embodiment. In the above, the semiconductor device 10 using the three-level flying capacitor circuit has been described. However, as the first to fourth flying capacitor circuits 11 to 14 of the semiconductor device 10, it is possible to output an output voltage having a number of levels larger than three. Flying capacitor circuits may be used. For example, when a two-stage flying capacitor circuit is used, one switching element is further connected in series to each of the high-potential side and the low-potential side of the four switching elements constituting the one-stage flying capacitor circuit, and the addition is added. A second flying capacitor FC (2) is further connected between the connection points of the two switching elements and the series circuit of the four switching elements constituting the one-stage flying capacitor circuit. In the same manner thereafter, the N (N is a natural number) stage flying capacitor circuit is composed of (2N + 4) switching switching elements and N flying capacitors.

The voltage of the first capacitor FC (1) is controlled to be {1 / (2N + 2)} times the DC power supply voltage E, and the voltage of the second capacitor FC (2) is the DC power supply voltage E. It is controlled to be {2 / (2N + 2)} times the voltage of, and the voltage of the Nth capacitor FC (N) is controlled to be {N / (2N + 2)} times the DC power supply voltage E. Will be done. As a result, the N-stage flying capacitor circuit can output an output voltage of (2N + 1) level. Therefore, the semiconductor device 10 composed of four N-stage flying capacitor circuits has the first output terminal OUT1 and the second. A (2N + 3) level voltage can be output from the output terminal OUT2.

From the embodiments described above, the following aspects are disclosed. In each of the following embodiments, each of the switching elements S1 to S4 may be replaced by a series circuit of a plurality of switching elements.

The semiconductor device according to an embodiment of the present embodiment includes a first flying capacitor circuit and a second flying capacitor circuit connected in series in parallel with a DC power supply, a first flying capacitor circuit connected in series with a DC power supply, and a first flying capacitor circuit. A third flying capacitor circuit and a fourth flying capacitor circuit connected in series with the second flying capacitor circuit, and a series connection between the output terminals of the first flying capacitor circuit and the second flying capacitor circuit. Switching element S1 and switching element S2, switching element S3 and switching element S4 connected in series between the output terminals of the third flying capacitor circuit and the fourth flying capacitor circuit, switching element S1 and switching element connected in series. A first output terminal provided at the midpoint of S2 and a second output terminal provided at the midpoint of the switching element S3 and the switching element S4 connected in series are provided with the first flying capacitor circuit. The connection point of the second flying capacitor circuit and the connection point of the third flying capacitor circuit and the fourth flying capacitor circuit are connected to the midpoint of the DC power supply voltage, and the first output terminal and the second output terminal are connected. Outputs AC power from.

According to this aspect, the withstand voltage of the switching elements S1 to S4 in the output stage can be reduced.

In this semiconductor device, a half wave of AC power is generated when the switching element S1 and the switching element S4 are in the on state, and the switching element S2 and the switching element S3 are in the off state, and the switching element S1 and the switching element S4 are in the off state, and switching. When the element S2 and the switching element S3 are on, a half wave of opposite polarity of AC power may be generated.

According to this aspect, since the output voltage closer to the sine wave can be output, the LC filter can be miniaturized.

In this semiconductor device, the switching element S1 and the switching element S4 are in the on state, the switching element S2 and the switching element S3 are in the off state, the switching element S1 and the switching element S4 are in the off state, and the switching element S2 and the switching element are in the off state. Switching from the state in which S3 is on may be controlled so as to operate when the polarity of the AC power output from the first output terminal and the second output terminal is switched.

According to this aspect, since the switching elements S1 to S4 can be controlled to operate only at the time of zero cross, the switching elements S1 to S4 can be configured by a plurality of directly connected switching elements.

This semiconductor device may have a configuration in which a plurality of switching elements having a lower withstand voltage are connected in series instead of the switching element S1, the switching element S2, the switching element S3, or the switching element S4.

According to this aspect, the withstand voltage of the switching elements S1 to S4 in the output stage can be further reduced.

In this semiconductor device, the difference between the output voltage of the first flying capacitor circuit and the output voltage of the second flying capacitor circuit, and the output voltage of the third flying capacitor circuit and the output voltage of the fourth flying capacitor circuit. The difference between the two may be controlled to be less than or equal to half the voltage of the DC power supply voltage.

According to this aspect, the withstand voltage of the switching elements S1 to S4 in the output stage can be reduced.

In this semiconductor device, the first flying capacitor circuit comprises a S5a switching element, a S5b switching element, a S5c switching element, and an S5d switching element connected in series, and an S5a switching element and an S5b switching element. The second flying capacitor circuit includes the first capacitor FC1 connected between the connection point and the connection point between the S5c switching element and the S5d switching element, and the second flying capacitor circuit is a series-connected S6a switching element. Connection between the S6b switching element, the S6c switching element, and the S6d switching element, the connection point between the S6a switching element and the S6b switching element, and the connection point between the S6c switching element and the S6d switching element. The third flying capacitor circuit includes the second capacitor FC2, and the third flying capacitor circuit includes the S7a switching element, the S7b switching element, the S7c switching element, the S7d switching element, and the S7a switching element connected in series. The fourth flying capacitor circuit is connected in series, including a third capacitor FC3 connected between a connection point with the S7b switching element and a connection point between the S7c switching element and the S7d switching element. The connection point between the S8a switching element, the S8b switching element, the S8c switching element, and the S8d switching element, the connection point between the S8a switching element and the S8b switching element, and the connection between the S8c switching element and the S8d switching element. It may include a fourth capacitor FC4 connected between the points.

According to this aspect, the withstand voltage of all the switching elements constituting the semiconductor device can be reduced to 1/4 of the DC power supply voltage.

In this semiconductor device, the first flying capacitor circuit comprises one capacitor, the second flying capacitor circuit comprises one capacitor, and the third flying capacitor circuit comprises one capacitor. The fourth flying capacitor circuit includes one capacitor, and the voltage of the capacitor is controlled to be 1/4 times the voltage of the DC power supply, and the voltage is controlled from the first output terminal and the second output terminal. Five levels of voltage may be output.

According to this aspect, a semiconductor device capable of outputting 5 levels of output voltage can be configured by a switching element having a low withstand voltage.

In this semiconductor device, the first flying capacitor circuit contains N (N is a natural number) capacitors, the second flying capacitor circuit contains N (N is a natural number) capacitors, and a third flying capacitor. The circuit contains N (N is a natural number) capacitors, the fourth flying capacitor circuit contains N (N is a natural number) capacitors, and the voltage of the first capacitor is (1 /) of the DC power supply voltage. The voltage of the second capacitor is controlled to be (2N + 2)) times the voltage of the DC power supply voltage, and the voltage of the Nth capacitor is controlled to be (2 / (2N + 2)) times the voltage of the DC power supply voltage. , The voltage is controlled to be (N / (2N + 2)) times the DC power supply voltage, and a voltage of (2N + 3) level may be output from the second output terminal with the first output terminal.

According to this aspect, a semiconductor device capable of outputting a (2N + 3) level output voltage can be configured by a low withstand voltage switching element.

In this semiconductor device, the switching element of the first flying capacitor circuit, the switching element of the second flying capacitor circuit, the switching element of the third flying capacitor circuit, and the switching element of the fourth flying capacitor circuit are DC power supplies. An element having a withstand voltage lower than the voltage may be used.

According to this aspect, an inexpensive and high-performance semiconductor device can be realized.

In this semiconductor device, a device having a withstand voltage lower than the voltage of the DC power supply may be used for the switching element S1, the switching element S2, the switching element S3, or the switching element S4.

According to this aspect, an inexpensive and high-performance semiconductor device can be realized.

It should be noted that any combination of the above components and the conversion of the expression of the present invention between methods, devices, systems, recording media, computer programs and the like are also effective as aspects of the present invention.

Next, the configuration of the semiconductor device 10 will be described in more detail with reference to FIGS. 12 and later.

In the following, the series circuit of the switching elements S5a to S5d (first switching element) will be referred to as the first series circuit 21, and the series circuit of the switching elements S6a to S6d (second switching element) will be referred to as the second series. The series circuit of the switching elements S7a to S7d (third switching element) is referred to as a circuit 22, and the series circuit of the switching elements S8a to S8d (fourth switching element) is referred to as a third series circuit 23. The series circuit of the switching elements S1a, S1b, S2a, S2b (fifth switching element) is referred to as a fifth series circuit 25, and the switching elements S3a, S3b, S4a, S4b (sixth). The series circuit of the switching element) is referred to as a sixth series circuit 26. That is, the semiconductor device 10 includes the first to sixth series circuits 21 to 26.

Each of the switching elements S5a to S5d, S6a to S6d, S7a to S7d, S8a to S8d, S1a, S1b, S2a, S2b, S3a, S3b, S4a, and S4b is composed of semiconductor switching elements.

The first series circuit 21 includes the switching elements S5a to S5d and is configured by connecting the switching elements S5a to S5d in series. The second series circuit 22 includes the switching elements S6a to S6d and is configured by connecting the switching elements S6a to S6d in series. The third series circuit 23 includes the switching elements S7a to S7d and is configured by connecting the switching elements S7a to S7d in series. The fourth series circuit 24 includes the switching elements S8a to S8d and is configured by connecting the switching elements S8a to S8d in series. The fifth series circuit 25 includes the switching elements S1a, S1b, S2a, and S2b, and is configured by connecting the switching elements S1a, S1b, S2a, and S2b in series. The sixth series circuit 26 includes the switching elements S3a, S3b, S4a, and S4b, and is configured by connecting the switching elements S3a, S3b, S4a, and S4b in series.

The second series circuit 22 is connected in series to the first series circuit 21. The fourth series circuit 24 is connected in series to the third series circuit 23.

The first end 45 of the fifth series circuit 25 is connected to the first connection point 31. The first connection point 31 is a connection point of two switching elements S5b and S5c among the switching elements S5a to S5d (first switching element). The second end 46 of the fifth series circuit 25 is connected to the second connection point 32. The second connection point 32 is a connection point of two switching elements S6b and S6c among the switching elements S6a to S6d (second switching element). That is, the fifth series circuit 25 is connected between the first connection point 31 and the second connection point 32.

The first end 47 of the sixth series circuit 26 is connected to the third connection point 33. The third connection point 33 is a connection point of two switching elements S7b and S7c among the switching elements S7a to S7d (third switching element). The second end 48 of the sixth series circuit 26 is connected to the fourth connection point 34. The fourth connection point 34 is a connection point of two switching elements S8b and S8c among the switching elements S8a to S8d (fourth switching element). That is, the sixth series circuit 26 is connected between the third connection point 33 and the fourth connection point 34.

The end 41 of the first series circuit 21 opposite to the second series circuit 22 side is connected to the end 43 of the third series circuit 23 opposite to the fourth series circuit 24 side. The end 42 of the second series circuit 22 opposite to the first series circuit 21 side is connected to the end 44 of the fourth series circuit 24 opposite to the third series circuit 23 side. The connection point 51 between the first series circuit 21 and the second series circuit 22 is connected to the connection point 52 between the third series circuit 23 and the fourth series circuit 24.

The semiconductor device 10 includes a plurality of modules M1 and M2 (devices) (two in FIG. 12). Each module M1 and M2 is at least two of the switching elements S5a to S5d, S6a to S6d, S7a to S7d, S8a to S8d, S1a, S1b, S2a, S2b, S3a, S3b, S4a, and S4b. A switching element group which is a switching element and a package P1 (see FIG. 13) containing the switching element group are included. The number of switching elements in each of the plurality of modules M1 and M2 is the same among the plurality of modules M1 and M2. Specifically, each of the plurality of modules M1 and M2 includes 12 switching elements. The connection relationship of the switching element group in each of the plurality of modules M1 and M2 is the same among the plurality of modules M1 and M2.

Specifically, the module M1 includes switching elements S5a to S5d, S6a to S6d, S1a, S1b, S2a, and S2b as the switching element group. The module M2 includes switching elements S7a to S7d, S8a to S8d, S3a, S3b, S4a, and S4b as the switching element group. That is, the module M1 includes the first series circuit 21, the second series circuit 22, and the fifth series circuit 25, and the module M2 includes the third series circuit 23 and the fourth series circuit. 24 and a sixth series circuit 26 are included.

As described above, the plurality of switching elements provided in the semiconductor device 10 are dispersedly provided in the module M1 and the module M2. Therefore, the modules M1 and M2 are more versatile than one module including all the switching elements of the semiconductor device 10. That is, as compared with one module including all the switching elements of the semiconductor device 10, the modules M1 and M2 are more likely to be used for circuits other than the circuits constituting the semiconductor device 10.

The modules M1 and M2 electrically form the same circuit. The modules M1 and M2 are manufactured by a common process.

The electric circuit including the first and second connection points 31, 32 and the connection point 51 is the configuration of the module M1, and the electric path including the third and fourth connection points 33 and 34 and the connection point 52 is a module. It is a configuration of M2.

As shown in FIG. 13, the module M1 includes a plurality of terminals 9. The plurality of terminals 9 are for inputting a gate signal to three terminals connected to any one of the first input terminal IN1, the second input end IN2, and the second output end OUT2, and to each switching element constituting the semiconductor device 10. A plurality of gate terminals of the above, and a plurality of source terminals for connecting to the source electrodes of each switching element constituting the semiconductor device 10 are included. Module M2 also includes a plurality of terminals. The plurality of terminals of the module M2 include three terminals connected to any one of the first input terminal IN1, the second input terminal IN2, and the first output terminal OUT1, a plurality of gate terminals, and a plurality of source terminals. ..

The flying capacitor FC1 (first capacitor) of the semiconductor device 10 is connected in parallel with the series circuit of the two switching elements S5b and S5c of the switching elements S5a to S5d (first switching element). The flying capacitor FC2 (second capacitor) of the semiconductor device 10 is connected in parallel with the series circuit of the two switching elements S6b and S6c of the switching elements S6a to S6d (second switching element). The flying capacitor FC3 (third capacitor) of the semiconductor device 10 is connected in parallel with the series circuit of the two switching elements S7b and S7c of the switching elements S7a to S7d (third switching element). The flying capacitor FC4 (fourth capacitor) of the semiconductor device 10 is connected in parallel with the series circuit of the two switching elements S8b and S8c of the switching elements S8a to S8d (fourth switching element).

That is, the first end of the flying capacitor FC1 is connected to the connection point 61 between the first switching element S5a and the second switching element S5b from one end side of the four switching elements S5a to S5d connected in series. There is. The second end of the flying capacitor FC1 is connected to the connection point 62 between the third switching element S5c and the fourth switching element S5d.

Further, the first end of the flying capacitor FC2 is connected to a connection point 63 between the first switching element S6a and the second switching element S6b from one end side of the four switching elements S6a to S6d connected in series. There is. The second end of the flying capacitor FC2 is connected to the connection point 64 between the third switching element S6c and the fourth switching element S6d.

Further, the first end of the flying capacitor FC3 is connected to a connection point 65 between the first switching element S7a and the second switching element S7b from one end side of the four switching elements S7a to S7d connected in series. There is. The second end of the flying capacitor FC3 is connected to the connection point 66 between the third switching element S7c and the fourth switching element S7d.

Further, the first end of the flying capacitor FC4 is connected to a connection point 67 between the first switching element S8a and the second switching element S8b from one end side of the four switching elements S8a to S8d connected in series. There is. The second end of the flying capacitor FC4 is connected to the connection point 68 between the third switching element S8c and the fourth switching element S8d.

The first connection point 31 is a connection point between the second switching element S5b and the third switching element S5c from one end side of the four switching elements S5a to S5d connected in series.

The second connection point 32 is a connection point between the second switching element S6b and the third switching element S6c from one end side of the four switching elements S6a to S6d connected in series.

The third connection point 33 is a connection point between the second switching element S7b and the third switching element S7c from one end side of the four switching elements S7a to S7d connected in series.

The fourth connection point 34 is a connection point between the second switching element S8b and the third switching element S8c from one end side of the four switching elements S8a to S8d connected in series.

The electric circuit including the connection points 61 to 64 has the configuration of the module M1, and the electric circuit including the connection points 65 to 68 has the configuration of the module M2.

FIG. 14 illustrates the inside of the package P1 of the module M2. The inside of the package of the module M1 has the same structure as the inside of the package P1 of the module M2. Each switching element is mounted on the substrate 7. The substrate 7 is, for example, a ceramic substrate or a lead frame. The substrate 7 is housed in the package P1.

A plurality of lands 71a to 71k and 71m made of conductors are formed on the substrate 7. Each switching element is mounted on these lands and is electrically connected to the lands. The drain of each switching element is in contact with the land. The source of each switching element and the land adjacent to the switching element are connected via a bonding wire. As a result, the switching elements are connected to each other. In FIGS. 14 and 16, 18 and 20 described later, the bonding wires are shown by thick lines.

A terminal 9 (see FIG. 13) for connecting to the first input terminal IN1 is connected to the land 71a on which the switching element S7a is mounted. A terminal 9 for connecting to the second input terminal IN2 is connected to the land 71i connected to the switching element S8d via the bonding wire. A terminal 9 for connecting a connection point 51 between the first series circuit 21 and the second series circuit 22 is connected to the land 71e on which the switching element S8a is mounted. A terminal 9 for connecting to the second output terminal OUT2 is connected to the land 71k on which the switching element S4a is mounted.

The flying capacitors FC3 and FC4 are provided outside the package P1 (see FIG. 13) of the module M1. A flying capacitor FC3 is connected to the land 71b on which the switching element S7b is mounted and the land 71d on which the switching element S7d is mounted. A flying capacitor FC4 is connected to the land 71f on which the switching element S8b is mounted and the land 71h on which the switching element S8d is mounted.

Further, a plurality of electrodes 72 are formed on the substrate 7. Each electrode 72 is formed, for example, by printing a conductor on a substrate 7. A plurality of sets of the plurality of electrodes 72 are provided in units of two sets. A set of electrodes corresponds to any of a plurality of switching elements. One of the set of electrodes 72 is connected to the gate terminal (one of the plurality of terminals 9) of the corresponding switching element, and the other is the source terminal (of the plurality of terminals 9) of the corresponding switching element. It is connected to one of). A terminal 9 (see FIG. 13) for connecting to the outside is connected to each electrode 72. A voltage is applied between the gate and source of each switching element via the plurality of terminals 9 and the plurality of electrodes 72.

(Variation example of Embodiment 1)
Next, modifications of the first embodiment are listed. The following modifications may be realized by combining them as appropriate.

In each of the first to sixth series circuits 21 to 26, the number of switching elements is not limited to four, and may be two, three, or five or more.

Further, the module M1 may include at least one of the flying capacitors FC1 and FC2. The module M2 may include at least one of the flying capacitors FC3 and FC4.

Further, a parallel circuit of a plurality of diodes may be connected between the source and drain of each switching element. In this case, the anodes of each diode are connected to each other, and the cathodes of each diode are connected to each other. When a current is passed through a parallel circuit of a plurality of diodes between the source and drain, a larger current can be passed as compared with the case where a current is passed through one diode. The plurality of diodes may include the body diode of the MOSFET.

Further, the semiconductor device 10 may perform at least one of an operation of converting DC power into AC power and an operation of converting AC power into DC power.

Further, the semiconductor device 10 of the first embodiment is configured to input or output single-phase AC power, but the semiconductor device 10 may be configured to input or output three-phase AC power. By providing another module which is the same as the module M1 in the semiconductor device 10 and connecting the newly provided module between the first input end IN1 and the second input end IN2, three from the three output ends of the three modules. It can output phase AC power. Further, by exchanging the relationship between the input and the output of the semiconductor device 10, it is possible to input the three-phase AC power to the semiconductor device 10 and output the DC power.

Further, each of the first input end IN1, the second input end IN2, the first output end OUT1 and the second output end OUT2 may be a terminal 9 or a lead wire.

(Summary of Embodiment 1 and modified examples of Embodiment 1)
The following aspects are disclosed from the above-described first embodiment and modified examples of the first embodiment.

The semiconductor device 10 performs at least one of an operation of converting DC power into AC power and an operation of converting AC power into DC power. The semiconductor device 10 includes a first series circuit 21 of the plurality of switching elements S5a to S5d, a second series circuit 22 of the plurality of second switching elements S6a to S6d, and a plurality of third switching elements S7a to S7d. The third series circuit 23 of the above, the fourth series circuit 24 of the plurality of fourth switching elements S8a to S8d, and the fifth series circuit 25 of the plurality of fifth switching elements S1a, S1b, S2a, S2b. , A sixth series circuit 26 of a plurality of sixth switching elements S3a, S3b, S4a, S4b. The second series circuit 22 is connected in series to the first series circuit 21. The fourth series circuit 24 is connected in series to the third series circuit 23. The fifth series circuit 25 is connected between the first connection point 31 and the second connection point 32. The first connection point 31 is a connection point of two first switching elements S5b and S5c among the plurality of first switching elements S5a to S5d. The second connection point 32 is a connection point of two second switching elements S6b and S6c among the plurality of second switching elements S6a to S6d. The sixth series circuit 26 is connected between the third connection point 33 and the fourth connection point. The third connection point 33 is a connection point of two third switching elements S7b and S7c among the plurality of third switching elements S7a to S7d. The fourth connection point 34 is a connection point of two fourth switching elements S8b and S8c among the plurality of fourth switching elements S8a to S8d. The end 41 of the first series circuit 21 opposite to the second series circuit 22 side is connected to the end 43 of the third series circuit 23 opposite to the fourth series circuit 24 side. The end 42 of the second series circuit 22 opposite to the first series circuit 21 side is connected to the end 44 of the fourth series circuit 24 opposite to the third series circuit 23 side. The connection point 51 between the first series circuit 21 and the second series circuit 22 is connected to the connection point 52 between the third series circuit 23 and the fourth series circuit 24. The semiconductor device 10 includes a plurality of modules. The plurality of modules M1 and M2 include a switching element group and a package P1. The switching element group includes a plurality of first switching elements S5a to S5d, a plurality of second switching elements S6a to S6d, a plurality of third switching elements S7a to S7d, and a plurality of fourth switching elements S8a to S8d. The fifth switching element S1a, S1b, S2a, S2b, and the plurality of sixth switching elements S3a, S3b, S4a, S4b are less than half and at least two switching elements. Package P1 houses a group of switching elements. The number of switching elements in each of the plurality of modules M1 and M2 is the same. The connection relationship of the switching element group in each of the plurality of modules M1 and M2 is the same.

According to the above configuration, in the semiconductor device 10, the plurality of first to sixth switching elements S5a to S5d, S6a to S6d, S7a to S7d, and S8a to S8d are arranged so that the connection relationship of the switching element groups is the same. , S1a, S1b, S2a, S2b, S3a, S3b, S4a, S4b are distributed in a plurality of modules M1 and M2, so that the plurality of first to sixth switching elements are integrated into one module. Compared with the case where the semiconductor device 10 is used, the versatility of the semiconductor device 10 is high. That is, by changing the connection relationship between the modules and the connection relationship between each module and another circuit, it is possible to form a circuit different from the semiconductor device 10 including at least a part of the semiconductor device 10.

Further, the semiconductor device 10 includes a first capacitor (flying capacitor FC1), a second capacitor (flying capacitor FC2), a third capacitor (flying capacitor FC3), and a fourth capacitor (flying capacitor FC4). , Are further provided. The first capacitor is connected in parallel with the series circuit of at least two first switching elements S5b and S5c of the plurality of first switching elements S5a to S5d. The second capacitor is connected in parallel with the series circuit of at least two second switching elements S6b and S6c among the plurality of second switching elements S6a to S6d. The third capacitor is connected in parallel with the series circuit of at least two third switching elements S7b and S7c among the plurality of third switching elements S7a to S7d. The fourth capacitor is connected in parallel with the series circuit of at least two fourth switching elements S8b and S8c among the plurality of fourth switching elements S8a to S8d.

According to the above configuration, the voltage between both ends of the first to fourth capacitors can be maintained by turning on and off each switching element to charge and discharge the first to fourth capacitors. The semiconductor device 10 is provided with a connection end for input and a connection end for output. By turning on and off each switching element, whether or not the current between the input end and the output end of the semiconductor device 10 passes through the first to fourth capacitors, and by switching the direction in which the current passes, the semiconductor device 10 is used. Output voltage can be switched.

Further, in the semiconductor device 10, the first series circuit 21 includes a series circuit of four first switching elements S5a to S5d as a plurality of first switching elements. The second series circuit 22 includes a series circuit of four second switching elements S6a to S6d as a plurality of second switching elements. The third series circuit 23 includes a series circuit of four third switching elements S7a to S7d as a plurality of third switching elements. The fourth series circuit 24 includes a series circuit of four fourth switching elements S8a to S8d as a plurality of fourth switching elements. The first end of the first capacitor (flying capacitor FC1) is the first switching element S5a and the second first switching element S5a from one end side of the four first switching elements S5a to S5d connected in series. It is connected to the connection point 61 with the switching element S5b of. The second end of the first capacitor is connected to the connection point 62 between the third first switching element S5c and the fourth first switching element S5d. The first end of the second capacitor (flying capacitor FC2) is a second switching element S6a first from one end side and a second second switching element S6a of four second switching elements S6a to S6d connected in series. It is connected to the connection point 63 with the switching element S6b of. The second end of the second capacitor is connected to the connection point 64 between the third second switching element S6c and the fourth second switching element S6d. The first end of the third capacitor (flying capacitor FC3) is a third switching element S7a first from one end side and a second third switching element S7a among four third switching elements S7a to S7d connected in series. It is connected to the connection point 65 with the switching element S7b of. The second end of the third capacitor is connected to the connection point 66 between the third third switching element S7c and the fourth third switching element S7d. The first end of the fourth capacitor (flying capacitor FC4) is the first fourth switching element S8a and the second fourth of the four fourth switching elements S8a to S8d connected in series from one end side. It is connected to the connection point 67 with the switching element S8b of. The second end of the fourth capacitor is connected to the connection point 68 between the third fourth switching element S8c and the fourth fourth switching element S8d. The first connection point 31 is a connection between the first switching element S5b second from one end side and the third first switching element S5c among the four first switching elements S5a to S5d connected in series. It is a point. The second connection point 32 is a connection between the second switching element S6b, which is the second from one end side, and the third second switching element S6c among the four second switching elements S6a to S6d connected in series. It is a point. The third connection point 33 is a connection between the third switching element S7b, which is the second from one end side of the four third switching elements S7a to S7d connected in series, and the third switching element S7c. It is a point. The fourth connection point 34 is a connection between the fourth switching element S8b, which is the second from one end side, and the third fourth switching element S8c among the four fourth switching elements S8a to S8d connected in series. It is a point.

According to the above configuration, the maximum voltage applied to each switching element can be made equal among the switching elements. Here, "equal" is not limited to exactly equality and may differ within the permissible margin of error. "Equal" includes, for example, a case where there is an error of 5% or 10%.

Further, in the semiconductor device 10, one of the plurality of modules M1 and M2, the module M1, includes a first series circuit 21, a second series circuit 22, and a fifth series circuit 25. Another module M2 among the plurality of modules M1 and M2 includes a third series circuit 23, a fourth series circuit 24, and a sixth series circuit 26.

According to the above configuration, the versatility of the semiconductor device 10 is enhanced as compared with the case where the first to sixth series circuits 21 to 26 are integrated into one module.

Further, the device is used in the semiconductor device 10 as one of a plurality of modules M1 and M2.

According to the above configuration, a plurality of first to sixth switching elements S5a to S5d, S6a to S6d, S7a to S7d, S8a to S8d, S1a, S1b, S2a, S2b, S3a, S3b, S4a, and S4b are 1. It is possible to provide modules M1 and M2 having higher versatility as compared with the case where they are integrated into one module.

(Embodiment 2)
Hereinafter, the semiconductor device 10A according to the second embodiment will be described with reference to FIGS. 15 and 16. The same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

The semiconductor device 10A includes modules M3 and M4 in place of the modules M1 and M2 of the first embodiment. The module M3 has a configuration in which the flying capacitors FC1 and FC2 are added to the configuration of the module M1 of the first embodiment. That is, the flying capacitors FC1 and FC2 are further housed in the package P1 (see FIG. 13) of the module M3. The module M4 has a configuration in which the flying capacitors FC3 and FC4 are added to the configuration of the module M2 of the first embodiment. That is, the flying capacitors FC3 and FC4 are further housed in the package P1 of the module M4.

FIG. 16 illustrates the inside of the package P1 of the module M4.

In the third series circuit 23, the switching elements S7a to S7d are arranged so as to be arranged vertically and horizontally when the substrate 7 is viewed in a plane. In the third series circuit 23, the flying capacitor FC3 is arranged between the two switching elements S7b and S7d located diagonally to each other. Therefore, as shown in FIG. 14, the wiring length between the flying capacitor FC3 and the switching elements S7b and S7d can be shortened as compared with the case where the switching elements S7a to S7d are arranged in a straight line.

In the fourth series circuit 24, the switching elements S8a to S8d are arranged so as to be arranged vertically and horizontally when the substrate 7 is viewed in a plan view. That is, the four switching elements S8a to S8d are arranged side by side in a matrix of 2 rows and 2 columns. In the fourth series circuit 24, the two switching elements S8b and S8d are located diagonally to each other. That is, the two switching elements S8b and S8d are arranged diagonally with respect to the row direction and the column direction in the matrix-like arrangement of 2 rows and 2 columns. In the fourth series circuit 24, the flying capacitor FC4 is arranged between the two switching elements S8b and S8d located diagonally to each other. Therefore, as shown in FIG. 14, the wiring length between the flying capacitor FC4 and the switching elements S8b and S8d can be shortened as compared with the case where the switching elements S8a to S8d are arranged in a straight line.

The module M3 has the same structure as the module M4. That is, in the first series circuit 21, the switching elements S5a to S5d are arranged so as to be arranged vertically and horizontally when the substrate 7 is viewed in a plane. In the first series circuit 21, the flying capacitor FC1 is arranged between the two switching elements S5b and S5d located diagonally to each other. In the second series circuit 22, the switching elements S6a to S6d are arranged so as to be arranged vertically and horizontally when the substrate 7 is viewed in a plan view. In the second series circuit 22, the flying capacitor FC2 is arranged between the two switching elements S6b and S6d located diagonally to each other.

In each of the modules M1 to M4, all the switching elements included in the module are arranged so as to be arranged vertically and horizontally when the substrate 7 is viewed in a plane. More specifically, in each module, switching elements are arranged in 4 rows and 3 columns. In FIG. 16, the switching elements S7a, S7b, S7c, S7d, S8a, S8b, S8c, and S8d are sequentially connected from the switching element S7a in the directions of left, bottom, right, bottom, left, bottom, and right on the paper. That is, in the substrate 7, the shape of the electric line connecting the switching elements S7a to the switching elements S8d via the switching elements S7b to S7d and S8a to S8c is crank-shaped. There is a space between the switching element S7a and the switching element S8d for two switching elements. Therefore, the wiring length between the switching element S7a and the switching element S8d is shortened as compared with the case where the switching element S7a and the switching element S8d are spaced by six switching elements as shown in FIG. can.

By shortening the wiring length in the semiconductor device 10A, it is possible to reduce the loss due to the resistance component and the noise due to the inductance component.

At least one of the flying capacitors FC1 to FC4 may be provided outside the modules M3 and M4.

Further, in each of the first to fourth series circuits 21 to 24, at least three switching elements may be arranged so as to be arranged vertically and horizontally when the substrate 7 is viewed in a plan view. Here, the fact that the three switching elements are arranged vertically and horizontally means the arrangement of the remaining three switching elements in a state where one of the four switching elements arranged in a matrix of 2 rows and 2 columns is missing. ..

(Summary of Embodiment 2 and modified examples of Embodiment 2)
The following aspects are disclosed from the above-described second embodiment and modified examples of the second embodiment.

In the semiconductor device 10A, in at least one of the first to fourth series circuits 21 to 24, three or more of the plurality of first, second, third or fourth switching elements S5a to S8d are switched. (For example, the third switching elements S7a to S7d) are mounted on the substrate 7 and arranged so as to be arranged vertically and horizontally when the substrate 7 is viewed in a plan view, and diagonally to each other when the substrate 7 is viewed in a plan view. A first, second, third or fourth capacitor (eg, for example) is located between two first, second, third or fourth switching elements (eg, third switching elements S7b, S7d) located. , The flying capacitor FC3, or the flying capacitor FC1, FC2 or FC4) is arranged.

According to the above configuration, in at least one of the first to fourth capacitors (flying capacitors FC1 to FC4), the wiring length between the first to fourth capacitors (flying capacitors FC1 to FC4) can be shortened.

Further, in the semiconductor device 10A, one of the plurality of modules M3 and M4, the module M3 is a first series circuit 21, a second series circuit 22, a fifth series circuit 25, and a first capacitor ( The flying capacitor FC1) and the second capacitor (flying capacitor FC2) are included. Another module M4 among the plurality of modules M3 and M4 includes a third series circuit 23, a fourth series circuit 24, a sixth series circuit 26, and a third capacitor (flying capacitor FC3). , A fourth capacitor (flying capacitor FC4).

According to the above configuration, the versatility of the semiconductor device 10 is enhanced as compared with the case where the first to sixth series circuits 21 to 26 are integrated into one module.

(Embodiment 3)
Hereinafter, the semiconductor device 10B according to the third embodiment will be described with reference to FIGS. 17 and 18. The same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

The semiconductor device 10B includes a plurality of modules M5 to M10 (six in FIG. 17) instead of the modules M1 and M2 of the first embodiment. The number of modules in the semiconductor device 10B is the same as the number of the first to sixth series circuits 21 to 26. The plurality of modules M5 to M10 have a one-to-one correspondence with the first to sixth series circuits 21 to 26 (see FIG. 12). Each of the plurality of modules M5 to M10 includes a corresponding series circuit among the first to sixth series circuits 21 to 26. In short, the module M5 has a first series circuit 21, the module M6 has a second series circuit 22, the module M7 has a third series circuit 23, the module M8 has a fourth series circuit 24, and the module M9 has a second series circuit. The series circuit 25 of 5 is included, and the module M10 includes a sixth series circuit 26.

FIG. 18 illustrates the inside of the package P1 (see FIG. 13) of the module M7. Modules M5, M6, and M8 to M10 have the same structure as the module M5.

The switching elements S7a to S7d included in the module M7 are arranged side by side in a row. One terminal 9 (see FIG. 13) for connecting to another module or the like is connected to each land 71a to 71d on which the switching elements S7a to S7d are mounted. A terminal 9 for connecting to another module or the like is connected to the land 71n connected to the switching element S7d via the bonding wire.

In the modules M5 to M10 of the present embodiment, the configuration of the semiconductor device 10B is further subdivided as compared with the modules M1 and M2 of the first embodiment, so that the versatility of the semiconductor device 10B can be further improved.

In the semiconductor device 10 of the first embodiment, since the first, second, and fifth series circuits 21, 22, and 25 are integrated into one module M1, compared with the semiconductor device 10B of the present embodiment. , The wiring length between the first, second, and fifth series circuits 21, 22, and 25 can be shortened. In the semiconductor device 10 of the first embodiment, since the third, fourth, and sixth series circuits 23, 24, and 26 are integrated in one module M2, the third, fourth, and sixth series circuits are integrated into one module M2. The wiring length between the third, fourth and sixth series circuits 23, 24 and 26 can be shortened.

(Summary of Embodiment 3)
From the third embodiment described above, the following aspects are disclosed.

In the semiconductor device 10B, the six modules M5 to M10 as a plurality of modules correspond one-to-one with the first to sixth series circuits 21 to 26. Each of the six modules M5 to M10 includes the corresponding series circuit of the first to sixth series circuits 21 to 26.

According to the above configuration, the versatility of the semiconductor device 10B is enhanced as compared with the case where the first to sixth series circuits 21 to 26 are integrated into one module.

(Embodiment 4)
Hereinafter, the semiconductor device 10C according to the fourth embodiment will be described with reference to FIGS. 19 and 20. The same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

The semiconductor device 10C includes first to sixth modules M11 to M16 in place of the modules M1 and M2 of the first embodiment. Each of the first to sixth modules M11 to M16 has two switching elements of one series circuit of the first to sixth series circuits 21 to 26 (see FIG. 12) and the first to sixth series. Each of the circuits 21 to 26 includes two switching elements of another one series circuit.

The plurality of switching elements S5a to S5d (first switching element) have switching elements S5a and S5b included in the first module M11 and switching elements S5c and S5d included in the second module M12.

The plurality of switching elements S7a to S7d (third switching element) have switching elements S7a and S7b included in the first module M11 and switching elements S7c and S7d included in the third module M13.

The plurality of switching elements S1a, S1b, S2a, S2b (fifth switching element) include switching elements S1a, S1b included in the second module M12 and switching elements S2a, S2b included in the fourth module M14. are doing.

The plurality of switching elements S3a, S3b, S4a, S4b (sixth switching element) include switching elements S3a, S3b included in the third module M13 and switching elements S4a, S4b included in the fifth module M15. are doing.

The plurality of switching elements S6a to S6d (second switching elements) include switching elements S6a and S6b included in the fourth module M14 and switching elements S6c and S6d included in the sixth module M16.

The plurality of switching elements S8a to S8d (fourth switching element) have switching elements S8a and S8b included in the fifth module M15 and switching elements S8c and S8d included in the sixth module M16.

FIG. 20 illustrates the inside of the package P1 (see FIG. 13) of the first module M11. The second to sixth modules M12 to M16 have the same structure as the first module M11.

The four switching elements S5a, S5b, S7a, and S7b included in the first module M11 are arranged side by side in a two-row, two-column matrix. One terminal 9 (see FIG. 13) for connecting to the first input terminal IN1 is connected to the land 71q on which the switching element S5a is mounted and the land 71a on which the switching element S7a is mounted. There is. One terminal 9 for connecting to the flying capacitor FC1 or FC3 is connected to the land 71r on which the switching element S5b is mounted and the land 71b on which the switching element S7b is mounted. The land 71s connected to the switching element S5b via the bonding wire and the land 71p connected to the switching element S7b via the bonding wire have terminals 9 for connecting to another module per land. One is connected.

In the first to sixth modules M11 to M16 of the present embodiment, the configuration of the semiconductor device 10C is more subdivided as compared with the modules M1 and M2 of the first embodiment, so that the versatility of the semiconductor device 10C can be improved. It can be further improved.

(Summary of Embodiment 4)
From the fourth embodiment described above, the following aspects are disclosed.

In the semiconductor device 10C, the plurality of first switching elements S5a to S5d include switching elements S5a and S5b included in the first module M11 and switching elements S5c and S5d included in the second module M12 among the plurality of modules. Has. The plurality of third switching elements S7a to S7d include switching elements S7a and S7b included in the first module M11 and switching elements S7c and S7d included in the third module M13 among the plurality of modules. The plurality of fifth switching elements S1a, S1b, S2a, and S2b include switching elements S1a and S1b included in the second module M12 and switching elements S2a and S2b included in the fourth module M14 among the plurality of modules. Have. The plurality of sixth switching elements S3a, S3b, S4a, and S4b include switching elements S3a and S3b included in the third module M13 and switching elements S4a and S4b included in the fifth module M15 among the plurality of modules. Have. The plurality of second switching elements S6a to S6d include switching elements S6a and S6b included in the fourth module M14 and switching elements S6c and S6d included in the sixth module M16 among the plurality of modules. The plurality of fourth switching elements S8a to S8d include switching elements S8a and S8b included in the fifth module M15 and switching elements S8c and S8d included in the sixth module M16 among the plurality of modules.

According to the above configuration, the versatility of the semiconductor device 10C is enhanced as compared with the case where the first to sixth series circuits 21 to 26 are integrated into one module.

(Embodiment 5)
Hereinafter, the semiconductor device 10D according to the fifth embodiment will be described with reference to FIG. 21. The same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

The semiconductor device 10D includes a plurality of modules M17 and M18 (two in FIG. 21) instead of the modules M1 and M2 of the first embodiment. The module M17 has a configuration in which the temperature detection element T1 is added to the module M1. The temperature detection element T1 is housed in the package P1 (see FIG. 13) of the module M17. The module M18 has a configuration in which the temperature detection element T2 is added to the module M2. The temperature detection element T2 is housed in the package P1 (see FIG. 13) of the module M18.

Each temperature detecting element T1 and T2 is, for example, a thermistor. A current flows through each of the temperature detection elements T1 and T2 from a control circuit provided outside the package P1. The control circuit detects the temperature in the package P1 of the module M17 by the temperature detecting element T1. The control circuit detects the temperature in the package P1 of the module M18 by the temperature detecting element T2.

The resistance value of each of the temperature detection elements T1 and T2 decreases as the temperature inside the package P1 increases. Therefore, the current flowing through each of the temperature detection elements T1 and T2 increases as the temperature in the package P1 increases. The control circuit detects the temperature in the package P1 in which the temperature detection elements T1 and T2 are housed by measuring the current flowing through the temperature detection elements T1 and T2.

As the temperature detecting elements T1 and T2, a thermistor whose resistance value increases as the temperature increases may be used.

Further, as the temperature detecting elements T1 and T2, for example, a thermo switch may be used instead of the thermistor. By using the thermo switch, it is possible to detect whether or not the temperature in the package P1 is equal to or higher than the threshold value.

Further, only one of the modules M17 and M18 may be provided with a temperature detecting element.
Further, each module in the second to fourth embodiments may also include a temperature detecting element.

(Summary of Embodiment 5)
The following aspects are disclosed from the fifth embodiment described above.

In the semiconductor device 10D, at least one of the plurality of modules M17 and M18 includes a temperature detecting element T1 (or T2). The temperature detection element T1 (or T2) is housed in the package P1.

According to the above configuration, the temperature in the package P1 can be detected by using the temperature detecting element T1 (or T2).

(Embodiment 6)
Hereinafter, the semiconductor device 10E according to the sixth embodiment will be described with reference to FIG. 22. The same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

The semiconductor device 10E includes a plurality of modules M19 and M20 (two in FIG. 22) instead of the modules M1 and M2 of the first embodiment. The module M19 has a configuration in which a plurality of resistors R1 are added to the module M1. The plurality of resistors R1 are housed in the package P1 (see FIG. 13) of the module M19. The module M20 has a configuration in which a plurality of resistors R1 are added to the module M2. The plurality of resistors R1 are housed in the package P1 of the module M20. Each resistor R1 is a discrete component, for example, a chip resistor.

Each module M19 and M20 includes 12 resistors R1. That is, in each of the modules M19 and M20, the same number of resistors R1 are provided as the number of switching elements included in each of the modules M19 and M20.

The plurality of (24) resistors R1 correspond one-to-one with the plurality (24) switching elements of the semiconductor device 10E. The resistors R1 and the switching element corresponding to each other are included in the same module among the plurality of modules M19 and M20. Each resistor R1 is connected in parallel with the corresponding switching element.

When a DC voltage is applied between the first input end IN1 and the second input end IN2, the presence of the resistor R1 can stabilize the voltage of the switching element connected in parallel with the resistor R1. Further, when a surge voltage is input to the semiconductor device 10E, the resistor R1 limits the voltage applied to the switching element connected in parallel with the resistor R1. Further, when some of the switching elements among the plurality of switching elements do not operate normally, the current can be bypassed by the resistor R1 connected in parallel with the switching elements.

The number of resistors R1 may be one or more. At least one resistor R1 may be connected in parallel with a switching element included in the same module as the resistor R1.

Further, a series circuit, a parallel circuit or a series-parallel circuit of a plurality of resistors R1 may be connected to each switching element.

Further, the resistor R1 is not limited to the discrete component. For example, as the resistor R1, a diffusion layer of impurities in a semiconductor may be used. Since the diffusion layer has a resistance value, it can be used as a resistor R1. The diffusion layer as the resistor R1 may be provided in the semiconductor constituting the switching element, or may be provided in a semiconductor different from the switching element.
Further, each module in the second to fifth embodiments may also include a resistor R1, and the resistor R1 may be connected in parallel with a switching element included in the same module as the resistor R1.

(Summary of Embodiment 6)
From the sixth embodiment described above, the following aspects are disclosed.

In the semiconductor device 10E, at least one of the plurality of modules includes at least one resistor R1. At least one resistor R1 is housed in package P1. A plurality of first switching elements S5a to S5d, a plurality of second switching elements S6a to S6d, a plurality of third switching elements S7a to S7d, a plurality of fourth switching elements S8a to S8d, and a plurality of fifth switching elements. At least one resistor R1 is connected in parallel to at least one of the elements S1a, S1b, S2a, S2b and the plurality of sixth switching elements S3a, S3b, S4a, S4b.

According to the above configuration, when a voltage is applied to the switching element, the voltage of the switching element connected in parallel with the resistor R1 can be stabilized.

Each of the above-described embodiments may be realized by appropriately combining them, including modifications.

10, 10A, 10B, 10C, 10D, 10E Semiconductor device 21 First series circuit 22 Second series circuit 23 Third series circuit 24 Fourth series circuit 25 Fifth series circuit 26 Sixth series circuit 31 1st connection point 32 2nd connection point 33 3rd connection point 34 4th connection point 41, 42, 43, 44 End 51, 52, 53, 54, 61, 62, 63, 64, 65, 66 , 67, 68 Connection point 7 Board FC1 Flying capacitor (first capacitor)
FC2 Flying Capacitor (2nd Capacitor)
FC3 Flying Capacitor (3rd Capacitor)
FC4 Flying Capacitor (4th Capacitor)
M1, M2, ..., M16 Module P1 Package R1 Resistors S5a, S5b, S5c, S5d First switching element S6a, S6b, S6c, S6d Second switching element S7a, S7b, S7c, S7d Third switching element S8a, S8b, S8c, S8d Fourth switching element S1a, S1b, S2a, S2b Fifth switching element S3a, S3b, S4a, S4b Sixth switching element T1, T2 Temperature detection element

Claims (11)

A semiconductor device that performs at least one of an operation of converting DC power into AC power and an operation of converting AC power into DC power.
A first series circuit of a plurality of first switching elements,
A second series circuit of a plurality of second switching elements connected in series to the first series circuit, and a second series circuit.
A third series circuit of a plurality of third switching elements,
A fourth series circuit of a plurality of fourth switching elements connected in series to the third series circuit, and a fourth series circuit.
A fifth series circuit of a plurality of fifth switching elements,
A sixth series circuit of a plurality of sixth switching elements, and
The fifth series circuit includes a first connection point of two first switching elements of the plurality of first switching elements and two second switching elements of the plurality of second switching elements. It is connected to the second connection point and
The sixth series circuit includes a third connection point of two third switching elements of the plurality of third switching elements and two fourth switching elements of the plurality of fourth switching elements. It is connected to the fourth connection point and
The end of the first series circuit opposite to the second series circuit side is connected to the end of the third series circuit opposite to the fourth series circuit side.
The end of the second series circuit opposite to the first series circuit side is connected to the end of the fourth series circuit opposite to the third series circuit side.
The connection point between the first series circuit and the second series circuit is connected to the connection point between the third series circuit and the fourth series circuit.
The plurality of first switching elements, the plurality of second switching elements, the plurality of third switching elements, the plurality of fourth switching elements, the plurality of fifth switching elements and the plurality of sixth. A plurality of modules including a switching element group which is less than half of the switching elements and at least two switching elements, and a package accommodating the switching element group are provided.
The number of switching elements in each of the plurality of modules is the same among the plurality of modules.
The connection relationship of the switching element group in each of the plurality of modules is the same among the plurality of modules .
A first capacitor connected in parallel with a series circuit of at least two first switching elements among the plurality of first switching elements,
A second capacitor connected in parallel with the series circuit of at least two second switching elements among the plurality of second switching elements,
A third capacitor connected in parallel with the series circuit of at least two third switching elements among the plurality of third switching elements.
A fourth capacitor connected in parallel with a series circuit of at least two fourth switching elements among the plurality of fourth switching elements is further provided.
The first module among the plurality of modules includes the first series circuit, the second series circuit, the fifth series circuit, the first capacitor, and the second capacitor. Including
The second module other than the first module among the plurality of modules includes the third series circuit, the fourth series circuit, the sixth series circuit, and the third capacitor. And the fourth capacitor.
Semiconductor device. A semiconductor device that performs at least one of an operation of converting DC power into AC power and an operation of converting AC power into DC power.
A first series circuit of a plurality of first switching elements,
A second series circuit of a plurality of second switching elements connected in series to the first series circuit, and a second series circuit.
A third series circuit of a plurality of third switching elements,
A fourth series circuit of a plurality of fourth switching elements connected in series to the third series circuit, and a fourth series circuit.
A fifth series circuit of a plurality of fifth switching elements,
A sixth series circuit of a plurality of sixth switching elements, and
The fifth series circuit includes a first connection point of two first switching elements of the plurality of first switching elements and two second switching elements of the plurality of second switching elements. It is connected to the second connection point and
The sixth series circuit includes a third connection point of two third switching elements of the plurality of third switching elements and two fourth switching elements of the plurality of fourth switching elements. It is connected to the fourth connection point and
The end of the first series circuit opposite to the second series circuit side is connected to the end of the third series circuit opposite to the fourth series circuit side.
The end of the second series circuit opposite to the first series circuit side is connected to the end of the fourth series circuit opposite to the third series circuit side.
The connection point between the first series circuit and the second series circuit is connected to the connection point between the third series circuit and the fourth series circuit.
The plurality of first switching elements, the plurality of second switching elements, the plurality of third switching elements, the plurality of fourth switching elements, the plurality of fifth switching elements and the plurality of sixth. A plurality of modules including a switching element group which is less than half of the switching elements and at least two switching elements, and a package accommodating the switching element group are provided.
The number of switching elements in each of the plurality of modules is the same among the plurality of modules.
The connection relationship of the switching element group in each of the plurality of modules is the same among the plurality of modules.
The six modules as the plurality of modules correspond one-to-one with the first to sixth series circuits.
Each of the six modules includes the corresponding series circuit of the first to sixth series circuits.
Semiconductor device. A semiconductor device that performs at least one of an operation of converting DC power into AC power and an operation of converting AC power into DC power.
A first series circuit of a plurality of first switching elements,
A second series circuit of a plurality of second switching elements connected in series to the first series circuit, and a second series circuit.
A third series circuit of a plurality of third switching elements,
A fourth series circuit of a plurality of fourth switching elements connected in series to the third series circuit, and a fourth series circuit.
A fifth series circuit of a plurality of fifth switching elements,
A sixth series circuit of a plurality of sixth switching elements, and
The fifth series circuit includes a first connection point of two first switching elements of the plurality of first switching elements and two second switching elements of the plurality of second switching elements. It is connected to the second connection point and
The sixth series circuit includes a third connection point of two third switching elements of the plurality of third switching elements and two fourth switching elements of the plurality of fourth switching elements. It is connected to the fourth connection point and
The end of the first series circuit opposite to the second series circuit side is connected to the end of the third series circuit opposite to the fourth series circuit side.
The end of the second series circuit opposite to the first series circuit side is connected to the end of the fourth series circuit opposite to the third series circuit side.
The connection point between the first series circuit and the second series circuit is connected to the connection point between the third series circuit and the fourth series circuit.
The plurality of first switching elements, the plurality of second switching elements, the plurality of third switching elements, the plurality of fourth switching elements, the plurality of fifth switching elements and the plurality of sixth. A plurality of modules including a switching element group which is less than half of the switching elements and at least two switching elements, and a package accommodating the switching element group are provided.
The number of switching elements in each of the plurality of modules is the same among the plurality of modules.
The connection relationship of the switching element group in each of the plurality of modules is the same among the plurality of modules.
The plurality of first switching elements include a switching element included in the first module and a switching element included in the second module among the plurality of modules.
The plurality of third switching elements include a switching element included in the first module and a switching element included in the third module among the plurality of modules.
The plurality of fifth switching elements include a switching element included in the second module and a switching element included in the fourth module among the plurality of modules.
The plurality of sixth switching elements include a switching element included in the third module and a switching element included in the fifth module among the plurality of modules.
The plurality of second switching elements include a switching element included in the fourth module and a switching element included in the sixth module among the plurality of modules.
The plurality of fourth switching elements include a switching element included in the fifth module and a switching element included in the sixth module among the plurality of modules.
Semiconductor device. A first capacitor connected in parallel with a series circuit of at least two first switching elements among the plurality of first switching elements,
A second capacitor connected in parallel with the series circuit of at least two second switching elements among the plurality of second switching elements,
A third capacitor connected in parallel with the series circuit of at least two third switching elements among the plurality of third switching elements.
A fourth capacitor connected in parallel with a series circuit of at least two fourth switching elements among the plurality of fourth switching elements is further provided.
The semiconductor device according to claim 2 or 3. The first series circuit includes a series circuit of four first switching elements as the plurality of first switching elements.
The second series circuit includes a series circuit of four second switching elements as the plurality of second switching elements.
The third series circuit has four third switches as the plurality of third switching elements.
Including the series circuit of the hatching element,
The fourth series circuit includes a series circuit of four fourth switching elements as the plurality of fourth switching elements.
The first end of the first capacitor is a connection point between the first switching element and the second first switching element from one end side of the four first switching elements connected in series. The second end of the first capacitor is connected to the connection point between the third first switching element and the fourth first switching element.
The first end of the second capacitor is a connection point between the second switching element first from one end side and the second second switching element of the four second switching elements connected in series. The second end of the second capacitor is connected to the connection point between the third second switching element and the fourth second switching element.
The first end of the third capacitor is a connection point between the first third switching element and the second third switching element from one end side of the four third switching elements connected in series. The second end of the third capacitor is connected to the connection point between the third third switching element and the fourth third switching element.
The first end of the fourth capacitor is a connection point between the first fourth switching element and the second fourth switching element from one end side of the four fourth switching elements connected in series. The second end of the fourth capacitor is connected to the connection point between the third fourth switching element and the fourth fourth switching element.
The first connection point is a connection point between the first switching element second from one end side and the third first switching element among the four first switching elements connected in series. ,
The second connection point is a connection point between the second switching element second from the one end side and the third second switching element among the four second switching elements connected in series. ,
The third connection point is a connection point between the third switching element second from one end side and the third third switching element among the four third switching elements connected in series. ,
The fourth connection point is a connection point between the second fourth switching element and the third fourth switching element from the one end side of the four fourth switching elements connected in series. ,
The semiconductor device according to claim 1 or 4. In at least one of the first to fourth series circuits,
Three or more of the plurality of first, second, third, or fourth switching elements are mounted on a substrate and arranged so as to be arranged vertically and horizontally when the substrate is viewed in a plan view.
Between the two first switching elements, the two second switching elements, the two third switching elements, or the two fourth switching elements, which are located diagonally to each other when the substrate is viewed in a plan view, The first, second, third or fourth capacitors are arranged,
The semiconductor device according to claim 1, 4 or 5. At least one of the plurality of modules includes a temperature sensing element housed in the package.
The semiconductor device according to any one of claims 1 to 6. At least one of the plurality of modules includes at least one resistor contained in the package.
The plurality of first switching elements, the plurality of second switching elements, the plurality of third switching elements, the plurality of fourth switching elements, the plurality of fifth switching elements and the plurality of sixth. The at least one resistor is connected in parallel to at least one of the switching elements of the above.
The semiconductor device according to any one of claims 1 to 7. The semiconductor device according to claim 1 is used as the first module or the second module.
device. Used as one of the six modules in the semiconductor device according to claim 2.
device. The semiconductor device according to claim 3 is used as one of the first to sixth modules.
device.

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