JP7056667B2 - Image sensor and image sensor - Google Patents

Description

The present invention relates to an image pickup device and an image pickup apparatus.

An image pickup device in which a chip on which a pixel is formed and a chip on which a pixel drive circuit for driving the pixel is formed is laminated is known (for example, Patent Document 1). In such an image pickup device, if the number of pixels is increased, the reading speed of the signal of the pixels cannot be increased.

Japanese Patent Application Laid-Open No. 2010-225927

According to the first aspect, the image pickup device outputs a signal based on the charge generated by the photoelectric conversion unit that converts light into an electric charge, and is provided with a plurality of output units in a row direction and a column direction different from the row direction. A first signal for outputting signals from the plurality of output units is output to a first signal line to which the plurality of output units are connected, and is output from the first control unit provided in the column direction and the output unit. A second signal is output to the second signal line to which the reading unit for reading the signal and the plurality of reading units are connected, and the second signal for causing the plurality of reading units to read the signal is output, and the second control is provided in the column direction . A unit and an adjusting unit for adjusting the deviation between the first signal and the second signal are provided.
According to the second aspect, the image pickup device outputs a signal based on the charge generated by the photoelectric conversion unit that converts light into an electric charge, and is provided with a plurality of output units in a row direction and a column direction different from the row direction. A first signal for outputting signals from the plurality of output units is output to a first signal line to which the plurality of output units are connected, and is output from the first control unit provided in the column direction and the output unit. A second signal for amplifying a signal to the plurality of amplification units is output to a second signal line to which the amplification unit for amplifying the signal and the plurality of the amplification units are connected, and a second control provided in the column direction is provided. A unit and an adjusting unit for adjusting the deviation between the first signal and the second signal are provided.
According to the third aspect, the image pickup apparatus includes the image pickup device according to the first or second aspect.

Cross-sectional view schematically showing the configuration of the image pickup device Cross-sectional view of the image sensor Top view schematically showing the configuration of the image sensor Circuit diagram schematically showing the configuration of the pixel section A circuit diagram showing a detailed configuration of each part shown in FIG. Timing chart showing the operation timing of one pixel block Cross-sectional view schematically showing the configuration of the image pickup device A circuit diagram showing a detailed configuration of each part shown in FIG. Top view schematically showing the circuit layout of the image sensor Cross-sectional view schematically showing the configuration of the image pickup device Circuit diagram schematically showing the configuration of the dummy load Time chart showing the phase difference adjustment process Cross-sectional view schematically showing the configuration of the image pickup device Circuit diagram schematically showing the configuration of the multi-stage relay buffer Block diagram of phase difference detection

(First Embodiment)
FIG. 1 is a cross-sectional view schematically showing a configuration of an image pickup apparatus using the image pickup device according to the first embodiment. The image pickup apparatus 1 includes an image pickup optical system 2, an image pickup element 3, a control unit 4, a lens drive unit 5, and a display unit 6.

The image pickup optical system 2 forms a subject image on the image pickup surface of the image pickup element 3. The imaging optical system 2 includes a lens 2a, a focusing lens 2b, and a lens 2c. The focusing lens 2b is a lens for adjusting the focus of the imaging optical system 2. The focusing lens 2b is configured to be driveable in the optical axis O direction.

The lens driving unit 5 has an actuator (not shown). The lens driving unit 5 drives the focusing lens 2b in the optical axis O direction by a desired amount by this actuator. The image sensor 3 captures a subject image and outputs an image. The control unit 4 controls each unit such as the image sensor 3. The control unit 4 performs image processing or the like on the image signal output by the image pickup device 3 to record it on a recording medium (not shown) or display an image on the display unit 6. The display unit 6 is a display device having a display member such as a liquid crystal panel.

FIG. 2 is a cross-sectional view of the image pickup device 3. Note that FIG. 2 shows only a part of the cross section of the entire image sensor 3. The image pickup device 3 is a so-called back-illuminated image pickup device. The image sensor 3 photoelectrically converts the incident light from the paper surface direction. The image pickup device 3 includes a first semiconductor substrate 7 and a second semiconductor substrate 8.

The first semiconductor substrate 7 includes at least a PD layer 71 and a wiring layer 72. The PD layer 71 is arranged on the back surface side of the wiring layer 72. A plurality of photodiodes 31 are arranged two-dimensionally on the PD layer 71. Various circuits (described later) for converting and storing the signal read from the photodiode 31 are arranged on the second semiconductor substrate 8.

A plurality of color filters 73 corresponding to each of the plurality of photodiodes 31 are provided on the incident side of the incident light in the PD layer 71. There are a plurality of types of color filters 73 that transmit through wavelength regions corresponding to, for example, red (R), green (G), and blue (B). In the color filter 73, for example, three types corresponding to red (R), green (G), and blue (B) are arranged so as to form a Bayer arrangement.

A plurality of microlenses 74 corresponding to each of the plurality of color filters 73 are provided on the incident side of the incident light in the color filter 73. The microlens 74 collects incident light toward the corresponding photodiode 31. The incident light that has passed through the microlens 74 is transmitted only in a part of the wavelength region by the color filter 73, and is incident on the photodiode 31. The photodiode 31 photoelectrically converts the incident light to generate an electric charge.

A plurality of joining pads 75 are arranged on the surface of the wiring layer 72. A plurality of bonding pads 76 corresponding to the plurality of bonding pads 75 are arranged on the surface of the second semiconductor substrate 8 facing the wiring layer 72. The plurality of joining pads 75 and the plurality of joining pads 76 are joined to each other. The first semiconductor substrate 7 and the second semiconductor substrate 8 are electrically connected via the plurality of bonding pads 75 and the plurality of bonding pads 76.

Although the details will be described later, the image pickup device 3 has a plurality of pixel units 30. One pixel unit 30 includes a first pixel unit 30x provided on the first semiconductor substrate 7 and a second pixel unit 30y provided on the second semiconductor substrate 8. One first pixel unit 30x includes one microlens 74, one color filter 73, one photodiode 31, and the like. In addition to this, the first pixel unit 30x includes various circuits (described later) provided on the first semiconductor substrate 7. The second pixel unit 30y includes various circuits (described later) provided on the second semiconductor substrate 8.

FIG. 3 is a plan view schematically showing the configuration of the image pickup device 3. The image pickup device 3 has a data transfer control unit 40 and n (plural) pixel block rows 33 arranged in the horizontal direction (x direction). Each pixel block row 33 has m (plural) pixel blocks 32 arranged in the vertical direction (y direction). That is, the image sensor 3 has a total of m × n pixel blocks 32.

The pixel block 32 has a total of Ma × Na pixel portions 30 arranged in Ma rows and Na columns. As described above, since the pixel block 32 has a total of m × n, the pixel unit 30 has a total of m × n × Ma × Na. Although the pixel portions 30 are arranged in a square in FIG. 3, the pixel portions 30 may be arranged in a manner different from the square.

In addition to the pixel unit 30 described above, the pixel block 32 includes Ma + 1 relay buffers 34 and Na amplifier circuits 35. Of the pixel blocks 32, the pixel block 32 not included in the leftmost pixel block row 33 (pixel block row 33 closest to the data transfer control unit 40) in FIG. 3 further includes Ma + 1 dummy loads 36.

The data transfer control unit 40 includes Ma × m (plural) row selection control units 41 and m (plural) amplifier control units 42. That is, the number of row selection control units 41 is the same as the number of rows of the pixel unit 30, and the number of amplifier control units 42 is the same as the number of rows of the amplifier circuit 35. The row selection control unit 41 is arranged in a row, and the amplifier control unit 42 is arranged for each Ma. That is, the arrangement of Ma row selection control units 41 and one amplifier control unit 42 is repeated m times.

The image pickup device 3 has Ma × m (plural) row selection signal lines 51 and m (plural) amplifier signal lines 52. That is, the number of line selection signal lines 51 is the same as the number of lines of the pixel unit 30, and the number of amplifier signal lines 52 is the same as the number of lines of the amplifier circuit 35.

The row selection signal line 51 connects the row selection control unit 41 and the n × Na pixel units 30. The n × Na pixel portions 30 are a plurality of pixel portions 30 arranged in the same row, each of the pixel blocks 32 adjacent to each other in the horizontal direction. A relay buffer 34 is provided between the row selection control unit 41 and the plurality of pixel units 30. A relay buffer 34 and a dummy load 36 are provided between the plurality of pixel portions 30 arranged in the same row of the pixel blocks 32 adjacent to each other in the horizontal direction.

The amplifier signal line 52 connects the amplifier control unit 42 and the n × Na amplifier circuits 35. The n × Na amplifier circuits 35 are a plurality of amplifier circuits 35 arranged in the same row, each of which is horizontally adjacent pixel blocks 32. A relay buffer 34 is provided between the amplifier control unit 42 and the plurality of amplifier circuits 35. A relay buffer 34 is also provided between the plurality of amplifier circuits 35 arranged in the same row, which each of the horizontally adjacent pixel blocks 32 has. A dummy load 36 is connected between a plurality of amplifier circuits 35 arranged in the same row, which each of the horizontally adjacent pixel blocks 32 has.

The image pickup device 3 has n × Na output signal lines 54 (vertical signal lines). That is, the number of output signal lines 54 is the same as the number of columns of the pixel unit 30. The output signal line 54 connects m × Ma pixel units 30. The m × Ma pixel portions 30 are a plurality of pixel portions 30 arranged in the same row, which are each possessed by the pixel blocks 32 (pixel blocks 32 arranged in the vertical direction) in the pixel block row 33. An amplifier circuit 35 is provided between a plurality of pixel portions 30 arranged in the same row of the pixel blocks 32 adjacent to each other in the vertical direction. Further, the amplifier circuit 35 is also provided in the pixel blocks 32 arranged in the bottom row.

In FIG. 3, the row selection signal line 51, the amplifier signal line 52, and the output signal line 54 are shown by one straight line for convenience. In reality, each of these signal lines is composed of a plurality of signal lines (described later).

An output I / F unit (not shown) is connected to the end of the amplifier circuit 35 provided in the pixel block 32 arranged in the bottom row. The output I / F unit outputs an image signal in a data format such as LVDS or SLVS.

FIG. 4 is a circuit diagram schematically showing the configuration of the pixel unit 30. The pixel unit 30 includes a first pixel unit 30x provided on the first semiconductor substrate 7 and a second pixel unit 30y provided on the second semiconductor substrate 8. The first pixel portion 30x and the second pixel portion 30y are electrically connected by the joining pads 75 and 76.

The first pixel unit 30x includes a photodiode 31, a transfer transistor 62, a reset transistor 63, an amplification transistor 64, and a constant current source 65. The photodiode 31 photoelectrically converts the incident light to generate a signal charge. The signal charge generated by the photodiode 31 is transferred by the transfer transistor 62 to the floating diffusion FD provided between the transfer transistor 62, the reset transistor 63, and the amplification transistor 64. The amplification transistor 64 outputs a signal voltage corresponding to the amount of signal charge stored in the floating diffusion FD to the second pixel unit 30y via the junction pads 75 and 76. The reset transistor 63 resets the signal charge stored in the floating diffusion FD and the photodiode 31.

The second pixel unit 30y includes an A / D conversion unit 67 and a storage unit 38. The signal voltage output from the first pixel unit 30x via the bonding pads 75 and 76 is converted into a digital value by the A / D conversion unit 67. The A / D conversion unit 67 outputs a K-bit digital signal to the storage unit 38 by means of K signal lines.

The storage unit 38 includes K storage circuits 68 and a selection switch 69. The storage circuit 68 is a circuit that stores a 1-bit digital value such as a flip-flop. The storage unit 38 stores the K-bit digital signal (digital value) output by the A / D conversion unit 67 by the K storage circuits 68. As described above, the first pixel unit 30x outputs a signal (voltage) based on the electric charge generated by the photoelectric conversion unit (photodiode) 31 to the second pixel unit 30y. The A / D conversion unit 67 of the second pixel unit 30y converts the signal based on the charge generated by the photoelectric conversion unit 31 into a digital signal and outputs the signal to the storage unit 38. The storage circuit 68 of the storage unit 38 stores a digital signal based on the electric charge generated by the photoelectric conversion unit 31.

The output signal line 54 is composed of K × 2 signal lines so that a complementary signal of a digital value of K bits can be transmitted as an output signal. The selection switch 69 outputs the K-bit digital signal stored in the K storage circuits 68 to the output signal line 54 in response to the line selection signal output to the line selection signal line 51. The selection switch 69 outputs a digital signal based on the electric charge generated by the photoelectric conversion unit 31 stored in the storage circuit 68 to the output signal line 54. The line selection signal line 51 includes a signal line SEL. The A / D conversion unit 67 may convert a signal based on the electric charge generated by the photoelectric conversion unit 31 into a digital signal and output it to the selection switch 69. The selection switch 69 may output the digital signal output from the A / D conversion unit 67 to the output signal line 54 based on the signal output to the row selection signal line 51. The selection switch 69 is an output unit that outputs a signal based on the electric charge generated by the photoelectric conversion unit 31. The row selection control unit 41 outputs a signal (signal line SEL signal) for outputting a signal from a plurality of selection switches 69 to the row selection signal line 51. The row selection control unit 41 is a control unit that outputs a signal for outputting a signal from the plurality of selection switches 69 to the row selection signal line 51 to which the plurality of selection switches 69 are connected.

FIG. 5 is a circuit diagram showing a detailed configuration of each part shown in FIG. Note that FIG. 5 illustrates only the portion related to one storage circuit 68 among the K storage circuits 68 possessed by one storage unit 38. That is, FIG. 5 illustrates only the portion related to the output of one bit per storage unit 38.

The complementary signals Q and / Q output from the storage circuit 68 are output to the positive logic signal line 54p and the negative logic signal line 54n of the output signal line 54, respectively. The equalizing circuit 71 is connected to the row selection control unit 41 via the signal line EQB included in the row selection signal line 51. Although not shown in FIG. 4, the equalization circuit 71 is arranged between the vertically adjacent pixel portions 30. The precharge circuit 72 is connected to the amplifier control unit 42 via the signal line PREB included in the amplifier signal line 52. The equalize circuit 71 and the precharge circuit 72 perform a precharge operation described later with respect to the positive logic signal line 54p and the negative logic signal line 54n. After the precharge operation, the complementary signals Q and / Q are read out and output to the next pixel block 32 via the amplifier circuit 35. The amplifier circuit 35 is connected to the amplifier control unit 42 via the signal line ASWB and the signal line AE included in the amplifier signal line 52. The amplifier circuit 35 is controlled by the signal line ASWB and the signal line AE. The amplifier signal line 52 further includes a signal line SELA. The output from the amplifier circuit 35 is output to the next pixel block 32 by the signal line SELA. The amplifier circuit 35 is a reading unit that reads out a signal output from the selection switch 69. The amplifier control unit 42 is a control unit that outputs a signal to be read by a plurality of amplifier circuits 35 to an amplifier signal line 52 to which a plurality of amplifier circuits 35 are connected. The operation of the circuit shown in FIG. 5 will be described in detail later.

Each signal line included in the line selection signal line 51 and each signal line included in the amplifier signal line 52 (hereinafter, these signal lines are collectively referred to as horizontal signal lines) are located between pixel blocks 32 adjacent to each other in the horizontal direction. A dummy load 36 is connected each time. Each of the dummy loads 36 has an individually adjusted size. The size of each dummy load 36 is determined, for example, by circuit simulation of the image pickup element 3 at the time of designing the image pickup element 3. The method for determining the size of the dummy load 36 will be described in detail later.

FIG. 6 is a timing chart showing the operation timing of one pixel block 32. In FIG. 6, among a plurality of line selection signal lines 51 connected to the target pixel block 32, the signal line SEL of the first line is the signal line SEL <1>, and the signal line SEL of the second line is the signal line. SEL <2> The signal line SEL on the third line is referred to as a signal line SEL <3>. Further, the output signal line 54 is referred to as a signal line Q and a signal line / Q, and the output signal in the amplifier circuit 35 is referred to as a signal line R and a signal line / R (see FIG. 5).

Until time t31, the signal levels of the signal line EQB and the signal line PREB are set to L level, and both the signal line Q and the signal line / Q are set to H level (precharge operation). Due to this precharging operation, changes in the signal line Q and the signal line / Q are reflected in the signal levels of the signal line R and the signal line / R in the amplifier circuit 35. That is, the signal levels of the signal line R and the signal line / R in the amplifier circuit 35 are both H levels.

At time t31, the data transfer control unit 40 outputs an H level signal to the signal line SEL <1>, outputs an H level signal to the signal line EQB and the signal line PREB, and outputs an H level signal to the signal line ASWB. Output a signal. By outputting the H level signal to the signal line SEL <1>, the selection switch 69 is turned on in the pixel unit 30 of the first line, and the output signal is output to the output signal line 54. As described above, the output signal is a complementary signal, and an H level signal is output to one of the signal line Q and the signal line / Q, and an L level signal is output to the other. When the signal levels of the signal line Q and the signal line / Q are both set to the H level by the precharge operation, such an output signal is output, so that one of the signal line Q and the signal line / Q is output. The signal level remains at the H level, and the other signal level gradually approaches the L level (the potential decreases). Since the output signal line 54 has a certain distance in the row direction (vertical direction on the paper in FIG. 5), the L level signal is not immediately transmitted to the amplifier circuit 35. Since the signal level of the signal line ASWB remains at the L level from time t31, the changes in the signal line Q and the signal line / Q are reflected in the signal levels of the signal line R and the signal line / R in the amplifier circuit 35. To. That is, the signal levels of the signal line R and the signal line / R remain at the H level on one side and gradually approach the L level on the other side.

At time t32 after the waiting time T2 has elapsed from time t31, the data transfer control unit 40 outputs an L level signal to the signal line ASWB and outputs an H level signal to the signal line AE. As a result, the signal levels of the signal line ASWB and the signal line AE change from the L level to the H level. When the signal level of the signal line ASWB becomes H level, the signal line R and the signal line / R in the amplifier circuit 35 are separated from the signal line Q and the signal line / Q. When the signal level of the signal line AE becomes H level, the amplifier circuit 35 is activated. That is, when the signal levels of the signal line ASWB and the signal line AE reach the H level, the signal levels of the signal line Q and the signal line / Q are latched, and the H level or the L level depends on the latched signal level. The signal is output from the amplifier circuit 35. By performing the above operation row by row, the output signal from the pixel unit 30 belonging to each row is relayed by the amplifier circuit 35.

The signal line SEL, the signal line EQB, the signal line PREB, the signal line ASWB, and the signal line AE of the image pickup device 3 extend horizontally long over a large number of pixel blocks 32. Therefore, the signals output from the data transfer control unit 40 to these signal lines are relative from the first (leftmost) pixel block 32 to the last (rightmost) pixel block 32. Will take a long time. In addition, many circuit elements (transistors, etc.) are connected to these signal lines, and the number, type, size, etc. of these are different for each signal line. Therefore, the delay time of the output signal is a signal. Variation occurs for each line.

If the delay time of the signal is different for each signal line, for example, the signal flowing through the signal line SEL shown in FIG. 6 and the signal flowing through the signal line AE are more likely to be displaced in the left-right direction. Therefore, in order to reliably latch the signal read from the pixel unit 30 to be read, the row selection signal is output for a sufficiently long period, and the H level signal is output to the signal line AE for a sufficiently long period. It needs to be long. As a result, the reading speed of the image pickup signal becomes slow.

In the present embodiment, a dummy load 36 is provided so as to adjust the variation in the signal delay time for each signal line and to make the signal delay times uniform in all the signal lines. The size of the dummy load 36 is adjusted so that the impedances of the signal lines are the same for all signal lines. For example, by performing a circuit simulation at the time of circuit design of the image pickup device 3, the size of the dummy load 36 required for aligning the impedance of the signal line is determined. For example, a signal line having a small impedance is provided with a dummy load 36 having a large size, and conversely, a signal line having a large impedance is provided with a dummy load 36 having a small size.

By providing the dummy load 36 in this way, the difference in impedance for each signal line becomes small, and the difference in signal delay time for each signal line becomes small. Therefore, the phase difference (deviation) of the signal for each signal line becomes small, and the image pickup signal can be read out at a higher speed than in the case where the dummy load 36 is not provided.
In an image sensor with a pixel parallel readout configuration, it is necessary to arrange an A / D converter and a storage unit for each pixel, and the control line that controls the output of the storage unit and the amplifier that amplifies during the output data transfer of the storage unit. A lot of load is applied to the control line. In such an image sensor, a phase error between the control line of the storage unit and the control line of the amplification amplifier tends to occur, so that the image signal (imaging signal) cannot be transferred at high speed. On the other hand, in the present embodiment, by providing the dummy load 36, the phase error between the control line of the storage unit, that is, the row selection signal line 51 and the control line of the amplification amplifier, that is, the amplifier signal line 52 is suppressed, and the imaging signal is captured. Can be read at high speed.

According to the above-described embodiment, the following effects can be obtained.
(1) The data transfer control unit 40 connects an amplifier signal line 52 and a plurality of line selection signal lines 51, sequentially outputs line selection signals to the plurality of line selection signal lines 51, and sequentially outputs a plurality of line selection signals. Every time a line selection signal is output to the line 51, an amplifier signal is output to the amplifier signal line 52. The dummy load 36 adjusts the phase difference (shift) between the row selection signal and the amplifier signal. Since this is done, it is possible to suppress the signal delay caused by the distance between the pixel units 30, and it is possible to achieve both a high number of pixels and a high read speed.

(2) Among a plurality of pixel blocks 32 including a plurality of storage units 38 capable of storing digital values and a dummy load 36, a plurality of output signal lines in other pixel blocks 32 excluding the terminal pixel block 32. 54 is connected to a plurality of output signal lines 54 of another pixel block 32. By doing so, since the signal between the pixel blocks 32 is relayed by the amplifier circuit 35, long-distance data transfer becomes possible, and high-speed read speed is achieved even when a large number of pixel units 30 are present. be able to.

(3) The plurality of pixel block columns 33 including the plurality of pixel blocks 32 are connected to each other via the plurality of row selection signal lines 51, and the row selection signal is relayed between the plurality of pixel block columns 33. A relay buffer 34 is provided. Since this is done, even in the pixel unit 30 far away from the row selection control unit 41, the influence of the signal delay or the like on the row selection signal can be minimized.

(4) The dummy load 36 adjusts the phase difference between the row selection signal and the amplifier signal by adjusting the impedances of the amplifier signal line 52 and the row selection signal line 51. Since this is done, even in the pixel unit 30 far away from the row selection control unit 41, the influence of the signal delay or the like on the row selection signal can be minimized.

(5) A plurality of photodiodes 31 corresponding to each of the storage units 38 are further provided, and the storage unit 38 stores the digital values of the photoelectric conversion signals output by the plurality of photodiodes 31. Since this is done, a digital signal can be output for each pixel unit 30, and the transmission of the output signal becomes easier than that of an analog signal.

(6) A plurality of photodiodes 31 are provided on the first semiconductor substrate 7. The plurality of storage units 38 and the amplifier circuit 35 are provided in a place different from that of the first semiconductor substrate 7. Since this is done, the opening area of the photodiode 31 is not compressed by the plurality of storage units 38 and the amplifier circuit 35.

(Second embodiment)
Hereinafter, the differences from the image pickup device according to the first embodiment will be described.

FIG. 7 is a plan view schematically showing the configuration of the image pickup device. The difference from FIG. 3 is that the dummy load 36 does not exist and the buffer 37 with delay adjustment is provided instead of the relay buffer 34.

FIG. 8 is a circuit diagram showing a detailed configuration of each part shown in FIG. 7. The difference from FIG. 5 is that the dummy load 36 does not exist and the buffer 37 is provided instead of the relay buffer 34.

The buffer 37 has one or more relay buffers 34 connected in series. The number of relay buffers 34 included in one buffer 37 is individually determined for each signal line so that there is no difference in the signal delay time for each signal line. For example, by performing a circuit simulation at the time of designing the image pickup device 3, the signal delay time for each signal line is obtained, and the number of relay buffers 34 is determined so that the delay time is uniform for each signal line. For example, a signal line having a large delay time is provided with a smaller number of relay buffers 34, and conversely, a signal line having a small delay time is provided with a larger number of relay buffers 34.

That is, in the first embodiment, the signal delay time for each signal line is adjusted by the size of the dummy load 36, whereas in the second embodiment, the relay buffer 34 included in the buffer 37 The signal delay time for each signal line is adjusted according to the number of signals.

The second embodiment described above has the same effect as that of the first embodiment.

(Third embodiment)
The image pickup device according to the present embodiment has the same configuration as the image pickup device according to the first embodiment shown in FIG. 3, except that the dummy load 36 does not exist. Hereinafter, the differences from the image pickup device according to the first embodiment will be described.

FIG. 9 is a plan view schematically showing the circuit layout of the image sensor. In the present embodiment, the wiring width W1 of the signal line SEL, the wiring width W2 of the signal line EQB, the wiring width W3 of the signal line PREB, the wiring width W4 of the signal line ASWB, the wiring width W5 of the signal line AE, and the signal line SELA. Wiring width W6 is individually determined for each signal line.

For example, by performing a circuit simulation at the time of designing the image sensor 3, the signal delay time for each signal line is obtained, and the wiring widths W1 to W6 of each signal line are determined so that the delay time is uniform for each signal line. Ru. For example, a signal line having a large delay time has a wider wiring width, and conversely, a signal line having a small delay time has a narrower wiring width. In this way, the wiring widths W1 to W6 are determined so that the impedances of the signal lines are uniform.

That is, in the first embodiment, the signal delay time for each signal line is adjusted by the size of the dummy load 36, whereas in the third embodiment, the signal line is adjusted by the wiring width for each signal line. The delay time of each signal is adjusted.

The third embodiment described above has the same effect as that of the first embodiment.

(Fourth Embodiment)
Hereinafter, the differences from the image pickup device according to the first embodiment will be described.

FIG. 10 is a plan view schematically showing the configuration of the image pickup device. The difference from FIG. 3 is that the first dummy load 38 and the second dummy load 39 are provided instead of the dummy load 36, and the delay control unit 80 and the phase difference detection unit 90 are newly provided. Is.

A first dummy load 38 connected to the row selection signal line 51 and a second dummy load 39 connected to the amplifier signal line 52 are provided between the pixel blocks 32 adjacent to each other in the horizontal direction. That is, Ma first dummy loads 38 are provided for each pixel block 32, and one second dummy load 39 is provided for each pixel block 32. However, neither the first dummy load 38 nor the second dummy load 39 is provided in the leftmost pixel block 32 (the pixel block closest to the data transfer control unit 40).

The delay control unit 80 has a plurality of row delay signal output units 81 and a plurality of amplifier delay signal output units 82, respectively. One line delay signal output unit 81 is provided for each line of the pixel block 32. That is, a total of m line delay signal output units 81 are provided. The row delay signal output unit 81 is connected to all the first dummy loads 38 of the pixel block 32 in one row via the row delay signal line 57.

One amplifier delay signal output unit 82 is provided for each line of the pixel block 32. That is, a total of m amplifier delay signal output units 82 are provided. The amplifier delay signal output unit 82 is connected to all the second dummy loads 39 of the pixel block 32 in one line via the amplifier delay signal line 58.

At the ends of the row selection signal line 51 and the amplifier signal line 52, a phase difference detection unit 90 is provided for each pixel block 32. That is, a total of m phase difference detection units 90 are provided. Ma line selection signal lines 51 and one amplifier signal line 52 are connected to one phase difference detection unit 90. All the phase difference detection units 90 are connected to the delay control unit 80 via the phase difference signal line 59.

FIG. 11A is a circuit diagram schematically showing the configuration of the first dummy load 38. The first dummy load 38 includes a dummy load 38a, a dummy load 38b, a dummy load 38c, and a dummy load 38d. The dummy load 38a, the dummy load 38b, the dummy load 38c, and the dummy load 38d are connected to the row selection signal line 51 via the transistor 78a, the transistor 78b, the transistor 78c, and the transistor 78d, respectively.

The dummy load 38a is composed of transistors having a predetermined size. The dummy load 38b is composed of transistors having a size half that of the dummy load 38a. The dummy load 38c is composed of transistors having a size half that of the dummy load 38b. The dummy load 38d is composed of transistors having a size half that of the dummy load 38c. That is, based on the size of the dummy load 38a, the size of the dummy load 38b is 1/2, the size of the dummy load 38c is 1/4, and the size of the dummy load 38d is 1/8.

The line delay signal line 57 includes four signal lines. These four signal lines are connected to the transistor 78a, the transistor 78b, the transistor 78c, and the transistor 78d, respectively. The signals flowing through these four signal lines individually turn on and off the transistor 78a, the transistor 78b, the transistor 78c, and the transistor 78d. By turning on / off the transistor 78a, the transistor 78b, the transistor 78c, and the transistor 78d, the dummy load 38a, the dummy load 38b, the dummy load 38c, and the dummy load 38d are connected to the row selection signal line 51 or are connected to the row selection signal line 51 or from the row selection signal line 51. It may be separated.

FIG. 11B is a circuit diagram schematically showing the configuration of the second dummy load 39. The second dummy load 39 includes a dummy load 39a, a dummy load 39b, a dummy load 39c, and a dummy load 39d. The dummy load 39a, the dummy load 39b, the dummy load 39c, and the dummy load 39d are connected to the amplifier signal line 52 via the transistor 79a, the transistor 79b, the transistor 79c, and the transistor 79d, respectively.

The dummy load 39a is composed of transistors having a predetermined size. The dummy load 39b is composed of transistors having a size half that of the dummy load 39a. The dummy load 39c is composed of transistors having a size half that of the dummy load 39b. The dummy load 39d is composed of transistors having a size half that of the dummy load 39c. That is, based on the size of the dummy load 39a, the size of the dummy load 39b is 1/2, the size of the dummy load 39c is 1/4, and the size of the dummy load 39d is 1/8.

The amplifier delay signal line 58 includes four signal lines. These four signal lines are connected to the transistor 79a, the transistor 79b, the transistor 79c, and the transistor 79d, respectively. The signals flowing through these four signal lines individually turn on and off the transistor 79a, the transistor 79b, the transistor 79c, and the transistor 79d. By turning on / off the transistor 79a, the transistor 79b, the transistor 79c, and the transistor 79d, the dummy load 39a, the dummy load 39b, the dummy load 39c, and the dummy load 39d are connected to the amplifier signal line 52 or disconnected from the amplifier signal line 52. Or something.

In the present embodiment, the phase difference detecting unit 90 dynamically detects the phase difference (deviation) of the signal for each signal line, and the delay control unit 80 sets the first dummy load 38 and the first dummy load 38 based on the detected phase difference. 2 By controlling the dummy load 39, the variation in the phase difference for each signal line is dynamically suppressed. Hereinafter, the control of the phase difference will be described with reference to FIG.

FIG. 12 is a time chart showing the process of adjusting the phase difference. At time t41, the row selection control unit 41 outputs an H level signal (row selection signal) to the signal line SEL. At the subsequent time t42, the amplifier control unit 42 outputs an H level signal (amplifier signal) to the signal line AE. Hereinafter, the difference between the time t41 and the time t42, that is, the delay of the amplifier signal with respect to the row selection signal is referred to as Δt1.

At time t43 after time t42, the row selection signal reaches the phase difference detection unit 90. At time t44 after time t42, the amplifier signal reaches the phase difference detection unit 90. Hereinafter, the difference between the time t43 and the time t44, that is, the delay of the detection time of the amplifier signal with respect to the detection time of the row selection signal is referred to as Δt2.

Ideally, Δt1 and Δt2 are equal. That is, ideally, the phase difference detection unit 90 should detect that the amplifier signal is delayed by Δt1 with respect to the row selection signal. Actually, as described in the description of each embodiment, Δt2 is different from Δt1 due to the difference in impedance for each signal line and the like. That is, the phase difference detection unit 90 detects a delay (phase difference) different from that of Δt1. For example, it may be detected that the amplifier signal is larger than Δt1 and lags behind the row selection signal, and conversely, the amplifier signal is ahead of the row selection signal (the row selection signal is behind the amplifier signal). ) May be detected.

The phase difference detection unit 90 reads out the expected value of the phase difference stored in advance in a storage unit (not shown). The expected value of this phase difference is determined, for example, by circuit simulation or the like at the time of design, and is stored in a storage unit (not shown) at the time of manufacturing the image pickup device 3.

When the amplifier signal is detected by the phase difference detection unit 90, the phase difference detection unit 90 calculates Δt2, that is, the phase difference between the row selection signal and the amplifier signal. The phase difference detection unit 90 compares the calculated actual phase difference with the expected value of the phase difference, and obtains the error of the phase difference. The phase difference detection unit 90 outputs a signal indicating a phase difference error to the phase difference signal line 59.

The delay control unit 80 adds a first dummy load 38 and a second dummy load to the row delay signal line 57 and the amplifier delay signal line 58 based on the signal indicating the phase difference error input via the phase difference signal line 59. A signal for adjusting 39 is output. The delay control unit 80 outputs a signal to the row delay signal line 57 and the amplifier delay signal line 58 so that the error of the phase difference is canceled and the phase difference is at least equal to or less than a predetermined threshold value. Since the first dummy load 38 and the second dummy load 39 include a plurality of dummy loads having different sizes from each other, the connection to these line selection signal lines 51 and the amplifier signal line 52 should be individually controlled. Therefore, the error of the phase difference can be canceled with sufficient accuracy.

The number of dummy loads included in the first dummy load 38 may be more than or less than four. Moreover, each size may be different from the above-mentioned description. The same applies to the second dummy load 39. The above-mentioned phase difference threshold value may be appropriately determined depending on the number and size of the dummy loads included in the first dummy load 38.

FIG. 15 is a block diagram of phase difference detection. The row delay signal output unit 81 of the delay control unit 80 switches the first dummy load 38 connected to the signal line SEL <0>. Similarly, the amplifier delay signal output unit 82 of the delay control unit 80 switches the second dummy load 39 connected to the signal line AE. The phase difference and the phase direction detected for the signal line SEL <0> and the signal line AE are compared with a predetermined phase difference expected value generated separately, and the phase difference error is counted. The counted phase difference error is fed back to the delay control unit 80.

According to the above-described embodiment, in addition to the action and effect described in the first embodiment, the following action and effect can be further obtained.
(1) Since the phase difference is adjusted based on the dynamically detected phase difference instead of the phase difference determined at the time of design, it is possible to deal with the phase difference caused by the external environment such as the manufacturing process, temperature, and voltage. , A higher performance image pickup device can be provided.

(Fifth Embodiment)
Hereinafter, the differences from the image pickup device according to the fourth embodiment will be described.

FIG. 13 is a plan view schematically showing the configuration of the image pickup device. The difference from FIG. 10 is that the first dummy load 38 and the second dummy load 39 do not exist, and a part of the relay buffer 34 is replaced with the first multi-stage relay buffer 94 and the second multi-stage relay buffer 95. Is.

Except for the leftmost pixel block 32 (the pixel block closest to the data transfer control unit 40), each pixel block 32 is connected to the first multi-stage relay buffer 94 connected to the row selection signal line 51 and the amplifier signal line 52. A second multi-stage relay buffer 95 to be connected is provided. That is, Ma first multi-stage relay buffers 94 are provided for each pixel block 32, and one second multi-stage relay buffer 95 is provided for each pixel block 32. However, the leftmost pixel block 32 (the pixel block closest to the data transfer control unit 40) is provided with a relay buffer 34, not a first multi-stage relay buffer 94 or a second multi-stage relay buffer 95.

The row delay signal output unit 81 is connected to all the first multi-stage relay buffers 94 included in the pixel block 32 of one row via the row delay signal line 57. The amplifier delay signal output unit 82 is connected to all the second multi-stage relay buffers 95 of the pixel block 32 in one line via the amplifier delay signal line 58.

FIG. 14A is a circuit diagram schematically showing the configuration of the first multi-stage relay buffer 94. The first multi-stage relay buffer 94 includes a buffer 94a, a buffer 94b, a buffer 94c, and a buffer 94d. The buffer 94a, the buffer 94b, the buffer 94c, and the buffer 94d are connected to the row selection signal line 51 via the transistor 98a, the transistor 98b, the transistor 98c, and the transistor 98d, respectively.

The line delay signal line 57 includes four signal lines. These four signal lines are connected to the transistor 98a, the transistor 98b, the transistor 98c, and the transistor 98d, respectively. The signals flowing through these four signal lines individually turn on and off the transistor 98a, the transistor 98b, the transistor 98c, and the transistor 98d. By turning on / off the transistor 98a, the transistor 98b, the transistor 98c, and the transistor 98d, the buffer 94a, the buffer 94b, the buffer 94c, and the buffer 94d are connected to the row selection signal line 51 or disconnected from the row selection signal line 51. ..

FIG. 14B is a circuit diagram schematically showing the configuration of the second multi-stage relay buffer 95. The second multi-stage relay buffer 95 includes a buffer 95a, a buffer 95b, a buffer 95c, and a buffer 95d. The buffer 95a, the buffer 95b, the buffer 95c, and the buffer 95d are connected to the amplifier signal line 52 via the transistor 99a, the transistor 99b, the transistor 99c, and the transistor 99d, respectively.

The amplifier delay signal line 58 includes four signal lines. These four signal lines are connected to the transistor 99a, the transistor 99b, the transistor 99c, and the transistor 99d, respectively. The signals flowing through these four signal lines individually turn on and off the transistor 99a, the transistor 99b, the transistor 99c, and the transistor 99d. By turning on / off the transistor 99a, the transistor 99b, the transistor 99c, and the transistor 99d, the buffer 95a, the buffer 95b, the buffer 95c, and the buffer 95d are connected to the amplifier signal line 52 or disconnected from the amplifier signal line 52.

In the fourth embodiment, as shown in FIG. 11, by connecting a plurality of dummy loads to the signal line or disconnecting from the signal line, the impedance of each signal line is dynamically adjusted. The phase difference (deviation) of the signal for each signal line was dynamically adjusted. On the other hand, in the present embodiment, by connecting a plurality of buffers to the signal line or disconnecting from the signal line, the delay of the signal for each signal line is dynamically adjusted, so that each signal line can be used. Dynamically adjust the phase difference of the signal.

The number of buffers included in the first multi-stage relay buffer 94 may be more or less than four. The same applies to the second multi-stage relay buffer 95.

The fifth embodiment described above has the same effect as that of the fourth embodiment.

The following modifications are also within the scope of the present invention, and one or more of the modifications can be combined with the above-described embodiment.
(Modification 1)
In each of the above-described embodiments, the dummy load is configured by the MOS transistor, but the dummy load can also be configured by other circuit elements. For example, a capacitance by MIM (Metal-Insulator-Metal) or MOM (Metal-Oxide-Metal) can be used as a dummy load.

(Modification 2)
The global wiring and the local wiring may be separated for each pixel block 32. That is, instead of directly connecting each pixel unit 30 to the signal line in the horizontal direction, the pixel unit 30 in the pixel block 32 may be connected in parallel via a buffer or the like.

(Modification 3)
The number of contacts connecting various transistors and wirings included in the image sensor 3 may be increased or decreased. It is possible to adjust the impedance of the signal line by increasing or decreasing the number of contacts.

(Modification example 4)
One signal line may be composed of a plurality of wiring layers. By bundling the signal lines formed in each of the plurality of wiring layers into one signal line, the impedance of the signal line can be lowered as in the case of increasing the wiring width.

Although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other aspects considered within the scope of the technical idea of the present invention are also included within the scope of the present invention.

The disclosure content of the following priority basic application is incorporated here as a quotation.
Japanese Patent Application No. 1922313 (filed on September 29, 2017)

1 ... Image pickup device, 2 ... Image pickup optical system, 3 ... Image sensor, 30 ... Pixel part, 31 ... Photodiode, 32 ... Pixel block, 33 ... Pixel block sequence, 34 ... Relay buffer, 35 ... Amplifier circuit, 38 ... Storage Unit, 40 ... Data transfer control unit, 41 ... Line selection control unit, 42 ... Amplifier control unit, 51 ... Line selection signal line, 52 ... Amplifier signal line, 54 ... Output signal line

Claims (19)

Outputs a signal based on the electric charge generated by the photoelectric conversion unit that converts light into electric charge, and a plurality of output units provided in the row direction and a column direction different from the row direction.
A first control unit provided in the column direction , which outputs a first signal for outputting signals from the plurality of output units to a first signal line to which the plurality of output units are connected,
A reading unit that reads out the signal output from the output unit, and a reading unit.
A second control unit provided in the column direction , which outputs a second signal for causing the plurality of reading units to read a signal, to a second signal line to which the plurality of reading units are connected.
An adjusting unit that adjusts the deviation between the first signal and the second signal,
An image sensor comprising. Outputs a signal based on the electric charge generated by the photoelectric conversion unit that converts light into electric charge, and a plurality of output units provided in the row direction and a column direction different from the row direction.
A first control unit provided in the column direction , which outputs a first signal for outputting signals from the plurality of output units to a first signal line to which the plurality of output units are connected,
An amplification unit that amplifies the signal output from the output unit, and
A second control unit provided in the column direction , which outputs a second signal for amplifying a signal to the plurality of amplification units, to a second signal line to which the plurality of amplification units are connected.
An adjusting unit that adjusts the deviation between the first signal and the second signal,
An image sensor comprising. In the image pickup device according to claim 2,
The amplification unit is an image pickup device provided between a plurality of output units in the column direction . The image pickup device according to any one of claims 1 to 3.
The adjustment unit is an image pickup device arranged between the plurality of output units. The image pickup device according to any one of claims 1 to 4.
It is equipped with a detection unit that detects the deviation.
The adjusting unit is an image pickup device that adjusts the deviation detected by the detecting unit. The image pickup device according to any one of claims 1 to 5.
The adjusting unit is an image pickup device that adjusts the deviation so as to be small. The image pickup device according to any one of claims 1 to 6.
The adjusting unit is an image pickup device that adjusts the deviation by adjusting the impedances of the first signal line and the second signal line. In the image pickup device according to any one of claims 1 to 7.
The adjusting unit is an image pickup device that reduces the deviation by reducing the difference in impedance between the first signal line and the second signal line. The image pickup device according to any one of claims 1 to 8.
The adjusting unit is an image pickup device which is a load connected to the first signal line and the second signal line. In the image pickup device according to any one of claims 1 to 6.
The adjusting unit is an image pickup device that adjusts the deviation by adjusting the other based on the delay of one of the first signal and the second signal. In the image pickup device according to claim 10,
The adjusting unit is an image pickup device that adjusts the deviation by matching one of the first signal and the second signal, which is delayed, with the other. In the image pickup device according to any one of claims 1 to 11.
The adjusting unit is an image pickup device that is a buffer that relays the first signal and the second signal. The image pickup device according to any one of claims 1 to 12.
Equipped with a plurality of the above-mentioned adjustment units
The plurality of adjustment units are image pickup devices arranged between the plurality of output units. In the image pickup device according to any one of claims 1 to 13.
A storage unit for storing a signal based on the electric charge generated by the photoelectric conversion unit is provided.
The output unit is an image pickup device that outputs a signal stored in the storage unit. The image pickup device according to any one of claims 1 to 14.
The first signal line and the second signal line are image pickup devices provided in the row direction . The image pickup device according to any one of claims 1 to 15.
The first control unit and the second control unit are a plurality of image pickup elements provided in the column direction . In the image pickup device according to claim 16,
The second control unit is an image pickup device provided between the plurality of first control units. In the image pickup device according to claim 16 or 17.
An image pickup device including a control unit having a plurality of the first control units and a plurality of the second control units. An image pickup apparatus comprising the image pickup device according to any one of claims 1 to 18.

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