JP7056826B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device.

In the method of manufacturing a semiconductor device, a semiconductor substrate in a wafer state may be attached to a glass mounting substrate or the like and then polished (for example, Patent Document 1). Specifically, the semiconductor substrate is attached to the mounting substrate using an adhesive such as wax. After polishing the semiconductor substrate, the adhesive is melted, the semiconductor substrate is removed from the mounting substrate, and post-processes such as dicing are performed.

Japanese Unexamined Patent Publication No. 2001-176761

A crosshatch is formed in the semiconductor layer due to lattice mismatch between the semiconductor substrate and the semiconductor layer growing on the semiconductor substrate. When removing the semiconductor substrate, the crosshatch may be the starting point and cracks may occur in the semiconductor substrate. Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor device capable of suppressing cracking of a semiconductor substrate.

In the method for manufacturing a semiconductor device according to the present invention, after a step of removing the outer peripheral portion of the first semiconductor layer formed on the first surface of the semiconductor substrate and a step of removing the outer peripheral portion of the first semiconductor layer, adhesion is performed. After the step of attaching the first surface of the semiconductor substrate to the mounting substrate and the step of attaching the semiconductor substrate using an agent, the semiconductor substrate is described from the second surface side opposite to the first surface. It has a step of thinning the semiconductor substrate, a step of melting the pressure-sensitive adhesive, and a step of separating the semiconductor substrate from the mounting substrate after the step of thinning the semiconductor substrate.

According to the above invention, it is possible to suppress cracking of the semiconductor substrate.

1 (a) to 1 (d) are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 2 is a plan view illustrating a method for manufacturing a semiconductor device. 3A to 3D are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a modified example.

[Explanation of Embodiments of the present invention]
First, the contents of the embodiments of the present invention will be listed and described.
One embodiment of the present invention comprises (1) a step of removing the outer peripheral portion of the first semiconductor layer formed on the first surface of the semiconductor substrate, and a step of removing the outer peripheral portion of the first semiconductor layer, followed by a pressure-sensitive adhesive. After the step of attaching the first surface of the semiconductor substrate to the mounting substrate and the step of attaching the semiconductor substrate, the semiconductor is from the second surface side opposite to the first surface of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising a step of thinning a substrate, a step of melting the pressure-sensitive adhesive after a step of thinning the semiconductor substrate, and a step of separating the semiconductor substrate from the mounting substrate. By removing the outer peripheral portion of the first semiconductor layer, the crosshatch generated in the first semiconductor layer can also be removed. Therefore, it is possible to suppress cracking of the semiconductor substrate starting from the cross hatch.
(2) Even if a second semiconductor layer is formed between the first surface of the semiconductor substrate and the first semiconductor layer, and the first semiconductor layer and the second semiconductor layer are formed of different compound semiconductors from each other. good. A crosshatch is generated in the first semiconductor layer due to the lattice mismatch, but the crosshatch on the outer peripheral portion is removed. This makes it possible to suppress cracking.
(3) The semiconductor substrate and the second semiconductor layer may be formed of indium phosphide, and the first semiconductor layer may be formed of indium gallium arsenide. A crosshatch is generated in the first semiconductor layer due to the lattice mismatch, but the crosshatch on the outer peripheral portion is removed. This makes it possible to suppress cracking. Further, the thickness and composition of the second semiconductor layer can be adjusted so as to suppress the cross hatch.
(4) In the step of removing the outer peripheral portion of the first semiconductor layer, the outer peripheral portion may be removed by wet etching. Cracking can be effectively suppressed by removing the region where many cross hatches occur by wet etching.
(5) The separation step may be a step of separating the semiconductor substrate by sliding one of the semiconductor substrate and the mounting substrate with respect to the other after melting the pressure-sensitive adhesive. It is possible to suppress cracking of the semiconductor substrate during the separation process.
(6) In the step of removing the outer peripheral portion, the first semiconductor layer in the outer peripheral portion may be removed to expose the lower layer of the first semiconductor layer. As a result, cracking can be effectively suppressed.
(7) After the step of removing the outer peripheral portion, the first semiconductor layer having a thickness of 1 μm or less may remain on the outer peripheral portion. Cracking can be suppressed by thickening the semiconductor substrate with respect to the remaining first semiconductor layer.
(8) A third semiconductor layer is formed on the first semiconductor layer, the step of removing a part of the third semiconductor layer is included, and the step of removing the outer peripheral portion is one of the third semiconductor layers. It may be carried out after the step of removing the portion. As a result, the third semiconductor layer can be formed with high accuracy.

[Details of Embodiments of the present invention]
Specific examples of the method for manufacturing a semiconductor device according to the embodiment of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited to these examples, and is indicated by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

1 (a) to 1 (d) and FIGS. 3 (a) to 3 (d) are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment, and FIG. 2 is a method for manufacturing the semiconductor device. It is a top view which illustrates. OF in FIG. 2 is an abbreviation for Orientation Flat, and IF is an abbreviation for Index Flat. 1 (a) to 2 show the process (surface process) before the wafer 20 is attached to the mounting substrate 30, and FIGS. 3 (a) to 3 (d) show the wafer 20 attached to the mounting substrate 30. The subsequent process (backside process) is shown in the figure. The size of the wafer 20 is, for example, 2 inches, and a plurality of light receiving elements are cut out from the wafer 20 after the illustrated process.

As shown in FIG. 1A, a buffer layer 12 (second semiconductor layer), an absorption layer 14 (first semiconductor layer), and indium phosphide (InP) are formed on the upper surface (first surface) of the semiconductor substrate 10 in a wafer state. The layer 16 and the indium gallium arsenide (InGaAs) layer 18 (third semiconductor layer) are epitaxially grown. Wafers 20 in which these semiconductor layers are formed on a semiconductor substrate 10 are collectively referred to as wafers 20. For the growth of the semiconductor layer, for example, an organic metal vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method can be used.

The semiconductor substrate 10 has a size of 2 inches and is formed of, for example, an InP having a thickness of 350 μm. The buffer layer 12 is formed of, for example, an InP having a thickness of 1.5 μm. The absorption layer 14 is a layer that receives light, and is formed of, for example, InGaAs having a thickness of 4 μm. The thickness of the InP layer 16 is, for example, 1 μm. The thickness of the InGaAs layer 18 is, for example, 0.15 μm. The buffer layer 12 contacts the surface of the semiconductor substrate 10, and the absorption layer 14 contacts the surface of the buffer layer 12. The InP layer 16 comes into contact with the surface of the absorption layer 14.

As shown in FIG. 2, a crosshatch 25 is generated in a part of the outer peripheral portion 24 of the wafer 20. The outer peripheral portion 24 is a portion having a width of 2 mm or less inward from the end portion of the wafer 20. The crosshatch 25 is generated by the lattice mismatch between the semiconductor substrate 10 and the absorption layer 14. The lattice constant of InP is 5.86 Å, and the lattice constant of InGaAs can be 5.65 Å to 6.05 Å depending on the composition. Since the lattice constants are different, lattice mismatch occurs between the semiconductor substrate 10 and the absorption layer 14, and the absorption layer 14 grows including the crosshatch 25. The crosshatch 25 also transfers to the InP layer 16 on the absorption layer 14. The crosshatch 25 appears as grid lines on the surface of the wafer 20. As the absorption layer 14 becomes thicker, so does the cross hatch 25. Such a cross hatch 25 causes cracking of the wafer 20. The crosshatch 25 is generated in addition to the outer peripheral portion 24 of the wafer 20, but tends to be generated more in the outer peripheral portion 24 as shown in FIG. Further, although the cross hatch 25 is shown in a part of the outer peripheral portion 24 in FIG. 2, there is a possibility that the cross hatch 25 may occur on the entire circumference of the outer peripheral portion 24.

As shown in FIG. 1 (b), the InGaAs layer 18 is etched to leave a plurality of island-shaped InGaAs layers 18. The island-shaped InGaAs layer 18 is used as a marker for alignment of masks, reticles, and the like. A resist mask 22 is formed on the upper surface of the InP layer 16 so as to cover the remaining InGaAs layer 18. The end portion of the resist mask 22 is separated from the end portion of the wafer 20 and is located on the center side of the end portion of the wafer 20. The region between the ends is defined as the outer peripheral portion 24, and the width W thereof is, for example, 2 mm. From the experimental results, the width W is preferably 1 mm or more and 2 mm or less. If the width W is less than 1 mm, the effect of suppressing wafer cracking cannot be expected. Further, when the width W is larger than 2 mm, the effect of suppressing the cracking of the wafer is obtained, but the collection rate of the semiconductor element 8 chips in the wafer is reduced. That is, the resist mask 22 does not cover the outer peripheral portion 24 of the wafer 20, and the InP layer 16 is exposed on the outer peripheral portion 24. Further, the step shown in FIG. 1 (b) can also be carried out after FIG. 1 (d) described below. However, in order to accurately form the marker of the island-shaped InGaAs layer 18, it is preferable to carry out in the order of FIG. 1 (b), FIG. 1 (c), and FIG. 1 (d). This is because the marker is formed so as to be aligned with the OF of the wafer 20 shown in FIG. 2 as a reference. That is, when the step shown in FIG. 1 (b) is carried out after FIG. 1 (d), the OF is lost due to etching, so that the alignment at the time of marker formation becomes difficult.

As shown in FIG. 1 (c), the InP layer 16 around the entire circumference of the outer peripheral portion 24 is etched for 60 seconds using, for example, hydrogen bromide (HBr) as a mask with the resist mask 22 as a mask. As a result, the InP layer 16 exposed from the resist mask 22 is removed, and the InGaAs 14 is exposed.

As shown in FIG. 1 (d), for example, a mixture of sulfuric acid, hydrogen peroxide, and water at a ratio of 1: 1: 1 is used as an etchant, and etching is performed for 8 minutes using the resist mask 22 as a mask. The absorption layer 14 is etched on the entire circumference of the outer peripheral portion 24, and the absorption layer 14 exposed from the resist mask 22 is removed. The absorption layer 14 may be completely removed and the buffer layer 12 under the absorption layer 14 may be exposed, or the absorption layer 14 having a thickness of about 1 μm may remain. From the experimental results, it has been confirmed that when the thickness of the absorption layer 14 is 3 μm or more, there is an effect of suppressing wafer cracking even if the thickness remains about 1 μm. By etching the outer peripheral portion 24, the cross hatch 25 is removed together with the absorption layer 14 and the InP layer 16 of the outer peripheral portion 24. In addition to removing the absorption layer 14 on the entire circumference of the outer peripheral portion 24, for example, the OF and IF regions in which the cross hatch 25 is frequently generated may be removed from the outer peripheral portion 24.

The etching in FIGS. 1 (c) and 1 (d) is performed on the entire circumference of the outer peripheral portion 24, that is, the portion completely surrounding the wafer 20. The mask used for the two etchings may be the same mask or different masks may be used. Further, by using a Br-based etchant having a small etching selectivity between InP and InGaAs, both the InP layer 16 and the absorption layer 14 can be etched at once. After etching, the resist mask 22 is removed, and an insulating film (not shown) such as silicon nitride (SiN) is formed on the surface of the wafer 20. As shown in FIG. 1, the etching of the InP layer 16 and the absorption layer 14 is preferably carried out in the initial step of the surface process, but if it is in the process of the surface process, it should be carried out in addition to the initial step. Is possible.

As shown in FIG. 3A, the surface of the wafer 20 on which the absorption layer 14 and the like are provided (the upper surface in FIGS. 1A to 1D and the lower surface in FIG. 3A) is waxed with a spinner. 32 is applied. For example, the glass mounting substrate 30 is placed on a stage (not shown) of the polishing apparatus, and the temperature of the stage is raised to, for example, 150 ° C. The wafer 20 is attached to the mounting substrate 30 using the wax 32.

As shown in FIG. 3B, the wafer 20 is polished from the surface (second surface) opposite to the surface attached to the mounting substrate 30 by using a polishing device. By polishing, the semiconductor substrate 10 of the wafer 20 becomes thin, for example, from 350 μm to about 150 μm.

As shown in FIG. 3C, the n-type electrode 34 is formed by, for example, a vacuum vapor deposition method. The n-type electrode 34 is in contact with the surface of the semiconductor substrate 10 of the wafer 20 and is made by laminating an alloy of gold and germanium (Au-Ge), Au, and titanium (Ti), and has a thickness of, for example, 0.3 μm. be. After forming the n-type electrode 34, heat treatment is performed at 300 ° C. for 2 minutes.

Paraffin paper is laid on a separation device (not shown), and the wafer 20 is placed on it. The wax 32 is melted by heating, and the wafer 20 is adsorbed through the paraffin paper. As shown by an arrow in FIG. 3D, the wafer 20 is removed from the mounting substrate 30 by sliding the mounting substrate 30 with respect to the wafer 20. The separated wafer 20 is washed with an organic solvent such as isopropyl alcohol (IPA) and water, and dicing is performed to cut out a plurality of light receiving elements (semiconductor devices).

According to the first embodiment, the entire circumference of the outer peripheral portion 24 of the wafer 20 is etched to remove the absorption layer 14 of the outer peripheral portion 24, whereby the cross hatch 25 formed on the outer peripheral portion 24 is also removed. As a result, cracking of the wafer 20 starting from the cross hatch 25 can be suppressed. When cracks were confirmed on the 50 wafers 20 according to the first embodiment, none of them were cracked.

The wafer 20 includes a plurality of layers of the semiconductor substrate 10 to the InP layer 16, and stress is generated between them. When the pressure-sensitive adhesive such as wax 32 melts, the stress is released and acts on the wafer 20. When the semiconductor substrate 10 becomes thin due to polishing, the wafer 20 warps due to stress, and the deformation of the outer peripheral portion 24 becomes large. Therefore, if a large number of cross hatches 25 are present on the outer peripheral portion 24, large cracks are likely to occur starting from the crosshatch 25. In Example 1, the crosshatch 25 is removed prior to pasting and melting with the wax 32. As a result, the semiconductor substrate 10 is less likely to crack even when stress is applied. By removing the crosshatch 25 on the outer peripheral portion 24, which is easily affected by warpage, cracking of the semiconductor substrate 10 can be effectively suppressed.

When the absorption layer 14 is thick, many cross hatches 25 are generated, and the stress generated by melting the wax 32 is also large. By thinning the absorption layer 14, the crosshatch 25 and stress can be suppressed. However, thinning the absorption layer 14 may change the characteristics (for example, light receiving sensitivity) of the semiconductor device. According to the first embodiment, since the crosshatch 25 is removed by etching, the absorption layer 14 does not have to be thinned. Therefore, it is possible to suppress cracking of the wafer 20 without affecting the characteristics of the semiconductor device.

Generally, the thickness of the buffer layer 12 and the lattice constant are adjusted in order to suppress the cross hatch 25. For example, the composition of the buffer layer 12 is selected so that the lattice constant of the buffer layer 12 is between the semiconductor substrate 10 and the absorption layer 14, and the lattice constants are close to those of the semiconductor substrate 10 and the absorption layer 14. Therefore, it is preferable to provide the buffer layer 12.

Further, the In composition of the absorption layer 14 can be adjusted to bring the lattice constant closer to the lattice constant of the semiconductor substrate 10. The In composition is adjusted within a range that does not affect the characteristics of the semiconductor device. Etching the outer peripheral portion 24 of Example 1 together with adjusting the compositions of the buffer layer 12 and the absorption layer 14 is effective in suppressing cracking.

The semiconductor included in the wafer 20 may be other than the above. In addition to InP, the buffer layer 12 may be a compound semiconductor such as InGaAs. The semiconductor substrate 10 may be a GaAs substrate, a SiC substrate, or the like, in addition to InP. Further, although the first embodiment is an example of manufacturing a light receiving element from the wafer 20, a semiconductor element other than the light receiving element may be manufactured.

The outer peripheral portion 24 is a region within 2 mm in width from the end portion of the wafer 20. As shown in FIG. 2, since many crosshatch 25s are generated near the end portion, the crosshatch 25 can be effectively removed by etching a region having a width of 2 mm or less. The crosshatch 25 can be removed more effectively by etching the entire circumference of the outer peripheral portion 24. The width of the outer peripheral portion 24 may be changed according to the size of the wafer 20 and the like, and may be, for example, a region having a width of 1 mm or less and a region having a width of 3 mm or less.

As shown in FIG. 3D, the wafer 20 is separated from the mounting substrate 30 by sliding one of the wafer 20 and the mounting substrate 30 with respect to the other. Although not shown, wax 32 remains between the wafer 20 and the mounting substrate 30. By etching the crosshatch 25, cracking of the wafer 20 at the time of separation can be suppressed. An adhesive other than the wax 32 may be used to attach the wafer 20 to the mounting substrate 30.

By completely removing the absorption layer 14 from the outer peripheral portion 24 as shown in FIG. 1 (d), the cross hatch 25 can also be removed, and cracking of the semiconductor substrate 10 can be effectively suppressed. FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a modified example. As in the example of FIG. 4, for example, the absorption layer 14 having a thickness of 1 μm or less may remain on the outer peripheral portion 24. The thickness of the semiconductor substrate 10 after polishing is 100 μm or more, which is much thicker than the remaining absorption layer 14. Therefore, the strength of the semiconductor substrate 10 is high and cracking is suppressed.

In order to increase the strength of the wafer 20, it is conceivable to increase the thickness of the n-type electrode 34. However, dicing of the wafer 20 becomes difficult. According to the first embodiment, cracking of the wafer 20 can be suppressed without thickening the n-type electrode 34.

10 Semiconductor substrate 12 Buffer layer 14 Absorption layer 16 InP layer 18 InGaAs layer 20 Wafer 22 Resist mask 24 Outer circumference 25 Cross hatch 30 Mounting substrate 32 Wafer 34 n-type electrode

Claims (7)

A third semiconductor layer is formed on the first semiconductor layer formed on the first surface of the semiconductor substrate, and the third semiconductor layer is formed.
The step of removing a part of the third semiconductor layer and
After the step of removing a part of the third semiconductor layer, a step of removing the outer peripheral portion of the first semiconductor layer and a step of removing the outer peripheral portion thereof.
After the step of removing the outer peripheral portion of the first semiconductor layer, a step of attaching the first surface of the semiconductor substrate to the mounting substrate using an adhesive, and a step of attaching the first surface to the mounting substrate.
After the step of attaching the semiconductor substrate, a step of thinning the semiconductor substrate from the second surface side opposite to the first surface of the semiconductor substrate, and a step of thinning the semiconductor substrate.
A method for manufacturing a semiconductor device, comprising a step of thinning the semiconductor substrate, a step of melting the pressure-sensitive adhesive, and a step of separating the semiconductor substrate from the mounting substrate. A second semiconductor layer is formed between the first surface of the semiconductor substrate and the first semiconductor layer, and a second semiconductor layer is formed.
The method for manufacturing a semiconductor device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed of compound semiconductors different from each other. The semiconductor substrate and the second semiconductor layer are formed of indium phosphide.
The method for manufacturing a semiconductor device according to claim 2, wherein the first semiconductor layer is made of indium gallium arsenide. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein in the step of removing the outer peripheral portion of the first semiconductor layer, the outer peripheral portion is removed by wet etching. The separation step is any one of claims 1 to 4, which is a step of separating the semiconductor substrate by sliding one of the semiconductor substrate and the mounting substrate with respect to the other after melting the pressure-sensitive adhesive. The method for manufacturing a semiconductor device according to item 1. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein in the step of removing the outer peripheral portion, the first semiconductor layer in the outer peripheral portion is removed to expose the lower layer of the first semiconductor layer. .. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein after the step of removing the outer peripheral portion, the first semiconductor layer having a thickness of 1 μm or less remains on the outer peripheral portion.

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