JP7061510B2 - Manufacturing method and inspection system for silicon carbide semiconductor devices - Google Patents

Description

The present invention relates to a technique for manufacturing a silicon carbide semiconductor device, and more particularly to a technique for manufacturing a silicon carbide semiconductor device having low deterioration over time and excellent reliability.

Since silicon carbide has a higher breaking electric field strength than conventional silicon, the trade-off between withstand voltage and on-resistance of power control semiconductor devices can be significantly improved. In particular, the superiority of silicon carbide is clear in unipolar operating elements such as Schottky barrier diodes and MOS (Metal-Oxide-Semiconductor) transistors, in which the performance of high withstand voltage products deteriorates significantly due to this trade-off. In recent years, vigorous development has been promoted.

However, as is well known, silicon carbide substrates have a wide variety of defects, including micropipes. The micropipe has a hollow cylindrical structure extending in the c-axis direction of the silicon carbide substrate. Since this structure forms a leak path with a PN junction or a MIS (Metal-Insulator-Semiconductor) structure, the withstand voltage of the semiconductor element is significantly deteriorated and becomes a defective product. Also, when an epitaxial layer is formed on the substrate, it is inherited in the epitaxial layer and remains as a leak path. However, depending on the conditions of epitaxial growth, growth also occurs inside the hollow structure, the inner diameter of the micropipe shrinks, and finally it closes and does not reach the outermost surface of the epitaxial layer. This structure is called a closed micropipe. According to Non-Patent Document 1, it has been pointed out that the semiconductor element including the closed micropipe may deteriorate in a long time operation while the leakage current in the initial state is almost the same as that of the normal product. There is.

To take this measure, it is necessary to identify the element containing the closed micropipe by a method other than the leakage current in the initial state. In general, the micropipe propagates in the crystal ingot in the c-axis direction, and one piece taken from the ingot is inspected by etching to determine the specified position as the micropipe. Further, Non-Patent Document 2 describes a method in which an avalanche current is passed by a pulse and a method in which a leak current increases before and after the current is removed. Further, Patent Document 1 discloses a method of etching a surface on the opposite side of a semiconductor element to reveal a micropipe to specify a position and removing the element including the micropipe.

Japanese Unexamined Patent Publication No. 2014-203833

Rupp, R et al., "Influence of Overgrown Micropips in the Active Area of SiC Schottky diodes on long term reliability", Materials Systems. 483-485, p. 925 (2005). Holz, M et al., "Reliability conversations for reliability Infineon SiC diode releases", Microlectronics Reliability 47, p. 1741 (2007).

As a result of the inventor's examination of the above-mentioned conventional method, first, the method using the etch pit position of the same ingot and another wafer does not have sufficient position accuracy due to the different wafers, and the closed micropipe is the invalid region of the semiconductor element. There was a problem that could not be discriminated whether it was in the effective domain or in the effective domain.

In addition, the method of detecting by the leak current change before and after the avalanche is effective when there is a blocked micropipe in the region where the avalanche current flows, but the sensitivity to other regions is relatively low, so there is a problem of detection omission. There is. In the method of etching the opposite surface, crystal defects that do not deteriorate the element characteristics are also etched to form pits. That is, the normal element region is also affected, so a repair process is required.

Therefore, it is required to remove defective chips with blocked micropipes while suppressing the increase in cost and the decrease in throughput.

A preferred aspect of the present invention is a method for manufacturing a semiconductor device having a first silicon carbide substrate and an epitaxial layer formed on the first silicon carbide substrate. In this manufacturing method, the first step of acquiring the defect position information of the epitaxial layer and the second step of acquiring the micropipe position information of the second silicon carbide substrate cut out from the same crystal as the first silicon carbide substrate. A third step of comparing the defect position information of the epitaxial layer with the micropipe position information of the second silicon carbide substrate to determine the micropipe position existing in the epitaxial layer is provided.

Another preferred aspect of the present invention is an inspection system for a semiconductor device having a first silicon carbide substrate and an epitaxial layer formed on the first silicon carbide substrate. This system is equipped with a position information collation calculation unit, and the position information collation calculation unit inputs visual inspection result information including defect position information of the epitaxial layer, and is cut out from the same crystal as the first silicon carbide substrate. Input the ingot defect position information including the micropipe position information of the silicon carbide substrate of 2. Then, after aligning the coordinates of the defect position information and the micropipe position information, it is determined whether the defect position information and the micropipe position information match within a predetermined margin of error, and if there is a match. The position of the micropipe existing in the epitaxial layer is determined based on the defect position information.

It is possible to remove defective chips with blocked micropipes while suppressing cost increase and throughput decrease.

The whole block diagram of the processing system in Example 1. FIG. The flow diagram which shows the process flow and the flow of defect information processing in Example 1. FIG. The figure which shows the minimum structure of the wafer stamping information used in embodiment of this invention. The figure which shows an example of the ingot defect position information database table used in embodiment of this invention. The figure which shows an example of the ingot defect position information composition used in embodiment of this invention. The figure which shows an example of the structure of the visual inspection defect position information used in embodiment of this invention. Schematic transmission perspective view illustrating the structure of a closed micropipe. Schematic transmission plan view showing an example of an image when the surface of a closed micropipe is observed with an optical defect inspection device. The figure which shows an example of the structure of the defective die number information used in embodiment of this invention. Top view showing an example of an effective region of a silicon carbide semiconductor device. The flow diagram which shows the example of the flow of the process performed by the position information collation calculation unit. A conceptual diagram illustrating the concept of processing performed by the position information collation calculation unit. The figure which shows an example of the structure of the non-defective product position information used in embodiment of this invention. The figure which shows an example of the structure of the determination result (GO NO GO) information used in the embodiment of this invention. The flow diagram which shows the process flow and the flow of defect information processing in Example 2. FIG. A scatter plot showing an example of electrical characteristics used in an embodiment of the present invention. The figure which shows an example of the electric characteristic information used in embodiment of this invention. The figure which shows an example of the structure of the chip classification determination result (GO NO GO) information used in the embodiment of this invention. The flow diagram which shows the process flow and the flow of defect information processing in Example 3. FIG. The figure which shows an example of the structure of the die tray correspondence information used in embodiment of this invention.

Hereinafter, preferred embodiments of the present invention will be described. However, the present invention is not limited to the description of the embodiments shown below. It is easily understood by those skilled in the art that a specific configuration thereof can be changed without departing from the idea or purpose of the present invention.

In the configuration of the invention described below, the same reference numerals may be used in common among different drawings for the same parts or parts having similar functions, and duplicate description may be omitted.

When there are a plurality of elements having the same or similar functions, they may be described by adding different subscripts to the same reference numerals. However, if it is not necessary to distinguish between multiple elements, the explanation may be omitted by omitting the subscript.

Notations such as "first", "second", and "third" in the present specification and the like are attached to identify components, and do not necessarily limit the number, order, or contents thereof. is not. Further, the numbers for identifying the components are used for each context, and the numbers used in one context do not always indicate the same composition in the other contexts. Further, it does not prevent the component identified by a certain number from functioning as the component identified by another number.

The position, size, shape, range, etc. of each configuration shown in the drawings and the like may not represent the actual position, size, shape, range, etc. in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the position, size, shape, range and the like disclosed in the drawings and the like.

In one example of this embodiment, first, the approximate micropipe coordinates are determined using the etch pits of the substrate of the same ingot as the substrate for manufacturing. The manufacturing substrate is visually inspected after the positioning mark is prepared in advance, and the defect coordinates that are candidates for the micropipe are determined with high accuracy. If these two coordinates match with the required accuracy, it is determined that there is an obstructed micropipe at the defective coordinate position obtained by the visual inspection, and the die is forcibly made defective.

Since the position of the closed micropipe is accurately determined as a local position in the manufactured semiconductor device, it may be in an invalid region such as on a dicing line and can be ignored, or it may have a serious effect such as an active region. Can be accurately distinguished from the case with. In addition, since the micropipe is detected by etching, it is possible to prevent detection omission. Further, the additional process is only the above-mentioned visual inspection, and does not require an additional process such as etching or polishing or a special inspection process. This makes it possible to remove defective chips with blocked micropipes while minimizing cost increases and throughput reductions.

FIG. 1 is an overall configuration diagram of the silicon carbide semiconductor device manufacturing system of this embodiment. The system includes a management server (1000), an ingot defect information database (116), manufacturing and inspection equipment (1100), and a network (1200) for connecting them to send and receive data and commands.

The management server (1000) includes a processing unit (CPU) (1001), an input / output device (I / O) (1002), and a storage device (MEM) (1003). As the hardware, known general hardware is used. The storage device (1003) stores software for realizing the position information collation calculation unit (117) and the defective die determination unit (118). The operation of each part will be described later.

In this embodiment, the functions such as calculation and control are realized by the processing device (1001) executing the program stored in the storage device (1003) in cooperation with other hardware. Will be done. A program executed by a computer, its function, or a means for realizing the function may be referred to as a "function", a "means", a "part", a "unit", a "module", or the like.

The ingot defect information database (116) is a server for storing and managing various data, and a well-known general hardware is used.

The manufacturing / inspection equipment (1200) is equipment for actually manufacturing, processing, and inspecting ingots and wafers of semiconductor devices. This equipment shall also be equipped with a server (1101) for communicating with the management server (1000) and the ingot defect information database (116). The data obtained in manufacturing, processing, and inspection shall be sent to the management server (1000) and ingot defect information database (116) as needed, and created by the management server (1000) and ingot defect information database (116). The obtained data will be accessible from the manufacturing / inspection facility (1200) as needed.

In the above configuration, we decided to use three servers connected by the network (1200), but it is configured by a single server that is adjacent to or included in the manufacturing / inspection equipment (1200) and does not go through the network (1200). You may. Alternatively, any part of the input device, the output device, the processing device, and the storage device may be composed of four or more servers connected by a network (1200). In addition, the same functions as those configured by software can be realized by hardware such as FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit).

The ingot defect information database (116) stores the correspondence table (1601), ingot defect information (1602), ingot defect position information (1603), defective die number information (1605), and GO / NOGO determination result (1607). Will be done. The server (1101) stores visual inspection result information (1604) and non-defective product index information (1606). The storage location of these information and data is an example, and may be another location as long as it is stored in a location accessible from the device that is the creator or the processor. The information stored in these servers will be described later. Further, the above data structure is also an example, and a plurality of the above data (tables) may be combined into one data (table), or one data may be divided into a plurality of data.

FIG. 2 is a flow chart showing a flow of a non-defective chip sorting process to which this embodiment is applied. With reference to FIGS. 1 and 2, the processing flow of the non-defective chip sorting system to which this embodiment is applied will be described.

First, in the manufacturing / inspection equipment (1100), when the wafer lot is loaded, the ingot symbol (engraving information) engraved on the wafer is read (S101), the wafer lot number (201), the wafer number (202), and the ingot symbol (203). Correspondence table (1601) is created and sent to the ingot defect information database (116) (110). The correspondence table (1601) may be manually input from the input device, or may be automatically generated from the collected data.

FIG. 3 is a table diagram showing an example of the correspondence table (1601). The ingot defect information database (116) generates ingot defect position information (1603) from the ingot defect information (1602) using the ingot symbol (203) in the correspondence table (1601) as a search key, and generates ingot defect position information (1603), and the position information collation calculation unit (117). ) To (114).

FIG. 4 is a table diagram showing an example of ingot defect information (1602). The ingot defect information (1602) is data of the ingot symbol (203), the center coordinate of the etch pit (301), the width of the etch pit (μm), the height of the etch pit (μm), and the area of the etch pit (μm ² ). including.

Here, the ingot defect information (1602) is generated from the result of analysis of the inspection-dedicated wafer cut out from the same ingot as the inserted wafer in the manufacturing / inspection equipment (1200). As an analysis method, first, a wafer dedicated to inspection is etched by known KOH (potassium hydroxide) etching, and micropipes are selectively exposed. By using this method, the micropipe will be expanded as, for example, a hexagonal etch pit that can be easily discriminated from other crystal defects. The position of this etch pit is identified by normal optical microscope observation and stored in the ingot defect information database 116 automatically or manually. Here, the center coordinate (301) is not strictly the information of the defect (micropipe) itself, but the information of the etch pit. The center coordinate (301) can be defined, for example, by the geometric center of gravity point of the planar shape of the etch pit. The center coordinate (301) can be defined as the coordinates on the x-axis and the y-axis defined on the inspection-dedicated wafer. Further, the width and height can also be defined as lengths in the x-axis and y-axis directions.

FIG. 5 is a table diagram showing an example of ingot defect position information (1603). The ingot defect position information (1603) includes data of lot number (201), wafer number (202), center coordinates (301), width (302), height (303), and area (304).

The ingot defect position information (1603) can be easily obtained by searching for information in which the ingot symbol (203) in the correspondence table (1601) and the ingot symbol (203) in the ingot defect information (1602) match. The ingot defect position information (1603) associates the detected etch pit position information with each wafer.

Next, in the manufacturing / inspection equipment (1100), a mark is formed at a position corresponding to the outer shape of the chip by a known photolithography technique and etching technique (S102). Next, the appearance inspection of the flow wafer was carried out based on this mark (S103), and the appearance inspection result information (1604) recording the chip index (501) of the chip having a defect and the defect position offset (502) in the chip was recorded. ) Is generated. The visual inspection result information (1604) is sent to the position information collation calculation unit (117) (111).

FIG. 6 is a table diagram showing an example of visual inspection result information (1604). The visual inspection result information (1604) includes data of lot number (201), wafer number (202), chip index (501), and in-chip defect position offset (502). The chip index (501) specifies the position of the chip in the wafer and the in-chip defect position offset (502) specifies the position of the defect in the chip.

FIG. 7 is a transparent perspective view illustrating the shape of the micropipe to be visually inspected. Since the visual inspection covers the entire effective area of all chips, it is desirable to use an optical defect inspection device from the viewpoint of throughput. The closed micropipe, which is the subject of this embodiment, has a hollow columnar structure abnormal structure (1703) in the substrate (1701), but after the epitaxial layer (7001) is formed, it is deposited on the inner wall of the hollow region during growth. Occurs, forming a cone-shaped cavity (1704) and then closing on the surface side of the epitaxial layer (1705).

FIG. 8 is a plan view illustrating a situation in which etch pits are observed by an optical defect inspection device, and a region defined by C', D', D, and C in FIG. 7 is viewed from the epitaxial layer (7001) side. It is a figure. As described above, since the hollow columnar structure abnormal structure (1703) is closed, the image expected from the hollow structure cannot always be obtained at the time of visual inspection (S103) of the epitaxial layer, and many observation images are obtained. There is only a fine dark spot (8001). The position of such a dark spot (8001) in the chip is recorded as an in-chip defect position offset (502).

In addition to the micropipes, the epitaxial layer (7001) has defects due to abnormal epitaxial growth and abnormal shape of the substrate surface, and normal process foreign substances are also detected as defects. Many of these defects are easy to distinguish from micropipes depending on their shape, but it is difficult to determine those with fine dimensions. Therefore, the visual inspection result information (1604) may include defect coordinates other than the closed micropipe.

Returning to FIG. 2, next, in the position information collation calculation unit (117), the defective die number information (1605) is generated from the ingot defect position information (1603) and the visual inspection result information (1604). The defective die number information (1605) is stored in, for example, the ingot defect information database (116).

FIG. 9 is a table diagram showing an example of defective die number information (1605). Dies determined to be defective by the micropipe are identified by lot number (201), wafer number (202) and chip index (501).

The calculation for obtaining the defective die number information (1605) is basically the center coordinates (301) of the ingot defect position information (1603), the chip index (501) of the visual inspection result information (1604), and the inside of the chip. The coordinates of the defect calculated from the defect position offset (502) are collated, and if they match, the chip index (501) including the coordinates is output. Here, it is necessary to consider the following three points.

First, it is necessary to have an appropriate margin in the range of 0.1 mm to 10 mm for the determination of matching. The center coordinate (301) of the ingot defect position information (1603) is not the position of the defect itself, but the etch pit position as a result of being manifested by etching. Further, since the etch pit analysis is a different wafer from the wafer subjected to the visual inspection (S103), there is a difference within the allowable tolerance in the outer diameter dimension of the wafer and the shape of the positioning flat portion. For these reasons, the two coordinates rarely match perfectly, and it is necessary to have an appropriate margin.

If this margin is taken large, the detection sensitivity will increase but the frequency of false positives will increase, and if it is taken small, the false detection will decrease but the sensitivity will also decrease. The appropriate value depends on the extent to which the initial characteristics of the target chip are affected by the obstructed micropipe. In the case of chips that are sensitive to obstructed micropipes, the side effects of false positives are large, so priority is given to suppressing false positives. In the case of a chip whose initial characteristics are insensitive to the closed micropipe, there is a high risk of overlooking, so improvement in detection sensitivity is prioritized.

Second, when comparing the ingot defect position information (1603) and the appearance inspection result information (1604), the position of the appearance inspection result information (1604) based on the mark on the wafer produced in (S102) is used. It is converted into the coordinates of the ingot defect position information (1603) based on the wafer outer shape. As described above, since the center coordinates (301) of the ingot defect position information (1603) are the position information of the etch pits enlarged by etching, they may be displaced from each other in a plurality of adjacent chip regions. In addition, since the above-mentioned wafer shape difference is also an offset of the coordinate values, there is a risk that the chip index will be erroneously determined near the boundary between adjacent chips. As a result, when the center coordinates (301) of the ingot defect position information (1603) are converted into the chip index (501) of the visual inspection result information (1604) and the defect position offset (502) in the chip and compared, they are overlooked. Occurs. That is, the arithmetic processing is not appropriate.

Third, if the coordinates match and there is no problem in chip operation even if the blocked micropipe exists in the chip effective area, processing is performed so that it is not included in the defective die number information (1605). The region where there is no problem in chip operation is generally the region where a high electric field is not applied.

FIG. 10 is a plan view showing an image of one chip (1901) when viewed from above. As shown in FIG. 10, since the outside of the outermost periphery (1903) of the peripheral termination region is a region having substantially the same potential as the back surface of the chip, the blocked micropipe here is used for defective die number information (1605). Is not included. Conversely, only the region inside (1903) where there is a possibility of a high electric field is output to the defective die number information (1605). This process can be realized by giving the exclusion area information to the position information collation calculation unit according to the chip design, or more preferably by limiting the target of the visual inspection to the inner area where the electric field becomes high (1903).

FIG. 11 is a flow chart showing a specific example of the defective die number information (1605) generation process executed by the position information collation calculation unit (117).

The process (S1101) reads the ingot defect position information (1603), and the process (S1102) reads the appearance inspection result information (1604).

In the process (S1103), data (referred to as "data A") for defining a circle having a radius r from the center coordinates (301) of the ingot defect position information (1603) is created. The radius r is in the range of 0.1 mm to 10 mm, because the actual position of the micropipe does not always match the center coordinates as described above, so it is necessary to have an appropriate margin. .. Instead of defining a circle with radius r, the shape of the etch pit defined from the data of the ingot defect position information (1603) may be used.

In the process (S1104), the position information of the visual inspection result information (1604) is converted into the coordinates of the ingot defect position information (1603) to create data (referred to as “data B” for convenience).

In the process (S1105), the data A and the data B are collated.

FIG. 12 is a conceptual diagram illustrating the concept of collation between data A and data B, and is a diagram in which a part of the wafer is enlarged and observed. The data A is the information obtained from the ingot defect position information (1603), and it can be determined that the micropipe exists in the circle (2201) having the radius r. However, it is uncertain where the micropipe is located within the circle (2201) of radius r.

On the other hand, the data B is information obtained from the visual inspection result information (1604), and includes information on the chip position offset (502), which is the position information of the defect (2202), and the chip index (501) to which the defect belongs. .. Conceptually, as shown in FIG. 12, it may be considered to include the position information of the defect (2202) and the information of the chip boundary (2203). Although the position information of the defect (2202) is highly accurate, it cannot be determined whether the defect is a micropipe.

In the collation determination by the process (S1106) of FIG. 11, when the defect (2202) of the data B overlaps in the circle (2201) of the data A, the chip (die) having the defect position information is set as FAIL. The chip (die) having defect position information is a chip designated by the chip index (501) corresponding to the defect in the visual inspection result information (1604; FIG. 6).

That is, in the lower figure of FIG. 12, the die B becomes FAIL because the defect (2202) of the data B overlaps in the circle (2201) of the data A and has the position information of the defect. Further, the die C does not become FAIL because the defect of the data B overlaps in the circle of the data A but does not have the position information of the defect. On the other hand, the die D becomes FAIL because the defect of the data B overlaps in the circle of the data A and has the position information of the defect. In this way, the ingot defect position information (1603) and visual inspection result information (1604) are used to determine the presence or absence of the micropipe, and the visual inspection result information (1604) is used to determine the position with high accuracy. The position of the micropipe can be determined.

Although the die A in FIG. 12 has the position information of the defect, it does not overlap with the circle (2201) having the radius r, so that the defect of the die A can be presumed to be something other than the micropipe (foreign matter or the like). On the contrary, for a die that does not have the defect position information but has the ingot defect position information (1603), it is conceivable to perform a visual inspection again.

In the process of FIG. 11 (S1107), even if the chip becomes FAIL, the chip whose defect position is outside the outermost periphery of the peripheral termination region is set as PASS. Then, in the process (S1108), the defective die number information (1605) is output. In the above example, the chip that once became FAIL is changed to PASS, but when the original ingot defect position information (1603) or visual inspection result information (1604) is acquired, the acquisition of position information is specified for the chip. It may be limited to the area.

Returning to FIG. 2, the description of the subsequent processing is continued. After the visual inspection (S103), a semiconductor device is formed on the wafer by a known process (S104), and a wafer test step (S105) is performed to inspect whether the desired characteristics are obtained. As a result, good product index information (good product position) (1606) is generated for each die and sent to the defective die determination unit (118) (112).

FIG. 13 is a table diagram showing an example of non-defective product index information (1606). The non-defective product index information (1606) includes data of lot number (201), wafer number (202), chip index (501), and inspection result (701).

The defective die determination unit (118) refers to the defective die number information (1605) generated by the non-defective product index information (1606) and the position information collation calculation unit (117), and uses the non-defective product index information (1606) for the inspection result (1606). 701) is a pass (PASS), but the chip index (501) searches the data registered in the defective die number information (1605). Then, in the non-defective product index information (1606), the inspection result (701) of the die included in the chip index (501) registered in the defective die number information (1605) is rewritten to reject (FAIL). The final GO / NOGO determination result (1607) is generated.

FIG. 14 is an example of the GO / NOGO determination result (1607). The item of the inspection result (701) of the non-defective product index information (1606) in FIG. 11 is corrected by referring to the defective die number information (1605), and becomes the determination result (801). For example, the first line of the non-defective product index information (1606) in FIG. 13 “chip index 05-06 of wafer number 1” is PASS, but the first line of the defective die number information (1605) in FIG. 9 is “wafer number”. Since there is "1 chip index 05-06", the first line of the non-defective product index information (1606) is rewritten from PASS to FAIL to generate the GO / NOGO determination result (1607).

The GO / NOGO determination result (1607) is stored in the ingot defect information database (116) and sent to the defective die marking process (S106) (113), and the defective die is marked with a defective product.

The defective die mark step (S106) is not essential. As another preferred embodiment, there is a method of sending the determination result to the subsequent pickup step (S107) and excluding it from the target chip. As yet another preferred embodiment, the defective die number may be sent to the wafer test step (S105) before the inspection is performed, and a failure determination may be forcibly determined regardless of the inspection result. Further, for the defective die number, it is also a preferred embodiment of the present invention to omit the wafer test (S105) and forcibly determine the failure.

The picked up non-defective chips are subjected to a chip test (S108) as necessary, and defective chips are removed (S109). As a result, the final pass chip is completed.

FIG. 15 illustrates another suitable embodiment of the present invention. Since the process up to the wafer process (104) of this embodiment and the position information collation calculation unit (117) for determining the defective die number are the same as those of the first embodiment, the description thereof will be omitted here. In this embodiment, as compared with Example 1 (FIG. 2), electrical characteristic data is sent (901) instead of sending the non-defective product position to the defective die determination unit (118) (112). Then, a non-defective product is determined from the electrical characteristic data and the defective die number information (1605).

Then, the chip classification determination result is sent to the dicing / pickup step (S107) (902). Therefore, in this embodiment, the chip classification determination result is not reflected in the defective die mark step (S106). That is, the feedback destination of the determination result is a subsequent process from the first embodiment. This is more suitable when the rate of defects is small.

Some dies having closed micropipes have a slight degree of deterioration visible in the wafer test (105) and fall within the range of variation depending on the material and manufacturing process, and cannot be distinguished from ordinary non-defective products.

FIG. 16 is an example of a scatter plot of the inspection value A and the inspection value B of the wafer test. In general, the test value A and the test value B are correlated, and the samples distributed on the diagonal line in FIG. 16 are often normal, and the samples off the diagonal line may be abnormal.

In FIG. 16, small black dots are the results of dies without obstructed micropipes, and white circles are the results of dies containing obstructed mypro pipes. The points indicated by "+" are defective products as a result of the determination by the inspection value B. That is, some of the dies including the micropipes pass the inspection value B. Considering the dependence of the inspection value B on the inspection value A, it is possible to identify the die group (1201) having a large deviation amount, but the die group (1202) having a small deviation amount has a die without a micropipe in the vicinity. Therefore, it cannot be specified only by the inspection values A and B. There is also a group of dies (1203) that are hardly affected by micropipes, and this cannot be identified either. By using the defective die number information (1605), these unidentifiable dies with micropipes can be easily identified.

In this embodiment, the wafer test device sends the electrical characteristics to the defective die determination unit (118), not the pass / fail determination result (901).

FIG. 17 is a table diagram showing an example of electrical characteristic data. The electrical characteristic data (1700) stores the data of the inspection results (1701) and (1702) for the chips specified by the lot number (201), the wafer number (202), and the chip index (501).

The defective die determination unit (118) refers to the defective die number information (1605; FIG. 9) to indicate that (1001) and (1002) are dies containing micropipes and (1003) are dies not included. know. From this result and the deviation from the distribution center of the inspection value, (1001) is a die with a micropipe included in the die group (1201), so performance category Z (defective product) and (1002) are included in the die group (1202). Since it is a die with a micropipe, it is judged to be performance category B (classification that does not ship the product but requires additional detailed inspection), and (1003) is included in the die group (1202) but does not include micropipes, so it is judged to be performance category A. (Fig. 11). In this way, in this embodiment, not only good / bad but also fine classification using inspection values is possible.

FIG. 18 is a table diagram showing an example of the classification determination result (1800) in which the determination result is stored. The data of the determination result (1801) is stored for the chip specified by the lot number (201), the wafer number (202), and the chip index (501).

The classification determination result (1800) is sent to the chip pickup process (S107) and stored in a tray for each classification. If necessary, a chip test (S108) is further performed on this chip to remove defective chips (S109), and a final pass chip is completed.

In the example of FIG. 17, the inspection values are two, A and B, but the present invention is not limited to this, and any number of one or more types can be used. Further, in FIG. 15, the inspection value is exemplified as the one output by the wafer test, but it is also a preferable embodiment of the present invention to refer to the process inspection result included in the wafer process (S104) such as the pattern dimension inspection result, or both. Is. Furthermore, these inspection results do not have to be information specific to the wafer lot to be inspected or individual wafers. For example, it is also a preferable embodiment of the present invention to refer to the average information of all the wafers contained in the same lot, the average information in the lot of the same type inspected most recently, and the like.

In this embodiment, the defective die number information (1605) is applied to the process flow for performing the chip classification (1307) in the chip test (S108).

This will be described with reference to FIG. Here, the steps up to the chip test (S108) and the data processing up to the defective die determination unit (1304) are the same as in the second embodiment (FIG. 15), and thus are omitted.

The defective chip determination unit (1306) first receives the defective die number information (1605; FIG. 9) and the wafer test inspection value (1700; FIG. 17) from the defective die determination unit (1304) as inspection history information (1305). .. This history information is managed by the lot number (201), the wafer number (202), and the chip index (501) in the wafer state.

On the other hand, the result of the chip test (S108) is managed by the ID information (1401) of the tray on which the chip is mounted and the pocket number (1402) in the tray. In order to collate these two types of management information, the die / tray correspondence information is sent from the pickup process (107) to the defective chip determination unit (1306) (1303).

FIG. 20 is a table diagram showing an example of die / tray correspondence information (2000). The die / tray correspondence information (2000) is associated with a wafer number (201), a chip index (501), a tray ID (1401), and a pocket number (1402). The die / tray correspondence information (2000) is usually automatically generated by a device for dicing / pickup.

Based on the die / tray correspondence information (2000), the inspection history information (1305) including the defective die number information (1605) is associated with the tray ID (1401) and the pocket number (1402). The method for determining the chip classification from the chip electrical characteristics (1301) and the defective die number information (1605) included in the inspection history information (1305) is the same as in the second embodiment.

The determination result of the chip classification is sent to the chip classification classification step (S1307) and stored in the tray corresponding to the classification. As a result, the final pass chip is completed.

In the third embodiment, the feedback destination of the determination result is a subsequent process from the second embodiment. This is more suitable when the percentage of defects is even smaller.

As described above, in this embodiment, the high-precision defect positions obtained by performing a visual inspection after forming the position marks corresponding to the completed elements on the silicon carbide substrate and the same ingot as the silicon carbide substrate are used. Using the ingot defect position information obtained by observing the etch pits of the substrate, the position of the blocked micropipe is determined, and the semiconductor chip containing the defect is identified and removed.

This makes it possible to provide a manufacturing method for reliably identifying blocked micropipe defects existing in a silicon carbide epitaxial wafer without affecting manufacturing cost or throughput and removing semiconductor chips containing defects. ..

The present invention is not limited to the above-described embodiment, and includes various modifications. For example, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is possible to add the configuration of another embodiment to the configuration of one embodiment. Further, it is possible to add / delete / replace the configurations of other embodiments with respect to a part of the configurations of each embodiment.

Management server (1000), ingot defect information database (116), manufacturing / inspection equipment (1100), processing device (1001), input / output device (1002), storage device (1003), location information collation calculation unit (117), Defective die determination unit (118)

Claims (15)

A method for manufacturing a semiconductor device having a first silicon carbide substrate and an epitaxial layer formed on the first silicon carbide substrate.
The first step of acquiring the defect position information of the epitaxial layer and
The second step of acquiring the micropipe position information of the second silicon carbide substrate cut out from the same crystal as the first silicon carbide substrate, and
A third step of comparing the defect position information of the epitaxial layer with the micropipe position information of the second silicon carbide substrate to determine the micropipe position existing in the epitaxial layer is provided.
A method for manufacturing a silicon carbide semiconductor device. In the method for manufacturing a silicon carbide semiconductor device according to claim 1 ,
A plurality of the semiconductor devices are arranged and manufactured on the first silicon carbide substrate.
In the first step,
After forming at least one mark that can specify the arrangement of the semiconductor device, the defect position information of the epitaxial layer is acquired.
A method for manufacturing a silicon carbide semiconductor device. In the method for manufacturing a silicon carbide semiconductor device according to claim 1 ,
In the second step,
The micropipe position information is acquired by etching the second silicon carbide substrate to make the micropipe manifest as an etch pit, and regarding the position of the etch pit as the micropipe position of the second silicon carbide substrate. ing,
A method for manufacturing a silicon carbide semiconductor device. In the method for manufacturing a silicon carbide semiconductor device according to claim 2 .
In the first step,
The defect position information of the epitaxial layer is composed of identification information defined so as to be able to identify one of the plurality of semiconductor devices and an offset which is position information in the semiconductor device having the identification information.
A method for manufacturing a silicon carbide semiconductor device. In the method for manufacturing a silicon carbide semiconductor device according to claim 2 .
In the first step,
Acquisition of defect position information of the epitaxial layer is limited to a specific region in the semiconductor device.
A method for manufacturing a silicon carbide semiconductor device. In the method for manufacturing a silicon carbide semiconductor device according to claim 4 .
A method for manufacturing a silicon carbide semiconductor device, which comprises performing a fourth step of outputting defect presence information in which the determined micropipe position is represented by the identification information. In the method for manufacturing a silicon carbide semiconductor device according to claim 1 ,
After the wafer process to form the semiconductor manufacturing equipment, an inspection process including a wafer test and a chip test is performed.
In the inspection process
At least one pass / fail of the chip and the die is judged from both the inspection result acquired in the inspection step and the position of the micropipe existing in the epitaxial layer.
A method for manufacturing a silicon carbide semiconductor device. In the method for manufacturing a silicon carbide semiconductor device according to claim 1 ,
After the wafer process to form the semiconductor manufacturing equipment, an inspection process including a wafer test and a chip test is performed.
In the inspection process
At least one chip performance category of chip and die is assigned from both the inspection result obtained in the inspection process and the micropipe position existing in the epitaxial layer.
A method for manufacturing a silicon carbide semiconductor device. In the method for manufacturing a silicon carbide semiconductor device according to claim 1 ,
In the third step,
When the defect position of the epitaxial layer and the micropipe position of the second silicon carbide substrate match within a predetermined allowable range, the micropipe existing in the epitaxial layer is detected, and the detected micro is according to the defect position of the epitaxial layer. Determine the pipe position,
A method for manufacturing a silicon carbide semiconductor device. In the method for manufacturing a silicon carbide semiconductor device according to claim 9 .
At least one pass / fail or performance classification of chips and dies is performed based on the determined micropipe position.
A method for manufacturing a silicon carbide semiconductor device. In the method for manufacturing a silicon carbide semiconductor device according to claim 9 .
Allows a misalignment of 0.1 mm to 10 mm as the predetermined allowable range,
A method for manufacturing a silicon carbide semiconductor device. An inspection system for a semiconductor device having a first silicon carbide substrate and an epitaxial layer formed on the first silicon carbide substrate.
Equipped with a position information collation calculation unit
The position information collation calculation unit is
The visual inspection result information including the defect position information of the epitaxial layer is input.
The ingot defect position information including the micropipe position information of the second silicon carbide substrate cut out from the same crystal as the first silicon carbide substrate is input.
After aligning the coordinates of the defect position information and the micropipe position information, it is determined whether or not the defect position information and the micropipe position information match within a predetermined margin of error, and the matching ones are found. In some cases, the position of the micropipe existing in the epitaxial layer is determined based on the defect position information.
Inspection system for silicon carbide semiconductor devices. The visual inspection result information is
As the defect position information of the epitaxial layer, an offset indicating the defect position of the epitaxial layer in the die or chip corresponds to the chip index information for specifying the die or chip formed on the first silicon carbide substrate. Including,
The position information collation calculation unit is
Corresponding to the chip index information that identifies the die or chip formed on the first silicon carbide substrate, the defective die information indicating the presence or absence of the micropipe present in the epitaxial layer of the die or chip is output.
The inspection system for a silicon carbide semiconductor device according to claim 12. Including the defective die judgment unit
The defective die determination unit is
Using the defective die information as input,
Corresponding to the chip index information that identifies the die or chip formed on the first silicon carbide substrate, the non-defective index information indicating the inspection result of the die or chip is input.
If the inspection result of the die or chip is good in the non-defective product index information, and if the defective die information indicates that the epitaxial layer of the die or chip has a micropipe, the non-defective product index information corresponds to the relevant product. Outputs the GO / NGO judgment result in which the inspection result of the die or chip is changed from a non-defective product to another type.
The inspection system for a silicon carbide semiconductor device according to claim 13. Allows a misalignment of 0.1 mm to 10 mm as the predetermined tolerance,
The inspection system for a silicon carbide semiconductor device according to claim 12.

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