JP7066382B2 - Semiconductor device, manufacturing method of semiconductor device, trimming method of semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, particularly a semiconductor device whose characteristics can be adjusted by trimming, and a method for manufacturing and trimming the semiconductor device.

A trimming technique for adjusting the characteristics of a semiconductor device after manufacturing is known. As an anti-fuse element used for trimming, a Zener diode is known, which maintains a "non-conducting state" in which current does not flow from the cathode to the anode immediately after manufacturing, and is set to a "conducting state" in which current flows by trimming. (See, for example, Patent Document 1). The Zener diode has a Zener diode portion having an N-type impurity region, a P-type impurity region, and a PN junction, and electrodes (cathode, anode) connected to both ends of the Zener diode portion.

In trimming for such an anti-fuse element (Zener diode), first, a voltage exceeding the withstand voltage of the PN junction of the Zener diode portion is applied in the reverse direction via the above-mentioned electrode. When a voltage exceeding the withstand voltage of the PN junction is applied, the PN junction yields and generates heat. As a result, for example, aluminum, which is a component of the electrode, is melted, and a current flows in the opposite direction from the N-type impurity region to the P-type impurity region. Then, the melted aluminum invades the Zener diode portion from the N-type impurity region. At this time, when the melted aluminum reaches the PN junction via the N-type impurity region, an aluminum filament is formed in the N-type impurity region, and both ends of the Zener diode portion are in a conductive state. ..

Japanese Unexamined Patent Publication No. 2005-183617

By the way, in the Zener diode described in Patent Document 1, the filament formation by aluminum is insufficient at the time of trimming, and it may not reach the PN junction. In such a case, the filament is brought to the PN junction by continuously applying a voltage in the reverse direction exceeding the PN junction withstand voltage multiple times.

However, when aluminum is introduced into the Zener diode portion by applying a voltage a plurality of times, the amount of aluminum contained in the electrode is reduced by that amount, and the electric resistance in the electrode is increased. Therefore, a sufficient current cannot flow, and it becomes difficult for aluminum to reach the PN junction of the Zener diode portion.

Therefore, the Zener diode cannot be reliably set to the "conducting state", and the internal circuit formed in the semiconductor device cannot be adjusted to a desired characteristic.

The present invention has been made in view of the above points, and provides a semiconductor device, a method for manufacturing a semiconductor device, and a trimming method capable of surely adjusting the characteristics of an internal circuit to a desired characteristic by trimming. With the goal.

The semiconductor device according to the present invention is made of an insulating layer formed on a substrate and a semiconductor material, and extends in a first direction along the surface of the substrate and is formed on the insulating layer. 1 so as to cover the conductive portion, the insulating portion that covers the end portion of the first conductive portion in the first direction, the surface of the insulating portion, and the region of the upper surface of the first conductive portion. The second conductive portion extending from the surface of the insulating portion to the region of the upper surface and the region of the upper surface of the second conductive portion facing the region of the upper surface of the first conductive portion are connected. It has a third conductive portion that has been formed.

The method for manufacturing a semiconductor device according to the present invention includes a semiconductor member forming step of forming a first conductive member made of a semiconductor material on an insulating layer formed on a substrate, and an impurity in the first conductive member. An impurity injection step of forming an N-type region and a P-type region in contact with the N-type region by injection, and a first opening for exposing a part of the P-type region and one of the upper surfaces of the N-type region. A step of forming an insulating portion having an insulating portion having a second opening for exposing the portion, a second conductivity on the upper surface of the N-type region exposed by the second opening, and the surface of the insulating portion. The second conductive portion forming step of forming the portion and the third conductive portion forming step of forming the third conductive portion on the upper surface of the region corresponding to the second opening in the second conductive portion. Have.

The method for trimming a semiconductor device according to the present invention is a PN junction portion in contact with an insulating layer formed on a substrate, a P-type semiconductor region, an N-type semiconductor region, the P-type semiconductor region, and the N-type semiconductor region. A first conductive portion extending in the first direction along the surface of the substrate and formed on the insulating layer, and an end of the N-type semiconductor region in the first direction. A first extending from the surface of the insulating portion to the region of the upper surface of the N-type semiconductor region so as to cover the insulating portion covering the portion, the surface of the insulating portion, and the region of the upper surface of the N-type semiconductor region. Formed on the upper surface of the P-type semiconductor region, the second conductive portion, the third conductive portion connected to the region of the upper surface of the second conductive portion facing the region of the upper surface of the N-type semiconductor region, and the upper surface of the P-type semiconductor region. A method for trimming a semiconductor device having a fourth conductive portion, wherein the fourth conductive portion is set to a ground potential, and a voltage exceeding the withstand voltage of the PN junction is applied to the third conductive portion. Apply to.

In the present invention, the first conductive portion made of a semiconductor material as an anti-fuse element is electrically connected to a third conductive portion (electrode) that receives a high voltage during trimming via the second conductive portion. do. The second conductive portion covers the lower region where the lower surface is in contact with a part of the region of the first conductive portion and the upper surface is connected to the third conductive portion, and the end portion of the first conductive portion. It consists of an upper region formed on the surface of the insulating layer to be formed.

According to such a configuration, at the time of trimming, the second conductive portion in contact with the first conductive portion generates heat, the metal contained in the lower region thereof melts and flows into the first conductive portion, and the flowed metal Becomes a filament and sets the first conductive portion in a conductive state. At this time, the metal that has disappeared from the lower region of the second conductive portion is replenished from the upper region of the second conductive portion that exists at a position higher than this lower region. As a result, the thinning of the metal film due to trimming does not occur in the path of the current flowing from the third conductive portion to the first conductive portion at the time of trimming, that is, in the lower region of the second conductive portion. Therefore, since a sufficient amount of metal can penetrate into the first conductive portion, the first conductive portion made of the semiconductor material can be reliably set to the conductive state.

Therefore, according to the present invention, it is possible to surely adjust the characteristics of the internal circuit of the semiconductor device to the desired characteristics by trimming.

It is sectional drawing which shows the cross section of the semiconductor device 100 which concerns on this invention. It is a flow figure which shows the manufacturing procedure of a semiconductor device 100. It is a process sectional view in the lower insulating layer forming process S1. It is a process sectional view in the semiconductor member forming process S2. It is a process sectional view in the impurity injection / patterning process S3. It is a process sectional view in the intermediate insulating layer / first conductive part formation process S4. It is a process sectional view in the opening formation step S5. It is a process sectional view of the 2nd conductive part formation process S6. It is a process sectional view of the upper layer insulating layer formation process S7. It is a process sectional view in the opening formation step S8. It is sectional drawing which shows the state of the semiconductor device 100 at the time of trimming.

Hereinafter, examples of the present invention will be described in detail.

FIG. 1 is a cross-sectional view showing a cross section of the semiconductor device 100 according to the present invention. It should be noted that FIG. 1 is a cross-sectional view showing an excerpt of a region where a Zener diode 20 as an anti-fuse element is formed in the entire region of the semiconductor device 100.

In FIG. 1, a lower insulating layer 11 containing, for example, a silicon oxide is formed on a semiconductor substrate 10 made of, for example, Si (silicon).

On the lower insulating layer 11, a Zener diode 20 as a first conductive portion extending in a first direction along the surface of the semiconductor substrate 10 is formed. The Zener diode 20 includes an N-type silicon region 201 containing N-type impurities, a P-type silicon region 202 containing P-type impurities, and a PN junction 203 formed by the N-type silicon region 201 and the P-type silicon region 202. Have.

An intermediate insulating layer 12 containing, for example, a silicon oxide is formed so as to cover the upper surfaces of the lower insulating layer 11 and the Zener diode 20. However, as shown in FIG. 1, the intermediate insulating layer 12 has a first opening for exposing the region PA on the upper surface of the N-type silicon region 201 and a second opening for exposing the region QA on the upper surface of the P-type silicon region 202. An opening is provided. As shown in FIG. 1, the intermediate insulating layer 12 covers the end portion of the Zener diode 20 in the first direction along the surface of the semiconductor substrate 10.

A metal layer 13a as a second conductive portion is formed on the upper surface region of the N-type silicon region 201 exposed at the first opening and the surface of the intermediate insulating layer 12. As shown in FIG. 1, the metal layer 13a covers the surface fa of the intermediate insulating layer 12 and the region PA on the upper surface of the N-type silicon region 201 from the surface fa of the intermediate insulating layer 12, and the N-type silicon region 201. It extends over the region PA on the upper surface of the. That is, the metal layer 13a includes a region formed on the surface fa of the intermediate insulating layer 12 (hereinafter referred to as an upper region), a region in contact with the N-type silicon region 201 (hereinafter referred to as a lower region), and a region. Consists of.

Further, a metal layer 13b is formed on the upper surface region of the P-type silicon region 202 exposed by the second opening and the surface of the intermediate insulating layer 12. As shown in FIG. 1, the metal layer 13b covers the surface of the intermediate insulating layer 12 and the region QA of the upper surface of the P-type silicon region 202 from the surface of the intermediate insulating layer 12 to the upper surface of the P-type silicon region 202. It extends over the area QA of.

Both the metal layers 13a and 13b include an Al (aluminum) film 131, an upper barrier metal 132 that covers the upper surface of the Al film 131, and a lower barrier metal 133 that covers the lower surface of the Al film 131. ..

As shown in FIG. 1, the upper insulating layer 14 is formed so as to cover the metal layers 13a and 13b.

Further, as shown in FIG. 1, the electrode 15a as the third conductive portion penetrates the upper layer insulating layer 14 and the upper layer barrier metal 132 of the metal layer 13a and is connected to the Al film 131 of the metal layer 13a. There is. That is, as shown in FIG. 1, the electrode 15a is connected to the region of the upper surface of the metal layer 13a facing the region PA described above. Further, the electrode 15b penetrates the upper insulating layer 14 and the upper barrier metal 132 of the metal layer 13b and is connected to the Al film 131 of the metal layer 13b. That is, as shown in FIG. 1, the electrode 15b is connected to the region of the upper surface of the metal layer 13b facing the region QA described above. The metal layer 13b and the electrode 15b form a fourth conductive portion.

As shown in FIG. 1, these electrodes 15a and 15b both have an Al (aluminum) film 151, an upper layer barrier metal 152 covering the upper surface of the Al film 151, and a lower layer barrier covering the lower surface of the Al film 151. Includes metal 153 and. The electrodes 15a and 15b serve as electrodes as anti-fuse elements.

Hereinafter, the manufacturing method of the semiconductor device 100 shown in FIG. 1 will be described along with the manufacturing flow shown in FIG. 2 with reference to the process cross-sectional views shown in FIGS. 3 to 10.

First, the surface of the semiconductor substrate 10 containing silicon is steam-oxidized at, for example, about 900 to 1000 ° C. to form a lower insulating layer 11 containing silicon oxide as a first insulating layer as shown in FIG. 3 ( Lower insulating layer forming step S1).

Next, a polycrystalline polysilicon film 120 is formed on the upper surface of the lower insulating layer 11 by a CVD (Chemical Vapor Deposition) method as shown in FIG. 4 (semiconductor member forming step S2).

Next, the polysilicon film 120 is patterned to a predetermined size by photolithography technology and anisotropic dry etching. Furthermore, using photolithography technology and ion implantation technology, N-type impurities are injected into a part of the polysilicon film 120 patterned to a predetermined size, and P-type impurities are injected into the other parts. Is injected to form the N-type silicon region 201 and the P-type silicon region 202 shown in FIG. 5 (impurity injection / patterning step S3).

Next, by performing a heat treatment at about 900 to 950 ° C., impurities injected into the N-type silicon region 201 and the P-type silicon region 202 are diffused to form the PN junction 203. As a result, the Zener diode portion 20 as the first conductive portion is formed. Then, subsequently, the intermediate insulating layer 12 containing the silicon oxide is formed on the N-type silicon region 201 and the P-type silicon region 202 by the CVD method as shown in FIG. (Intermediate insulating layer / first conductive portion forming step S4).

Next, by photolithography technology, a photoresist is applied to a region on the upper surface of the intermediate insulating layer 12 excluding the region above both ends of the Zener diode portion 20 and the region above the central portion including the PN junction 203. Form. Then, anisotropic dry etching is performed on the intermediate insulating layer 12. As a result, as shown in FIG. 7, the intermediate insulating layer 12 is formed with an opening APa that exposes the upper surface of the N-type silicon region 201 and an opening APb that exposes the upper surface of the N-type silicon region 201. (Opening opening step S5).

Next, by sputtering, the surface of the intermediate insulating layer 12, the upper surface of the N-type silicon region 201 exposed at the opening APa, and the upper surface of the P-type silicon region 202 exposed at the opening APb, for example, Ti ( Barrier metals such as titanium) and TiN (titanium nitride) are deposited. Subsequently, aluminum is deposited by sputtering, and barrier metal is deposited again by sputtering. Then, the three layers of metal deposited in order by the above-mentioned sputtering are patterned by a photolithography technique and a RIE (Reactive Ion Etching) technique. As a result, as shown in FIG. 8, the upper surface of the N-type silicon region 201 and the surface of the intermediate insulating layer 12 are covered with the Al film 131, and the upper barrier metal 132 and the lower layer covering the upper surface and the lower surface of the Al film 131, respectively. A metal layer 13a as a second conductive portion having the barrier metal 133 is formed. Further, a metal having an Al film 131 and an upper barrier metal 132 and a lower barrier metal 133 covering the upper surface and the lower surface of the Al film 131, respectively, over the upper surface of the P-type silicon region 202 and the surface of the intermediate insulating layer 12. The layer 13b is formed (second conductive portion forming step S6).

Next, the upper insulating layer 14 containing the silicon oxide is formed as shown in FIG. 9 by the CVD method (upper insulating layer forming step S7).

Next, the photoresist is formed in the region of the upper surface of the upper insulating layer 14 excluding the region of the recess shown in FIG. 9 by the photolithography technique. That is, a photoresist having an opening that exposes a region included in the surface region of the upper insulating layer 14 facing the opening APa and the opening APb shown in FIG. 7 is formed. Then, anisotropic dry etching is performed on the upper insulating layer 14. As a result, as shown in FIG. 10, the upper insulating layer 14 has an opening OPa that exposes a part of the upper surface region of the metal layer 13a facing the opening APa of the Al film 131, and an Al film in the metal layer 13b. An opening OPb that exposes a part of the upper surface region facing the opening APb of 131 is formed (opening forming step S8).

Next, by sputtering, the surface of the upper insulating layer 14, the upper surface of the Al film 131 of the metal layer 13a exposed at the opening OPa, and the upper surface of the Al film 131 of the metal layer 13b exposed at the opening OPb are formed. , The above-mentioned barrier metal is deposited. Subsequently, aluminum is deposited by sputtering, and barrier metal is deposited again by sputtering. Then, the three layers of metal deposited in order by the above sputtering are patterned by the photolithography technique and the RIE technique.

As a result, as shown in FIG. 1, the Al film 151 connected to the region included in the region facing the above-mentioned region PA on the upper surface of the metal layer 13a and the upper surface and the lower surface of the Al film 151 are each covered. An electrode 15a having an upper layer barrier metal 152 and a lower layer barrier metal 153 is formed as a third conductive portion. Further, as shown in FIG. 1, in the region of the upper surface of the metal layer 13b facing the above-mentioned region QA, the Al film 151, the upper barrier metal 152 and the lower barrier metal 153 covering the upper surface and the lower surface of the Al film 151, respectively. And the electrode 15b having the above is formed (third conductive portion forming step S9).

The method of trimming the Zener diode 20 as the anti-fuse element shown in FIG. 1 will be described below.

First, during non-trimming immediately after the semiconductor device 100 is manufactured, even if a positive electrode voltage is applied to the electrode 15a and a ground potential is applied to the electrode 15b, no current flows through the Zener diode 20. That is, at this time, the Zener diode 20 is set to the "non-conducting state" as an anti-fuse element.

Here, in order to set the Zener diode 20 to the "conducting state", as shown in FIG. 11, a high voltage VD exceeding the PN junction withstand voltage is applied to the electrode 15a by the voltage supply device 400 over a predetermined period. .. As a result, the Zener yields at the PN junction 203 of the Zener diode 20 to generate heat, and the Al film 131 of the metal layer 13a is melted. Then, a part of the Al film 131 penetrates into the N-type silicon region 201, and as shown by the broken line arrow in FIG. 11, a filament extending toward the PN junction 203 of the Zener diode 20 is formed.

When the reverse bias is applied over a predetermined period as described above, a part of the Al film 131, that is, a filament made of melted aluminum reaches the PN junction 203 through the N-type silicon region 201, and the Zener diode 20 Repeat until it becomes "conducting". As a result, a filament extending from the metal layer 13a as the second conductive portion to the PN junction 203 is formed in the N-type silicon region 201.

At this time, the lower region of the metal layer 13a is equal to the amount of aluminum contained in the upper region of the metal layer 13a (the region on the surface fa of the intermediate insulating layer 12) that has penetrated into the N-type silicon region 201. It flows into (the region in contact with the N-type silicon region 201).

Along with this, a cavity Ca is formed in the upper region of the metal layer 13a as shown in FIG. By forming the cavity Ca, as shown in FIG. 11, a section in which the film thickness of the Al film 131 becomes thin is formed in the upper region of the metal layer 13a. In the section where the film thickness of the Al film 131 is thin, the electric resistance is higher than in the other sections.

By the way, in the semiconductor device 100, the electrode 15a that receives the current from the voltage supply device 400 is connected to the lower region of the metal layer 13a that is in contact with the N-type silicon region 201.

Therefore, the current received by the electrode 15a flows into the N-type silicon region 201 without passing through the upper region where the film thickness of the Al film 131 becomes thin. Therefore, at the time of trimming, a sufficient amount of current can be passed from the N-type silicon region 201 to the P-type silicon region 202. As a result, a sufficient amount of aluminum can penetrate into the N-type silicon region 201, so that the anti-fuse element (Zener diode 20) can be reliably set to the “conducting state”.

As described above, in the semiconductor device 100, the N-type silicon region 201 of the Zener diode 20 and the electrode 15a that receives the supply of the high voltage VD at the time of trimming are electrically connected via the metal layer 13a. Here, the lower surface of the metal layer 13a is in contact with the N-type silicon region 201, the lower region in which the electrode 15a is formed on the upper surface thereof, and the surface of the intermediate insulating layer 12 that covers the end portion of the Zener diode 20. It consists of an upper region formed in.

Therefore, according to such a configuration, at the time of trimming, the metal layer 13a in contact with the N-type silicon region 201 generates heat, and the metal contained in the lower region thereof, for example, aluminum, melts and flows into the N-type silicon region 201. At this time, the amount of aluminum lost from the lower region of the metal layer 13a is replenished from the upper region of the metal layer 13a existing at a position higher than this lower region. As a result, the thinning of the Al film due to trimming does not occur in the path of the current flowing from the electrode 15a to the N-type silicon region 201, that is, in the lower region of the metal layer 13a. Therefore, since a sufficient amount of aluminum can penetrate into the N-type silicon region 201, the Zener diode 20 can be reliably set to the “conducting state”.

In the above embodiment, the Al film 131 coated with the upper barrier metal 132 and the lower barrier metal 133 is used as the metal layers 13a and 13b, but instead of the Al film, for example, Au (gold) or Ag. A metal film made of (silver) or Cu (copper) may be adopted.

Further, in the embodiment shown in FIG. 1, the electrode 15a and the electrode 15b having the same shape as the metal layer 13a are configured to be supplied to the P-type silicon region 202 of the Zener diode 20 at the time of trimming by receiving the ground potential. The metal layer 13b is adopted. However, the aluminum in the metal layer 13b does not invade the P-type silicon region 202 at the time of trimming. Therefore, the shape of the metal layer 13b and the position of the metal layer 13b to which the electrode 15b is connected are not limited.

In short, the semiconductor device 100 may have any of the following first to third conductive portions and an anti-fuse element including an insulating portion.

That is, the first conductive portion (201 to 203) is made of a semiconductor material (for example, silicon) and extends in the first direction along the surface of the substrate (10) and is formed on the insulating layer (11). ing. The insulating portion (12) covers the end portion of the first conductive portion in the first direction. The second conductive portion (13a) covers a region from the surface of the insulating portion to the upper surface of the first conductive portion so as to cover the surface of the insulating portion (12) and the region (PA) on the upper surface of the first conductive portion. It is extended over. The third conductive portion (15a) is connected to a region on the upper surface of the second conductive portion (13a) facing the region (PA) on the upper surface of the first conductive portion.

11 Lower insulating layer 12 Intermediate insulating layer 13a Metal layer 15a Electrode 20 Zener diode 131 Al film 201 N-type silicon region 202 P-type silicon region 203 PN junction

Claims (14)

The insulating layer formed on the substrate and
A PN junction formed on the insulating layer and extending in a first direction along the surface of the substrate, in contact with the P-type semiconductor region , the N-type semiconductor region , the P-type semiconductor region, and the N-type semiconductor region. The first conductive part, which is a Zener diode consisting of parts,
An insulating portion formed on the upper surface of the first conductive portion and having an opening that exposes a part of the upper surface of the N-type semiconductor region of the first conductive portion .
A second conductive portion made of a metal that covers the surface of the insulating portion and the opening of the insulating portion and extends from the surface of the insulating portion to the region of the upper surface of the N-type semiconductor region.
It has a third conductive portion formed on the upper surface of the second conductive portion and connected to the second conductive portion .
The second conductive portion includes a first region formed on the upper surface of the N-type semiconductor region and a second region formed on the surface of the insulating portion and having a height position higher than that of the first region.
The semiconductor device, characterized in that the third conductive portion is in contact with only a part of the first region of the second conductive portion . The semiconductor device according to claim 1, wherein a voltage supply device is connected to the third conductive portion. The semiconductor device according to claim 1 or 2, wherein the semiconductor device includes a fourth conductive portion formed on the upper surface of the P-type semiconductor region. Claims 1 to 1, wherein a filament extending from the second conductive portion to the PN junction is formed in the N-type semiconductor region by trimming by applying a voltage to the third conductive portion. 3. The semiconductor device according to any one of 3. The second conductive portion is
A barrier metal in contact with a region of the surface of the insulating portion and the upper surface of the first conductive portion,
The semiconductor device according to any one of claims 1 to 4, further comprising a metal film formed on the barrier metal. The semiconductor device according to claim 5, wherein the metal film is aluminum. The insulating layer formed on the substrate and
A first conductive portion which is a Zener diode composed of a P-type semiconductor region, an N-type semiconductor region, the P-type semiconductor region, and a PN junction in contact with the N-type semiconductor region formed on the insulating layer.
An insulating portion having a first opening for exposing a part of the upper surface of the N -type semiconductor region and a second opening for exposing a part of the upper surface of the P -type semiconductor region.
A region formed from the upper surface of the N-type semiconductor region exposed by the first opening to the surface of the insulating portion on the peripheral edge of the first opening and corresponding to the first opening on the upper surface. The second metal layer in which the recess was formed , and
A semiconductor device comprising: a third metal layer that is in electrical contact with the second metal layer only in a part of a region of the bottom surface of the recess of the second metal layer. The insulating film formed on the substrate and
A first conductive portion, which is a Zener diode made of a semiconductor material and extending in a first direction along the surface of the substrate.
A first insulating portion formed on the upper surface of the first conductive portion and having an opening that exposes a part of the upper surface of the first conductive portion.
It covers the surface of the first insulating portion and the opening of the first insulating portion, extends from the surface of the first insulating portion to the upper surface of the first conductive portion, and is formed of metal. The second conductive part that was made,
A second insulating portion that covers a part of the upper surface of the second conductive portion, and a second insulating portion.
It has a third conductive portion formed on the upper surface of the second conductive portion and connected to the second conductive portion .
The second conductive portion is formed on a first region formed on the upper surface of the first conductive portion and a second region formed on the surface of the first insulating portion and having a higher height position than the first region. Including and
A semiconductor device characterized in that the third conductive portion is in contact with only a part of the first region of the second conductive portion . The semiconductor device according to claim 8, wherein the third conductive portion is formed on the second region of the second conductive portion via the second insulating portion. A semiconductor member forming step of forming a first conductive member made of a semiconductor material on an insulating layer formed on a substrate,
An impurity injection step of forming an N-type region and a P-type region in contact with the N-type region by injecting an impurity into the first conductive member to form a first conductive portion which is a Zener diode .
An insulating portion having a first opening for exposing a part of the upper surface of the N -shaped region and a second opening for exposing a part of the upper surface of the P -shaped region on the upper surface of the first conductive portion. Insulation part forming process to form
A second conductive portion made of metal that covers the surface of the insulating portion and the first opening of the insulating portion and extends from the surface of the insulating portion to the region of the upper surface of the N-shaped region. The process of forming the second conductive portion to be formed and
It has a third conductive portion forming step of forming a third conductive portion on the upper surface of the second conductive portion .
In the second conductive portion forming step, the second conductive portion is formed on the surface of the first region and the insulating portion formed on the upper surface of the first conductive portion, and is located at a height higher than the first region. The second region with a high value is formed so as to be continuous,
A method for manufacturing a semiconductor device, characterized in that , in the third conductive portion forming step, the third conductive portion is formed so as to be in contact with only a part of the first region of the second conductive portion . The method for manufacturing a semiconductor device according to claim 10, wherein the second conductive portion forming step further includes a step of forming a conductive portion on the upper surface of the P-shaped region exposed by the second opening. .. In the second conductive portion forming step,
10 . The method for manufacturing a semiconductor device according to the above. The method for manufacturing a semiconductor device according to claim 12, wherein the metal film is made of aluminum. The insulating layer formed on the substrate and
A PN junction formed on the insulating layer and extending in a first direction along the surface of the substrate, in contact with the P-type semiconductor region, the N-type semiconductor region, the P-type semiconductor region, and the N-type semiconductor region. The first conductive part, which is a Zener diode consisting of parts,
An insulating portion formed on the upper surface of the first conductive portion and having an opening that exposes a part of the upper surface of the N-type semiconductor region of the first conductive portion.
It covers the surface of the insulating portion and the opening of the insulating portion, extends from the surface of the insulating portion to the region of the upper surface of the N-type semiconductor region, and is formed on the upper surface of the N-type semiconductor region. A second conductive portion made of a metal including a first region and a second region formed on the surface of the insulating portion and having a height position higher than that of the first region .
A third conductive portion connected only to a part of the first region of the second conductive portion, and a third conductive portion.
A method for trimming a semiconductor device having a fourth conductive portion formed on the upper surface of the P-type semiconductor region.
The fourth conductive portion is set to the ground potential, and the fourth conductive portion is set to the ground potential.
A method for trimming a semiconductor device, which comprises applying a voltage exceeding the withstand voltage of the PN junction to the third conductive portion.

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