JP7067103B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
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- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
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- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
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Description
図1は、実施の形態にかかるパワー半導体モジュールを示す側面図である。パワー半導体モジュールは、パワー半導体チップ(不図示)を内部に有する封止部1と、パワー半導体チップと接続され、封止部1から外部に立設する接続端子3と、接続端子3に設けられた台座2とを備える。
図6は、実施例にかかるパワー半導体モジュールの根本部の高さとガイド部の高さを示す表である。この表は、実施例1~実施例3における根本部21の高さbと、ガイド部22の高さaと、それぞれの和a+bの値を示し、単位はmmである。ここで、実施例1は、a/(a+b)が、0.05以上0.50以下の例であり、実施例2は、より好ましい0.10以上0.30以下の例であり、実施例3は、さらに好ましい0.15以上0.25以下の例である。
2、102 台座
3、103 接続端子
4、104 配線板
6、106 平坦部
7、107 スルーホール
11 締結部
21 根本部
211 上部根本部
212 下部根本部
22 ガイド部
Claims (6)
- 半導体素子を内部に有する封止部と、
前記半導体素子と電気的に接続され、前記封止部から外部に立設する接続端子と、
前記接続端子に設けられた台座と、
を備え、
前記台座は、前記封止部に設けられた根本部と、前記根本部上に設けられた傾斜部を有するガイド部と、からなり、
前記根本部が前記封止部の表面となす角度は、前記傾斜部が前記根本部の表面となす角度以上であることを特徴とする半導体装置。 - 前記ガイド部の上面に平坦部が設けられていないことを特徴する請求項1に記載の半導体装置。
- 前記傾斜部が前記根本部の表面となす角度は、30°より大きく、90°より小さいことを特徴とする請求項1または2に記載の半導体装置。
- 前記根本部が前記封止部の表面となす角度は、30°より大きく、90°以下であることを特徴とする請求項1~3のいずれか一つに記載の半導体装置。
- 前記傾斜部の高さと前記根本部の高さとの和に対する前記傾斜部の高さの比は、0.05以上で0.50未満であることを特徴とする請求項1~4のいずれか一つに記載の半導体装置。
- 半導体素子と電気的に接続された接続端子を立設する第1工程と、
樹脂を注入し、前記半導体素子を内部に封入し、前記接続端子に、前記樹脂上の根本部と、前記根本部上の傾斜部を有するガイド部と、からなる台座を形成する第2工程と、
を含むことを特徴とする半導体装置の製造方法。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018024562A JP7067103B2 (ja) | 2018-02-14 | 2018-02-14 | 半導体装置および半導体装置の製造方法 |
| US16/241,099 US10966322B2 (en) | 2018-02-14 | 2019-01-07 | Semiconductor device and manufacturing method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018024562A JP7067103B2 (ja) | 2018-02-14 | 2018-02-14 | 半導体装置および半導体装置の製造方法 |
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| Publication Number | Publication Date |
|---|---|
| JP2019140334A JP2019140334A (ja) | 2019-08-22 |
| JP7067103B2 true JP7067103B2 (ja) | 2022-05-16 |
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| JP2018024562A Active JP7067103B2 (ja) | 2018-02-14 | 2018-02-14 | 半導体装置および半導体装置の製造方法 |
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| JP (1) | JP7067103B2 (ja) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013145619A1 (ja) | 2012-03-28 | 2013-10-03 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
| JP2016174112A (ja) | 2015-03-18 | 2016-09-29 | 日立オートモティブシステムズ株式会社 | 電子制御装置 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS511592B2 (ja) | 1971-08-27 | 1976-01-19 | ||
| JPS5222880A (en) * | 1975-08-15 | 1977-02-21 | Nippon Telegr & Teleph Corp <Ntt> | Integrated circuit package |
| US4677526A (en) * | 1984-03-01 | 1987-06-30 | Augat Inc. | Plastic pin grid array chip carrier |
| US6896526B2 (en) * | 1999-12-20 | 2005-05-24 | Synqor, Inc. | Flanged terminal pins for DC/DC converters |
| KR101463075B1 (ko) * | 2008-02-04 | 2014-11-20 | 페어차일드코리아반도체 주식회사 | 히트 싱크 패키지 |
| JP5101592B2 (ja) | 2009-12-03 | 2012-12-19 | 三菱電機株式会社 | パワーモジュールの製造方法 |
| US9119327B2 (en) * | 2010-10-26 | 2015-08-25 | Tdk-Lambda Corporation | Thermal management system and method |
| EP2908338A4 (en) | 2012-10-15 | 2016-07-13 | Fuji Electric Co Ltd | SEMICONDUCTOR COMPONENT |
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- 2018-02-14 JP JP2018024562A patent/JP7067103B2/ja active Active
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013145619A1 (ja) | 2012-03-28 | 2013-10-03 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
| JP2016174112A (ja) | 2015-03-18 | 2016-09-29 | 日立オートモティブシステムズ株式会社 | 電子制御装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20190254167A1 (en) | 2019-08-15 |
| US10966322B2 (en) | 2021-03-30 |
| JP2019140334A (ja) | 2019-08-22 |
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