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JP7068380B2 - How to make a dresser - Google Patents
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JP7068380B2 - How to make a dresser - Google Patents

How to make a dresser Download PDF

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Publication number
JP7068380B2
JP7068380B2 JP2020082197A JP2020082197A JP7068380B2 JP 7068380 B2 JP7068380 B2 JP 7068380B2 JP 2020082197 A JP2020082197 A JP 2020082197A JP 2020082197 A JP2020082197 A JP 2020082197A JP 7068380 B2 JP7068380 B2 JP 7068380B2
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Japan
Prior art keywords
wafer
dresser
chip
chip portion
manufacturing
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JP2020123751A (en
Inventor
貴彦 川崎
之輝 松井
聡文 側瀬
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Kioxia Corp
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Kioxia Corp
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  • Mechanical Treatment Of Semiconductor (AREA)
  • Grinding-Machine Dressing And Accessory Apparatuses (AREA)
  • Chemical Vapour Deposition (AREA)

Description

本発明の実施形態は、ドレッサーの製造方法に関する。 Embodiments of the present invention relate to a method of manufacturing a dresser.

半導体装置の製造プロセスにおいて、溝に埋め込まれた絶縁膜、金属膜、多結晶ケイ素
膜等を平坦化するための技術として化学機械研磨(Chemical Mechanic
al Polishing:CMP)が知られている。CMPでは、繰り返しの研磨に伴
い研磨パッドの表面が変形し研磨能力が低下するため、この低下を抑制するために一定時
間毎にドレッサーを用いて研磨パッドをドレッシングする。
Chemical Mechanical Polishing (Chemical Mechanical) as a technique for flattening insulating films, metal films, polycrystalline silicon films, etc. embedded in grooves in the manufacturing process of semiconductor devices.
al Polishing (CMP) is known. In CMP, the surface of the polishing pad is deformed with repeated polishing and the polishing ability is lowered. Therefore, in order to suppress this deterioration, the polishing pad is dressed with a dresser at regular intervals.

特開平10-71559号公報Japanese Unexamined Patent Publication No. 10-71559 特表2014-522739号公報Japanese Patent Publication No. 2014-522739

本実施形態が解決しようとする課題は、高生産性に優れたドレッサーの製造方法を提供
する。
The problem to be solved by this embodiment is to provide a method for manufacturing a dresser having excellent high productivity.

実施形態のドレッサーの製造方法は、Siウエハ上にSiとOを含む膜を形成し、Si
とOを含む膜上にレジスト膜を形成し、SiとOを含む膜とレジスト膜を円形状にパター
ニングし、パターニング後のSiとOを含む膜とレジスト膜をマスクにして、Siウエハ
をエッチングすることにより、Siウエハに突起を形成し、突起を有するSiウエハをダ
イシングにより個片化してチップ部を形成し、チップ部の突起上にダイヤモンド薄膜層を
形成し、台金上にダイヤモンド薄膜層が形成されたチップ部を設けることにより形成され
る。
In the method of manufacturing a dresser of the embodiment, a film containing Si and O is formed on a Si wafer, and Si is formed.
A resist film is formed on the film containing Si and O, and the film containing Si and O and the resist film are puttered in a circular shape.
Si wafer by masking the film containing Si and O after patterning and the resist film.
By etching, a protrusion is formed on the Si wafer, and the Si wafer having the protrusion is formed.
The chip part is formed by individualizing by icing, and a diamond thin film layer is formed on the protrusion of the chip part.
It is formed by forming and providing a chip portion on which a diamond thin film layer is formed on a base metal .

第1の実施形態に係るドレッサーを説明する図。The figure explaining the dresser which concerns on 1st Embodiment. 図1のチップ部の詳細を説明する図。The figure explaining the details of the chip part of FIG. 第1及び第2の実施形態のチップ部の製造方法を説明する図。The figure explaining the manufacturing method of the chip part of 1st and 2nd Embodiment. 第1及び第2の実施形態のチップ部の製造方法を説明する図。The figure explaining the manufacturing method of the chip part of 1st and 2nd Embodiment. マスクの平面図。Top view of the mask. 第1の実施形態に係るドレッサーの製造方法を説明する図。The figure explaining the manufacturing method of the dresser which concerns on 1st Embodiment. ドレッサー1を用いた具体例を示す図。The figure which shows the specific example using the dresser 1. 第2の実施形態に係るドレッサーを説明する図。The figure explaining the dresser which concerns on 2nd Embodiment. 第2の実施形態に係るドレッサーの製造方法を説明する図。The figure explaining the manufacturing method of the dresser which concerns on 2nd Embodiment.

以下、発明を実施するための実施形態について説明する。 Hereinafter, embodiments for carrying out the invention will be described.

(第1の実施形態)
第1の実施形態に係るドレッサーについて図1乃至図7を参照して説明する。なお、以
下の図面の記載において、同一な部分には同一の符号で表している。ただし、図面は厚さ
と平面寸法との関係、比率等は現実のものとは異なり、模式的なものである。
(First Embodiment)
The dresser according to the first embodiment will be described with reference to FIGS. 1 to 7. In the description of the following drawings, the same parts are represented by the same reference numerals. However, in the drawings, the relationship between the thickness and the plane dimensions, the ratio, etc. are different from the actual ones and are schematic.

第1の実施形態に係るドレッサー1の構成を図1及び図2を用いて説明する。図1は本
実施形態のドレッサー1の作用面を示す平面模式図である。なお、作用面とは例えば研磨
パッド等のドレッシング対象物と対向する面のことである。
The configuration of the dresser 1 according to the first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a schematic plan view showing the working surface of the dresser 1 of the present embodiment. The working surface is a surface facing a dressing object such as a polishing pad.

図1に示すように、ドレッサー1の作用面は台金10上に複数のチップ部20を有する
。台金10は例えばステンレス(SUS)や鉄を含むがその材料は特に限定されない。チ
ップ部20はたとえばSiウエハ(Si基板)より形成される。チップ部20の大きさは
例えば、1mm~50mmであるが、本実施形態においてチップ部20の大きさは特に限
定されない。また、本実施形態のドレッサー1のチップ部20の数も特に限定されないが
、チップ部20が複数個あることで均一にドレッシングされやすくなる。
As shown in FIG. 1, the working surface of the dresser 1 has a plurality of chip portions 20 on the base metal 10. The base metal 10 includes, for example, stainless steel (SUS) and iron, but the material thereof is not particularly limited. The chip portion 20 is formed of, for example, a Si wafer (Si substrate). The size of the chip portion 20 is, for example, 1 mm to 50 mm, but the size of the chip portion 20 is not particularly limited in the present embodiment. Further, the number of chip portions 20 of the dresser 1 of the present embodiment is not particularly limited, but the presence of a plurality of chip portions 20 facilitates uniform dressing.

次にチップ部20の詳細について説明する。図2(a)はチップ部20の平面模式図、
図2(b)は図2(a)のA-A‘断面を示す断面模式図である。
Next, the details of the chip portion 20 will be described. FIG. 2A is a schematic plan view of the chip portion 20.
FIG. 2B is a schematic cross-sectional view showing a cross section taken along the line AA'of FIG. 2A.

図2(a)、(b)に示すように、チップ部20は基板21と基板21上の複数の突起
22とを有する。突起22は例えば半径0.15mm程度の円錐形状を有する。チップ部
20において、1つのチップ部20内にできるだけ多くの突起22を形成するために突起
22は例えばハニカム状に並んでいる。突起22は例えばSiを含み、基板21と一体化
している。図2(b)に示すように、突起22上にはダイヤモンド薄膜層23が形成され
ている。ダイヤモンド薄膜層23は突起22及び突起22から露出した基板21を含むチ
ップ部20の全面に亘って形成される。また、ダイヤモンド薄膜層23の厚みは略均一に
形成されている。なお、チップ部20における突起22の配置は図2のように限定されな
い。
As shown in FIGS. 2A and 2B, the chip portion 20 has a substrate 21 and a plurality of protrusions 22 on the substrate 21. The protrusion 22 has, for example, a conical shape having a radius of about 0.15 mm. In the chip portion 20, the projections 22 are arranged in a honeycomb shape, for example, in order to form as many projections 22 as possible in one chip portion 20. The protrusion 22 contains, for example, Si and is integrated with the substrate 21. As shown in FIG. 2B, a diamond thin film layer 23 is formed on the protrusion 22. The diamond thin film layer 23 is formed over the entire surface of the chip portion 20 including the protrusions 22 and the substrate 21 exposed from the protrusions 22. Further, the thickness of the diamond thin film layer 23 is formed to be substantially uniform. The arrangement of the protrusions 22 on the tip portion 20 is not limited as shown in FIG.

次に、図3乃至図6を用いて、本実施形態のチップ部及びドレッサーの製造方法につい
て説明する。
Next, a method of manufacturing the chip portion and the dresser of the present embodiment will be described with reference to FIGS. 3 to 6.

図3及び図4はSiウエハの一部の領域を示す断面模式図である。なお、以下の製造方
法においてSiウエハ内の位置による偏り等は無く、ウエハ全面に亘り略均一な構造に形
成されるものとする。
3 and 4 are schematic cross-sectional views showing a part of a region of a Si wafer. In the following manufacturing method, there is no bias due to the position in the Si wafer, and the structure is formed to be substantially uniform over the entire surface of the wafer.

図3(a)に示すように、まずSiウエハを用意する。Siウエハ上に下地膜30をCV
D(Chemical Vapor Deposition)法を用いて形成する。下地
膜30は、例えば500nm程度のTEOS膜である。本実施形態では、Siウエハは半
導体製造プロセスにおいて一般的に用いられ、低価格で一定の硬度を有するため適してい
る。特に面方位が(111)面のSiウエハ(Si(111))は、結晶面方位が??って
いるためビッカーズ硬度(Gpa)が高く(例えば、10.6Gpa以上)、より適して
いる。さらには、他の高硬度材料と比較して熱膨張係数がダイヤモンドと同程度(例えば
2.56×10‐6/K以下)なため適している。なお、Si(111)とは結晶内でS
i間の距離が等しくなるような原子配列を有する構造のことを言う。
As shown in FIG. 3A, first, a Si wafer is prepared. CV the base film 30 on the Si wafer
It is formed by using the D (Chemical Vapor Deposition) method. The undercoat film 30 is, for example, a TEOS film having a size of about 500 nm. In this embodiment, the Si wafer is generally used in the semiconductor manufacturing process, and is suitable because it has a constant hardness at a low price. In particular, a Si wafer having a (111) plane orientation (Si (111)) has a high Vickers hardness (Gpa) (for example, 10.6 Gpa or more) because the crystal plane orientation is different, and is more suitable. Furthermore, it is suitable because it has a coefficient of thermal expansion comparable to that of diamond (for example, 2.56 × 10-6 / K or less) as compared with other high-hardness materials. In addition, Si (111) is S in the crystal.
It refers to a structure having an atomic arrangement such that the distances between i are equal.

次に、図3(b)に示すように下地膜30上にレジスト膜40を形成する。レジスト膜
40は例えばi線用レジスト膜である。その後例えば図5に示すようなマスクを介して例
えばi線によってレジスト膜を露光する。ただし、波長等は特に限定されない。
Next, the resist film 40 is formed on the undercoat film 30 as shown in FIG. 3 (b). The resist film 40 is, for example, an i-line resist film. Then, for example, the resist film is exposed by, for example, i-line through a mask as shown in FIG. However, the wavelength and the like are not particularly limited.

次に、図3(c)に示すように、露光されたレジスト膜40を現像した後、ドライエッ
チングによってレジスト膜40をマスクに下地膜30を略垂直にエッチングする。この時
、例えばCF4ガス等を用いる。
Next, as shown in FIG. 3C, after developing the exposed resist film 40, the undercoat film 30 is etched substantially vertically with the resist film 40 as a mask by dry etching. At this time, for example, CF4 gas or the like is used.

次に、図3(d)に示すように、Siウエハのエッチングを行う。例えば、SF6=7
0secm、C4F8=200sccm、O2=500sccmの混合ガスを用いてエッチ
ングを行う。同条件下でさらにエッチングを進めると、図4(a)に示すように、Siウ
エハの上端が角の円錐形状に近づく。同時に、レジスト膜40及び下地膜30の大きさも
縮小していく。最終的には、Siウエハに複数の円錐状の突起22が形成される(図4(
b))。縮小したレジスト膜40及び下地膜30は突起22間に落下する。
Next, as shown in FIG. 3D, the Si wafer is etched. For example, SF6 = 7
Etching is performed using a mixed gas of 0 secm, C4F8 = 200 sccm, and O2 = 500 sccm. When the etching is further advanced under the same conditions, the upper end of the Si wafer approaches the conical shape of the corner as shown in FIG. 4 (a). At the same time, the sizes of the resist film 40 and the undercoat film 30 are also reduced. Eventually, a plurality of conical protrusions 22 are formed on the Si wafer (FIG. 4 (FIG. 4).
b)). The reduced resist film 40 and the base film 30 fall between the protrusions 22.

次に、アッシャー又はNH4OH洗浄等によって縮小したレジスト膜40及び下地膜3
0を除去する。以上の工程により、例えば円錐形状等の所望の形状の突起が形成されたS
iウエハが得られる。
Next, the resist film 40 and the undercoat film 3 reduced by Usher or NH4OH cleaning or the like.
Remove 0. By the above steps, a protrusion having a desired shape such as a conical shape is formed.
i-wafer is obtained.

次に、上述した複数の円錐形状の突起22が形成されたSiウエハを個片化するため、
所望のサイズにダイシングし、ベースプレートとなるチップ部20を得る(図6(a))。
チップ部20は例えば、300mmウエハの場合160チップ以上、200mmウエハの
場合70チップ以上取得可能であるが、チップ数は特に限定されない。
Next, in order to individualize the Si wafer on which the plurality of conical protrusions 22 described above are formed,
Dicing to a desired size obtains a chip portion 20 to be a base plate (FIG. 6 (a)).
For example, the chip portion 20 can acquire 160 chips or more in the case of a 300 mm wafer and 70 chips or more in the case of a 200 mm wafer, but the number of chips is not particularly limited.

次に、チップ部20上にダイヤモンド薄膜層23を形成する。ダイヤモンド薄膜層23
は、例えばプラズマCVD法を用い、減圧容器の中に設けられる接地した陽極上にチップ
部20を置いて800度に加熱する。その後メタンと水素の混合気体を減圧下に流入させ
、陰極に直流1000V程度をかけ、異常グロー放電を行うことにより形成される。なお
、上記の形成方法は一例である。上記のようにして、ダイヤモンド薄膜層23が形成され
た突起22を有するチップ部20を得る。
Next, the diamond thin film layer 23 is formed on the chip portion 20. Diamond thin film layer 23
For example, using a plasma CVD method, a chip portion 20 is placed on a grounded anode provided in a decompression container and heated to 800 degrees. After that, a mixed gas of methane and hydrogen is made to flow under reduced pressure, a direct current of about 1000 V is applied to the cathode, and an abnormal glow discharge is performed to form the cathode. The above forming method is an example. As described above, the chip portion 20 having the protrusions 22 on which the diamond thin film layer 23 is formed is obtained.

次に、図6(b)に示すように、チップ部20の突起22形成面の裏面に樹脂を塗布し
、例えばステンレス(SUS)等を含む台金10に貼付する。樹脂は、例えばエポキシ樹
脂とアミン系接着剤との混合剤又はエポキシ樹脂とポリアミドアミン系接着剤との混合剤
を用いる。台金10は例えば、リング状構造を有するが特に限定されない。
Next, as shown in FIG. 6B, a resin is applied to the back surface of the projection 22 forming surface of the chip portion 20 and attached to a base metal 10 containing, for example, stainless steel (SUS) or the like. As the resin, for example, a mixture of an epoxy resin and an amine-based adhesive or a mixture of an epoxy resin and a polyamide amine-based adhesive is used. The base metal 10 has, for example, a ring-shaped structure, but is not particularly limited.

以上のようにして、本実施形態のドレッサー1が完成する。 As described above, the dresser 1 of the present embodiment is completed.

次に、本実施形態に係るドレッサー1を用いた具体例について説明する。 Next, a specific example using the dresser 1 according to the present embodiment will be described.

図7はドレッサー1を用いた具体例である研磨装置100の構成示す模式図である。図
7に示すように、研磨装置100はドレッシング機構2、研磨ヘッド3、ノズル4、研磨
パッド5、回転テーブル6を有する。また、この他に一部図示しない構成があっても良い
FIG. 7 is a schematic diagram showing the configuration of the polishing apparatus 100, which is a specific example using the dresser 1. As shown in FIG. 7, the polishing apparatus 100 includes a dressing mechanism 2, a polishing head 3, a nozzle 4, a polishing pad 5, and a rotary table 6. In addition, there may be a configuration (partially not shown).

回転テーブル6は、図示しない回転軸に下から支承され、回転軸が外部の駆動装置によ
り回転駆動されることによって所定速度で回転する。
The rotary table 6 is supported from below by a rotary shaft (not shown), and the rotary shaft is rotationally driven by an external drive device to rotate at a predetermined speed.

研磨ヘッド3の下部には半導体ウエハが位置する。ウエハは、研磨対象面を研磨パッド
5に対向するように設置され、研磨ヘッド3に保持される。研磨ヘッド3は、ウエハを回
転テーブル6に押圧可能な機構等が備えられている。
A semiconductor wafer is located below the polishing head 3. The wafer is installed so that the surface to be polished faces the polishing pad 5, and is held by the polishing head 3. The polishing head 3 is provided with a mechanism that can press the wafer against the rotary table 6.

回転テーブル6の上方にはスラリーを吐出するノズル4が配置されている。スラリーは
、例えば二酸化セリウムを砥粒としたものである。
A nozzle 4 for discharging the slurry is arranged above the rotary table 6. The slurry is, for example, cerium dioxide as abrasive grains.

研磨処理時には、ノズル4から研磨パッド5上にスラリーを供給し、研磨ヘッド3を降
下させることによってウエハを研磨パッド5に接触させる。そして、回転テーブル6およ
び研磨ヘッド3を同一方向に回転させる。このようにして、ウエハ上に設けられた所定の
研磨対象材料を研磨することで半導体装置を製造する。
During the polishing process, the slurry is supplied from the nozzle 4 onto the polishing pad 5, and the polishing head 3 is lowered to bring the wafer into contact with the polishing pad 5. Then, the rotary table 6 and the polishing head 3 are rotated in the same direction. In this way, a semiconductor device is manufactured by polishing a predetermined material to be polished provided on the wafer.

また、ドレッシング機構2には研磨パッド5側にドレッサー1が設けられている。ドレ
ッサー1は研磨パッド5と対向する面(作用面)にチップ部20の複数の突起22が位置
するように配置されている。ドレッシング機構2は、ウエハの研磨中または研磨前後にド
レッサー1を回転させ、ドレッサー1を揺動させながら研磨パッド5の目立てを行う。ド
レッシング機構2が設けられることで、ウエハの通過領域の表面を万遍なく目立てするこ
とが可能になる。
Further, the dressing mechanism 2 is provided with a dresser 1 on the polishing pad 5 side. The dresser 1 is arranged so that a plurality of protrusions 22 of the chip portion 20 are located on a surface (working surface) facing the polishing pad 5. The dressing mechanism 2 rotates the dresser 1 during or before and after polishing the wafer, and sharpens the polishing pad 5 while swinging the dresser 1. By providing the dressing mechanism 2, it is possible to evenly sharpen the surface of the passing region of the wafer.

以上、本実施形態に係るドレッサー1によれば、Si基板上にダイヤモンド薄膜層を成
膜するため、金属系の基板にダイヤモンド薄膜層を成膜する場合と比較して高温環境に強
いドレッサーを形成することが可能になる。例えば、ダイヤモンド薄膜層の成膜時に80
0度の高温環境下に晒した時に金属が溶出し、金属中の炭素が成長してすす状になると言
う問題を回避できる。また、Si基板とダイヤモンドの熱膨張係数が同程度のため、高温
環境下においてダイヤモンドとの熱膨張係数の差が大きいことによりダイヤモンド薄膜層
にクラックが発生してしまう虞を回避できる。
As described above, according to the dresser 1 according to the present embodiment, since the diamond thin film layer is formed on the Si substrate, a dresser resistant to a high temperature environment is formed as compared with the case where the diamond thin film layer is formed on the metal-based substrate. It will be possible to do. For example, 80 when the diamond thin film layer is formed.
It is possible to avoid the problem that the metal elutes when exposed to a high temperature environment of 0 ° C., and the carbon in the metal grows and becomes soot-like. Further, since the coefficient of thermal expansion of the Si substrate and that of diamond are about the same, it is possible to avoid the possibility that cracks occur in the diamond thin film layer due to the large difference in the coefficient of thermal expansion from that of diamond in a high temperature environment.

さらには、Si基板を円錐形状に加工し突起を形成するため、より効率的に研磨パッド
のドレッシングが可能になり、また、四角錐や他の突起形状と比較して、突起間に研磨パ
ッドの屑が溜まりにくくなる。
Furthermore, since the Si substrate is processed into a conical shape to form protrusions, it is possible to dress the polishing pad more efficiently, and compared to quadrangular pyramids and other protrusion shapes, the polishing pad between the protrusions can be dressed. It becomes difficult for waste to collect.

本実施形態に係るドレッサー1の製造方法によれば、Siウエハに突起を形成した後に
ダイシング工程により複数のチップ状にダイシングし、得たチップ部を台金に取り付ける
。そのため、一枚のウエハから製造できるドレッサーの数が多くなり、コストの削減が可
能になる。
According to the method for manufacturing the dresser 1 according to the present embodiment, after forming protrusions on the Si wafer, dicing is performed in the form of a plurality of chips by a dicing step, and the obtained chip portions are attached to the base metal. Therefore, the number of dressers that can be manufactured from one wafer increases, and the cost can be reduced.

(第2の実施形態)
以下、第2の実施形態に係るドレッサーについて図8を用いて説明する。第2の実施形
態に係るドレッサーは第1の実施形態と比較して、台金とチップ部との間にチップ保持台
を用いるという点が異なる。
(Second embodiment)
Hereinafter, the dresser according to the second embodiment will be described with reference to FIG. The dresser according to the second embodiment is different from the first embodiment in that a chip holding table is used between the base metal and the chip portion.

図8に第2の実施形態に係るドレッサー1の構成を示す。なお、チップ部20の構造は
第1の実施形態と同様なためその説明は省略する。図8に示すように、本実施形態のドレ
ッサー1は台金10と、台金10上に設けられた複数のチップ保持台50を有し、各チッ
プ保持台50上にはそれぞれチップ部20を有する。
FIG. 8 shows the configuration of the dresser 1 according to the second embodiment. Since the structure of the chip portion 20 is the same as that of the first embodiment, the description thereof will be omitted. As shown in FIG. 8, the dresser 1 of the present embodiment has a base metal 10 and a plurality of chip holding bases 50 provided on the base metal 10, and each chip portion 20 is provided on each chip holding base 50. Have.

チップ保持台50は例えばステンレス(SUS)等を含むがその材料は特に限定されな
い。台金10と同材料で構成され、台金10の一部分として一体化していても良い。また
、チップ保持台50の数は特に限定されず、少なくとも1つあればよい。なお、本実施形
態において、チップ保持台50を台金10の一部に含めても良い。
The chip holding table 50 includes, for example, stainless steel (SUS) and the like, but the material thereof is not particularly limited. It may be made of the same material as the base metal 10 and integrated as a part of the base metal 10. Further, the number of the chip holding tables 50 is not particularly limited, and at least one may be sufficient. In this embodiment, the chip holding table 50 may be included as a part of the base metal 10.

次に本実施形態のドレッサー1の製造方法について図9を用いて説明する。 Next, the manufacturing method of the dresser 1 of the present embodiment will be described with reference to FIG.

まずチップ部20を作製する。なお、チップ部20の形成方法は第1の実施形態と同様
であるためその説明は省略する(図3、図4及び図6(a)図参照)。
First, the chip portion 20 is manufactured. Since the method of forming the chip portion 20 is the same as that of the first embodiment, the description thereof will be omitted (see FIGS. 3, 4 and 6 (a)).

次に、上記の方法で得たダイヤモンド薄膜層23が成膜されたチップ部20を突起22
形成面の裏面に樹脂を塗布し、チップ部20をチップ保持台50上に貼付する(図9(a
))。樹脂は例えばエポキシ樹脂とアミン系接着剤との混合剤を用いる。
Next, the protrusion 22 is formed on the chip portion 20 on which the diamond thin film layer 23 obtained by the above method is formed.
Resin is applied to the back surface of the formed surface, and the chip portion 20 is attached onto the chip holding table 50 (FIG. 9 (a).
)). As the resin, for example, a mixture of an epoxy resin and an amine-based adhesive is used.

最後に、チップ部20が貼付されたチップ保持台50を例えばネジ等を用いて台金10
に固定する。以上のようにして第2の実施形態のドレッサー1完成する。なお、固定方法
は特に限定されない。
Finally, the chip holding base 50 to which the chip portion 20 is attached is attached to the base 10 using, for example, a screw or the like.
To fix. As described above, the dresser 1 of the second embodiment is completed. The fixing method is not particularly limited.

本実施形態に係るドレッサー1によれば、第1の実施形態と同様な効果を有し、かつチ
ップ部と台金との間にチップ保持台を有することによって、チップ部のみを研磨パッドに
作用させやすくなる。具体的には、研磨パッドが軟質な場合に台金からのチップ部の突出
量が小さいと台金にも研磨パッドが接触してしまい、研磨パッドに対するチップ部からの
圧力が台金に逃げる可能性がある。上記を回避するために、厚いSiウエハを用いてチッ
プ部の厚さを厚くする方法があるが、本実施形態では金属のチップ保持台を用いるためコ
ストを削減できる。
According to the dresser 1 according to the present embodiment, the dresser 1 has the same effect as that of the first embodiment, and by having the tip holding base between the tip portion and the base metal, only the tip portion acts on the polishing pad. It will be easier to make it. Specifically, when the polishing pad is soft and the amount of protrusion of the tip portion from the base metal is small, the polishing pad also comes into contact with the base metal, and the pressure from the tip portion on the polishing pad can escape to the base metal. There is sex. In order to avoid the above, there is a method of increasing the thickness of the chip portion by using a thick Si wafer, but in this embodiment, since a metal chip holder is used, the cost can be reduced.

以上、本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示
したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は
、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、
種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の
範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含
まれる。
Although some embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, as long as they do not deviate from the gist of the invention.
Various omissions, replacements and changes can be made. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

1 ドレッサー
2 ドレッシング機構
3 研磨ヘッド
4 ノズル
5 研磨パッド
6 回転テーブル
10 台金
20 チップ部
21 基板
22 突起
23 ダイヤモンド薄膜層
30 下地膜
40 レジスト膜
50 チップ保持台
100 研磨装置
1 Dresser 2 Dressing mechanism 3 Polishing head 4 Nozzle 5 Polishing pad 6 Rotating table 10 Base metal 20 Chip part 21 Substrate 22 Projection 23 Diamond thin film layer 30 Base film 40 Resist film 50 Chip holding table 100 Polishing device

Claims (4)

Siウエハ上にSiとOを含む膜を形成し、
前記SiとOを含む膜上にレジスト膜を形成し、
前記SiとOを含む膜と前記レジスト膜を円形状にパターニングし、
前記パターニング後のSiとOを含む膜とレジスト膜をマスクにして、前記Siウエハ
をエッチングすることにより、前記Siウエハに突起を形成し、
前記突起を有するSiウエハダイシングにより個片化してチップ部を形成し、
前記チップ部の前記突起上にダイヤモンド薄膜層を形成し、
台金上に前記ダイヤモンド薄膜層が形成された前記チップ部を設けるドレッサーの製造
方法。
A film containing Si and O is formed on the Si wafer ,
A resist film is formed on the film containing Si and O, and the resist film is formed.
The film containing Si and O and the resist film are patterned in a circular shape to form a circular shape.
The Si wafer is masked with a film containing Si and O after patterning and a resist film.
By etching the Si wafer , protrusions are formed on the Si wafer.
The Si wafer having the protrusions is diced into pieces to form a chip portion.
A diamond thin film layer is formed on the protrusions of the chip portion to form a diamond thin film layer.
A method for manufacturing a dresser in which the chip portion in which the diamond thin film layer is formed is provided on a base metal.
前記Siウエハのエッチングは、CとFを含むガスを用いる、請求項に記載のドレッ
サーの製造方法。
The method for manufacturing a dresser according to claim 1 , wherein the etching of the Si wafer uses a gas containing C and F.
前記Siウエハのエッチングは、SとFを含むガス、CとFを含むガスおよびOを含む
ガスの混合ガスを用いる、請求項に記載のドレッサーの製造方法。
The method for manufacturing a dresser according to claim 1 , wherein the etching of the Si wafer uses a mixed gas of a gas containing S and F, a gas containing C and F, and a gas containing O.
前記SiとOを含む膜はTEOS膜である、請求項乃至のいずれか1項に記載のド
レッサーの製造方法。
The method for manufacturing a dresser according to any one of claims 1 to 3 , wherein the film containing Si and O is a TEOS film.
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