JP7072497B2 - Power converter and its status monitoring method - Google Patents

Description

The present invention relates to a gate drive circuit of a voltage-driven semiconductor element and a method for predicting element failure.

IGBTs (Insulated Gate Bipolar Transistors) that can switch at high speed and control high power are widely used from small-capacity inverters for home use to large-capacity inverters used in railways and the like. As a circuit for driving a voltage-driven semiconductor element such as an IGBT, a gate drive circuit such as a gate driver that controls on / off of the semiconductor element by controlling the voltage applied to the gate is used. In recent years, inverters that use low-loss SiC (silicon carbide) MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) have become widespread in place of Si (silicon) IGBTs. In the meantime, even in railway inverters, there is a demand for a gate drive circuit suitable for driving a SiC-PWM.

International Publication No. 2016/209754 Japanese Unexamined Patent Publication No. 2000-324846

As a result of diligent studies on the failure of the inverter by the inventor of the present application, the following findings have been obtained.

Failure to occur while the inverter is running can result in system damage and unplanned system outages, which can result in significant economic loss. In order to prevent such a situation, it is required to detect deterioration or abnormality of the semiconductor element before the semiconductor element fails.

In a three-phase AC inverter (power conversion device) for railways, each phase of UVW is composed of semiconductor elements connected in series. The high-voltage side semiconductor element close to the overhead wire voltage is called the upper arm element, and the low-voltage side semiconductor element close to the ground potential (rail) is called the lower arm element.

When a SiC- MOSFET is applied as an element constituting a power conversion device, it is common to connect and drive a plurality of elements in parallel in railway applications. That is, in a state where a plurality of elements are connected in parallel in the same arm, each element is turned on and off according to a command from the gate drive circuit. Therefore, the currents flowing through the elements connected in parallel may be unbalanced with each other due to the variation in the characteristics of the elements and the variation in the impedance of the main circuit. When the current between the parallel elements becomes non-uniform, the switching loss (heat generation) generated in the element through which a large amount of current flows increases, so that a temperature difference occurs between the parallel elements. For this reason, there is a concern that the temperature change of an element in which a large amount of current flows becomes large and the life of the element is shorter than that of other elements, which lowers the reliability of the inverter system.

Therefore, if the current flowing through each element can be measured and compared, the non-uniformity of the current flowing through each element in the inverter can be evaluated. By detecting an element whose current value is significantly different from that of other elements, deterioration or abnormality is detected before the element fails, and measures such as element replacement are taken before the element fails. It is possible to prevent the life of the device from being shortened. Here, the element failure refers to a state in which the on / off of the semiconductor element cannot be controlled by controlling the voltage applied to the gate in the case of a voltage-driven semiconductor element.

In addition, the advantages of measuring current instead of temperature and voltage are that (1) changes (deterioration) in the characteristics of the element itself can be detected, and (2) it can be applied to elements connected in parallel in the same arm. Can be mentioned. In (1), the temperature difference between the elements is not limited to the change in the characteristics of the element itself, such as the difference in heat transfer coefficient depending on the installation location of each element in the inverter and the change in thermal resistance over time. It is more suitable to measure the current and voltage of the element than to measure the temperature near the element with a temperature sensor etc. for the purpose of detecting deterioration or abnormality of the element before it leads to failure. Because it is. This is because the elements connected in parallel to each other show the same voltage value, and it is more suitable to measure the current of each element for the purpose of detecting the imbalance between the parallel elements.

Patent Document 1 is a prior art for detecting deterioration or abnormality of an element. In Patent Document 1, the element (IGBT) "conductance of the current waveform, the current change rate per hour at the time of interruption depends on the temperature of the power semiconductor", and the fluctuation of the current change rate is used to determine the IGBT. An example of detecting the temperature is disclosed. However, from the investigation by the inventors, it was confirmed that in the case of SiC- MOSFET, the current change rate does not change depending on the temperature, especially when the current is conducting (when the switching is turned on). Therefore, it is difficult to apply the method of Patent Document 1 to SiC- MOSFET as it is.

Further, in Patent Document 2, as one means for measuring the current flowing through the semiconductor element for determining the short-circuit state, the current is generated by integrating the voltage generated at the time of switching across the parasitic inductance inside the semiconductor element. The technique of calculating is disclosed. However, there is no disclosure of a means for detecting deterioration or abnormality of the semiconductor element before the semiconductor element fails or for comparing the current flowing through each element in the inverter.

An object of the present invention is to detect deterioration or abnormality of a semiconductor element before it causes a failure without providing an additional sensor on the semiconductor element.

INDUSTRIAL APPLICABILITY In a gate drive circuit for driving a voltage-driven semiconductor element, the present invention applies a voltage between terminals between a sense emitter terminal (SS) and an emitter main terminal (MS) of the semiconductor element in each arm of a power conversion device. The present invention relates to a configuration in which a device is measured, a current flowing through the element is calculated based on the measurement, and an element having a possibility of failure is estimated from a relative change in the current flowing through each element.

According to the present invention, by comparing the current and voltage applied to the semiconductor element relative to those of other semiconductor elements without providing an additional sensor in the semiconductor element, the allowable range in which the temperature difference between the semiconductor elements is set is set in advance. Since it is possible to detect whether or not the semiconductor element has been exceeded, deterioration or abnormality can be detected before the semiconductor element fails. Therefore, it is possible to prevent the occurrence of a failure during the operation of the power conversion device and provide a highly reliable power conversion device and a gate drive circuit. It is also useful for condition monitoring and maintenance.

Configuration diagram of the railway inverter system according to the first embodiment Configuration diagram of the failure prediction device for the semiconductor element according to the first embodiment. Detailed configuration diagram of the failure prediction device for the semiconductor element according to the first embodiment. Procedure for determining the failure determination value of the semiconductor element according to the first embodiment Explanatory diagram of the relationship between the magnitude of the threshold voltage of the semiconductor element and the switching waveform Explanatory diagram of the relationship between the difference in the threshold voltage of the semiconductor element and the difference in the switching loss Explanatory diagram of a method of detecting an element in which a failure is predicted by a relative comparison of currents flowing through a semiconductor element in each phase and each arm of a power conversion device. Explanatory drawing of a method of detecting a device which is predicted to fail by tracking the time change of the current flowing through each semiconductor device. Configuration diagram of the failure prediction device for the semiconductor element according to the second embodiment. Configuration diagram of the failure prediction device for the semiconductor element according to the third embodiment. Configuration diagram of the failure prediction device for the semiconductor element according to the fourth embodiment.

In the embodiment, it is a method of monitoring the state of a plurality of semiconductor elements constituting each arm of the power conversion device, and the failure prediction unit of the power conversion device determines the Ve voltage between the sense emitter terminal and the emitter main terminal of the semiconductor element. Disclosed is a device that detects a semiconductor device in which deterioration or abnormality has occurred from a relative change in current and / or Ve voltage flowing through a plurality of semiconductor devices.

Further, in the embodiment, in a power conversion device in which each arm is composed of a plurality of semiconductor elements, the Ve voltage between the sense emitter terminal and the emitter main terminal of the semiconductor element is measured, and the current flowing through the plurality of semiconductor elements is measured. And / or those provided with a failure prediction unit for detecting a semiconductor element in which deterioration or abnormality has occurred from a relative change in Ve voltage are disclosed.

Further, in the embodiment, it is disclosed that the failure prediction unit or the current detection unit on the gate drive circuit of the power conversion device calculates the current flowing through the semiconductor element based on the Ve voltage.

Further, in the embodiment, it is disclosed that the failure prediction unit directly compares the measured Ve voltage as it is.

Further, in the embodiment, the current value flowing through each semiconductor element deviates from the average current value ± ΔI of each semiconductor element based on the current difference ΔI between the plurality of semiconductor elements corresponding to the allowable temperature difference between the plurality of semiconductor elements. It is disclosed that the semiconductor element is detected as a semiconductor element in which deterioration or abnormality has occurred.

Further, in the embodiment, the Ve voltage value of each semiconductor element determines the average Ve value ± ΔVe of each semiconductor element based on the Ve voltage difference ΔVe between the plurality of semiconductor elements corresponding to the allowable temperature difference between the plurality of semiconductor elements. It is disclosed that a deviated semiconductor element is detected as a semiconductor element in which deterioration or abnormality has occurred.

Further, in the embodiment, the current value flowing through each semiconductor element deviates from the initial current value ± ΔI of each semiconductor element based on the current difference ΔI between the plurality of semiconductor elements corresponding to the allowable temperature difference between the plurality of semiconductor elements. It is disclosed that the semiconductor element is detected as a semiconductor element in which deterioration or abnormality has occurred.

Further, in the embodiment, the Ve voltage value of each semiconductor element sets the initial Ve value ± ΔVe of each semiconductor element based on the Ve voltage difference ΔVe between the plurality of semiconductor elements corresponding to the allowable temperature difference between the plurality of semiconductor elements. It is disclosed that a deviated semiconductor element is detected as a semiconductor element in which deterioration or abnormality has occurred.

Further, in the embodiment, it is disclosed that the failure prediction unit relatively compares the maximum value of the current value or the Ve voltage value flowing through the plurality of semiconductor elements at regular time intervals. Further, it is disclosed that the constant time interval is a time interval of one cycle or more of the AC current of the three-phase AC motor driven by the power conversion device.

Further, in the embodiment, it is disclosed that a plurality of semiconductor elements are connected in parallel in the same arm of the power conversion device. Further, based on the current difference ΔI or Ve voltage difference ΔV between the semiconductor elements connected in parallel, the gate drive current at the time of switching of each of the semiconductor elements connected in parallel is adjusted, and the current difference or Ve voltage between the parallel elements is adjusted. Disclose that the difference is reduced. Further, the gate drive circuit is connected in parallel so as to reduce the current difference or Ve voltage difference between the parallel elements based on the current difference ΔI or Ve voltage difference ΔV between the semiconductor elements connected in parallel. It discloses that the gate drive current at each switching is adjusted.

Further, in the embodiment, it is disclosed that the semiconductor element is a SiC- MOSFET.

Further, in the embodiment, when the gate drive circuit for driving the semiconductor element has a short-circuit detection unit and a gate cut-off unit, and the short-circuit detection unit detects that the current flowing through each semiconductor element exceeds a specified value. Disclosed that the gate of the semiconductor element is blocked by the gate blocking section without going through the failure prediction section and the command logic section above the gate drive circuit. Further, when the current flowing through each semiconductor element exceeds the specified value, the gate drive circuit shuts off the gate of the semiconductor element without going through the failure prediction unit and the command logic unit above the gate drive circuit. Disclose. Further, it is disclosed that the specified value is a current value exceeding the rated current of the semiconductor element.

Hereinafter, the above and other novel features and effects of the present invention will be described with reference to the drawings. The drawings are used exclusively for understanding the invention and do not reduce the scope of rights.

FIG. 1 is a configuration diagram of a railway inverter system according to this embodiment.

In the railway inverter system according to this embodiment, the power unit 100 is composed of a MOSFET (voltage-driven semiconductor element) 101 and a filter capacitor 103. A MOSFET 101 is connected in series in each of the UVW phases, and a freewheeling diode 102 is connected in parallel to each MOSFET 101 so that the flow direction is opposite. Further, in each MOSFET 101, a gate drive circuit 104 for driving the MOSFET is arranged according to a command from the command logic unit 105. The connection points between the upper arm MOSFET and the lower arm MOSFET in each UVW phase are connected to the motor 106 as the output of the power unit 100. Further, each MOSFET 101 is connected to the failure prediction unit 113 via the gate drive circuit 104. The command logic unit 105 is included in the failure prediction unit 113. The failure prediction unit 113 measures and compares the current of each MOSFET 101, and predicts an element having a possibility of failure.

The DC power from the overhead wire 107 is smoothed via the current collector 108, the plurality of breakers 109, and the filter reactor 110, and is input to the high voltage side of the filter capacitor 103 for removing noise. The low voltage side of the filter capacitor 103 is connected to the rail 112, which is an electrical ground, via the wheel 111. Then, the railway inverter system generates a three-phase alternating current by alternately switching the UVW phase MOSFETs in the power unit and sends the three-phase alternating current to the motor 106. The gate drive circuit 104 arranged in the power unit 100 together with the MOSFET 101 and the filter capacitor 103 drives the MOSFET 101 in accordance with a command from the command logic unit 105. The command logic unit 105 includes an arithmetic unit, a memory, and input / output means, and outputs a command for driving the MOSFET according to a predetermined program. In the gate drive circuit according to this embodiment, an example of driving a MOSFET as a semiconductor element will be described, but the semiconductor element is not limited to the MOSFET, and may be, for example, an IGBT.

FIG. 2 is a configuration diagram of a failure prediction device for a semiconductor element according to this embodiment. Of the configuration diagrams of the railway inverter system shown in FIG. 1, only the upper and lower arms of the U phase are shown in detail, and the V phase and the W phase have the same configuration, and are therefore omitted. The same applies to the following description. A MOSFET 101 is connected in series between the power supply voltage 114 (the applied voltage of the filter capacitor 103 in FIG. 1) and the ground potential 115, and the freewheeling diode 102 is connected to each MOSFET 101 so that the flow direction is opposite. Are connected in parallel. Each MOSFET 101 is originally provided with a sense emitter terminal (SS) and an emitter main terminal (MS), and a gate terminal (G), an SS terminal, and an MS terminal of the MOSFET 101 are connected to the gate drive circuit 104, respectively. There is. Since the G terminal, SS terminal, and MS terminal are originally installed in the power semiconductor module that integrates the semiconductor element and the freewheeling diode so that they can be mounted in the inverter system, a new terminal only for failure prediction is used as the power semiconductor module. No need to install. The gate drive circuit 104 that drives each element is connected to a higher-level failure prediction unit 113. The failure prediction unit 113 includes an interface unit 1, a command logic unit 105, a current detection unit 2, a relative comparison unit 3, an allowable fluctuation amount designation unit 4, and an output unit 5.

A drive command is input from the command logic unit 105 to the gate drive circuit 104 of each element via the interface unit 1. While the drive command is input, the gate drive circuit 104 applies a voltage exceeding the threshold voltage of the MOSFET 101 between the G-SS terminals of the MOSFET 101 (for example, + 15V), turns on the MOSFET 101, and causes a current to flow (turn-on). Further, the gate drive circuit 104 applies a voltage below the threshold voltage between the G-SS terminals of the MOSFET 101 (for example, -10V) while the drive command is not input from the command logic unit 105, and turns off the MOSFET 101. Cut off the current (turn off).

Further, the gate drive circuit 104 measures the voltage between the MS and SS terminals (Ve voltage in FIG. 2), and measures the current flowing through the MOSFET 101. There is a relationship (Equation 1) between the Ve voltage and the current (I) flowing between the MS and SS terminals.
Ve = -Le * dI / dt ... (Equation 1)
Here, Le is the parasitic inductance between the MS and SS terminals, and dI / dt is the time change rate of the current (I) flowing between the MS and SS terminals. A negative sign means that the counter electromotive force Ve is generated in a direction that hinders the change in current. Further, the current flowing between the MS and SS terminals is equal to the current flowing through the MOSFET 101. Therefore, if the value of Le is measured in advance from (Equation 1), the dI / dt of the MOSFET 101 can be detected using the Ve voltage input to the gate drive circuit 104, and the dI / dt of the MOSFET 101 can be integrated over time. For example, the current (I) flowing through the MOSFET 101 can be detected.

The Ve voltage of all the elements in each phase and each arm of the power conversion device is collected in the upper failure prediction unit 113 via the gate drive circuit 104. In FIG. 1, the Ve voltage of the U-phase upper arm is shown by U1 and the Ve voltage of the U-phase lower arm is shown by U2 (the same applies to the V phase and the W phase). The current detection unit 2 in the failure prediction unit 113 integrates the Ve voltage as described above and calculates the current flowing through each element. The integral of the Ve voltage may be configured by an analog circuit or may be calculated by a digital integrator or the like. Note that FIG. 2 shows an example in which the current detection unit 2 inside the failure prediction unit 113 calculates the current after consolidating the Ve voltage of each element in the upper failure prediction unit 113, but the gate drive of each element is shown. The current detection unit 2 may be provided inside the circuit 104, the current value may be calculated from the Ve voltage in each element, and then the current value of each element may be aggregated in the upper failure prediction unit 113.

The current values of all the elements in each arm calculated by the current detection unit 2 are compared with each other by the relative comparison unit 3 inside the failure prediction unit 113, and the current values are relatively significantly different from those of the other elements. An element whose value deviates is detected as an element having a possibility of failure and displayed on the output unit 5. Whether or not the current value deviates by a relatively significant difference with respect to the other elements is determined by whether or not it deviates from the fluctuation range designated by the permissible fluctuation amount designating unit 4.

FIG. 3 shows a detailed configuration diagram of the failure prediction device for the semiconductor element according to this embodiment. The relative comparison unit 3 is composed of a storage unit 6 and a comparison unit 7. The storage unit 6 holds the current value of each arm of each phase calculated by the current detection unit 2. The permissible fluctuation amount designation unit 4 determines whether or not the current value deviates by a relative significant difference with respect to other elements, so that the permissible fluctuation range (upper limit value: UL, lower limit value: LL) is determined. ) Is specified in the comparison unit 7. The comparison unit 7 compares the current value (Ical) held in the storage unit 6 with the permissible fluctuation range designated by the permissible fluctuation amount designation unit 4 for each arm of each phase, and LL ≦ Ical ≦ UL. In the case of, it is regarded as normal, and in the case of Ical <LL or UL <Ical, it is detected as an element in which a failure is predicted. When the comparison unit 7 detects an element predicted to be faulty, the output unit 5 outputs the information to the outside and clearly indicates it to the user. With this configuration, elements that may fail can be detected before failure, so the timing of maintenance and replacement of parts (elements) can be optimized, leading to longer life of the inverter system and reduction of maintenance costs.

It is conceivable that the cause of the deterioration of the element with time is that the current concentrates on a specific element and causes overheating, and the characteristics of the element change. Therefore, as a means for holding the current flowing through the element of each phase and each arm in the storage unit 6, the peak value (maximum value) of the current may be held. In that case, when comparing the current values relative to each other, the timing at which the peak current flows is temporally different for elements with different phases or arms, so the current of each element that is input to the failure detection unit 113 every moment. The method of comparing information at the same time is not always appropriate. Therefore, as shown in FIG. 3, a configuration (comparison timing designation unit 8) for designating the comparison timing may be provided. The comparison timing specifying unit 8 is connected to the comparison unit 7 and designates the comparison timing of the current value. In the case of a PWM-controlled three-phase AC inverter, it is utilized that a peak current flows through each element constituting the inverter at least once in principle within one cycle of the AC current flowing through the motor 106. For example, since the frequency of the motor current for electric railway is generally in the range of 0 to 200 Hz, a peak current flows through each element in the power converter at least once in 10 ms at 100 Hz. Therefore, the comparison timing designating unit 8 can instruct the comparison unit 7 to compare the peak currents at intervals of 10 ms or more, so that the peak currents of the elements can be compared relative to each other.

FIG. 4 shows a procedure for deriving an allowable fluctuation range (upper limit value: UL, lower limit value: LL) given to the comparison unit 7 by the allowable fluctuation amount designation unit 4. The main factors that affect the life of the semiconductor elements that make up the inverter system include deterioration of the characteristics of the elements (MOSFETs) and thermal fatigue of the solder joints. Current imbalance occurs due to fluctuations and variations in the threshold voltage of the MOSFET, which increases the switching loss (heat generation) of a specific element and widens the temperature difference between the elements. When the temperature difference between the elements becomes large, the element with a relatively large temperature change develops thermal fatigue at the solder joint, which shortens the life of the other elements, resulting in the reliability of the entire inverter system. It becomes a factor to damage. In particular, in the case of a railway inverter to which SiC- MOSFET is applied, since it is common to use multiple elements connected in parallel in the same arm, they are connected in parallel not only between the arms but also in the same arm. It is also important to reduce the temperature difference between the elements. In the following, the procedure for deriving the allowable fluctuation range for predicting a failed element will be described by taking the case of two elements (MOSFETs) connected in parallel in the same arm as an example, but when comparing between different arms or , The same method can be applied to other voltage-driven semiconductor devices such as IGBTs.

The current change rate (dI / dt) during switching of the MOSFET can be expressed by (Equation 2). Here, gm is the mutual conductance, and dVgs / dt is the time change rate of the gate-source voltage (Vgs). Since the MOSFET is operating in the saturation region at the timing when dI / dt is generated during switching, gm can be expressed by (Equation 3). Here, β is a gain coefficient and Vth is the threshold voltage of the MOSFET.
dI / dt = gm * dVgs / dt ... (Equation 2)
gm = β * (Vgs-Vth) ... (Equation 3)
Since the same Vgs is applied between two elements connected in parallel, the imbalance of dI / dt (hence the imbalance of current) at the time of switching between the two elements is Vth from (Equation 2) and (Equation 3). It depends greatly on the difference between.

FIG. 5 shows an explanatory diagram of the relationship between the magnitude of the threshold voltage of the semiconductor element and the switching waveform. Further, FIG. 6 shows an explanatory diagram of the relationship between the difference in the threshold voltage of the semiconductor element and the difference in the switching loss. As shown in FIG. 5, of the two elements, the element with the smaller Vth (element 1) turns on earlier than the other (element 2), and conversely, when it is off, the element with the larger Vth (element 2) is the other. Since the turn-off is faster than that of (element 1), the current is concentrated on the element 1 having the smaller Vth both when it is turned on and when it is turned off. Therefore, the switching loss of the element 1 having the smaller Vth becomes relatively large, and a temperature difference occurs between the two elements connected in parallel. Therefore, as shown in FIG. 6, when the difference from the average of Vth (ΔVth) between parallel elements is plotted on the horizontal axis and the difference from the average of switching loss (ΔE) is plotted on the vertical axis, the right shoulder passing through the origin is plotted. A downward relationship is obtained.

Based on the above principle, the procedure for deriving the permissible fluctuation range (upper limit value: UL, lower limit value: LL) given to the comparison unit 7 by the permissible fluctuation amount designation unit 4 is shown.

[Procedure 1] Specifying the allowable temperature difference The user specifies the allowable temperature difference (ΔT) between the elements. The temperature difference (ΔT) between the elements connected in parallel can be estimated by (Equation 4) as the product of the thermal resistance (Rth) of the elements and the difference in switching loss (ΔE) between the elements, and ΔE corresponding to ΔT is derived. do.
ΔT = Rth * ΔE ... (Equation 4)

[Procedure 2] Derivation of the relationship between the threshold voltage difference and the switching loss difference As described above, ΔE largely depends on the difference in Vth (ΔVth) between the two elements, and therefore, the correlation between ΔE and ΔVth as shown in FIG. Derive the relationship. Since the relationship between ΔE and ΔVth depends on the type of semiconductor element, main circuit conditions (power supply voltage, drive current), gate drive conditions (drive frequency), and temperature, it may be derived experimentally or statistically. It is also possible to analyze and model the element (circuit model, physical model) and calculate in advance by circuit simulation.

[Procedure 3] Derivation of allowable threshold voltage difference (derivation of allowable ΔVth)
From the relationship between (Equation 4) and ΔE−ΔVth derived in step 2, the threshold voltage difference (ΔVth_clit) allowed to suppress ΔT to the allowable temperature difference or less can be estimated.

[Procedure 4] Derivation of the difference in the permissible current change rate (derivation of the permissible ΔdI / dt)
The difference in dI / dt (ΔdI / dt) at the time of switching between two elements connected in parallel corresponding to ΔVth_clit is derived. It may be derived experimentally or statistically, or it may be calculated analytically from (Equation 2) and (Equation 3).

[Procedure 5] Derivation of allowable current difference (derivation of allowable ΔI)
By multiplying ΔdI / dt in step 4 by the switching time of the semiconductor element, the current difference (ΔI) allowed to suppress ΔT to the allowable temperature difference or less can be derived.

[Procedure 6] Input to the permissible fluctuation amount designation unit Based on the ΔI derived in step 5, the permissible fluctuation range (upper limit value: UL, lower limit value: LL) is input to the permissible fluctuation amount designation unit 4.

FIG. 7 is an explanatory diagram of a method of detecting an element in which a failure is predicted by a relative comparison of currents flowing through a semiconductor element in each phase and each arm of the power conversion device. Based on the current difference (ΔI) between each element corresponding to the allowable temperature difference (ΔT), a failure is predicted for an element in which the current value flowing through each element deviates from the current average value (Iave) ± ΔI of each element. Detect as an element. That is, as the permissible fluctuation range given to the permissible fluctuation amount designation unit 4, the upper limit value is UL = Iave + ΔI, and the lower limit value is LL = Iave−ΔI.

By the above method, ΔI for suppressing the temperature difference between the elements connected in parallel to the allowable value or less (for example, ΔT ≦ 5K) can be derived, and the current values flowing through the elements of each phase and each arm can be compared relative to each other. It is possible to determine whether or not the temperature difference between the elements deviates from the allowable amount specified in advance, and to detect the element having a possibility of failure. By setting the permissible temperature difference (ΔT) sufficiently lower than the temperature at which the element fails, the element that may fail can be detected at the stage before the failure. In this method, it is not necessary to additionally provide a temperature sensor and a current sensor in the element itself, which contributes to low cost and miniaturization of the inverter device. Further, by measuring and comparing the currents of each element, there is an advantage that it can be applied even when a plurality of elements are connected in parallel in the same arm.

FIG. 8 is an explanatory diagram of a method of detecting an element in which a failure is predicted by tracking a time change of a current flowing through each semiconductor element. An element in which the current value flowing through each element deviates from the initial value (I ₀ ) ± ΔI based on the current difference (ΔI) between each element corresponding to the allowable temperature difference (ΔT) is regarded as an element in which failure is predicted. To detect. That is, as the permissible fluctuation range given to the permissible fluctuation amount designation unit 4, the upper limit value is UL = I ₀ + ΔI, and the lower limit value is LL = I ₀ −ΔI. In the case of FIG. 7, since the relative change in the current of each element is detected, if the currents of all the elements fluctuate in the same manner, almost no change can be detected. Has the advantage of being able to be detected because it can be tracked.

FIG. 9 shows a configuration diagram of a failure prediction device for a semiconductor element according to this embodiment. In this embodiment, unlike the first embodiment, the current detection unit 2 does not intervene between the interface unit 1 and the relative comparison unit 3, and the voltage (Ve voltage) between the MS and SS terminals of the semiconductor element is applied to each phase. Relative comparison between arms. That is, the Ve voltage is not integrated, and the relative comparison is performed with the Ve voltage as it is.

Compared with the first embodiment, since the current detection unit 2 is not provided, the configuration of the failure prediction unit 113 can be simplified, and as described above, the Ve voltage is the current change rate (dI / dt) of the element. Since it is a physical parameter that largely reflects the fluctuation (ΔVth) of the threshold voltage and the threshold voltage, it is a method suitable for the purpose of measuring and comparing the change in the element characteristics described above.

As a procedure for deriving the allowable fluctuation range (upper limit value: UL, lower limit value: LL) designated by the allowable fluctuation amount designation unit 4, procedure 5 and procedure 6 shown in the first embodiment are replaced with procedure 5'and procedure 6'. For example, the difference in Ve voltage (ΔVe) corresponding to the allowable temperature difference (ΔT) can be derived.

[Procedures 1 to 4]
It is the same as Example 1.

[Procedure 5'] Derivation of allowable Ve voltage difference Since the Ve voltage is expressed by the product of the parasitic inductance (Le) between MS and SS and the current change rate (dI / dt), ΔdI / dt in step 4 By multiplying Le, the Ve voltage difference (ΔVe) allowed to suppress ΔT to the allowable temperature difference or less can be derived.

[Procedure 6']
Based on the ΔVe derived in step 5', the allowable fluctuation range (upper limit value: UL, lower limit value: LL) is input to the allowable fluctuation amount designation unit 4. That is, as the permissible fluctuation range given to the permissible fluctuation amount designation unit 4, the upper limit value is UL = Wave (mean value) + ΔVe, and the lower limit value is LL = Veave (mean value) −ΔVe.

FIG. 10 shows a configuration diagram of a failure prediction device for a semiconductor element according to this embodiment. In this embodiment, a plurality of elements are connected in parallel in the same arm, and the gate current for driving each element is corrected so that the current flowing through each element is made uniform. Hereinafter, the differences from Examples 1 and 2 will be mainly described.

The MOSFETs 101a and 101b are connected in parallel in the same arm, and the Ve voltage (Ve1, Ve2) of each element is input to the gate drive circuit 104a. The U-phase lower arm and the other-phase arm have the same connection mode, and the Ve voltage of all the phases and all arms is collected in the upper failure detection unit 113.

The differential amplification unit 12 is connected between the relative comparison unit 3 and the command logic unit 105 in the failure prediction unit 113. A drive control unit 9, a first gate current control unit 10, and a second gate current control unit 11 are provided in the gate drive circuit 104a. The drive control unit 9 is connected to the command logic unit 105 via the interface unit 1. The first gate current control unit 10 is between the gate terminal of the first MOSFET 101a and the drive control unit 9, and the second gate current control unit 11 is between the gate terminal of the second MOSFET 101b and the drive control unit 9. It is connected to the. The same connection mode is used in the gate drive circuit of the U-phase lower arm and the arm of the other phase.

The currents flowing through the MOSFETs 101a and 101b of each phase and each arm are calculated by the current detection unit 2 and compared by the relative comparison unit 3. The difference between the currents flowing through the MOSFETs 101a and 101b detected by the relative comparison unit 3 is amplified by the differential amplification unit 12 and sent to the command logic unit 105. At this time, the command logic unit 105 transmits a gate current control signal to the drive control unit 9 in the gate drive circuit 104a in addition to the drive commands of the MOSFETs 101a and 101b. The drive control unit 9 adjusts the second gate current control unit 11 so as to reduce the difference between the currents flowing through the MOSFETs 101a and 101b according to the value of the gate current control signal, and the second gate current (Ig2). To control. For example, when the current flowing through the MOSFET 101a is larger than the current flowing through the 101b, Ig2 is increased to increase the current flowing through the MOSFET 101b, and the current flowing between the parallel elements is made uniform. In this embodiment, only the second gate current control unit 11 is adjusted and the first gate current 10 is fixed, but of course, a method of adjusting both to reduce the current imbalance may be used. As a means for adjusting the gate current (Ig1, Ig2), a method of varying the gate resistance (Rg1, Rg2) between the constant voltage source and the gate terminal of the MOSFET 101 may be used, or the variable current source and the gate terminal of the MOSFET 101 may be used. It may be connected to control the gate current.

In this embodiment, there is an advantage that not only the current difference of each element can be detected but also the drive control that suppresses the current imbalance becomes possible.

FIG. 11 shows a configuration diagram of a failure prediction device for a semiconductor element according to this embodiment. In this embodiment, when a short circuit occurs, the gate of the element is cut off in the gate drive circuit in each arm without going through the upper command logic unit. Hereinafter, the differences from the first to third embodiments will be mainly described.

A short circuit detection unit 13 and a gate cutoff unit 14 are provided in the gate drive circuit 104c. Other connection modes are the same as in the third embodiment. The input unit of the short-circuit detection unit 13 is connected between the MS-SS terminals of the voltage-driven semiconductor element 101, and the output unit of the short-circuit detection unit 13 is the voltage-driven semiconductor element 101 via the gate cutoff unit 14. It is connected to the gate terminal (G). The U-phase lower arm and the other-phase arm have the same connection mode.

The short circuit detection unit 13 calculates the current flowing through the element based on the voltage between the MS and SS terminals (Ve voltage), and determines that an arm short circuit has occurred when the current value exceeds a predetermined value. At this time, as in the third embodiment, the gate cutoff unit 14 turns off the gate of the voltage-driven semiconductor element 101 without going through the upper command logic unit 105 or the failure prediction unit 113, and the semiconductor element is short-circuited by the arm. It is possible to cut off the current flowing through the element before it is destroyed, minimize the scale of destruction of the inverter system, and reduce the system recovery cost.

In particular, since the saturation current of the SiC- MOSFET is larger than that of the Si-IGBT, it is necessary to detect the arm short circuit at high speed and protect the element from the destruction in the inverter to which the SiC- MOSFET is applied. It is valid.

In order to determine whether or not an arm short circuit has occurred, a detection level is set inside the short circuit detection unit 13, and it can be determined whether or not the current value calculated from the Ve voltage exceeds the detection level. For example, the short-circuit current (saturation current) of a SiC- MOSFET is sufficiently larger than the rated drive current (for example, 15 times), so if the detection level is set to 2 to 3 times the rated value, it will be normally driven. High-speed detection is possible only when an arm short circuit occurs without false detection. Further, in FIG. 11, the short-circuit detection unit 13 and the gate cutoff unit 14 are shown only for the U-phase upper arm, but in order to provide the same configuration to the elements of all phases and all arms, for example, while the element of the lower arm is on, the upper arm is on. When the element of the arm is suddenly destroyed, the gate drive circuit 104d of the element of the lower arm can detect and cut off the arm short circuit, and has an advantage that the arm short circuit can be dealt with in all modes.

In addition, the failure prediction accuracy, the drive control, and the short circuit protection function may be improved by combining Examples 1 to 4.

1: Interface unit 2: Current detection unit 3: Relative comparison unit 4: Allowable fluctuation amount specification unit 5: Output unit 6: Storage unit 7: Comparison unit 8: Comparison timing specification unit 9: Drive control unit 10: First gate Current control unit 11: Second gate current control unit 12: Differential amplification unit 13: Short circuit detection unit 14: Gate cutoff unit 100: Power unit 101: Voltage-driven semiconductor element (IGBT, MOSFET, etc.)
102: Freewheeling diode 103: Filter capacitor 104: Gate drive circuit 105: Command logic unit 106: Motor 107: Overhead wire 108: Current collector 109: Breaker 110: Filter reactor 111: Wheel 112: Rail 113: Failure prediction unit 114: Power supply voltage 115: Ground potential G: Gate terminal of semiconductor element SS: Sense emitter terminal of semiconductor element MS: Emitter main terminal of semiconductor element Le: Parasitic inductance between SS and MS Ve: Terminal between SS and MS Intermittent voltage Vth: Threshold voltage of semiconductor element

Claims (22)

It is a method for monitoring the state of a plurality of semiconductor elements constituting each arm of a power conversion device.
The failure prediction unit of the power conversion device measures the Ve voltage between the sense emitter terminal and the emitter main terminal of the semiconductor element, and deteriorates from the relative change of the current and / or the Ve voltage flowing through the plurality of semiconductor elements. Alternatively, a state monitoring method for detecting the semiconductor element in which an abnormality has occurred. In the condition monitoring method according to claim 1,
A state monitoring method characterized in that a failure prediction unit or a current detection unit in a gate drive circuit of a power conversion device calculates a current flowing through the semiconductor element based on the Ve voltage. In the condition monitoring method according to claim 1,
A condition monitoring method in which the failure prediction unit directly compares the measured Ve voltage as it is. In the condition monitoring method according to any one of claims 1 to 3,
Based on the current difference ΔI or Ve voltage difference ΔV between the plurality of semiconductor elements corresponding to the permissible temperature difference between the plurality of semiconductor elements, the current value flowing through each semiconductor element is the average current value ± ΔI of each semiconductor element. Alternatively, the semiconductor element that deviates from the initial current value ± ΔI, or the semiconductor element whose Ve voltage value of each semiconductor element deviates from the average Ve value ± ΔVe of each semiconductor element or the initial Ve value ± ΔVe of each semiconductor element is deteriorated or abnormal. A state monitoring method characterized by detecting as a semiconductor element in which a current is generated. In the condition monitoring method according to any one of claims 1 to 4,
A condition monitoring method, wherein the failure prediction unit makes a relative comparison of the maximum values of current values or Ve voltage values flowing through the plurality of semiconductor elements at regular time intervals. In the condition monitoring method according to claim 5,
The state monitoring method, wherein the fixed time interval is a time interval of one cycle or more of the alternating current of the three-phase alternating current motor driven by the power conversion device. In the condition monitoring method according to any one of claims 1 to 6,
A condition monitoring method characterized in that a plurality of semiconductor elements are connected in parallel in the same arm of the power conversion device. In the condition monitoring method according to claim 7,
Based on the current difference ΔI or Ve voltage difference ΔV between the semiconductor elements connected in parallel, the gate drive current at the time of switching of each of the semiconductor elements connected in parallel is adjusted, and the current difference or Ve voltage difference between the parallel elements is adjusted. A state monitoring method characterized by reduction. In the condition monitoring method according to any one of claims 1 to 8,
A condition monitoring method characterized in that the semiconductor element is a SiC-PWM. In the condition monitoring method according to any one of claims 1 to 9,
When the gate drive circuit for driving the semiconductor element has a short-circuit detection unit and a gate cut-off unit, and the short-circuit detection unit detects that the current flowing through each semiconductor element exceeds a specified value, the failure prediction is performed. A state monitoring method comprising blocking the gate of the semiconductor element by the gate blocking section without going through the section and the command logic section above the gate drive circuit. In the condition monitoring method according to claim 10,
A condition monitoring method, wherein the specified value is a current value that exceeds the rated current of the semiconductor element. A power conversion device that constitutes each arm with a plurality of semiconductor elements.
The Ve voltage between the sense emitter terminal and the emitter main terminal of the semiconductor element is measured, and the semiconductor element whose deterioration or abnormality has occurred due to the relative change of the current and / or the Ve voltage flowing through the plurality of semiconductor elements is obtained. A power conversion device equipped with a failure prediction unit for detection. In the power conversion device according to claim 12,
A power conversion device characterized in that a failure prediction unit or a current detection unit on a gate drive circuit of the power conversion device calculates a current flowing through the semiconductor element based on the Ve voltage. In the power conversion device according to claim 12,
A power conversion device characterized in that the failure prediction unit directly compares the measured Ve voltage as it is. In the power conversion device according to any one of claims 12 to 14,
Based on the current difference ΔI or Ve voltage difference ΔVe between the plurality of semiconductor elements corresponding to the permissible temperature difference between the plurality of semiconductor elements, the current value flowing through each semiconductor element is the average current value ± ΔI of each semiconductor element or Deterioration or abnormality of a semiconductor element that deviates from the initial current value ± ΔI, or a semiconductor element whose Ve voltage value of each semiconductor element deviates from the average Ve value ± ΔVe of each semiconductor element or the initial Ve value ± ΔVe of each semiconductor element. A power conversion device characterized in that it is detected as a generated semiconductor element. The power conversion device according to any one of claims 12 to 15.
A power conversion device, wherein the failure prediction unit makes a relative comparison of the maximum values of current values or Ve voltage values flowing through the plurality of semiconductor elements at regular time intervals. In the power conversion device according to claim 16,
The power conversion device is characterized in that the fixed time interval is a time interval of one cycle or more of the AC current of the three-phase AC motor driven by the power conversion device. In the power conversion device according to any one of claims 12 to 17.
A power conversion device characterized in that a plurality of semiconductor elements are connected in parallel on the same arm. In the power conversion device according to claim 18,
The gate drive circuit of each of the semiconductor elements connected in parallel so as to reduce the current difference or Ve voltage difference between the parallel elements based on the current difference ΔI or Ve voltage difference ΔV between the semiconductor elements connected in parallel. A power conversion device characterized by adjusting the gate drive current during switching. In the power conversion device according to any one of claims 12 to 19.
A power conversion device characterized in that the semiconductor element is a SiC- MOSFET. In the power conversion device according to any one of claims 12 to 20,
When the current flowing through each semiconductor element exceeds a specified value, the gate drive circuit shuts off the gate of the semiconductor element without going through the failure prediction unit and the command logic unit above the gate drive circuit. A power conversion device characterized by. In the power conversion device according to claim 21,
A power conversion device characterized in that the specified value is a current value exceeding the rated current of the semiconductor element.

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