JP7082464B2 - Ultrasonic sensor - Google Patents

Description

The present invention relates to an ultrasonic sensor.

FIG. 23 of Patent Document 1 discloses an ultrasonic sensor element as an example of an ultrasonic sensor. This ultrasonic sensor element includes a semiconductor substrate having a surface on which an opening is formed. An insulating layer is formed on the surface of the semiconductor substrate. A lower electrode layer is formed on the insulating layer. A piezoelectric layer is formed on the lower electrode layer. An upper electrode layer is formed on the piezoelectric layer.
The lower electrode layer includes a region facing the opening of the semiconductor substrate with the insulating layer interposed therebetween and a region facing the surface of the semiconductor substrate with the insulating layer interposed therebetween. The upper electrode layer includes a region facing the lower electrode layer with the piezoelectric layer interposed therebetween, and a region facing the surface of the semiconductor substrate with the piezoelectric layer and the insulating layer interposed therebetween without interposing the lower electrode layer. ..

JP-A-2009-244234

The sensitivity of an ultrasonic sensor is expressed by a g constant (g = d / ε) defined by the ratio of the piezoelectric constant d to the dielectric constant ε of the piezoelectric body. The higher the g constant, the higher the sensitivity of the ultrasonic sensor. In the conventional ultrasonic sensor disclosed in FIG. 23 of Patent Document 1, the g constant is theoretically determined by the dielectric constant of the piezoelectric layer interposed between the lower electrode layer and the upper electrode layer.
However, in a conventional ultrasonic sensor, the lower electrode layer includes a first facing region facing the surface of the semiconductor substrate with the insulating layer interposed therebetween, while the upper electrode layer does not go through the lower electrode layer. A second facing region facing the surface of the semiconductor substrate with the piezoelectric layer and the insulating layer interposed therebetween is included.

Therefore, the first parasitic capacitance is formed in the first facing region, and the second parasitic capacitance is formed in the second facing region. The first parasitic capacitance and the second parasitic capacitance are electrically connected to each other via the substrate. Therefore, a parasitic capacitance circuit containing a first parasitic capacitance and a second parasitic capacitance is formed in the region between the substrate and the upper electrode layer.
As a result, the permittivity that determines the g constant may fluctuate due to the parasitic capacitance circuit. That is, in a conventional ultrasonic sensor, the sensitivity may fluctuate due to the parasitic capacitance.

Therefore, one object of the present invention is to provide an ultrasonic sensor capable of suppressing fluctuations in sensitivity.

The ultrasonic sensor according to the first aspect of the present invention includes a substrate having a main surface on which an opening is formed, a vibration plate formed on the main surface of the substrate and closing the opening, and the substrate. It has a first area in a plan view seen from the normal direction of the main surface of the above surface, and has a lower electrode layer formed on the vibrating plate and a first piezoelectric layer formed on the lower electrode layer. A second layer having a body layer and a second area which is equal to or less than the first area in the plan view, and formed on the first piezoelectric layer so as to be entirely overlapped with the lower electrode layer in the plan view. The first upper electrode layer includes one upper electrode layer, and the first upper electrode layer includes a first upper drawer portion that is drawn out to a region outside the opening in a plan view .

According to this ultrasonic sensor, the first upper electrode layer can be capacitively coupled to the lower electrode layer, while the first upper electrode layer can be electrically separated from the substrate.
As a result, it is possible to suppress the formation of parasitic capacitance in the region between the first upper electrode layer and the substrate. In addition, the parasitic capacitance formed in the region between the lower electrode layer and the substrate can be suppressed from being electrically connected to the first upper electrode layer. Therefore, it is possible to provide an ultrasonic sensor capable of suppressing a decrease in sensitivity.

The ultrasonic sensor according to the second aspect of the present invention includes a substrate having a main surface on which an opening is formed, a vibration plate formed on the main surface of the substrate and closing the opening, and vibration. The first lower electrode layer formed on the plate and formed in the region surrounded by the inner wall of the opening in a plan view from the normal direction of the main surface of the substrate, and the above. A second lower electrode layer formed on a vibrating plate and in a region surrounded by an inner wall of the opening in the plan view, the first lower electrode layer and the first. The second lower electrode layer is formed on the vibrating plate and the second lower electrode layer formed so as to be separated from each other in a plan view, and the first lower electrode layer and the second lower electrode layer are formed. It is formed on the first piezoelectric layer and the first piezoelectric layer, and overlaps the first lower electrode layer, the second lower electrode layer, and the opening in the plan view. Includes a first upper electrode layer formed.

According to this ultrasonic sensor, the first upper electrode layer can be capacitively coupled to the first lower electrode layer and the second lower electrode layer, while the first upper electrode layer is electrically separated from the substrate. be able to.
As a result, it is possible to suppress the formation of parasitic capacitance in the region between the first upper electrode layer and the substrate. In addition, the parasitic capacitance formed in the region between the first lower electrode layer and the substrate can be suppressed from being electrically connected to the first upper electrode layer. In addition, the parasitic capacitance formed in the region between the second lower electrode layer and the substrate can be suppressed from being electrically connected to the first upper electrode layer. Therefore, it is possible to provide an ultrasonic sensor capable of suppressing a decrease in sensitivity.

FIG. 1 is a plan view showing an ultrasonic sensor according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG. FIG. 3 is a cross-sectional view taken along the line III-III shown in FIG. FIG. 4 is an enlarged view of region IV shown in FIG. FIG. 5 is an enlarged view of the region V shown in FIG. FIG. 6 is a cross-sectional view showing an ultrasonic sensor according to a reference example. FIG. 7 is a circuit diagram showing an electrical structure of an ultrasonic sensor according to a reference example. FIG. 8 is a graph obtained by simulating the charge-voltage characteristics of an ultrasonic sensor according to a reference example. FIG. 9 is a graph obtained by simulation of the capacitance-voltage characteristics of an ultrasonic sensor according to a reference example. FIG. 10 is a circuit diagram showing an electrical structure of the ultrasonic sensor shown in FIG. FIG. 11 is a graph obtained by simulating the charge-voltage characteristics of the ultrasonic sensor shown in FIG. 1. FIG. 12 is a graph obtained by simulation of the capacitance-voltage characteristics of the ultrasonic sensor shown in FIG. FIG. 13A is a cross-sectional view for explaining a method for manufacturing an ultrasonic sensor shown in FIG. FIG. 13B is a cross-sectional view showing the process after FIG. 13A. FIG. 13C is a cross-sectional view showing the process after FIG. 13B. FIG. 13D is a cross-sectional view showing the process after FIG. 13C. FIG. 13E is a cross-sectional view showing the process after FIG. 13D. FIG. 13F is a cross-sectional view showing the process after FIG. 13E. FIG. 13G is a cross-sectional view showing the process after FIG. 13F. FIG. 13H is a cross-sectional view showing the process after FIG. 13G. FIG. 13I is a cross-sectional view showing the process after FIG. 13H. FIG. 13J is a cross-sectional view showing the process after FIG. 13I. FIG. 13K is a cross-sectional view showing the process after FIG. 13J. FIG. 13L is a cross-sectional view showing the process after FIG. 13K. FIG. 14 is a plan view showing an ultrasonic sensor according to a second embodiment of the present invention. FIG. 15 is a cross-sectional view taken along the line XV-XV shown in FIG. FIG. 16 is a cross-sectional view taken along the line XVI-XVI shown in FIG. FIG. 17 is a circuit diagram showing an electrical structure of the ultrasonic sensor shown in FIG. FIG. 18 is a plan view showing an ultrasonic sensor according to a third embodiment of the present invention. FIG. 19 is a cross-sectional view taken along the line XIX-XIX shown in FIG. FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. FIG. 21 is a plan view showing an ultrasonic sensor according to a fourth embodiment of the present invention. FIG. 22 is a cross-sectional view taken along the line XXII-XXII shown in FIG. FIG. 23 is a cross-sectional view taken along the line XXIII-XXIII shown in FIG. FIG. 24 is a circuit diagram showing the electrical structure of the ultrasonic sensor shown in FIG. 21. FIG. 25 is a plan view showing an ultrasonic sensor according to a fifth embodiment of the present invention. FIG. 26 is a cross-sectional view taken along the line XXVI-XXVI shown in FIG. FIG. 27 is a cross-sectional view taken along the line XXVII-XXVII shown in FIG. FIG. 28 is a cross-sectional view taken along the line XXVIII-XXVIII shown in FIG. FIG. 29 is a circuit diagram showing the electrical structure of the ultrasonic sensor shown in FIG. 25.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First Embodiment>
FIG. 1 is a plan view showing an ultrasonic sensor 1 according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG. FIG. 3 is a cross-sectional view taken along the line III-III shown in FIG. FIG. 4 is an enlarged view of region IV shown in FIG. FIG. 5 is an enlarged view of the region V shown in FIG.

The ultrasonic sensor 1 includes a sensor body 2 formed in a rectangular parallelepiped shape. The sensor body 2 includes a first main surface 3 on one side, a second main surface 4 on the other side, and a side surface 5 connecting the first main surface 3 and the second main surface 4. The second main surface 4 may be a ground surface. The side surface 5 may be a ground surface.
The first main surface 3 and the second main surface 4 of the sensor main body 2 have a rectangular shape (more specifically, a rectangular shape) in a plan view (hereinafter, simply referred to as “planar view”) when viewed from their normal directions. ) Is formed. The side surface 5 of the sensor body 2 extends along the normal direction of the first main surface 3 and the second main surface 4.

The length L along the long side of the sensor main body 2 may be 0.8 mm or more and 1.4 mm or less. The length W along the short side of the sensor main body 2 may be 0.8 mm or more and 1.4 mm or less.
The sensor main body 2 has a laminated structure including a substrate 10, a diaphragm 11, a piezoelectric element layer 12, a surface insulating layer 13, and a surface electrode layer 14. With this laminated structure, the first main surface 3, the second main surface 4, and the side surface 5 of the sensor main body 2 are formed.

The substrate 10 is formed in a rectangular parallelepiped shape. The substrate 10 includes a first substrate main surface 15 on one side, a second substrate main surface 16 on the other side, and a substrate side surface 17 connecting the first substrate main surface 15 and the second substrate main surface 16. The substrate 10 forms a part of the side surface 5 of the sensor main body 2 and the second main surface 4.
The substrate 10 may be made of a semiconductor substrate. The semiconductor substrate may include silicon, silicon carbide or a compound semiconductor. The compound semiconductor may include an oxide semiconductor (for example, gallium oxide), a nitride semiconductor (for example, gallium nitride), and the like. The semiconductor substrate is preferably made of silicon from the viewpoint of mass productivity.

An opening 21 is formed on the first substrate main surface 15 of the substrate 10. The opening 21 penetrates the substrate 10 along the thickness direction. The opening 21 is opened in each of the first substrate main surface 15 and the second substrate main surface 16.
The opening 21 is formed in the central portion of the first substrate main surface 15 in a plan view. The opening 21 may be formed in a square shape in a plan view. The four sides of the opening 21 may be formed parallel to the four substrate side surfaces 17 of the substrate 10, respectively.

The opening 21 may be formed in a polygonal shape such as a triangular shape or a hexagonal shape in a plan view. The opening 21 may be formed in a circular shape or an elliptical shape in a plan view.
The opening 21 may have an inner wall surface perpendicular to each of the first substrate main surface 15 and the second substrate main surface 16. The opening 21 may be formed in a tapered shape in which the opening width on the main surface 15 side of the first substrate is narrower than the opening width on the main surface 16 side of the second substrate.

The diaphragm 11 is formed in a film shape on the first substrate main surface 15 of the substrate 10. The diaphragm 11 covers almost the entire main surface 15 of the first substrate of the substrate 10. The diaphragm 11 has a closing portion 22 that closes the opening 21 and partitions the top surface portion of the opening 21.
The diaphragm 11 forms a part of the side surface 5 of the sensor main body 2. The diaphragm 11 has a side surface flush with respect to the substrate side surface 17 of the substrate 10. The thickness of the diaphragm 11 may be 30 μm or more and 80 μm or less (for example, about 45 μm).

The diaphragm 11 may have a single-layer structure including a silicon oxide (SiO ₂ ) layer, a silicon nitride (SiN) layer, or an aluminum nitride (AlN) layer. The diaphragm 11 may have a laminated structure including at least one of a silicon oxide layer, a silicon nitride layer, and an aluminum nitride layer.
The piezoelectric element layer 12 includes a lower electrode layer 23, a first piezoelectric layer 24, a first upper electrode layer 25, a second piezoelectric layer 26, and a second upper electrode layer 27, which are laminated in this order from the top of the vibrating plate 11. It has a laminated structure including.

The lower electrode layer 23 is formed on the diaphragm 11. In this form, the lower electrode layer 23 covers almost the entire diaphragm 11. The lower electrode layer 23 has a first area S1 in a plan view.
The lower electrode layer 23 faces the first substrate main surface 15 and the opening 21 of the substrate 10 with the diaphragm 11 interposed therebetween. The lower electrode layer 23 forms a part of the side surface 5 of the sensor body 2. The lower electrode layer 23 has a side surface flush with respect to the substrate side surface 17 of the substrate 10.

The lower electrode layer 23 may include a molybdenum (Mo) layer. The lower electrode layer 23 may be made of a molybdenum layer. The thickness of the lower electrode layer 23 may be 40 nm or more and 200 nm or less (for example, about 100 nm).
The first piezoelectric layer 24 is formed on the lower electrode layer 23. In this form, the first piezoelectric layer 24 covers almost the entire surface of the lower electrode layer 23. The first piezoelectric layer 24 forms a part of the side surface 5 of the sensor body 2. The first piezoelectric layer 24 has a side surface flush with respect to the substrate side surface 17 of the substrate 10.

The first piezoelectric layer 24 may include an aluminum nitride layer. The first piezoelectric layer 24 may be made of an aluminum nitride layer. The thickness of the first piezoelectric layer 24 may be 0.5 μm or more and 2 μm or less (for example, about 1 μm).
The first upper electrode layer 25 is formed on the first piezoelectric layer 24. The first upper electrode layer 25 has a second area S2 in a plan view. The second area S2 of the first upper electrode layer 25 is preferably the first area S1 or less (S2 ≦ S1) of the lower electrode layer 23. It is more preferable that the second area S2 of the first upper electrode layer 25 is less than the first area S1 (S2 <S1) of the lower electrode layer 23.

As a result, the entire first upper electrode layer 25 faces the lower electrode layer 23 in a plan view. The first upper electrode layer 25 is capacitively coupled to the lower electrode layer 23 with the first piezoelectric layer 24 interposed therebetween. The first piezoelectric element C1 for transmission or reception is formed by the capacitive coupling of the lower electrode layer 23 and the first upper electrode layer 25.
The first upper electrode layer 25 includes a first upper inner portion 30, a first upper drawer portion 31, and a second upper drawer portion 32.

The first upper inner portion 30 of the first upper electrode layer 25 is formed in a region surrounded by the inner wall of the opening 21 in a plan view. In a plan view, the entire first upper inner portion 30 overlaps the opening 21.
In a plan view, the area of the first upper inner portion 30 is equal to or less than the area of the opening 21. More specifically, in a plan view, the area of the first upper inner portion 30 is smaller than the area of the opening 21. The first upper inner portion 30 is formed only in the region surrounded by the inner wall surface of the opening 21 in a plan view. The first upper inner portion 30 does not overlap the substrate 10 in a plan view.

The first upper inner portion 30 is formed in a circular shape in a plan view. The first upper inner portion 30 may be formed in a polygonal shape such as a triangle shape, a quadrangular shape, or a hexagonal shape in a plan view. The first upper inner portion 30 may be formed in an elliptical shape in a plan view.
The first upper drawer portion 31 of the first upper electrode layer 25 is drawn out from the first upper inner portion 30 to the region outside the opening 21 in a plan view. In this embodiment, the first upper drawer portion 31 is pulled out in a strip shape from the first upper inner portion 30 toward the substrate side surface 17 on one side (upper side in FIG. 1) in the lateral direction of the substrate 10. The end portion of the first upper drawer portion 31 is formed in a region between the substrate side surface 17 and the opening 21 in a plan view.

The second upper drawer portion 32 of the first upper electrode layer 25 is drawn out from the first upper inner portion 30 to the region outside the opening 21 in a plan view. The second upper drawer portion 32 is pulled out in a direction intersecting the first upper drawer portion 31 in a plan view.
In this embodiment, the second upper drawer portion 32 is pulled out in a band shape from the first upper inner portion 30 toward the substrate side surface 17 on one side (left side in FIG. 1) in the longitudinal direction of the substrate 10. The end of the second upper drawer 32 is formed in the region between the substrate side surface 17 and the opening 21 in a plan view.

With reference to FIG. 4, the first upper electrode layer 25 includes an iridium (IrOx) layer 34, an iridium (Ir) layer 35, a titanium (Ti) layer 36, which are laminated in this order from the first piezoelectric layer 24 side. It has a laminated structure including a platinum (Pt) layer 37.
The thickness of the iridium oxide layer 34 may be 20 nm or more and 80 nm or less (for example, about 50 nm). The thickness of the iridium layer 35 may be 20 nm or more and 80 nm or less (for example, about 50 nm).

The thickness of the titanium layer 36 may be 5 nm or more and 35 nm or less (for example, about 20 nm). The thickness of the platinum layer 37 may be 100 nm or more and 300 nm or less (for example, about 200 nm).
The second piezoelectric layer 26 is formed on the first upper electrode layer 25. The second piezoelectric layer 26 has a shape that matches the shape of the first upper electrode layer 25 in a plan view. The second piezoelectric layer 26 includes a piezoelectric internal portion 40, a first piezoelectric pull-out portion 41, and a second piezoelectric lead-out portion 42.

The piezoelectric inner side 40, the first piezoelectric drawer 41, and the second piezoelectric drawer 42 of the second piezoelectric layer 26 are the first upper inner portion 30 of the first upper electrode layer 25 in a plan view, respectively. It has a shape consistent with the first upper drawer portion 31 and the second upper drawer portion 32.
The second piezoelectric layer 26 has a side surface flush with the side surface of the first upper electrode layer 25. The first upper electrode layer 25 and the second piezoelectric layer 26 form a mesa structure 43 on the first piezoelectric layer 24.

The second piezoelectric layer 26 may include a lead zirconate titanate (PbZr _x Ti _1-x O ₃ : PZT) layer. The second piezoelectric layer 26 may be made of a PZT layer. The thickness of the second piezoelectric layer 26 may be 0.8 μm or more and 2.0 μm or less (for example, about 1.0 μm).
The second upper electrode layer 27 is formed on the second piezoelectric layer 26. The second upper electrode layer 27 has a third area S3 in a plan view. The third area S3 of the second upper electrode layer 27 is equal to or less than the first area S1 of the lower electrode layer 23, and is equal to or less than the second area S2 of the first upper electrode layer 25 (S3 ≦ S2 ≦ S1). You may.

The third area S3 of the second upper electrode layer 27 is smaller than the first area S1 of the lower electrode layer 23, and is equal to or less than the second area S2 of the first upper electrode layer 25 (S3 ≦ S2 <S1). Is preferable. The third area S3 of the second upper electrode layer 27 is smaller than the first area S1 of the lower electrode layer 23 and less than the second area S2 of the first upper electrode layer 25 (S3 <S2 <S1). Is even more preferable.

In a plan view, the entire second upper electrode layer 27 overlaps the first upper electrode layer 25. The second upper electrode layer 27 is capacitively coupled to the first upper electrode layer 25 with the second piezoelectric layer 26 interposed therebetween. The second piezoelectric element C2 for transmission or reception is formed by the capacitive coupling of the first upper electrode layer 25 and the second upper electrode layer 27.
When the first piezoelectric element C1 is for reception, the second piezoelectric element C2 is for transmission. When the first piezoelectric element C1 is for transmission, the second piezoelectric element C2 is for reception.

The second upper electrode layer 27 includes a second upper inner portion 44 and a third upper drawer portion 45.
The second upper inner portion 44 of the second upper electrode layer 27 is formed on the piezoelectric inner side portion 40 of the second piezoelectric layer 26. In a plan view, the entire second upper inner portion 44 overlaps the opening 21. In a plan view, the area of the second upper inner portion 44 is equal to or less than the area of the opening 21. More specifically, the area of the second upper inner portion 44 in a plan view is smaller than the area of the opening 21.

The second upper inner portion 44 is formed only in the region surrounded by the inner wall surface of the opening 21 in a plan view. The peripheral edge of the second upper inner portion 44 is formed in a region inside the peripheral edge of the piezoelectric inner inner portion 40 of the second piezoelectric layer 26 in a plan view. The second upper inner portion 44 does not overlap the substrate 10 in a plan view.
The second upper inner portion 44 is formed in a circular shape in a plan view. The second upper inner portion 44 may be formed in a polygonal shape such as a triangular shape, a quadrangular shape, or a hexagonal shape in a plan view. The second upper inner portion 44 may be formed in an elliptical shape in a plan view.

The third upper drawer portion 45 of the second upper electrode layer 27 is formed on the second piezoelectric drawer portion 42 of the second piezoelectric layer 26. The third upper drawer portion 45 is drawn out from the second upper inner portion 44 to the region outside the opening 21 in a plan view.
The third upper drawer portion 45 is pulled out in a strip shape from the second upper inner portion 44 toward the substrate side surface 17 on one side (left side in FIG. 1) in the longitudinal direction of the substrate 10. The end portion of the third upper drawer portion 45 is formed in a region between the end portion and the opening portion 21 of the second upper drawer portion 32 of the first upper electrode layer 25 in a plan view.

In a plan view, the area of the third upper drawer portion 45 is equal to or smaller than the area of the first upper drawer portion 31 of the first upper electrode layer 25. More specifically, in a plan view, the area of the third upper drawer portion 45 is smaller than the area of the first upper drawer portion 31. In a plan view, the entire third upper drawer portion 45 overlaps with the first upper drawer portion 31.
With reference to FIG. 5, the second upper electrode layer 27 has a laminated structure including an iridium (IrOx) layer 46 and an iridium (Ir) layer 47 laminated in this order from the second piezoelectric layer 26 side. May be.

The thickness of the iridium oxide layer 46 may be 20 nm or more and 80 nm or less (for example, about 50 nm). The thickness of the iridium layer 47 may be 20 nm or more and 80 nm or less (for example, about 50 nm).
With reference to FIGS. 1 and 2, a lower pad opening 51 is formed in the first piezoelectric layer 24. The lower pad opening 51 penetrates the first piezoelectric layer 24 and exposes a part of the lower electrode layer 23 as a pad region.

In this embodiment, the lower pad opening 51 is a region opposite to the first upper drawer portion 31 of the first upper electrode layer 25 with respect to the first upper inner portion 30 of the first upper electrode layer 25 in a plan view. (That is, it is formed in the region on the other end side of the substrate 10).
With reference to FIGS. 1 and 3, the second piezoelectric layer 26 is formed with a first upper pad opening 52. The first upper pad opening 52 penetrates the second piezoelectric layer 26 and exposes a part of the first upper drawer portion 31 of the first upper electrode layer 25 as a pad region.

The surface insulating layer 13 is formed in a film shape along the surface of the first piezoelectric layer 24 and the surface of the mesa structure 43. The surface insulating layer 13 may include at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and an aluminum nitride layer.
The surface insulating layer 13 is formed in a film shape in the lower pad opening 51 along the inner wall of the lower pad opening 51 so as to expose the lower electrode layer 23. The surface insulating layer 13 is formed in a film shape in the first upper pad opening 52 along the inner wall of the first upper pad opening 52 so as to expose the first upper electrode layer 25.

With reference to FIGS. 1 and 2, a second upper pad opening 53 is formed in the surface electrode layer 14. The second upper pad opening 53 exposes a part of the first piezoelectric material extraction portion 41 of the second upper electrode layer 27 as a pad region.
The surface electrode layer 14 is formed on the surface insulating layer 13. The surface electrode layer 14 is a copper layer, an aluminum layer, a gold layer, a titanium layer, a titanium nitride layer, a titanium tungsten layer, an aluminum-copper alloy layer, an aluminum-silicon alloy layer, or an aluminum-silicon-copper alloy layer. It may contain at least one.

The surface electrode layer 14 may have a single-layer structure composed of an aluminum-copper alloy layer. The surface electrode layer 14 may have a laminated structure including a titanium nitride layer and an aluminum-silicon alloy layer laminated in this order on the surface insulating layer 13. The surface electrode layer 14 may have a laminated structure including a titanium tungsten layer and a gold layer laminated in this order on the surface insulating layer 13.

The surface electrode layer 14 includes a lower pad electrode layer 54, a first upper pad electrode layer 55, and a second upper pad electrode layer 56.
The lower pad electrode layer 54 is formed in an arbitrary region on the surface insulating layer 13. The lower pad electrode layer 54 includes an island-shaped lower pad region 57 and a line-shaped lower wiring region 58. The lower pad region 57 is formed in an arbitrary region on the surface insulating layer 13 in a square shape in a plan view.

The lower wiring region 58 is routed to a region between the lower pad region 57 and the lower electrode layer 23. The lower wiring region 58 is drawn out from the lower pad region 57 and enters the lower pad opening 51 from above the surface insulating layer 13.
The lower wiring region 58 is connected to the lower electrode layer 23 in the lower pad opening 51. The lower pad region 57 is electrically connected to the lower electrode layer 23 via the lower wiring region 58.

A lower pad electrode layer 54 that does not have a lower wiring region 58 may be adopted. In this case, the lower pad region 57 enters the lower pad opening 51 from above the surface insulating layer 13. The lower pad region 57 is directly connected to the lower electrode layer 23 within the lower pad opening 51.
The first upper pad electrode layer 55 is formed in an arbitrary region on the surface insulating layer 13. The first upper pad electrode layer 55 includes an island-shaped first upper pad region 59 and a line-shaped first upper wiring region 60. The first upper pad region 59 is formed in an arbitrary region on the surface insulating layer 13 in a square shape in a plan view.

The first upper wiring region 60 is routed to a region between the first upper pad region 59 and the first upper electrode layer 25. The first upper wiring region 60 is drawn out from the first upper pad region 59 and enters the first upper pad opening 52 from above the surface insulating layer 13.
The first upper wiring region 60 is connected to the first upper electrode layer 25 in the first upper pad opening 52. The first upper pad region 59 is electrically connected to the first upper electrode layer 25 via the first upper wiring region 60.

The first upper pad electrode layer 55 having no first upper wiring region 60 may be adopted. In this case, the first upper pad region 59 enters the first upper pad opening 52 from above the surface insulating layer 13. The first upper pad region 59 is directly connected to the first upper electrode layer 25 in the first upper pad opening 52.
The second upper pad electrode layer 56 is formed in an arbitrary region on the surface insulating layer 13. The second upper pad electrode layer 56 includes an island-shaped second upper pad region 61 and a line-shaped second upper wiring region 62. The second upper pad region 61 is formed in an arbitrary region on the surface insulating layer 13 in a square shape in a plan view.

The second upper wiring region 62 is routed to a region between the second upper pad region 61 and the second upper electrode layer 27. The second upper wiring region 62 is drawn out from the second upper pad region 61 and enters the second upper pad opening 53 from above the surface insulating layer 13.
The second upper wiring region 62 is connected to the second upper electrode layer 27 in the second upper pad opening 53. The second upper pad region 61 is electrically connected to the second upper electrode layer 27 via the second upper wiring region 62.

A second upper pad electrode layer 56 that does not have a second upper wiring region 62 may be adopted. In this case, the second upper pad region 61 enters the second upper pad opening 53 from above the surface insulating layer 13. The second upper pad region 61 is directly connected to the second upper electrode layer 27 in the second upper pad opening 53.
FIG. 6 is a cross-sectional view showing an ultrasonic sensor 65 according to a reference example. In FIG. 6, the same structure as that of the ultrasonic sensor 1 is designated by the same reference numeral, and the description thereof will be omitted.

With reference to FIG. 6, in the ultrasonic sensor 65 according to the reference example, the lower electrode layer 23 is formed on the diaphragm 11 so as to expose a part of the region of the diaphragm 11.
The first upper electrode layer 25 is formed on the first piezoelectric layer 24 so as to expose a part of the region of the first piezoelectric layer 24. A part of the region of the first upper electrode layer 25 faces the substrate 10 without sandwiching the lower electrode layer 23. The second piezoelectric layer 26 covers the entire surface of the first upper electrode layer 25. Therefore, the mesa structure 43 is not formed.

The second upper electrode layer 27 is formed on the second piezoelectric layer 26 so as to expose a part of the region of the second piezoelectric layer 26. A part of the region of the second upper electrode layer 27 faces the substrate 10 without sandwiching the first upper electrode layer 25 and the lower electrode layer 23.
The lower pad opening 51 penetrates the second piezoelectric layer 26, the first upper electrode layer 25, and the first piezoelectric layer 24, and exposes a part of the lower electrode layer 23. Although not shown, the first upper pad opening 52 penetrates the second piezoelectric layer 26 and exposes a part of the first upper electrode layer 25.

The surface insulating layer 13 is formed in a film shape along the surface of the second piezoelectric layer 26 so as to cover the second upper electrode layer 27. The surface insulating layer 13 is formed in a film shape along the inner wall surface of the lower pad opening 51 so as to expose the lower electrode layer 23.
The surface insulating layer 13 is formed in a film shape along the inner wall surface of the first upper pad opening 52 so as to expose the first upper electrode layer 25. The second upper pad opening 53 penetrates the surface insulating layer 13 and exposes a part of the second upper electrode layer 27.

FIG. 7 is a circuit diagram showing an electrical structure of an ultrasonic sensor 65 according to a reference example.
In the ultrasonic sensor 65 according to the reference example with reference to FIGS. 6 and 7, a first piezoelectric element C1 for transmission or reception is formed by capacitive coupling of the lower electrode layer 23 and the first upper electrode layer 25. Has been done. Further, the second piezoelectric element C2 for transmission or reception is formed by the capacitive coupling of the first upper electrode layer 25 and the second upper electrode layer 27.

In the ultrasonic sensor 65 according to the reference example, the parasitic capacitance Cp1 is formed in the region where the first upper electrode layer 25 faces the substrate 10 without sandwiching the lower electrode layer 23. Parasitic capacitance Cp1 may also include capacitance due to the depletion layer formed on the surface layer portion of the substrate 10.
Further, a parasitic capacitance Cp2 is formed in a region where the second upper electrode layer 27 faces the substrate 10 without sandwiching the first upper electrode layer 25 and the lower electrode layer 23.

A parasitic capacitance Cp3 is formed in a region where the lower electrode layer 23 faces the substrate 10 with the diaphragm 11 interposed therebetween. Parasitic capacitance Cp3 may also include capacitance due to the depletion layer formed on the surface layer portion of the substrate 10.
The parasitic capacitance Cp1, the parasitic capacitance Cp2 and the parasitic capacitance Cp3 are electrically connected to each other via the substrate 10. As a result, a parasitic capacitance circuit including the parasitic capacitance Cp1, the parasitic capacitance Cp2 and the parasitic capacitance Cp3 is formed in the region between the substrate 10 and the surface electrode layer 14.

FIG. 8 is a graph obtained by simulating the charge Q-voltage V characteristics of the ultrasonic sensor 65 according to the reference example. In FIG. 8, the vertical axis is the charge Q [μC · cm ^-2 ] and the horizontal axis is the voltage V [V].
Here, the change in charge Q when the applied voltage V between the lower electrode layer 23 and the first upper electrode layer 25 was continuously changed in the order of 0V, -30V, 0V, and + 30V was investigated. With reference to FIG. 8, it was found that the charge amount of the ultrasonic sensor 65 according to the reference example draws a hysteresis curve according to the fluctuation of the applied voltage V.

FIG. 9 is a graph obtained by simulating the capacitance C-voltage V characteristics of the ultrasonic sensor 65 according to the reference example. In FIG. 9, the vertical axis is the capacitance C [pF], and the horizontal axis is the voltage V [V].
Here, the change in capacitance C when the applied voltage V between the lower electrode layer 23 and the first upper electrode layer 25 was continuously changed in the order of 0V, -30V, 0V, and + 30V was investigated. With reference to FIG. 9, it was found that the capacitance C of the ultrasonic sensor 65 according to the reference example draws a hysteresis curve according to the fluctuation of the applied voltage V.

According to the ultrasonic sensor 65 according to the reference example with reference to FIGS. 8 and 9, it was found that the charge Q-voltage V characteristic and the capacitance C-voltage V characteristic are both non-linear. That is, according to the ultrasonic sensor 65 according to the reference example, it was found that the sensitivity fluctuates.
The sensitivity of an ultrasonic sensor is expressed by a g constant (g = d / ε) defined by the ratio of the piezoelectric constant d to the dielectric constant ε of the piezoelectric body. The higher the g constant, the higher the sensitivity of the ultrasonic sensor. In the ultrasonic sensor 65 according to the reference example, the g constant is theoretically determined by the dielectric constant of the first piezoelectric layer 24 interposed between the lower electrode layer 23 and the first upper electrode layer 25.

However, in the ultrasonic sensor 65 according to the reference example, a parasitic capacitance circuit (see FIG. 7) including a parasitic capacitance Cp1, a parasitic capacitance Cp2, and a parasitic capacitance Cp3 is formed in a region between the substrate 10 and the surface electrode layer 14. There is. As a result, it is considered that the sensitivity fluctuated due to the parasitic capacitance circuit.
FIG. 10 is a circuit diagram showing an electrical structure of the ultrasonic sensor 1 shown in FIG. The electrical structure of an ultrasonic sensor 1 is shown by a solid line portion.

With reference to FIGS. 2 and 10, in the ultrasonic sensor 1, the first piezoelectric element C1 for transmission or reception is formed by the capacitive coupling of the lower electrode layer 23 and the first upper electrode layer 25. Further, the second piezoelectric element C2 for transmission or reception is formed by the capacitive coupling of the first upper electrode layer 25 and the second upper electrode layer 27.
In the ultrasonic sensor 1, the entire first upper electrode layer 25 overlaps with the lower electrode layer 23 in a plan view. Therefore, the entire first upper electrode layer 25 is capacitively coupled to the lower electrode layer 23 with the first piezoelectric layer 24 interposed therebetween. As a result, the formation of the parasitic capacitance Cp1 is suppressed in the region between the substrate 10 and the first upper electrode layer 25.

Further, in the ultrasonic sensor 1, the entire second upper electrode layer 27 overlaps with the first upper electrode layer 25 in a plan view. Therefore, the entire second upper electrode layer 27 is capacitively coupled to the first upper electrode layer 25 with the second piezoelectric layer 26 interposed therebetween. As a result, the formation of the parasitic capacitance Cp2 is suppressed in the region between the substrate 10 and the second upper electrode layer 27.
Moreover, the lower electrode layer 23 covers the entire surface of the diaphragm 11. As a result, the substrate 10 can be appropriately electrically separated from the first upper electrode layer 25 and the second upper electrode layer 27.

Therefore, the parasitic capacitance Cp3 formed in the region between the lower electrode layer 23 and the substrate 10 is electrically open and does not function. As described above, the ultrasonic sensor 1 can suppress the formation of the parasitic capacitance circuit. The charge Q-voltage V characteristic and the capacitance C-voltage V characteristic of the ultrasonic sensor 1 are shown in FIGS. 11 and 12, respectively.
FIG. 11 is a graph obtained by simulating the charge Q-voltage V characteristics of the ultrasonic sensor 1 shown in FIG. In FIG. 11, the vertical axis is the charge Q [μC · cm ^-2 ] and the horizontal axis is the voltage V [V].

Here, the change in charge Q when the applied voltage V between the lower electrode layer 23 and the first upper electrode layer 25 was continuously changed in the order of 0V, -30V, 0V, and + 30V was investigated. With reference to FIG. 11, it was found that the amount of charge Q of the ultrasonic sensor 1 fluctuates linearly according to the fluctuation of the applied voltage V.
FIG. 12 is a graph obtained by simulating the capacitance C-voltage V characteristics of the ultrasonic sensor 1 shown in FIG. In FIG. 12, the vertical axis is the capacitance C [pF] and the horizontal axis is the voltage V [V].

Here, the change in capacitance C when the applied voltage V between the lower electrode layer 23 and the first upper electrode layer 25 was continuously changed in the order of 0V, -30V, 0V, and + 30V was investigated. With reference to FIG. 12, it was found that the capacitance C of the ultrasonic sensor 1 fluctuates linearly according to the fluctuation of the applied voltage V.
With reference to FIGS. 11 and 12, according to the ultrasonic sensor 1, it was found that the charge Q-voltage V characteristic and the capacitance C-voltage V characteristic are both linear. From this, it was found that fluctuations in the sensitivity of ultrasonic sensors can be suppressed by suppressing the formation of parasitic capacitance.

As described above, according to the present embodiment, it is possible to provide an ultrasonic sensor 1 capable of suppressing a decrease in sensitivity due to parasitic capacitance.
13A to 13L are cross-sectional views for explaining an example of the manufacturing method of the ultrasonic sensor 1 shown in FIG. 1.
First, a disc-shaped wafer 81 is prepared with reference to FIG. 13A. The wafer 81 may be a semiconductor wafer. The semiconductor wafer may contain silicon.

The wafer 81 has a first wafer main surface 82 on one side and a second wafer main surface 83 on the other side. The first wafer main surface 82 and the second wafer main surface 83 of the wafer 81 correspond to the first substrate main surface 15 and the second substrate main surface 16 of the substrate 10, respectively.
Next, a plurality of sensor forming regions 84 are set on the wafer 81. Each of the plurality of sensor forming regions 84 is a region in which an ultrasonic sensor 1 is formed. In FIG. 13A, only one sensor forming region 84 out of the plurality of sensor forming regions 84 is shown (hereinafter, the same in FIGS. 13B to 13L).

Next, with reference to FIG. 13B, the diaphragm 11 is formed on the first wafer main surface 82 of the wafer 81. The diaphragm 11 is formed on the entire surface of the first wafer main surface 82 of the wafer 81. The step of forming the diaphragm 11 may include a step of forming an aluminum nitride layer on the first wafer main surface 82 of the wafer 81 by a sputtering method.
Next, with reference to FIG. 13C, the lower electrode layer 23 is formed on the diaphragm 11. The lower electrode layer 23 is formed on the entire surface of the diaphragm 11. The step of forming the lower electrode layer 23 may include a step of forming a molybdenum layer on the entire surface of the first wafer main surface 82 of the wafer 81 by a sputtering method.

Next, with reference to FIG. 13D, the first piezoelectric layer 24 is formed on the lower electrode layer 23. The first piezoelectric layer 24 is formed on the entire surface of the lower electrode layer 23. The step of forming the first piezoelectric layer 24 may include a step of forming an aluminum nitride layer on the diaphragm 11 by a sputtering method.
Next, with reference to FIG. 13E, the first upper electrode layer 25 is formed on the first piezoelectric layer 24. The first upper electrode layer 25 is formed on the entire surface of the first piezoelectric layer 24. The step of forming the first upper electrode layer 25 includes a step of forming the iridium oxide layer 34, the iridium layer 35, the titanium layer 36, and the platinum layer 37 in this order from the first piezoelectric layer 24 side by a sputtering method. May be good.

In this step, the iridium oxide layer 34 may be formed on the entire surface of the second piezoelectric layer 26. The iridium layer 35 may be formed on the entire surface of the surface of the iridium oxide layer 34. The titanium layer 36 may be formed on the entire surface of the iridium layer 35. The platinum layer 37 may be formed on the entire surface of the titanium layer 36.
Next, with reference to FIG. 13F, the second piezoelectric layer 26 is formed on the first upper electrode layer 25. The second piezoelectric layer 26 is formed on the entire surface of the first upper electrode layer 25. The step of forming the second piezoelectric layer 26 may include a step of forming an aluminum nitride layer on the first piezoelectric layer 24 by a sputtering method.

Next, with reference to FIG. 13G, the second upper electrode layer 27 is formed on the second piezoelectric layer 26. The step of forming the second upper electrode layer 27 may include a step of forming the iridium oxide layer 46 and the iridium layer 47 from the second piezoelectric layer 26 side in this order by a sputtering method.
In this step, the iridium oxide layer 46 may be formed on the entire surface of the second piezoelectric layer 26. The iridium layer 47 may be formed on the entire surface of the iridium oxide layer 46.

Next, a first resist mask 85 having a predetermined pattern is formed on the second upper electrode layer 27. Next, an unnecessary portion of the second upper electrode layer 27 is removed by an etching method via the first resist mask 85. As a result, the second upper electrode layer 27 having a predetermined pattern is formed. After that, the first resist mask 85 is removed.
Next, with reference to FIG. 13H, a second resist mask 86 having a predetermined pattern is formed on the second piezoelectric layer 26. The second resist mask 86 covers the region where the mesa structure 43 should be formed.

Next, the unnecessary portion of the second piezoelectric layer 26 and the unnecessary portion of the first upper electrode layer 25 are removed by the etching method via the second resist mask 86. As a result, the mesa structure 43 is formed. After that, the second resist mask 86 is removed.
Next, with reference to FIG. 13I, a third resist mask 87 having a predetermined pattern is formed on the first piezoelectric layer 24. The third resist mask 87 has an opening 88 that covers the mesa structure 43 and exposes the region where the lower pad opening 51 should be formed.

Next, an unnecessary portion of the first piezoelectric layer 24 is removed by an etching method via a third resist mask 87. As a result, the lower pad opening 51 is formed. After that, the third resist mask 87 is removed.
Next, with reference to FIG. 13J, the surface insulating layer 13 is formed in a film shape along the surface of the first piezoelectric layer 24 and the surface of the mesa structure 43. Further, the surface insulating layer 13 is formed in a film shape along the inner wall surface of the lower pad opening 51 and the surface of the lower electrode layer 23.

Next, a fourth resist mask 89 having a predetermined pattern is formed on the surface insulating layer 13. The fourth resist mask 89 includes a first opening 90 and a second opening 91. The first opening 90 exposes a region of the surface insulating layer 13 that covers the lower electrode layer 23. The second opening 91 exposes a region of the surface insulating layer 13 that covers the third upper drawer portion 45 of the second upper electrode layer 27.

Next, an unnecessary portion of the surface insulating layer 13 is removed by an etching method via the fourth resist mask 89. The lower electrode layer 23 and the second upper electrode layer 27 are each formed as an etching stopper layer for etching of the surface insulating layer 13. As a result, the lower electrode layer 23 is exposed from the surface insulating layer 13. Further, the second upper electrode layer 27 is exposed from the surface insulating layer 13. After that, the fourth resist mask 89 is removed.

Next, with reference to FIG. 13K, the surface electrode layer 14 is formed on the surface insulating layer 13. The step of forming the surface electrode layer 14 may include a step of forming an electrode layer on the entire surface of the surface insulating layer 13 by a sputtering method.
The step of forming the surface electrode layer 14 may include a step of forming the electrode layer into a predetermined pattern by an etching method using a mask. As a result, the surface electrode layer 14 including the lower pad electrode layer 54, the first upper pad electrode layer 55, and the second upper pad electrode layer 56 is formed.

Next, the second wafer main surface 83 of the wafer 81 is ground. The grinding step of the wafer 81 is executed until the thickness of the wafer 81 becomes a desired thickness.
Next, with reference to FIG. 13L, a fifth resist mask 92 that covers the second wafer main surface 83 and has a predetermined pattern is formed on the second wafer main surface 83 side of the wafer 81. The fifth resist mask 92 includes an opening 93 that exposes a region to form the opening 21.

Next, an unnecessary portion of the wafer 81 is removed by an etching method via a fifth resist mask 92. The diaphragm 11 is formed as an etching stopper layer for etching the wafer 81. As a result, the opening 21 that exposes the diaphragm 11 is formed in the wafer 81. After that, the fifth resist mask 92 is removed.
After that, the wafer 81 is cut along the peripheral edge of the plurality of sensor forming regions 84. As a result, a plurality of ultrasonic sensors 1 are cut out from one wafer 81. Through the above steps, an ultrasonic sensor 1 is formed.
<Second Embodiment>
FIG. 14 is a plan view showing an ultrasonic sensor 101 according to a second embodiment of the present invention. FIG. 15 is a cross-sectional view taken along the line XV-XV shown in FIG. FIG. 16 is a cross-sectional view taken along the line XVI-XVI shown in FIG.

In the following, the same reference numerals will be given to the same configurations as those described in the first embodiment, and the description thereof will be omitted.
With reference to FIGS. 14 to 16, the piezoelectric element layer 12 has a laminated structure further including an intermediate electrode layer 102 and an intermediate piezoelectric layer 103. The intermediate electrode layer 102 and the intermediate piezoelectric layer 103 are formed in the region between the first piezoelectric layer 24 and the mesa structure 43.

The intermediate electrode layer 102 is formed on the first piezoelectric layer 24 in the region between the first piezoelectric layer 24 and the mesa structure 43. The intermediate electrode layer 102 has a fourth area S4 in a plan view.
The fourth area S4 of the intermediate electrode layer 102 is preferably the first area S1 or less (S4 ≦ S1) of the lower electrode layer 23. It is more preferable that the fourth area S4 of the intermediate electrode layer 102 is less than the first area S1 (S4 <S1) of the lower electrode layer 23.

In a plan view, the entire intermediate electrode layer 102 overlaps the lower electrode layer 23. The intermediate electrode layer 102 is capacitively coupled to the lower electrode layer 23 with the first piezoelectric layer 24 interposed therebetween. The first piezoelectric element C11 for transmission or reception is formed by the capacitive coupling of the intermediate electrode layer 102 and the first upper electrode layer 25.
The intermediate electrode layer 102 includes an intermediate inner portion 104 and an intermediate drawer portion 105. The intermediate inner portion 104 of the intermediate electrode layer 102 is formed in a region surrounded by the inner wall surface of the opening 21 in a plan view. In plan view, the entire intermediate inner portion 104 overlaps the opening 21.

In a plan view, the area of the intermediate inner portion 104 is equal to or smaller than the area of the opening 21. More specifically, the area of the intermediate inner portion 104 in the plan view is smaller than the area of the opening 21. The intermediate inner portion 104 is formed only in the region surrounded by the inner wall surface of the opening 21 in a plan view. The intermediate inner portion 104 does not overlap the substrate 10 in a plan view.
The intermediate inner portion 104 is formed in a circular shape in a plan view. The intermediate inner portion 104 may be formed in a polygonal shape such as a triangular shape, a square shape, or a hexagonal shape in a plan view. The intermediate inner portion 104 may be formed in an elliptical shape in a plan view.

The intermediate drawer portion 105 of the intermediate electrode layer 102 is drawn out from the intermediate inner portion 104 to the region outside the opening 21 in a plan view. In this embodiment, the intermediate drawer portion 105 is drawn out in a band shape from the intermediate inner portion 104 toward the substrate side surface 17 on one side (left side in FIG. 14) in the longitudinal direction of the substrate 10. The end of the intermediate drawer 105 is formed in the region between the substrate side surface 17 and the opening 21 in a plan view.

The intermediate electrode layer 102 may include a molybdenum (Mo) layer. The intermediate electrode layer 102 may be made of a molybdenum layer. The thickness of the intermediate electrode layer 102 may be 40 nm or more and 200 nm or less (for example, about 100 nm).
The intermediate piezoelectric layer 103 of the intermediate electrode layer 102 is formed on the first piezoelectric layer 24 so as to cover the intermediate electrode layer 102 in the region between the first piezoelectric layer 24 and the mesa structure 43. ..

In this form, the intermediate piezoelectric layer 103 covers almost the entire surface of the intermediate electrode layer 102. The intermediate piezoelectric layer 103 forms a part of the side surface 5 of the sensor body 2. The intermediate piezoelectric layer 103 has a side surface flush with respect to the side surface 17 of the substrate.
The intermediate piezoelectric layer 103 may include an aluminum nitride layer. The intermediate piezoelectric layer 103 may be made of an aluminum nitride layer. The thickness of the intermediate piezoelectric layer 103 may be 0.5 μm or more and 1.5 μm or less (for example, about 1.0 μm).

The first upper electrode layer 25 is formed on the intermediate piezoelectric layer 103. In a plan view, the second area S2 of the first upper electrode layer 25 is preferably the fourth area S4 or less (S2 ≦ S4) of the intermediate electrode layer 102.
It is more preferable that the second area S2 of the first upper electrode layer 25 is less than the fourth area S4 (S2 <S4) of the intermediate electrode layer 102. In a plan view, the entire first upper electrode layer 25 overlaps the intermediate electrode layer 102.

The first upper electrode layer 25 includes a first upper inner portion 30. Further, the first upper electrode layer 25 includes a first upper drawer portion 106 in place of the first upper drawer portion 31 and the second upper drawer portion 32.
The first upper inner portion 30 of the first upper electrode layer 25 is formed in a region surrounded by the inner wall surface of the opening 21 in a plan view. The first upper inner portion 30 overlaps the intermediate inner portion 104 of the intermediate electrode layer 102 in a plan view.

In a plan view, the area of the first upper inner portion 30 is equal to or smaller than the area of the intermediate inner portion 104 of the intermediate electrode layer 102. More specifically, in a plan view, the area of the first upper inner portion 30 is smaller than the area of the intermediate inner portion 104. The entire first upper inner portion 30 in the plan view overlaps the intermediate inner portion 104 in the plan view. In a plan view, the first upper inner portion 30 does not overlap the substrate 10.

The first upper drawer portion 106 of the first upper electrode layer 25 is drawn out from the first upper inner portion 30 to the region outside the opening 21 in a plan view.
In this embodiment, the first upper drawer portion 106 is pulled out in a band shape from the first upper inner portion 30 toward the substrate side surface 17 on one side (upper side in FIG. 14) in the longitudinal direction of the substrate 10. The end portion of the first upper drawer portion 106 is formed in a region between the end portion and the opening portion 21 of the intermediate drawer portion 105 of the intermediate electrode layer 102 in a plan view.

In a plan view, the area of the first upper drawer portion 106 is equal to or smaller than the area of the intermediate drawer portion 105 of the intermediate electrode layer 102. More specifically, in a plan view, the area of the first upper drawer portion 106 is smaller than the area of the intermediate drawer portion 105. In a plan view, the entire first upper drawer portion 106 overlaps with the intermediate drawer portion 105.
The second piezoelectric layer 26 has a shape that matches the shape of the first upper electrode layer 25 in a plan view. The second piezoelectric layer 26 includes the piezoelectric internal portion 40. The second piezoelectric layer 26 includes a piezoelectric pull-out portion 107 in place of the first piezoelectric pull-out portion 41 and the second piezoelectric pull-out portion 42.

The piezoelectric body side portion 40 and the piezoelectric body drawer portion 107 have shapes that match the first upper inner portion 30 and the first upper drawer portion 106 of the first upper electrode layer 25, respectively, in a plan view. The first upper electrode layer 25 and the second piezoelectric layer 26 form a mesa structure 43 on the intermediate piezoelectric layer 103.
The second upper electrode layer 27 is formed on the second piezoelectric layer 26. The second upper electrode layer 27 has a third area S3 in a plan view. The third area S3 of the second upper electrode layer 27 is smaller than the second area S2 (S3 <S2) of the first upper electrode layer 25. In a plan view, the entire second upper electrode layer 27 overlaps the first upper electrode layer 25.

The second upper electrode layer 27 includes a second upper inner portion 44. Further, the second upper electrode layer 27 includes a second upper drawer portion 108 instead of the third upper drawer portion 45.
The second upper inner portion 44 of the second upper electrode layer 27 is formed in a region surrounded by the inner wall surface of the opening 21 in a plan view. The second upper inner portion 44 overlaps the first upper inner portion 30 of the first upper electrode layer 25 in a plan view.

In a plan view, the area of the second upper inner portion 44 is smaller than the area of the piezoelectric inner portion 40 of the intermediate piezoelectric layer 103. More specifically, in a plan view, the area of the second upper inner portion 44 is smaller than the area of the piezoelectric inner portion 40. In a plan view, the entire second upper inner portion 44 overlaps the first upper inner portion 30 of the first upper electrode layer 25. The second upper inner portion 44 does not overlap the substrate 10 in a plan view.

The second upper drawer portion 108 is pulled out from the second upper inner portion 44 to the region outside the opening 21 in a plan view. In this embodiment, the second upper drawer portion 108 is pulled out in a strip shape from the second upper inner portion 44 toward the substrate side surface 17 on one side (left side in FIG. 14) in the longitudinal direction of the substrate 10.
The second upper drawer portion 108 of the second upper electrode layer 27 is formed on the piezoelectric drawer portion 107 of the intermediate piezoelectric layer 103. The end of the second upper drawer 108 is formed in the region between the end of the piezoelectric drawer 107 and the opening 21 in a plan view.

In a plan view, the area of the second upper drawer portion 108 is less than or equal to the area of the piezoelectric drawer portion 107 of the intermediate piezoelectric layer 103. More specifically, in a plan view, the area of the second upper drawer portion 108 is smaller than the area of the piezoelectric material drawer portion 107. In a plan view, the entire second upper drawer portion 108 overlaps the piezoelectric material drawer portion 107.
The lower pad opening 51 penetrates the intermediate piezoelectric layer 103 and the first piezoelectric layer 24 to expose a part of the lower electrode layer 23 as a pad region. An intermediate pad opening 109 is formed in the intermediate piezoelectric layer 103. The intermediate pad opening 109 penetrates the intermediate piezoelectric layer 103 to expose a part of the intermediate lead-out portion 105 of the intermediate electrode layer 102 as a pad region.

The surface insulating layer 13 is formed in a film shape in the lower pad opening 51 along the inner wall of the lower pad opening 51 so as to expose the lower electrode layer 23. Further, the surface insulating layer 13 is formed in a film shape along the inner wall of the intermediate pad opening 109 so as to expose a part of the intermediate drawer portion 105 of the intermediate electrode layer 102 in the intermediate pad opening 109.
In a plan view, the first upper pad opening 52, the second upper pad opening 53, and the intermediate pad opening 109 are formed on the same straight line with a gap from each other. The first upper pad opening 52, the second upper pad opening 53, and the intermediate pad opening 109 are formed on the same straight line extending along the longitudinal direction of the substrate 10 in this form.

The surface electrode layer 14 further includes an intermediate pad electrode layer 110. The intermediate pad electrode layer 110 is formed in an arbitrary region on the surface insulating layer 13. The intermediate pad electrode layer 110 includes an island-shaped intermediate pad region 111 and a line-shaped intermediate wiring region 112. The intermediate pad region 111 is formed in an arbitrary region on the surface insulating layer 13 in a square shape in a plan view.

The intermediate wiring region 112 is routed to the region between the intermediate pad region 111 and the intermediate electrode layer 102. The intermediate wiring region 112 is drawn out from the intermediate pad region 111 and enters the intermediate pad opening 109 from above the surface insulating layer 13.
The intermediate wiring region 112 is connected to the intermediate electrode layer 102 in the intermediate pad opening 109. As a result, the intermediate pad region 111 is electrically connected to the intermediate electrode layer 102 via the intermediate wiring region 112.

An intermediate pad electrode layer 110 having no intermediate wiring region 112 may be adopted. In this case, the intermediate pad region 111 enters the intermediate pad opening 109 from above the surface insulating layer 13. The intermediate pad region 111 is directly connected to the intermediate electrode layer 102 in the intermediate pad opening 109.
FIG. 17 is a circuit diagram showing an electrical structure of the ultrasonic sensor 101 shown in FIG. The electrical structure of an ultrasonic sensor 101 is shown by a solid line portion.

With reference to FIGS. 15 and 17, in the ultrasonic sensor 101, the first piezoelectric element C11 for transmission or reception is formed by the capacitive coupling of the lower electrode layer 23 and the intermediate electrode layer 102. The second piezoelectric element C12 for transmission or reception is formed by the capacitive coupling of the intermediate electrode layer 102 and the first upper electrode layer 25.
In the ultrasonic sensor 101, the entire intermediate electrode layer 102 overlaps with the lower electrode layer 23 in a plan view. Therefore, the entire intermediate electrode layer 102 is capacitively coupled to the lower electrode layer 23 with the first piezoelectric layer 24 interposed therebetween. As a result, the formation of the parasitic capacitance Cp11 is suppressed in the region between the substrate 10 and the intermediate electrode layer 102.

Further, in the ultrasonic sensor 101, the entire first upper electrode layer 25 overlaps with the lower electrode layer 23 in a plan view. Further, in a plan view, the entire first upper electrode layer 25 overlaps with the intermediate electrode layer 102.
As a result, the formation of the parasitic capacitance Cp12 is suppressed in the region between the first upper electrode layer 25 and the intermediate electrode layer 102. Further, in the region between the substrate 10 and the first upper electrode layer 25, the formation of the parasitic capacitance Cp13 is suppressed.

Further, in the ultrasonic sensor 101, the entire second upper electrode layer 27 overlaps with the lower electrode layer 23 in a plan view. More specifically, in a plan view, the entire second upper electrode layer 27 overlaps with the first upper electrode layer 25.
Therefore, the entire second upper electrode layer 27 is capacitively coupled to the first upper electrode layer 25 with the second piezoelectric layer 26 interposed therebetween. As a result, the formation of the parasitic capacitance Cp14 is suppressed in the region between the substrate 10 and the second upper electrode layer 27.

Moreover, the lower electrode layer 23 covers the entire surface of the diaphragm 11. As a result, the substrate 10 is electrically separated from the intermediate electrode layer 102, the first upper electrode layer 25, and the second upper electrode layer 27.
Therefore, the parasitic capacitance Cp15 formed in the region between the lower electrode layer 23 and the substrate 10 is electrically open and does not function. As described above, in the ultrasonic sensor 101, the formation of the parasitic capacitance circuit is suppressed, so that the decrease in sensitivity due to the parasitic capacitance can be suppressed.
<Third Embodiment>
FIG. 18 is a plan view showing an ultrasonic sensor 121 according to a third embodiment of the present invention. FIG. 19 is a cross-sectional view taken along the line XIX-XIX shown in FIG. FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG.

In the following, the same reference numerals will be given to the same configurations as those described in the second embodiment, and the description thereof will be omitted.
With reference to FIGS. 18 to 20, in the ultrasonic sensor 121, in a plan view, the entire intermediate electrode layer 102, the entire first upper electrode layer 25, the entire second piezoelectric layer 26, and the second upper electrode layer 27 are used. Each of the above is formed in the area surrounded by the inner wall of the opening 21.

Further, the intermediate pad opening 109 for the intermediate electrode layer 102, the first upper pad opening 52 for the first upper electrode layer 25, and the second upper pad opening 53 for the second upper electrode layer 27 are each surrounded by the inner wall of the opening 21. It is formed in the area.
As a result, the pad region of the intermediate electrode layer 102, the pad region of the first upper electrode layer 25, and the pad region of the second upper electrode layer 27 are each formed in the region surrounded by the inner wall of the opening 21. ..

That is, the connection portion of the first upper pad electrode layer 55 to the first upper electrode layer 25 is formed in the region surrounded by the inner wall of the opening 21.
Further, the connection portion of the second upper pad electrode layer 56 to the second upper electrode layer 27 is formed in the region surrounded by the inner wall of the opening 21.
Further, the connection portion of the intermediate pad electrode layer 110 to the intermediate electrode layer 102 is formed in the region surrounded by the inner wall of the opening 21.

In the ultrasonic sensor 121, the first upper inner portion 30 and the first upper drawer portion 106 of the first upper electrode layer 25 are formed in a region surrounded by the inner wall of the opening 21 in a plan view.
Further, the piezoelectric inner side portion 40 and the piezoelectric material extraction portion 107 of the second piezoelectric layer 26 are formed in a region surrounded by the inner wall of the opening 21 in a plan view.

Further, the second upper inner portion 44 and the second upper drawer portion 108 of the second upper electrode layer 27 are formed in a region surrounded by the inner wall of the opening 21 in a plan view.
Further, the intermediate inner portion 104 and the intermediate drawer portion 105 of the intermediate electrode layer 102 are formed in a region surrounded by the inner wall of the opening 21 in a plan view.
The intermediate drawer 105 of the intermediate electrode layer 102, the first upper drawer 106 of the first upper electrode layer 25 (piezoelectric drawer 107 of the second piezoelectric layer 26), and the second upper drawer of the second upper electrode layer 27. The 108 are pulled out in different directions.

In this embodiment, the intermediate drawer portion 105 of the intermediate electrode layer 102 is drawn out in a band shape from the intermediate inner portion 104 toward the substrate side surface 17 on one side (left side in FIG. 18) in the longitudinal direction of the substrate 10.
In this embodiment, the first upper drawer portion 106 of the first upper electrode layer 25 is directed from the first upper inner portion 30 toward the substrate side surface 17 on one side (upper side in FIG. 18) in the lateral direction of the substrate 10. It is pulled out in a band shape. Similarly, the piezoelectric pull-out portion 107 of the second piezoelectric layer 26 is pulled out in a band shape from the piezoelectric inner side portion 40 toward the substrate side surface 17 on one side (upper side in FIG. 18) in the lateral direction of the substrate 10. ing.

In this embodiment, the second upper drawer portion 108 of the second upper electrode layer 27 is directed from the second upper inner portion 44 toward the other side (right side of FIG. 18) of the substrate side surface 17 in the lateral direction of the substrate 10. It is pulled out in a band shape.
As described above, in the ultrasonic sensor 121, in a plan view, the entire intermediate electrode layer 102, the entire first upper electrode layer 25, the entire second piezoelectric layer 26, and the entire second upper electrode layer 27 are openings, respectively. It is formed in the area surrounded by the inner wall of 21.

Thereby, the formation of the parasitic capacitance Cp12 can be appropriately suppressed in the region between the substrate 10 and the intermediate electrode layer 102. Further, in the region between the first upper electrode layer 25 and the intermediate electrode layer 102, the formation of the parasitic capacitance Cp13 can be appropriately suppressed.
Further, in the region between the substrate 10 and the first upper electrode layer 25, the formation of the parasitic capacitance Cp14 can be appropriately suppressed. Further, the parasitic capacitance Cp15 can be appropriately suppressed in the region between the second upper electrode layer 27 and the substrate 10. Therefore, it is possible to provide an ultrasonic sensor 121 that can appropriately suppress a decrease in sensitivity due to parasitic capacitance.
<Fourth Embodiment>
FIG. 21 is a plan view showing an ultrasonic sensor 131 according to a fourth embodiment of the present invention. FIG. 22 is a cross-sectional view taken along the line XXII-XXII shown in FIG. FIG. 23 is a cross-sectional view taken along the line XXIII-XXIII shown in FIG.

In the following, the same reference numerals will be given to the same configurations as those described in the first embodiment, and the description thereof will be omitted.
With reference to FIGS. 21 to 23, the ultrasonic sensor 131 includes a first lower electrode layer 132 and a second lower electrode layer 133 in place of the lower electrode layer 23. The second lower electrode layer 133 may be fixed at the same potential as the first lower electrode layer 132.

The first lower electrode layer 132 is formed on the diaphragm 11. The first lower electrode layer 132 includes a first lower inner portion 134 and a first lower drawer portion 135. The first lower inner portion 134 of the first lower electrode layer 132 is formed in a region surrounded by the inner wall surface of the opening 21 in a plan view.
In a plan view, the entire first lower inner portion 134 overlaps the opening 21. In a plan view, the area of the first lower inner portion 134 is equal to or less than the area of the opening 21. More specifically, in a plan view, the area of the first lower inner portion 134 is smaller than the area of the opening 21.

The first lower inner portion 134 is formed only in the region surrounded by the inner wall surface of the opening 21 in a plan view. The first lower inner portion 134 does not overlap the substrate 10 in a plan view.
The first lower inner portion 134 is formed in a circular shape in a plan view. The first lower inner portion 134 may be formed in a polygonal shape such as a triangle shape, a quadrangular shape, or a hexagonal shape in a plan view. The first lower inner portion 134 may be formed in an elliptical shape in a plan view.

The first lower drawer portion 135 of the first lower electrode layer 132 is drawn out from the first lower inner portion 134 to the region outside the opening 21 in a plan view. In this embodiment, the first lower drawer portion 135 is pulled out in a strip shape from the first lower inner portion 134 toward the substrate side surface 17 on one side (upper side in FIG. 21) in the lateral direction of the substrate 10. There is. The end of the first lower drawer 135 is formed in the region between the substrate side surface 17 and the opening 21 in plan view.

The first lower electrode layer 132 may include a molybdenum (Mo) layer. The first lower electrode layer 132 may be made of a molybdenum layer. The thickness of the first lower electrode layer 132 may be 40 nm or more and 200 nm or less (for example, about 100 nm).
The second lower electrode layer 133 is formed on the diaphragm 11. The second lower electrode layer 133 includes a second lower inner portion 136 and a second lower drawer portion 137.

The second lower inner portion 136 of the second lower electrode layer 133 is formed in a region surrounded by the inner wall surface of the opening 21 in a plan view at a distance from the first lower inner portion 134. ing. The second lower inner portion 136 straddles the inside and the outside of the region surrounded by the inner wall surface of the opening 21 in a plan view.
The second lower inner portion 136 extends in a strip shape along the inner wall of the opening 21 in a plan view. The second lower inner portion 136 is formed in an endd ring shape surrounding the first lower inner portion 134 of the first lower electrode layer 132 in a plan view.

The open portion 138 is partitioned by a region between one end and the other end of the second lower inner portion 136. The first lower drawer portion 135 of the first lower electrode layer 132 is drawn out from the inner region of the opening 21 to the outer region across the open portion 138 of the second lower inner portion 136 in a plan view. It has been.
The second lower drawer portion 137 of the second lower electrode layer 133 is drawn out from the second lower inner portion 136 to the region outside the opening 21 in a plan view. The second lower drawer portion 137 is pulled out along the direction in which the first lower drawer portion 135 of the first lower electrode layer 132 intersects in the extending direction.

In this embodiment, the second lower drawer portion 137 faces the substrate side surface 17 and the opening 21 on one side (left side of FIG. 21) of the substrate 10 from the second lower inner portion 136 in the longitudinal direction of the substrate 10. It is pulled out in a strip shape. The end portion of the second lower drawer portion 137 is formed in the region between the substrate side surface 17 and the opening 21 in a plan view.
The second lower electrode layer 133 may be formed of the same conductive material as the conductive material of the first lower electrode layer 132. The second lower electrode layer 133 may have the same thickness as the thickness of the first lower electrode layer 132.

The second lower electrode layer 133 may include a molybdenum (Mo) layer. The second lower electrode layer 133 may be made of a molybdenum layer. The thickness of the second lower electrode layer 133 may be 40 nm or more and 200 nm or less (for example, about 100 nm).
The first piezoelectric layer 24 is formed on the diaphragm 11 so as to cover the first lower electrode layer 132 and the second lower electrode layer 133. The first piezoelectric layer 24 forms a part of the side surface 5 of the sensor body 2. The first piezoelectric layer 24 has a side surface flush with respect to the substrate side surface 17 of the substrate 10.

The first upper electrode layer 25 overlaps the first lower electrode layer 132, the second lower electrode layer 133, and the opening 21 in a plan view.
More specifically, the first upper electrode layer 25 overlaps only the first lower electrode layer 132, the second lower electrode layer 133, and the opening 21 in a plan view, avoiding the substrate 10. The first upper electrode layer 25 is capacitively coupled to the first lower electrode layer 132 and the second lower electrode layer 133 with the first piezoelectric layer 24 interposed therebetween.

The first piezoelectric element C21 for transmission or reception is provided by the capacitive coupling of the first lower electrode layer 132 and the first upper electrode layer 25, and the capacitive coupling of the second lower electrode layer 133 and the first upper electrode layer 25. Is formed.
The first upper electrode layer 25 includes a first upper inner portion 30. Further, the first upper electrode layer 25 includes a first upper drawer portion 139 instead of the first upper drawer portion 31 and the second upper drawer portion 32.

The first upper inner portion 30 of the first upper electrode layer 25 is formed in this form in a region surrounded by the inner wall of the opening 21 in a plan view. In a plan view, the entire first upper inner portion 30 overlaps the opening 21. The first upper inner portion 30 is formed only in the region surrounded by the inner wall surface of the opening 21 in a plan view.
The first upper inner portion 30 is the opening 21, the first lower inner portion 134 and the second lower side of the first lower electrode layer 132 in the region surrounded by the inner wall of the opening 21 in a plan view. It overlaps the second lower inner portion 136 of the electrode layer 133.

The first upper drawer portion 139 of the first upper electrode layer 25 is drawn out from the first upper inner portion 30 to the region outside the opening 21 in a plan view. In this embodiment, the first upper drawer portion 139 is pulled out in a band shape from the first upper inner portion 30 toward the substrate side surface 17 on one side (left side in FIG. 21) in the longitudinal direction of the substrate 10.
The end portion of the first upper drawer portion 139 is formed in a region between the end portion of the second lower drawer portion 137 and the opening 21 of the second lower electrode layer 133 in a plan view.

The second piezoelectric layer 26 has a shape that matches the shape of the first upper electrode layer 25 in a plan view. The second piezoelectric layer 26 includes the piezoelectric internal portion 40. Further, the second piezoelectric layer 26 includes a piezoelectric pull-out portion 140 in place of the first piezoelectric pull-out portion 41 and the second piezoelectric pull-out portion 42.
The piezoelectric body side portion 40 and the piezoelectric body drawer portion 140 have shapes that match the first upper inner portion 30 and the first upper drawer portion 139 of the first upper electrode layer 25, respectively, in a plan view. The first upper electrode layer 25 and the second piezoelectric layer 26 form a mesa structure 43 on the first piezoelectric layer 24.

The second upper electrode layer 27 is formed on the second piezoelectric layer 26. The second upper electrode layer 27 overlaps with the first upper electrode layer 25 in a plan view. More specifically, in a plan view, the entire second upper electrode layer 27 overlaps with the first upper electrode layer 25.
The second upper electrode layer 27 is capacitively coupled to the first upper electrode layer 25 with the second piezoelectric layer 26 interposed therebetween. The second piezoelectric element C22 for transmission or reception is formed by the capacitive coupling of the first upper electrode layer 25 and the second upper electrode layer 27.

The second upper electrode layer 27 includes a second upper inner portion 44. Further, the second upper electrode layer 27 includes a second upper drawer portion 141 instead of the third upper drawer portion 45.
The second upper inner portion 44 of the second upper electrode layer 27 is formed in a region surrounded by the inner wall of the opening 21 in a plan view. In a plan view, the entire second upper inner portion 44 overlaps the opening 21.

The second upper inner portion 44 is formed only in the region surrounded by the inner wall surface of the opening 21 in a plan view. In a plan view, the entire second upper inner portion 44 overlaps the first upper inner portion 30 of the first upper electrode layer 25. The second upper inner portion 44 does not overlap the substrate 10 in a plan view.
In a plan view, the area of the second upper inner portion 44 is equal to or smaller than the area of the first upper inner portion 30 of the first upper electrode layer 25. More specifically, in a plan view, the area of the second upper inner portion 44 is smaller than the area of the first upper inner portion 30.

The second upper drawer portion 141 is pulled out from the second upper inner portion 44 to the region outside the opening 21 in a plan view. In this embodiment, the second upper drawer portion 141 is pulled out in a band shape from the second upper inner portion 44 toward the substrate side surface 17 on one side (left side in FIG. 21) in the longitudinal direction of the substrate 10.
The second upper drawer portion 141 of the second upper electrode layer 27 is formed on the piezoelectric drawer portion 140 of the second piezoelectric layer 26. The end portion of the second upper drawer portion 141 is formed in a region between the end portion and the opening portion 21 of the first upper drawer portion 106 of the first upper electrode layer 25 in a plan view.

In a plan view, the area of the second upper drawer portion 141 is equal to or smaller than the area of the first upper drawer portion 106 of the first upper electrode layer 25. More specifically, in a plan view, the area of the second upper drawer portion 141 is smaller than the area of the first upper drawer portion 106. In a plan view, the entire second upper drawer portion 141 overlaps with the first upper drawer portion 106.
The first piezoelectric layer 24 is formed with a first lower pad opening 147 and a second lower pad opening 148 in place of the lower pad opening 51.

The first lower pad opening 147 penetrates the first piezoelectric layer 24 and exposes a part of the first lower drawer portion 135 of the first lower electrode layer 132 as a pad region.
The second lower pad opening 148 penetrates the first piezoelectric layer 24 and exposes a part of the second lower drawer portion 137 of the second lower electrode layer 133 as a pad region.
The first upper pad opening 149 is formed in the second piezoelectric layer 26. The first upper pad opening 149 penetrates the second piezoelectric layer 26 and exposes a part of the first upper drawer portion 139 of the first upper electrode layer 25 as a pad region.

The surface insulating layer 13 is a film along the inner wall of the first lower pad opening 147 so as to expose the first lower drawer portion 135 of the first lower electrode layer 132 in the first lower pad opening 147. It is formed in a shape.
The surface insulating layer 13 is a film along the inner wall of the second lower pad opening 148 so as to expose the second lower drawer portion 137 of the second lower electrode layer 133 in the second lower pad opening 148. It is formed in a shape.

The surface insulating layer 13 is formed in a film shape along the inner wall of the second lower pad opening 148 so as to expose the first upper drawer portion 139 of the first upper electrode layer 25 in the first upper pad opening 149. Has been done.
The surface insulating layer 13 is formed with a second upper pad opening 150. The second upper pad opening 150 exposes a part of the second upper drawer portion 141 of the second upper electrode layer 27 as a pad region.

In a plan view, the first lower pad opening 147, the first upper pad opening 149, and the second upper pad opening 150 are formed on the same straight line at intervals from each other. The first lower pad opening 147, the first upper pad opening 149, and the second upper pad opening 150 are formed in this form on the same straight line extending along the longitudinal direction of the substrate 10.
The surface electrode layer 14 includes a first lower pad electrode layer 151 and a second lower pad electrode layer 152 in place of the lower pad electrode layer 54.

The first lower pad electrode layer 151 is formed in an arbitrary region on the surface insulating layer 13. The first lower pad electrode layer 151 includes an island-shaped first lower pad region 153 and a line-shaped first lower wiring region 154. The first lower pad region 153 is formed in an arbitrary region on the surface insulating layer 13 in a square shape in a plan view.
The first lower wiring region 154 is routed to a region between the first lower pad region 153 and the first lower electrode layer 132. The first lower wiring region 154 is drawn out from the first lower pad region 153 and enters the first lower pad opening 147 from above the surface insulating layer 13.

The first lower wiring region 154 is connected to the first lower electrode layer 132 in the first lower pad opening 147. The first lower pad region 153 is electrically connected to the first lower electrode layer 132 via the first lower wiring region 154.
A first lower pad electrode layer 151 that does not have a first lower wiring region 154 may be adopted. In this case, the first lower pad region 153 enters the first lower pad opening 147 from above the surface insulating layer 13. The first lower pad region 153 is directly connected to the first lower electrode layer 132 in the first lower pad opening 147.

The second lower pad electrode layer 152 is formed in an arbitrary region on the surface insulating layer 13. The second lower pad electrode layer 152 includes an island-shaped second lower pad region 155 and a line-shaped second lower wiring region 156. The second lower pad region 155 is formed in an arbitrary region on the surface insulating layer 13 in a square shape in a plan view.
The second lower wiring region 156 is routed to a region between the second lower pad region 155 and the second lower electrode layer 133. The second lower wiring region 156 is drawn out from the second lower pad region 155 and enters the second lower pad opening 148 from above the surface insulating layer 13.

The second lower wiring region 156 is connected to the second lower electrode layer 133 in the second lower pad opening 148. The second lower pad region 155 is electrically connected to the second lower electrode layer 133 via the second lower wiring region 156.
A second lower pad electrode layer 152 that does not have a second lower wiring region 156 may be adopted. In this case, the second lower pad region 155 enters the second lower pad opening 148 from above the surface insulating layer 13. The second lower pad region 155 is directly connected to the second lower electrode layer 133 within the second lower pad opening 148.

FIG. 24 is a circuit diagram showing the electrical structure of the ultrasonic sensor 131 shown in FIG. The electrical structure of an ultrasonic sensor 131 is shown by a solid line.
With reference to FIGS. 21 and 24, in the ultrasonic sensor 131, the capacitive coupling of the first lower electrode layer 132 and the first upper electrode layer 25, and the second lower electrode layer 133 and the first upper electrode layer 25 are performed. The first piezoelectric element C21 for transmission or reception is formed by the capacitive coupling of the above. The second piezoelectric element C22 for transmission or reception is formed by the capacitive coupling of the first upper electrode layer 25 and the second upper electrode layer 27.

In the ultrasonic sensor 131, the first upper electrode layer 25 is formed so as to overlap only the first lower electrode layer 132, the second lower electrode layer 133, and the opening 21 in a plan view. The first lower electrode layer 132 or the second lower electrode layer 133 is always interposed in the region between the first upper electrode layer 25 and the substrate 10.
Therefore, the first upper electrode layer 25 can be appropriately capacitively coupled to the first lower electrode layer 132 and the second lower electrode layer 133. Thereby, the formation of the parasitic capacitance Cp21 can be suppressed in the region between the first upper electrode layer 25 and the substrate 10.

Further, in the ultrasonic sensor 131, the entire second upper electrode layer 27 overlaps with the first upper electrode layer 25 in a plan view. As a result, the second upper electrode layer 27 can be appropriately capacitively coupled to the first upper electrode layer 25. Therefore, the formation of the parasitic capacitance Cp22 can be suppressed in the region between the first upper electrode layer 25 and the substrate 10.
Moreover, the parasitic capacitance Cp23 formed in the region between the first lower electrode layer 132 and the substrate 10 and the region between the second lower electrode layer 133 and the substrate 10 is electrically open. , Does not work. As described above, in the ultrasonic sensor 131, the formation of the parasitic capacitance circuit is suppressed.

Further, the ultrasonic sensor 131 includes a second lower electrode layer 133 formed on the diaphragm 11. The second lower electrode layer 133 is a first lower electrode so as to be along the peripheral edge of the first lower inner portion 134 of the first lower electrode layer 132 in the region surrounded by the inner wall of the opening 21. It is formed at a distance from the layer 132.
Thereby, the static amount of bending of the diaphragm 11 and the bending direction of the diaphragm 11 can be controlled. Therefore, it is possible to provide an ultrasonic sensor 131 capable of appropriately suppressing fluctuations in sensitivity.
<Fifth Embodiment>
FIG. 25 is a plan view showing an ultrasonic sensor 161 according to a fifth embodiment of the present invention. FIG. 26 is a cross-sectional view taken along the line XXVI-XXVI shown in FIG. FIG. 27 is a cross-sectional view taken along the line XXVII-XXVII shown in FIG. FIG. 28 is a cross-sectional view taken along the line XXVIII-XXVIII shown in FIG.

In the following, the same reference numerals will be given to the same configurations as those described in the fourth embodiment, and the description thereof will be omitted.
With reference to FIGS. 25-28, the first lower electrode layer 132 includes a first lower inner portion 134 and a first lower drawer portion 135. In this embodiment, the first lower drawer portion 135 is pulled out in a band shape from the first lower inner portion 134 toward the other side (lower side of FIG. 25) of the substrate side surface 17 in the lateral direction of the substrate 10. ing.

The second lower electrode layer 133 includes a second lower inner portion 136. The second lower electrode layer 133 includes a third lower drawer portion 162 and a fourth lower drawer portion 163 in addition to the second lower drawer portion 137.
In this embodiment, the second lower drawing portion 137 of the second lower electrode layer 133 is pulled out along the directions intersecting the longitudinal direction and the lateral direction of the substrate 10 in a plan view. The second lower drawer portion 137 is a substrate side surface 17 on the other side (right side in FIG. 25) in the longitudinal direction of the substrate 10 and a substrate side surface 17 on the other side (lower side in FIG. 25) in the lateral direction of the substrate 10. Extends towards the corners that connect.

The third lower drawer portion 162 of the second lower electrode layer 133 is drawn out from the second lower inner portion 136 to the region outside the opening 21 in a plan view. The third lower drawer portion 162 extends along a direction intersecting the direction in which the second lower drawer portion 137 extends in a plan view.
In this embodiment, the third lower drawer portion 162 is pulled out in a strip shape from the second lower inner portion 136 toward the substrate side surface 17 on one side (upper side in FIG. 25) in the lateral direction of the substrate 10. There is. The end of the third lower drawer 162 is formed in the region between the substrate side surface 17 and the opening 21 in a plan view.

The fourth lower drawer portion 163 of the second lower electrode layer 133 is drawn out from the second lower inner portion 136 to the region outside the opening 21 in a plan view. The fourth lower drawer portion 163 extends along a direction intersecting a direction in which the second lower drawer portion 137 extends and a direction in which the third lower drawer portion 162 extends in a plan view.
In this embodiment, the fourth lower drawer portion 163 is pulled out in a band shape from the second lower inner portion 136 toward the substrate side surface 17 on one side (left side in FIG. 25) in the longitudinal direction of the substrate 10. .. The end of the fourth lower drawer 163 is formed in the region between the substrate side surface 17 and the opening 21 in plan view.

The piezoelectric element layer 12 has a laminated structure further including an intermediate electrode layer 164 and an intermediate piezoelectric layer 165. The intermediate electrode layer 164 and the intermediate piezoelectric layer 165 are formed in the region between the first piezoelectric layer 24 and the mesa structure 43.
The intermediate electrode layer 164 overlaps the first lower electrode layer 132, the second lower electrode layer 133, and the opening 21 in a plan view. More specifically, the intermediate electrode layer 164 overlaps only the first lower electrode layer 132, the second lower electrode layer 133, and the opening 21 in a plan view, avoiding the substrate 10.

The intermediate electrode layer 164 is capacitively coupled to the first lower electrode layer 132 and the second lower electrode layer 133 with the first piezoelectric layer 24 interposed therebetween. Capacitive coupling of the first lower electrode layer 132 and the intermediate electrode layer 164, and capacitive coupling of the second lower electrode layer 133 and the intermediate electrode layer 164 form a first piezoelectric element C31 for transmission or reception. There is.
More specifically, the intermediate electrode layer 164 includes an intermediate inner portion 166, a first intermediate drawer portion 167, and a second intermediate drawer portion 168.

The intermediate inner portion 166 of the intermediate electrode layer 164 is formed in a region surrounded by the inner wall surface of the opening 21 in a plan view. In plan view, the entire intermediate inner portion 166 overlaps the opening 21.
In a plan view, the area of the intermediate inner portion 166 is equal to or less than the area of the opening 21. More specifically, the area of the intermediate inner portion 166 in a plan view is smaller than the area of the opening 21. The intermediate inner portion 166 is formed only in the region surrounded by the inner wall surface of the opening 21 in a plan view. The intermediate inner portion 166 does not overlap the substrate 10 in a plan view.

The intermediate inner portion 166 is formed in a circular shape in a plan view. The intermediate inner portion 166 may be formed in a polygonal shape such as a triangular shape, a square shape, or a hexagonal shape in a plan view. The intermediate inner portion 166 may be formed in an elliptical shape in a plan view.
The first intermediate drawer portion 167 of the intermediate electrode layer 164 is drawn out from the intermediate inner portion 166 to the region outside the opening 21 in a plan view. In this embodiment, the first intermediate drawer portion 167 is pulled out in a strip shape from the intermediate inner portion 166 toward the substrate side surface 17 on one side (upper side in FIG. 25) in the lateral direction of the substrate 10.

The end portion of the first intermediate drawer portion 167 is formed in a region between the end portion and the opening portion 21 of the third lower drawer portion 162 of the second lower electrode layer 133 in a plan view.
In a plan view, the area of the first intermediate drawer portion 167 is equal to or less than the area of the third lower drawer portion 162 of the second lower electrode layer 133. More specifically, in a plan view, the area of the first intermediate drawer portion 167 is smaller than the area of the third lower drawer portion 162. In a plan view, the entire first intermediate drawer portion 167 overlaps the third lower drawer portion 162.

The second intermediate drawer portion 168 of the intermediate electrode layer 164 is drawn out from the intermediate inner portion 166 to the region outside the opening 21 in a plan view. In this embodiment, the second intermediate drawer portion 168 is pulled out in a band shape from the intermediate inner portion 166 toward the substrate side surface 17 on one side (left side in FIG. 25) in the longitudinal direction of the substrate 10. The end portion of the second intermediate drawer portion 168 is formed in a region between the end portion and the opening portion 21 of the fourth lower drawer portion 163 of the second lower electrode layer 133 in a plan view.

In a plan view, the area of the second intermediate drawer portion 168 is equal to or smaller than the area of the fourth lower drawer portion 163 of the second lower electrode layer 133. More specifically, in a plan view, the area of the second intermediate drawer portion 168 is smaller than the area of the fourth lower drawer portion 163. In a plan view, the entire second intermediate drawer portion 168 overlaps with the fourth lower drawer portion 163.
The intermediate electrode layer 164 may include a molybdenum (Mo) layer. The intermediate electrode layer 164 may be made of a molybdenum layer. The thickness of the intermediate electrode layer 164 may be 40 nm or more and 200 nm or less (for example, about 100 nm).

The intermediate piezoelectric layer 165 is formed on the first piezoelectric layer 24 so as to cover the intermediate electrode layer 164 in the region between the first piezoelectric layer 24 and the mesa structure 43. In this form, the intermediate piezoelectric layer 165 covers almost the entire surface of the intermediate electrode layer 164. The intermediate piezoelectric layer 165 forms a part of the side surface 5 of the sensor body 2. The intermediate piezoelectric layer 165 has a side surface flush with respect to the substrate side surface 17 of the substrate 10.

The intermediate piezoelectric layer 165 may include an aluminum nitride layer. The intermediate piezoelectric layer 165 may be made of an aluminum nitride layer. The thickness of the intermediate piezoelectric layer 165 may be 0.5 μm or more and 1.5 μm or less (for example, about 1.0 μm).
The first upper electrode layer 25 is formed on the intermediate piezoelectric layer 165. In a plan view, the area of the first upper electrode layer 25 is equal to or less than the area of the intermediate electrode layer 164. More specifically, the area of the first upper electrode layer 25 is smaller than the area of the intermediate electrode layer 164 in a plan view. In a plan view, the entire first upper electrode layer 25 overlaps the intermediate electrode layer 164.

The first upper electrode layer 25 includes a first upper inner portion 30 and a first upper drawer portion 139.
The first upper inner portion 30 of the first upper electrode layer 25 is formed in a region surrounded by the inner wall surface of the opening 21 in a plan view. In a plan view, the area of the first upper inner portion 30 is smaller than the area of the intermediate inner portion 166 of the intermediate electrode layer 164. More specifically, in a plan view, the area of the first upper inner portion 30 is smaller than the area of the intermediate inner portion 166.

In a plan view, the entire first upper inner portion 30 overlaps the opening 21. In a plan view, the entire first upper inner portion 30 overlaps the middle inner portion 166. The first upper inner portion 30 does not overlap the substrate 10 in a plan view.
The first upper drawer portion 139 of the first upper electrode layer 25 is drawn out from the first upper inner portion 30 to the region outside the opening 21 in a plan view. In this embodiment, the first upper drawer portion 139 is pulled out in a band shape from the first upper inner portion 30 toward the substrate side surface 17 on one side (left side in FIG. 25) in the longitudinal direction of the substrate 10.

The end portion of the first upper drawer portion 139 is formed in a region between the end portion and the opening portion 21 of the second intermediate drawer portion 168 of the intermediate electrode layer 164 in a plan view.
In a plan view, the area of the first upper drawer portion 139 is equal to or less than the area of the second intermediate drawer portion 168. More specifically, in a plan view, the area of the first upper drawer portion 139 is smaller than the area of the second intermediate drawer portion 168. In a plan view, the entire first upper drawer portion 139 overlaps with the second intermediate drawer portion 168.

The second piezoelectric layer 26 has a shape that matches the shape of the first upper electrode layer 25 in a plan view. The second piezoelectric layer 26 includes a piezoelectric internal portion 40 and a piezoelectric pull-out portion 140.
The piezoelectric body side portion 40 and the piezoelectric body drawer portion 140 have shapes that match the first upper inner portion 30 and the first upper drawer portion 139 of the first upper electrode layer 25, respectively, in a plan view. The first upper electrode layer 25 and the second piezoelectric layer 26 form a mesa structure 43 on the first piezoelectric layer 24.

In the ultrasonic sensor 161 the second upper electrode layer 27 has a third area S3 in a plan view. The third area S3 of the second upper electrode layer 27 is the second area S2 or less (S3 ≦ S2) of the first upper electrode layer 25, or less than the second area S2 of the first upper electrode layer 25 (S3 <S2). Is. In a plan view, the entire second upper electrode layer 27 overlaps the first upper electrode layer 25.
In a plan view, the entire second upper electrode layer 27 overlaps the first upper inner portion 30 of the first upper electrode layer 25. Therefore, both the second upper inner portion 44 and the second upper drawer portion 141 of the second upper electrode layer 27 overlap the first upper inner portion 30 of the first upper electrode layer 25 in a plan view.

In this embodiment, the second upper drawer portion 141 of the second upper electrode layer 27 is located on the substrate side surface 17 on the other side of the substrate 10 (right side in FIG. 25) from the second upper inner portion 44 in the longitudinal direction of the substrate 10. It is pulled out in a strip shape toward it.
The ultrasonic sensor 161 further includes a third upper electrode layer 169 formed on the second piezoelectric layer 26. The third upper electrode layer 169 may be fixed at the same potential as the second upper electrode layer 27.

The third upper electrode layer 169 includes a third upper inner portion 170 and a third upper drawer portion 171. The third upper inner portion 170 of the third upper electrode layer 169 is formed in a region surrounded by the inner wall surface of the opening 21 in a plan view at intervals from the second upper electrode layer 27.
More specifically, the third upper inner portion 170 straddles the inside and the outside of the region surrounded by the inner wall surface of the opening 21 in a plan view. The third upper inner portion 170 extends in a strip shape along the inner wall of the opening 21 in a plan view.

The third upper inner portion 170 is formed in a ring shape surrounding the second upper electrode layer 27 in a plan view. The third upper inner portion 170 overlaps the second lower inner portion 136 in a plan view.
The third upper drawer portion 171 of the third upper electrode layer 169 is drawn out from the third upper inner portion 170 to the region outside the opening 21 in a plan view. In this embodiment, the third upper drawer portion 171 is pulled out along the directions intersecting the longitudinal direction and the lateral direction of the substrate 10 in a plan view.

The third upper drawer portion 171 connects the substrate side surface 17 on one side (left side in FIG. 25) with respect to the longitudinal direction of the substrate 10 and the substrate side surface 17 on one side (upper side in FIG. 25) with respect to the lateral direction of the substrate 10. It extends toward the corner.
In this embodiment, the third upper drawer portion 171 is pulled out in a band shape from the third upper inner portion 170 toward the substrate side surface 17 on one side (left side in FIG. 25) in the longitudinal direction of the substrate 10.

In a plan view, the entire third upper drawer portion 171 overlaps with the first upper electrode layer 25. In a plan view, the entire third upper drawer portion 171 may overlap the first upper inner portion 30 of the first upper electrode layer 25.
The third upper electrode layer 169 may be formed of the same conductive material as the conductive material of the second upper electrode layer 27. The third upper electrode layer 169 may have the same thickness as the thickness of the second upper electrode layer 27.

The third upper electrode layer 169 may have a laminated structure including an iridium oxide layer 46 and an iridium layer 47 laminated in this order from the second piezoelectric layer 26 side (see also FIG. 5).
The thickness of the iridium oxide layer 46 may be 20 nm or more and 80 nm or less (for example, about 50 nm). The thickness of the iridium layer 47 may be 20 nm or more and 80 nm or less (for example, about 50 nm).

The second upper electrode layer 27 and the third upper electrode layer 169 are capacitively coupled to the first upper electrode layer 25 with the second piezoelectric layer 26 interposed therebetween. The second piezoelectric element C32 for transmission or reception is formed by the capacitive coupling of the first upper electrode layer 25 and the second upper electrode layer 27 and the capacitive coupling of the first upper electrode layer 25 and the third upper electrode layer 169. Has been done.
The first piezoelectric layer 24 is formed with a first lower pad opening 147 and a second lower pad opening 148.

In this embodiment, the first lower pad opening 147 penetrates the intermediate piezoelectric layer 165 and the first piezoelectric layer 24, and pads a part of the first lower drawer portion 135 of the first lower electrode layer 132. It is exposed as an area.
In this embodiment, the second lower pad opening 148 penetrates the intermediate piezoelectric layer 165 and the first piezoelectric layer 24, and pads a part of the second lower drawer portion 137 of the second lower electrode layer 133. It is exposed as an area.

An intermediate pad opening 176 is formed in the intermediate piezoelectric layer 165. In this embodiment, the intermediate pad opening 176 penetrates the intermediate piezoelectric layer 165 and exposes a part of the first intermediate drawer portion 167 of the intermediate electrode layer 164 as a pad region.
The first upper pad opening 149 is formed in the second piezoelectric layer 26. The first upper pad opening 149 penetrates the second piezoelectric layer 26 and exposes a part of the first upper drawer portion 139 of the first upper electrode layer 25 as a pad region.

The surface insulating layer 13 is a film along the inner wall of the first lower pad opening 147 so as to expose the first lower drawer portion 135 of the first lower electrode layer 132 in the first lower pad opening 147. It is formed in a shape.
The surface insulating layer 13 is a film along the inner wall of the second lower pad opening 148 so as to expose the second lower drawer portion 137 of the second lower electrode layer 133 in the second lower pad opening 148. It is formed in a shape.

The surface insulating layer 13 is formed in a film shape along the inner wall of the second lower pad opening 148 so as to expose the first upper drawer portion 139 of the first upper electrode layer 25 in the first upper pad opening 149. Has been done.
The surface insulating layer 13 is formed in a film shape along the inner wall of the intermediate pad opening 176 so as to expose the first intermediate drawer portion 167 of the intermediate electrode layer 164 in the intermediate pad opening 176.

In addition to the second upper pad opening 150, the surface insulating layer 13 is formed with a third upper pad opening 177. The third upper pad opening 177 exposes a part of the third upper drawer portion 171 of the third upper electrode layer 169 as a pad region.
The surface electrode layer 14 includes an intermediate pad electrode layer 178 and a first layer in addition to the first upper pad electrode layer 55, the second upper pad electrode layer 56, the first lower pad electrode layer 151, and the second lower pad electrode layer 152. 3 The upper pad electrode layer 179 is included.

The intermediate pad electrode layer 178 is formed in an arbitrary region on the surface insulating layer 13. The intermediate pad electrode layer 178 includes an island-shaped intermediate pad region 180 and a line-shaped intermediate wiring region 181. The intermediate pad region 180 is formed in an arbitrary region on the surface insulating layer 13 in a square shape in a plan view.
The intermediate wiring region 181 is routed to the region between the intermediate pad region 180 and the intermediate electrode layer 164. The intermediate wiring region 181 is drawn out from the intermediate pad region 180 and enters the intermediate pad opening 176 from above the surface insulating layer 13.

The intermediate wiring region 181 is connected to the intermediate electrode layer 164 in the intermediate pad opening 176. The intermediate pad region 180 is electrically connected to the intermediate electrode layer 164 via the intermediate wiring region 181.
An intermediate pad electrode layer 178 having no intermediate wiring region 181 may be adopted. In this case, the intermediate pad region 180 enters the intermediate pad opening 176 from above the surface insulating layer 13. The intermediate pad region 180 is directly connected to the intermediate electrode layer 164 in the intermediate pad opening 176.

The third upper pad electrode layer 179 is formed in an arbitrary region on the surface insulating layer 13. The third upper pad electrode layer 179 includes an island-shaped third upper pad region 182 and a line-shaped third upper wiring region 183. The third upper pad region 182 is formed in an arbitrary region on the surface insulating layer 13 in a square shape in a plan view.
The third upper wiring region 183 is routed to a region between the third upper pad region 182 and the third upper electrode layer 169. The third upper wiring region 183 is drawn out from the third upper pad region 182 and enters the third upper pad opening 177 from above the surface insulating layer 13.

The third upper wiring region 183 is connected to the third upper electrode layer 169 in the third upper pad opening 177. The third upper pad region 182 is electrically connected to the third upper electrode layer 169 via the third upper wiring region 183.
A third upper pad electrode layer 179 that does not have a third upper wiring region 183 may be adopted. In this case, the third upper pad region 182 enters the third upper pad opening 177 from above the surface insulating layer 13. The third upper pad region 182 is directly connected to the third upper electrode layer 169 in the third upper pad opening 177.

FIG. 29 is a circuit diagram showing an electrical structure of the ultrasonic sensor 161 shown in FIG. 25. The electrical structure of an ultrasonic sensor 161 is shown by a solid line.
With reference to FIG. 29, in the ultrasonic sensor 161 for transmission by the capacitive coupling of the first lower electrode layer 132 and the intermediate electrode layer 164 and the capacitive coupling of the second lower electrode layer 133 and the intermediate electrode layer 164. Alternatively, a first piezoelectric element C31 for reception is formed.

The second piezoelectric element C32 for transmission or reception is formed by the capacitive coupling of the first upper electrode layer 25 and the second upper electrode layer 27 and the capacitive coupling of the first upper electrode layer 25 and the third upper electrode layer 169. Has been done.
In the ultrasonic sensor 161 the intermediate electrode layer 164 overlaps only the first lower electrode layer 132, the second lower electrode layer 133, and the opening 21 in a plan view. The first lower electrode layer 132 or the second lower electrode layer 133 is always interposed in the region between the first upper electrode layer 25 and the substrate 10.

Therefore, the intermediate electrode layer 164 can be appropriately capacitively coupled to the first lower electrode layer 132 and the second lower electrode layer 133. Thereby, the formation of the parasitic capacitance Cp31 can be suppressed in the region between the intermediate electrode layer 164 and the substrate 10.
Further, in the ultrasonic sensor 161, the entire first upper electrode layer 25 overlaps with the intermediate electrode layer 164 in a plan view. As a result, the formation of the parasitic capacitance Cp32 is suppressed in the region between the first upper electrode layer 25 and the intermediate electrode layer 164. Further, in the region between the substrate 10 and the first upper electrode layer 25, the formation of the parasitic capacitance Cp33 is suppressed.

Further, in the ultrasonic sensor 161, the entire second upper electrode layer 27 overlaps with the first upper electrode layer 25 in a plan view. As a result, the second upper electrode layer 27 can be appropriately capacitively coupled to the first upper electrode layer 25. Therefore, the formation of the parasitic capacitance Cp34 can be suppressed in the region between the substrate 10 and the second upper electrode layer 27.
Moreover, in the ultrasonic sensor 161, the parasitic capacitance Cp35 formed in the region between the first lower electrode layer 132 and the substrate 10 and the region between the second lower electrode layer 133 and the substrate 10 is electrically generated. It will not work because it will be open. Therefore, in the ultrasonic sensor 161, the formation of the parasitic capacitance circuit is suppressed.

Further, the ultrasonic sensor 161 includes a second lower electrode layer 133 formed on the diaphragm 11. The second lower electrode layer 133 is a first lower electrode so as to be along the peripheral edge of the first lower inner portion 134 of the first lower electrode layer 132 in the region surrounded by the inner wall of the opening 21. It is formed at a distance from the layer 132.
Thereby, the static amount of bending of the diaphragm 11 and the bending direction of the diaphragm 11 can be controlled. Therefore, it is possible to provide an ultrasonic sensor 161 capable of appropriately suppressing fluctuations in sensitivity.

Although the embodiment of the present invention has been described above, the present invention can also be implemented in other embodiments.
In the first to third embodiments described above, the lower electrode layer 23 does not necessarily have to cover the entire surface of the diaphragm 11 as long as it can suppress the formation of parasitic capacitance. For example, a part of the lower electrode layer 23 is interposed in the region between the substrate 10 and the first upper electrode layer 25, and the lower electrode layer 23 is located in the region between the substrate 10 and the second upper electrode layer 27. When a part is interposed, a lower electrode layer 23 that does not cover the entire surface of the diaphragm 11 may be adopted.

In the fourth and fifth embodiments described above, the second lower inner portion 136 may be formed only in the region surrounded by the inner wall surface of the opening 21 in a plan view. Further, the second lower inner portion 136 may be formed only in the outer region of the region surrounded by the inner wall surface of the opening 21 in a plan view.
In the fifth embodiment described above, the third upper inner portion 170 may be formed only in the region surrounded by the inner wall surface of the opening 21 in a plan view. Further, the third upper inner portion 170 may be formed only in the outer region of the region surrounded by the inner wall surface of the opening 21 in a plan view.

The ultrasonic sensors 1, 101, 121, 131, 161 according to each of the above-described embodiments can be used for an ultrasonic transmission / reception device, an ultrasonic reception device, an ultrasonic transmission device, a piezoelectric transformer, and the like.
In addition, various design changes can be made within the scope of the matters described in the claims.

1 Ultrasonic sensor 10 Substrate 11 Vibrating plate 15 First substrate main surface 16 Second substrate main surface 17 Substrate side surface 21 Opening 23 Lower electrode layer 24 First piezoelectric layer 25 First upper electrode layer 26 Second piezoelectric layer 27 Second upper electrode layer 101 Ultrasonic sensor 102 Intermediate electrode layer 103 Intermediate piezoelectric layer 121 Ultrasonic sensor 131 Ultrasonic sensor 132 First lower electrode layer 133 Second lower electrode layer 161 Ultrasonic sensor 164 Intermediate electrode layer 165 Intermediate piezoelectric layer

Claims (3)

A substrate having a first main surface on one side and a second main surface on the other side, and having an opening formed along the thickness direction from the first main surface side to the second main surface side. ,
A diaphragm formed on the first main surface of the substrate and covering the entire first main surface including the opening,
A piezoelectric element layer having a laminated structure including a lower electrode layer, a first piezoelectric layer, a first upper electrode layer, a second piezoelectric layer, and a second upper electrode layer laminated on the vibrating plate in this order. Including,
The lower electrode layer covers almost the entire diaphragm and has a first area S1 in a plan view.
The first upper electrode layer is formed on the first piezoelectric layer and has a second area S2 equal to or less than the first area S1 in a plan view.
The second piezoelectric layer is formed on the first upper electrode layer and has a shape that matches the shape of the first upper electrode layer in a plan view.
The second upper electrode layer is formed on the second piezoelectric layer and has a third area S3 equal to or less than the second area S2 in a plan view.
In a plan view, the entire first upper electrode layer overlaps with the lower electrode layer.
The first upper electrode layer is an ultrasonic sensor including a first upper drawer portion that is pulled out to a region outside the opening in a plan view. The ultrasonic sensor according to claim 1 , wherein the substrate is a semiconductor substrate. The ultrasonic sensor according to claim 2 , wherein the semiconductor substrate contains silicon.

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