JP7084232B2 - Signal transduction device - Google Patents

Description

The invention disclosed herein relates to a signal transduction device.

Conventionally, a signal transmission device that transmits a pulse signal while electrically insulating between input and output has been used in various applications (power supply device, motor drive device, etc.).

In addition, as an example of the prior art related to the above, Patent Document 1 to Patent Document 4 can be mentioned.

Japanese Unexamined Patent Publication No. 2014-007502 Japanese Unexamined Patent Publication No. 2018-014549 Japanese Unexamined Patent Publication No. 2014-003515 JP-A-2010-010762

However, in the conventional signal transmission device, the cancellation process of the instantaneous transient in-phase noise (so-called CMTI [common mode transient immunity] noise) superimposed on the received pulse signal input in parallel to the pulse receiving circuit on the secondary side is further described. There was room for improvement.

The invention disclosed in the present specification is a signal transmission device capable of speeding up noise canceling processing and reducing signal delay in view of the above-mentioned problems found by the inventor of the present application, and a signal transmission device thereof. It is intended to provide a noise canceling circuit.

The noise canceling circuit disclosed in the present specification includes a first received signal generation unit that generates a first received signal in response to the first input signal, and a second input that is input in parallel with the first input signal. A second reception signal generation unit that generates a second reception signal according to the signal, a first mask signal generation unit that generates a first mask signal according to the second input signal, and a first mask signal generation unit according to the first input signal. A second mask signal generation unit that generates a second mask signal, a first logical gate that logically calculates the first received signal and the first mask signal to generate a first output signal, and the second received signal. A second logic gate that logically calculates the second mask signal and generates a second output signal, a first discharge transistor that discharges the first input signal using the first mask signal, and the second. It has a configuration (first configuration) including a second discharge transistor that discharges the second input signal using a mask signal.

In the noise canceling circuit having the first configuration, the first received signal generation unit generates the first received signal having the first pulse width when the first input signal exceeds the threshold value. The second received signal generation unit generates the second received signal having the first pulse width when the second input signal exceeds the threshold value, and the first mask signal generation unit generates the second input signal. When the signal exceeds the threshold value, the first mask signal having a second pulse width larger than the first pulse width is generated, and the second mask signal generation unit generates the first input signal exceeding the threshold value. Occasionally, it may be configured to generate the second mask signal having the second pulse width (second configuration).

Further, in the noise canceling circuit having the second configuration described above, the first received signal generation unit and the second received signal generation unit each have a first delay time from the timing when their own input signal exceeds the threshold value. When the elapsed time, the output signal of itself is switched from the logic level at the steady state to the logic level at the time of pulse generation, while the second delay time longer than the first delay time elapses from the timing when the input signal exceeds the threshold value. At that time, the output signal is switched from the logic level at the time of pulse generation to the logic level at the steady state, so that the first pulse width is set to the difference value between the first delay time and the second delay time. The first mask signal generation unit and the second mask signal generation unit, including the delay stage, each mask their output signal from the logic level at the time of unmasking without delay at the timing when their input signal exceeds the threshold value. While switching to the logic level of time, the output signal is unmasked from the logic level at the time of masking when the second delay time elapses from the timing when the input signal exceeds the threshold value and then the third delay time elapses. It is preferable to have a configuration (third configuration) including a second delay stage in which the second pulse width is set to the sum of the second delay time and the third delay time by switching to the logic level of time.

Further, in the noise canceling circuit having the third configuration, the second pulse width is longer than the pulse duration of the first input signal and the second input signal, and the third delay time is the pulse duration. It is preferable to use a configuration shorter than the period (fourth configuration).

Further, in the noise canceling circuit having the third or fourth configuration, the first discharge transistor and the second discharge transistor are included in the first received signal generation unit and the second received signal generation unit, respectively. It is preferable to have a configuration (fifth configuration) connected between the input end and the grounding end of the first delay stage.

Further, the signal transmission device disclosed in the present specification includes a pulse generation circuit that generates a first transmission pulse signal and a second transmission pulse signal according to an input signal, and the first transmission device while insulating the input / output signal. The first received pulse signal comprises an insulating circuit that transmits the transmitted pulse signal and the second transmitted pulse signal as a first received pulse signal and a second received pulse signal to the subsequent stage, respectively, and any of the first to fifth configurations. And the second received pulse signal are input as the first input signal and the second input signal, respectively, and the first output signal and the second output signal are noise-cancelled, respectively, of the first received pulse signal and the first received pulse signal. 2 A noise canceling circuit that outputs as a received pulse signal, a pulse receiving circuit that generates a received pulse signal corresponding to the noise-cancelled first received pulse signal and the second received pulse signal, and a received pulse signal. It is preferable to have a configuration (sixth configuration) having an output drive circuit that generates an output signal.

With the signal transmission device disclosed in the present specification, it is possible to speed up the noise canceling process and reduce the signal delay.

The figure which shows one configuration example of a signal transmission device. The figure which shows one configuration example of a noise canceling circuit Timing chart showing the basic operation of the noise canceling circuit Timing chart showing an example of mask time setting (without discharge transistor) Timing chart showing an operation example (without discharge transistor) when noise is applied Timing chart showing an example of mask time setting (with discharge transistor) Timing chart showing an operation example (with a discharge transistor) when noise is applied Timing chart showing the minimum input pulse width during normal operation

<Signal transmission device>
FIG. 1 is a diagram showing a configuration example of a signal transmission device. The signal transmission device 100 of this configuration example includes a pulse generation circuit 110, an insulation circuit 120, a pulse reception circuit 130, and an output drive circuit 140.

The pulse generation circuit 110 generates transmission pulse signals S11 and S12 according to the input signal Si. More specifically, the pulse generation circuit 110 performs pulse drive (single or multiple transmission pulse output) of the transmission pulse signal S11 when notifying that the input signal Si is at a high level, and the input signal Si When notifying that the level is low, the transmission pulse signal S12 is pulse-driven. That is, the pulse generation circuit 110 pulse-drives one of the transmission pulse signals S11 and S12 according to the logic level of the input signal Si.

The insulation circuit 120 transmits the transmission pulse signals S11 and S12 to the pulse reception circuit 130 as reception pulse signals S21 and S22, respectively, while insulating between the input and output using insulating elements 121 and 122 such as a transformer.

The pulse receiving circuit 130 generates the received pulse signal S30 corresponding to the received pulse signals S21 and S22. More specifically, the pulse receiving circuit 130 receives the pulse drive of the received pulse signal S21 to raise the received pulse signal S30 to a high level, while receives the pulse drive of the received pulse signal S22 to generate the received pulse signal S30. Lower to low level. That is, the pulse receiving circuit 130 switches the logic level of the received pulse signal S30 according to the logic level of the input signal Si.

The output drive circuit 140 generates an output signal So in response to the received pulse signal S30 input from the pulse receiving circuit 130. More specifically, the output drive circuit 140 sets the output signal So to the high level when the received pulse signal S30 is high level, and sets the output signal So to low level when the received pulse signal S30 is low level. ..

<Noise canceling circuit>
FIG. 2 is a diagram showing a configuration example of a noise canceling circuit provided between the insulation circuit 120 and the pulse receiving circuit 130.

In the noise canceling circuit 150 of this configuration example, the received pulse signals S21 and S22 input in parallel from the insulating elements 121 and 122 are input signals INH and INL, respectively, and instantaneous transient in-phase noise (so-called CMTI noise) superimposed on each is used. , Hereinafter, simply abbreviated as in-phase noise), the clock signals CLKH and CLKL are generated, and these are output to the pulse receiving circuit 130 (for example, RS flip flop 131) as a noise-cancelled received pulse signal.

The noise canceling circuit 150 has received signal generation units 151 and 152, mask signal generation units 153 and 154, NOR gates 155 and 156, and discharge transistors 157 and 158 (all of which are N MOSFETs in this figure) as its components. ) And, including.

The reception signal generation unit 151 is a circuit block that generates a reception signal RCVH according to the input signal INH, and includes a resistor R1 and a delay stage DLY1.

The first end of the resistor R1 is connected to the application end of the input signal INH (= the secondary output end of the insulating element 121). The second end of the resistor R1 is connected to the input end of the delay stage DLY1.

For example, when the input signal INH rises to a high level, the delay stage DLY1 raises the received signal RCVH from the high level (= steady state logic level) when a predetermined delay time T11 elapses from the rise timing of the input signal INH. The signal is lowered to a low level (= logical level at the time of pulse generation), and the received signal RCVH is raised from the low level to the high level when a predetermined delay time T12 (> T11) has elapsed from the rising timing of the input signal INH.

That is, the received signal generation unit 151 generates a received signal RCVH having a predetermined pulse width W1 (= T12-T11) when the input signal INH rises to a high level.

The reception signal generation unit 152 is a circuit block that generates a reception signal RCVL according to the input signal INL, and includes a resistor R2 and a delay stage DLY2.

The first end of the resistor R2 is connected to the application end of the input signal INL (= the secondary output end of the insulating element 122). The second end of the resistor R2 is connected to the input end of the delay stage DLY2.

For example, when the input signal INL rises to a high level, the delay stage DLY2 raises the received signal RCVL from the high level (= steady state logic level) when a predetermined delay time T11 elapses from the rise timing of the input signal INL. The signal is lowered to a low level (= logical level at the time of pulse generation), and the received signal RCVL is raised from the low level to the high level when a predetermined delay time T12 (> T11) has elapsed from the rising timing of the input signal INL.

That is, the received signal generation unit 152 generates a received signal RCVL having a predetermined pulse width W1 (= T12-T11) when the input signal INL rises to a high level.

By the waveform shaping process in the received signal generation units 151 and 152 described above, even if the pulse widths of the input signals INH and INL are very narrow, the pulse reception process in the pulse receiving circuit 130 (= RS flip-flop 131 set / reset). ) Can be performed reliably.

The mask signal generation unit 153 is a circuit block that generates a mask signal MSKH according to the input signal INL, and includes a resistor R3 and a delay stage DLY3.

The first end of the resistor R3 is connected to the application end of the input signal INL (= the secondary output end of the insulating element 122). The second end of the resistor R3 is connected to the input end of the delay stage DLY3.

For example, when the input signal INL rises to a high level, the delay stage DLY3 changes the mask signal MSKH from the low level (= logic level at the steady state) to the high level (= at the time of pulse generation) without delay at the rising timing of the input signal INL. The mask signal MSKH is lowered from the high level to the low level when the predetermined delay time T12 elapses from the rise timing of the input signal INL and then the predetermined delay time T13 elapses.

That is, the mask signal generation unit 153 generates a mask signal MSKH having a pulse width W2 (= T12 + T13) larger than the pulse width W1 when the input signal INL rises to a high level.

The mask signal generation unit 154 is a circuit block that generates a mask signal MSKL according to the input signal INH, and includes a resistor R4 and a delay stage DLY4.

The first end of the resistor R4 is connected to the application end of the input signal INH (= the secondary output end of the insulating element 121). The second end of the resistor R4 is connected to the input end of the delay stage DLY4.

For example, when the input signal INH rises to a high level, the delay stage DLY4 changes the mask signal MSKL from the low level (= logic level at the steady state) to the high level (= at the time of pulse generation) without delay at the rising timing of the input signal INH. The mask signal MSKL is lowered from the high level to the low level when the predetermined delay time T12 elapses from the rise timing of the input signal INH and then the predetermined delay time T13 elapses.

That is, the mask signal generation unit 154 generates a mask signal MSKL having a pulse width W2 (= T12 + T13) larger than the pulse width W1 when the input signal INH rises to a high level.

The NOR gate 155 generates a clock signal CLKH by performing a NOR operation between the received signal RCVH and the mask signal MSKH. Therefore, when the mask signal MSKH is low level, the logic inversion signal of the received signal RCVH is output as the clock signal CLKH. On the other hand, when the mask signal MSKH is at a high level, the clock signal CLKH is fixed at a low level regardless of the logic level of the received signal RCVH. The clock signal CLKH generated in this way is used as a set signal of the RS flip-flop 131.

The NOR gate 156 generates a clock signal CLKL by performing a NOR operation of the received signal RCVL and the mask signal MSKL. Therefore, when the mask signal MSKL is low level, the logic inversion signal of the received signal RCVL is output as the clock signal CLKL. On the other hand, when the mask signal MSKL is at a high level, the clock signal CLKL is fixed at a low level regardless of the logic level of the received signal RCVL. The clock signal CLKL generated in this way is used as a reset signal of the RS flip-flop 131.

The drain of the discharge transistor 157 is connected to the input end of the delay stage DLY1. The source and backgate of the discharge transistor 157 are connected to the ground end. A mask signal MSKH is input to the gate of the discharge transistor 157. The discharge transistor 157 connected in this way is turned off when the mask signal MSKH is at a low level and turned on when the mask signal MSKH is at a high level. Therefore, when the mask signal MSKH is at a high level, the input signal INH (particularly the voltage applied to the input end of the delay stage DLY1) is discharged via the discharge transistor 157. That is, the discharge transistor 157 invalidates the reception of the input signal INH while receiving the input signal INL.

The drain of the discharge transistor 158 is connected to the input end of the delay stage DLY2. The source and backgate of the discharge transistor 158 are connected to the ground end. A mask signal MSKL is input to the gate of the discharge transistor 158. The discharge transistor 158 connected in this way is turned off when the mask signal MSKL is at low level and turned on when the mask signal MSKL is at high level. Therefore, when the mask signal MSKL is at a high level, the input signal INL (particularly the voltage applied to the input end of the delay stage DLY2) is discharged via the discharge transistor 158. That is, the discharge transistor 158 invalidates the reception of the input signal INL when the input signal INH is being received.

FIG. 3 is a timing chart showing the basic operation of the noise canceling circuit 150, in order from the top, input signals INH and INL (= received pulse signals S21 and S22), received signals RCVH and RCVL, mask signals MSKH and MSKL, and , Clock signals CLKH and CLKL (= received pulse signal with noise canceled) are depicted.

When a normal pulse (= a legitimate pulse input from the insulating element 121) rises in the input signal INH at time t31, a received signal RCVH (time t32 to t33) having a pulse width W1 and a mask signal having a pulse width W2 MSKL (time t31 to t34) are generated respectively. On the other hand, at time t31, since the pulse does not rise in the input signal INL, the received signal RCVL and the mask signal MSKH are each maintained at the logic level at the steady state.

As described above, when the mask signal MSKH is low level, the logic inversion signal of the received signal RCVH is output as the clock signal CLKH. Further, when the mask signal MSKL is at a high level, the clock signal CLKL is fixed at a low level regardless of the logic level of the received signal RCVL. Since the clock signal CLKL should be originally maintained at a low level, no inconsistency occurs.

Further, at time t35, when a normal pulse (= a legitimate pulse input from the insulating element 122) rises in the input signal INL, it has a received signal RCVL (time t36 to t37) having a pulse width W1 and a pulse width W2. Mask signals MSKH (time t35 to t38) are generated respectively. On the other hand, at time t35, since the pulse does not rise in the input signal INH, the received signal RCVH and the mask signal MSKL are each maintained at the logic level at the steady state.

As described above, when the mask signal MSKL is low level, the logic inversion signal of the received signal RCVL is output as the clock signal CLKL. Further, when the mask signal MSKH is at a high level, the clock signal CLKH is fixed at a low level regardless of the logic level of the received signal RCVH. Since the clock signal CLKH should be originally maintained at a low level, no inconsistency occurs.

Next, consider the case where common mode noise is superimposed on both the input signals INH and INL. For example, when a noise pulse rises in both the input signals INH and INL at time t39, the received signals RCVH and RCVL (time t40 to t41) having a pulse width W1 and the mask signal MSKH having a pulse width W2 and MSKL (time t39 to t42) are generated respectively.

Here, when the mask signal MSKH is at a high level, the clock signal CLKH is fixed at a low level regardless of the logic level of the received signal RCVH. Similarly, when the mask signal MSKL is at a high level, the clock signal CLKL is fixed at a low level regardless of the logic level of the received signal RCVL. Therefore, it is possible to appropriately cancel the common mode noise superimposed on both the input signals INH and INL.

In order to reliably cancel the in-phase noise, the pulse width W2 of the mask signals MSKH and MSKL is wider than the pulse width W1 of the received signals RCVH and RCVL caused by noise superimposition, and the pulse width W2 is a pulse. It is desirable that the width W1 completely overlaps.

That is, as shown in this figure, after the mask signals MSKH and MSKL rise to a high level (= logic level at the time of masking), the received signals RCVH and RCVL stand at a low level (= logic level at the time of pulse generation). Received signals so that the mask signals MSKH and MSKL fall to the low level (= logic level at the time of unmasking) after falling and the received signals RCVH and RCVL rise to the high level (= logic level at the steady state). It is desirable to generate RCVH and RCVL, as well as mask signals MSKH and MSKL.

In the pulse generation circuit 110 on the transmission side, at least the mask time of the mask cancel circuit 150 (= pulse width W2 of the mask signals MSKH and MSKL) elapses after one of the transmission pulse signals S11 and S12 is pulse-driven. Until then, there is a restriction that the other pulse drive of the transmission pulse signals S11 and S12 must be waited for.

That is, if the pulse widths W2 of each of the mask signals MSKH and MSKL can be narrowed, the noise canceling process can be speeded up by that amount, and the signal delay of the signal transmission device 100 can be reduced accordingly. In the following, the technical significance of the discharge transistors 157 and 158 introduced to realize this will be described in detail while comparing the behavior when they are not introduced and the behavior when they are introduced. ..

FIG. 4 is a timing chart showing an example of setting the mask time (= pulse width W2) when the discharge transistors 157 and 158 are not introduced, and the input signals INH and INL (= received pulse signals S21 and) are shown in order from the top. S22), the received signal RCVH, the mask signal MSKH, the received signal RCVL, the mask signal MSKL, the clock signals CLKH and CLKL, and the received pulse signal S30 (and thus the output signal So) are depicted.

As shown in this figure, during the pulse drive of the input signal INH, the received signal RCVH falls from the high level to the low level when the delay time T11 elapses from the timing when the input signal INH exceeds the reception threshold Vth. , When the delay time T12 (> T11) elapses from the timing when the input signal INH exceeds the reception threshold Vth, the signal rises from the low level to the high level (see time t52 to t54). As a result, the pulse width W1 of the received signal RCVH is set to the difference value (= T12-T11) of the delay times T11 and T12.

Further, the mask signal MSKL rises from the low level to the high level without delay at the timing when the input signal INH exceeds the reception threshold Vth, and further after the delay time T12 elapses from the timing when the input signal INH exceeds the reception threshold Vth. When the delay time T13'has elapsed, it falls from the high level to the low level (see time t52 to t56'). As a result, the pulse width W2'of the mask signal MSKL is set to the added value (= T12 + T13') of the delay times T12 and T13'.

Similarly, when the input signal INL is driven by a pulse, the received signal RCVL falls from the high level to the low level when the delay time T11 elapses from the timing when the input signal INL exceeds the reception threshold value Vth, while the input signal INL. When the delay time T12 (> T11) elapses from the timing when the reception threshold value Vth is exceeded, the signal rises from the low level to the high level (see time t58 to t60). As a result, the pulse width W1 of the received signal RCVL is set to the difference value (= T12-T11) of the delay times T11 and T12.

Further, the mask signal MSKH rises from the low level to the high level without delay at the timing when the input signal INL exceeds the reception threshold Vth, and further after the delay time T12 elapses from the timing when the input signal INL exceeds the reception threshold Vth. When the delay time T13'has elapsed, it falls from the high level to the low level (see time t58 to t62'). As a result, the pulse width W2'of the mask signal MSKH is set to the added value (T12 + T13') of the delay times T12 and T13'.

When the discharge transistors 157 and 158 have not been introduced, the delay time T13'must be longer than the pulse duration Tw of the input signals INH and INL. The above-mentioned pulse duration Tw means a period from when a high-level normal pulse is launched to the input signals INH and INL until it converges to a low level (= logic level at the steady state) again (time t51). (See t55 and times t57-t71).

In the following, the reason why T13'> Tw should be set when the discharge transistors 157 and 158 are not introduced will be described in detail with reference to FIG.

FIG. 5 is a timing chart showing an operation example when in-phase noise is applied when the discharge transistors 157 and 158 are not introduced. As in FIG. 6, the input signals INH and INL (= received pulse signal S21) are shown in order from the top. And S22), the received signal RCVH, the mask signal MSKH, the received signal RCVL, the mask signal MSKL, the clock signals CLKH and CLKL, and the received pulse signal S30 (and thus the output signal So) are depicted.

As shown in FIG. 3 above, when common-mode noise is superimposed on both the input signals INH and INL at the same time, the noise canceling circuit 150 can appropriately cancel the superimposed common-mode noise. can.

However, during the pulse drive of the input signals INH and INL (= receiving the normal pulse), the input signals INH and INL swing to a negative potential (= lower potential than the low level at the steady state) (time t53 to t56). , And time 59 to t62), and if in-phase noise is superimposed during this period, it is possible that only one of the input signals INH and INL exceeds the reception threshold Vth.

In this figure, due to the superposition of in-phase noise during the period when the input signal INH swings to the negative potential (= time t5x), only the input signal INL exceeds the reception threshold value Vth, and only the reception signal RCVL has noise. The resulting pulse is occurring. On the other hand, since the input signal INH does not exceed the reception threshold value Vth, the trigger for raising the mask signal MSKL to a high level is not applied.

Therefore, in order to cancel the pulse caused by noise generated in the received signal RCVL, the mask signal MSKL which has already become a high level due to the normal pulse of the input signal INH is used as it is after the delay time T12 elapses. It is necessary to maintain a high level throughout.

In particular, if T13'> Tw is set, the noise-induced pulse generated in the received signal RCVL can be appropriately canceled even in the worst case where in-phase noise is superimposed immediately before the expiration of the pulse duration Tw. Can be done. Therefore, an unnecessary pulse is not generated in the clock signal CLKL, and the drive of the received pulse signal S30 (and thus the output signal So) is not hindered.

However, when the discharge transistors 157 and 158 are not introduced, the pulse width W2'(= T12 + T13') of the mask signals MSKH and MSKL becomes large, so that there is room for further improvement in speeding up the noise canceling process.

FIG. 6 is a timing chart showing an example of setting the mask time (= pulse width W2) when the discharge transistors 157 and 158 are introduced, and is the same as in FIGS. 4 and 5, in order from the top, the input signal INH and INL (= received pulse signals S21 and S22), received signal RCVH, mask signal MSKH, received signal RCVL, mask signal MSKL, clock signals CLKH and CLKL, and received pulse signal S30 (and output signal So) are depicted. ing.

As shown in this figure, when the discharge transistors 157 and 158 are introduced, it is sufficient that the pulse width W2 (= T12 + T13) of the mask signals MSKH and MSKL is longer than the pulse duration Tw of the input signals INH and INL. The delay time T13 can be set shorter than the pulse duration Tw of the input signals INH and INL.

That is, by introducing the discharge transistors 157 and 158, the pulse width W2 of the mask signals MSKH and MSKL can be shortened from the pulse width W2'when not introduced (Tw <W2 <W2').

In the following, the reason why T13 <Tw can be set by introducing the discharge transistors 157 and 158 will be described in detail with reference to FIG. 7.

FIG. 7 is a timing chart showing an operation example when in-phase noise is applied when the discharge transistors 157 and 158 are introduced, and as in FIGS. 4 to 6, the input signals INH and INL (= reception) are shown in order from the top. Pulse signals S21 and S22), received signal RCVH, mask signal MSKH, received signal RCVL, mask signal MSKL, clock signals CLKH and CLKL, and received pulse signal S30 (and output signal So) are depicted.

In this figure, as in FIG. 5, in-phase noise is superimposed during the period (= time t5x) when the input signal INH swings to a negative potential due to the pulse drive of the input signal INH.

Here, if the pulse width W2 (= T12 + T13) of the mask signal MSKL is set longer than the pulse duration Tw of the input signals INH and INL, the worst such that in-phase noise is superimposed immediately before the expiration of the pulse duration Tw. Even in the case, the mask signal MSKL can be maintained at a high level at the time of the noise superimposition.

When the mask signal MSKL is at a high level, the input signal INL is discharged via the discharge transistor 158, as described above. As a result, the common mode noise superimposed on the input signal INL is quickly discharged and does not exceed the reception threshold value Vth, so that noise-induced pulses do not occur in the reception signal RCVL. Therefore, since it is not necessary to mask the received signal RCVL with the mask signal MSKL, the delay time T13 can be shortened and the pulse width W2 of the mask signal MSKL can be narrowed to the minimum necessary (T13 <Tw <W2).

FIG. 8 is a timing chart showing the minimum input pulse width during normal operation, and in order from the top, the input signal Si, the input signals INH and INL (= received pulse signals S21 and S22), the received signal RCVH, and the mask signal MSKH. , The received signal RCVL, the mask signal MSKL, the clock signals CLKH and CLKL, and the received pulse signal S30 (and thus the output signal So) are depicted.

As described above, the pulse generation circuit 110 on the transmission side is pulse-driven with one of the transmission pulse signals S11 and S12, and then at least the mask time of the mask cancel circuit 150 (= pulse width of the mask signals MSKH and MSKL). There is a restriction that the other pulse drive of the transmission pulse signals S11 and S12 must be waited until W2) elapses. That is, the transmission standby time Twait (= signal delay from the pulse edge detection of the input signal Si to the pulse drive) of the pulse generation circuit 110 becomes shorter as the pulse width W2 of the mask signals MSKH and MSKL is narrowed.

Therefore, if the discharge transistors 157 and 158 are introduced, the pulse width W2 of the mask signals MSKH and MSKL can be narrowed to speed up the noise canceling process, so that the signal delay of the signal transmission device 100 can be reduced. Become. Further, by shortening the transmission standby time Twait, it is possible to increase the drive frequency fsw of the switch output unit 10.

<Other variants>
The signal transmission device disclosed in the present specification includes general applications (for example, an insulated gate driver, a motor driver, and an isolator that handle high voltage) that require signal transmission while electrically insulating between input and output. , Or other ICs, etc.) can be widely applied.

In addition to the above embodiments, the various technical features disclosed herein can be modified in various ways without departing from the spirit of the technical creation. For example, mutual replacement between a bipolar transistor and a MOS field effect transistor and logic level inversion of various signals are arbitrary. That is, it should be considered that the above-described embodiment is exemplary in all respects and is not restrictive, and the technical scope of the present invention is not limited to the above-described embodiment and claims for a patent. It should be understood that the meaning of the scope and equality and all changes belonging to the scope are included.

The invention disclosed herein can be used, for example, in all applications where signal transmission is required while electrically insulating between input and output.

100 Signal transmission device 110 Pulse generation circuit 120 Insulation circuit 121, 122 Insulation element 130 Pulse reception circuit 131 RS flip-flop 140 Output drive circuit 150 Noise cancellation circuit 151, 152 Receive signal generator 153, 154 Mask signal generator 155, 156 NOR Gate 157, 158 Discharge transistor (NHPLC)
DLY1, DLY2, DLY3, DLY4 Delay stage R1, R2, R3, R4 Resistance

Claims (6)

A first received signal generator that generates a first received signal according to the first input signal,
A second received signal generation unit that generates a second received signal according to a second input signal input in parallel with the first input signal.
A first mask signal generation unit that generates a first mask signal in response to the second input signal,
A second mask signal generation unit that generates a second mask signal in response to the first input signal,
A first logic gate that logically operates the first received signal and the first mask signal to generate a first output signal,
A second logic gate that logically operates the second received signal and the second mask signal to generate a second output signal, and
A first discharge transistor that discharges the first input signal using the first mask signal, and
A second discharge transistor that discharges the second input signal using the second mask signal, and
A noise canceling circuit characterized by having. The first received signal generation unit generates the first received signal having the first pulse width when the first input signal exceeds the threshold value.
The second received signal generation unit generates the second received signal having the first pulse width when the second input signal exceeds the threshold value.
The first mask signal generation unit generates the first mask signal having a second pulse width larger than the first pulse width when the second input signal exceeds the threshold value.
The second mask signal generation unit generates the second mask signal having the second pulse width when the first input signal exceeds the threshold value.
The noise canceling circuit according to claim 1. The first received signal generation unit and the second received signal generation unit are respectively.
When the first delay time elapses from the timing when the own input signal exceeds the threshold, the own output signal is switched from the steady logic level to the pulse generation logic level, while the input signal exceeds the threshold. By switching the output signal from the logic level at the time of pulse generation to the logic level at the steady state when the second delay time longer than the first delay time elapses from the timing, the first pulse width is set to the first delay. Includes a first delay stage that is set to the difference between the time and the second delay time.
The first mask signal generation unit and the second mask signal generation unit are respectively.
While switching its own output signal from the logic level at the time of unmasking to the logic level at the time of masking without delay at the timing when its own input signal exceeds the threshold value, the second delay time from the timing when the input signal exceeds the threshold value. By switching the output signal from the logic level at the time of masking to the logic level at the time of unmasking when the third delay time elapses after the lapse of time, the second pulse width is changed to the second delay time and the third delay time. Includes a second delay stage to set to the value added to the delay time,
The noise canceling circuit according to claim 2, wherein the noise canceling circuit is characterized in that. The third aspect of claim 3, wherein the second pulse width is longer than the pulse duration of the first input signal and the second input signal, and the third delay time is shorter than the pulse duration. Noise canceling circuit. The first discharge transistor and the second discharge transistor are connected between the input end and the ground end of the first delay stage included in the first received signal generation unit and the second received signal generation unit, respectively. The noise canceling circuit according to claim 3 or 4, wherein the noise canceling circuit is characterized by the above. A pulse generation circuit that generates a first transmission pulse signal and a second transmission pulse signal according to the input signal, and
An insulating circuit that transmits the first transmission pulse signal and the second transmission pulse signal as a first reception pulse signal and a second reception pulse signal to the subsequent stage while insulating between the input and output, respectively.
The first received pulse signal and the second received pulse signal are input as the first input signal and the second input signal, respectively, and the first output signal and the second output signal are noise-cancelled, respectively. The noise canceling circuit according to any one of claims 1 to 5, which is output as a received pulse signal and the second received pulse signal.
A pulse reception circuit that generates a reception pulse signal corresponding to the noise-canceled first reception pulse signal and the second reception pulse signal, and
An output drive circuit that generates an output signal corresponding to the received pulse signal,
A signal transmission device characterized by having.

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