JP7086705B2 - Interface circuits and electronic devices - Google Patents

Description

The present invention relates to an interface circuit and an electronic device in which a master device and a plurality of slave devices are connected by a two-wire communication means.

In recent years, electronic devices equipped with many sensors (for example, cameras, proximity sensors, orientation sensors, acceleration sensors, angular velocity sensors, illuminance sensors, etc.) such as smartphones have become widespread. In such electronic devices, a two-wire communication protocol such as an I2C interface is used for sensor control and sensing data acquisition.

By the way, many sensors (devices) are also installed in electronic devices such as self-propelled robot vacuum cleaners, and it is expected that they will become more widespread. Robot vacuum cleaners are required to be equipped with a plurality of distance measuring sensors to accurately measure the distance to surrounding obstacles and perform efficient cleaning. Therefore, sensing data is acquired for a plurality of sensors of the same type via as few signal lines as possible. Further, the configuration in which a plurality of devices are connected by a two-wire communication protocol is applied not only to a robot vacuum cleaner but also to, for example, an image forming apparatus (see, for example, Patent Document 1 and Patent Document 2).

Japanese Unexamined Patent Publication No. 2009-118155 Japanese Unexamined Patent Publication No. 2010-188574

In the image forming apparatus described in Patent Document 1, a slave node is connected to a bus-type serial communication system including a master node, and the slave node sets its own slave address based on an input analog voltage value. It has an address generator. In the image forming apparatus described above, since the analog voltage value is converted into a slave address by A / D conversion, there is a problem that the circuit scale increases and the configuration becomes complicated.

The image forming apparatus described in Patent Document 2 includes an ink cartridge (device) that is interchangeably mounted at a plurality of loading positions, a memory held in the ink cartridge, and a communication means for accessing the memory. The address data is generated based on the correspondence between the loading position and the ink type by the address generation means. And I2C communication is used as a communication means. In the image forming apparatus described above, a plurality of terminals are provided on the ink cartridge, and a slave address is set by a combination of signals transmitted via the terminals. Therefore, when increasing the number of devices to be connected, it is necessary to increase the number of terminals for setting addresses, which causes problems such as an increase in size and complexity of the devices.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an interface circuit and an electronic device capable of easily identifying a slave device.

The interface circuit according to the present invention is an interface circuit in which a master device and a plurality of slave devices are connected by a two-wire communication means, and the master device is an address setting separately provided for the communication means. The plurality of slave devices are connected in order via the means, and each of the plurality of slave devices has a unique slave address due to a slave address setting signal transmitted from the master device via the address setting means. A default slave address that is set and is common to each other is set in combination with the unique slave address, and the slave device has a register map including preset valid registers and signals to the default slave address. Upon receipt, the valid register is accessed to enable the unique slave address .

In the interface circuit according to the present invention, the register map includes a preset limit register, and the limit register is a communication transmitted to the unique slave address when the unique slave address is enabled. It may be configured to allow access only to.

In the interface circuit according to the present invention, the slave address setting signal has a waveform in which a plurality of pulses are combined, and the plurality of slave devices count the number of the pulses to set the unique slave address. May be.

In the interface circuit according to the present invention, the slave device may be configured to output a slave address setting signal in which the number of pulses is changed with respect to the input slave address setting signal to the next connected slave device. ..

The electronic device according to the present invention is characterized by comprising an interface circuit according to the present invention.

According to the present invention, a unique slave address can be assigned to a plurality of slave devices by transmitting a slave address setting signal from the master device. That is, since the slave address to be assigned is determined according to the connection status in the interface circuit, the slave device does not need to individually specify the address and can be easily identified.

It is a schematic block diagram which shows the outline of the interface circuit which concerns on 1st Embodiment of this invention. It is a communication format in the I2C interface, and is explanatory drawing which shows an example of the data structure at the time of Read. It is a communication format in the I2C interface, and is explanatory drawing which shows an example of the data structure at the time of Write. It is explanatory drawing which shows the slave address setting signal transmitted through the address setting means. It is a schematic block diagram which shows the outline of a slave device. It is explanatory drawing which shows an example of the register map used in the interface circuit which concerns on 3rd Embodiment of this invention. It is a schematic external view which shows the robot vacuum cleaner which is an example of an electronic device.

(First Embodiment)
Hereinafter, the interface circuit according to the first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram showing an outline of an interface circuit according to a first embodiment of the present invention.

In the interface circuit 1 according to the first embodiment of the present invention, the master device 10 and the plurality of slave devices 20 are connected by a two-wire communication means. A serial communication unit 2 (an example of a two-wire communication means) provided for each of the master device 10 and the slave device 20 is connected to the SCL line 71 and the SDA line 72. The SCL line 71 is a reference clock line, and the SDA line 72 is a data line. FIG. 1 shows a configuration in which five slave devices 21 to 25 are connected as slave devices 20, but the number of slave devices 20 connected to the master device 10 is not limited to this. It may be changed as appropriate. The SCL line 71 and the SDA line 72 are connected to the VIO of the I / O power supply voltage via the resistance RSCL and the resistance RSDA, and are pulled up to reach a high level when communication is not performed. The detailed configuration of the slave device 20 will be described with reference to FIG. 4 described later.

In the interface circuit 1, two-wire synchronous serial communication is performed using the SCL line 71 and the SDA line 72, and a serial clock signal and a serial data signal are transmitted and received. The serial clock signal is generated by the bus master, and the serial data signal is bidirectional communication in which the direction of input and output is switched by transmission / reception. The I2C interface is a two-wire synchronous serial communication interface, and for the sake of explanation below, communication using I2C may be referred to as I2C communication. When a plurality of slave devices 20 are connected to the master device 10, the slave device 20 can determine which slave device 20 the communication is for by setting different unique slave addresses. ..

Therefore, the interface circuit 1 is configured to set a unique slave address by the address setting means 3. Specifically, the master device 10 and the slave device 20 each include an address setting means 3, from the master device 10, a first slave device 21, a second slave device 22, ..., And a fifth slave device 25. It is connected in the order of. The communication performed by the address setting means 3 will be described in detail with reference to FIG. 3 described later.

FIG. 2A is an explanatory diagram showing an example of a data configuration at the time of Read, which is a communication format in the I2C interface, and FIG. 2B is an explanatory diagram showing an example of a data structure at the time of Write, which is a communication format in the I2C interface. It is a figure. In FIGS. 2A and 2B, in order to distinguish between the signal transmitted from the master device 10 to the slave device 20 and the signal transmitted from the slave device 20 to the master device 10, the signal transmitted from the slave device 20 to the master device 10 is transmitted. The signal is hatched.

2A and 2B show an example of a data configuration transmitted / received by the interface circuit 1, and data is transmitted / received in the order from the left side to the right side of the drawing.

As a communication procedure, first, the master device 10 specifies a start condition (Start), a slave address (Slave Address) to be communicated with, and data (Read / Write) for all slave devices 20. RW) "0" is transmitted.

The slave device 20 that has received the signal transmitted from the master device 10 checks whether the received slave address matches its own slave address. As a result, if the slave addresses do not match, the system returns to the standby state. On the other hand, if the slave addresses match, "ACK" is transmitted to inform the master device 10 that communication is possible.

After that, in the read signal RS at the time of Read shown in FIG. 2A, the word address (Word Address) of the register is transmitted from the master device 10, and the slave device 20 outputs “ACK”. Then, the master device 10 issues a stop condition (Stop), outputs the start condition and the slave address again, and outputs "1" indicating the Read mode, whereby the slave device 20 is in the Read mode. become.

The slave device 20 targeted for communication sequentially transmits the register contents (Read Data) starting with the word address in 8-bit units, and the master device 10 outputs "ACK". This process is repeated as appropriate, and when the master device 10 changes to "ACK" and issues "NACK" and a stop condition, communication is stopped and the slave device 20 is put into a communication standby state.

Further, in the write signal WS at the time of Write shown in FIG. 2B, after the master device 10 issues the start condition and the slave address, the corresponding slave device 20 returns "ACK". After that, the master device 10 transmits the word address of the register to be written, and the slave device 20 returns "ACK" to be in a writable state. Then, the master device 10 sequentially transmits 8-bit write data (Write Data), the slave device 20 outputs "ACK", and the information is written to the register of the slave device 20. Finally, the master device 10 issues a stop condition, communication is stopped, and the slave device 20 is in a communication standby state.

FIG. 3 is an explanatory diagram showing a slave address setting signal transmitted via the address setting means.

FIG. 3 shows waveforms of slave address setting signals (signals S1 to S5) transmitted to each of the first slave device 21 to the fifth slave device 25. As shown in FIG. 3, the slave address setting signal is a waveform in which a plurality of pulse PSs are combined.

Specifically, the signal S1 is a slave address setting signal transmitted from the master device 10 to the first slave device 21, and has seven pulse PSs. The signal S2 is a slave address setting signal transmitted from the first slave device 21 to the second slave device 22, and has six pulse PSs. The signal S3 is a slave address setting signal transmitted from the second slave device 22 to the third slave device 23, and has five pulse PSs. The signal S4 is a slave address setting signal transmitted from the third slave device 23 to the fourth slave device 24, and has four pulse PSs. The signal S5 is a slave address setting signal transmitted from the fourth slave device 24 to the fifth slave device 25, and has three pulse PSs. That is, in the signal S1 to the signal S5, the number of pulse PSs decreases by one in order.

In the slave address setting means 3, the output terminal (GPIO terminal) of the master device 10 and the input terminal (DI terminal) of the first slave device 21 are connected. The output terminal (DO terminal) of each slave device 20 is connected to the DI terminal of the next slave device 20. That is, the interface circuit 1 is a daisy chain connection in which the serial communication unit 2 and the slave address setting means 3 are connected by two types.

When the signal S1 is input, the first slave device 21 cuts off the first pulse PS and outputs the second and subsequent pulse PSs. The signal S2, which has one less pulse PS than the signal S1, is input to the second slave device 22, and the pulse PS is further reduced by one and output. As described above, the slave device 20 is configured to output the slave address setting signal in which the number of pulse PSs is changed to the input slave address setting signal to the next connected slave device 20.

The slave address setting means 3 sets the slave address by counting the number of rising edges of the pulse PS in the signal input by the end of the slave address setting. In the signals S1 to S5 shown in FIG. 3, the number of rising edges is 3 to 7, so that, for example, the lower three digits of the slave address can be set to 3 to 7 to allocate a unique slave address. .. That is, in the first slave device 21, the slave address is set to "0000111", in the second slave device 22, the slave address is set to "0000110", and in the third slave device 23, the slave address is set to "0000101". In the fourth slave device 24, the slave address is set to "0000100", and in the fifth slave device 25, the slave address is set to "00000011". The slave address setting means 3 may convert to an arbitrary I2C slave address by using a decoder or a conversion table instead of using a continuous slave address.

In the present embodiment, the slave address is 7 bits, but the present invention is not limited to this, and the number of bits of the slave address may be appropriately changed. When the slave address is 7 bits, a maximum of 128 slave addresses can be set.

As described above, each of the plurality of slave devices 20 is set with a unique slave address by the slave address setting signal transmitted from the master device 10 via the address setting means 3. By transmitting the slave address setting signal from the master device 10 in this way, a unique slave address can be assigned to the plurality of slave devices 20. That is, since the slave address to be assigned is determined according to the connection status in the interface circuit 1, the slave device 20 does not need to individually specify the address and can be easily identified.

In the present embodiment, since the number of pulse PSs is counted, it is possible to easily set a unique slave address while avoiding erroneous detection due to a minute waveform deviation or the like. Further, by changing the number of pulse PSs of the slave address setting signal in order and outputting them, it is possible to easily set each unique slave address.

(Second Embodiment)
Next, the interface circuit according to the second embodiment of the present invention will be described with reference to the drawings. In the second embodiment, the components having substantially the same functions as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

FIG. 4 is a schematic configuration diagram showing an outline of a slave device.

In the interface circuit 1 according to the second embodiment of the present invention, the slave device 20 has a sensor circuit 31, a control logic 32, and a register in addition to the I2C circuit 34 corresponding to the serial communication unit 2 and the address setting means 3. It is equipped with 33. The sensor circuit 31 is connected to the I2C circuit 34 via the control logic 32 and the register 33. In the I2C circuit 34, the SCL terminal (corresponding to the SCL line 71) and the SDA terminal (corresponding to the SDA line 72) are connected to perform I2C communication.

The address setting means 3 is provided between the DI terminal and the DO terminal, and each part will be described along with the flow of signals from the DI terminal. The signal input from the DI terminal (hereinafter abbreviated as DI signal) passes through the Schmitt trigger buffer SB1 and is input to the counter 36, the pulse detecting means 37, and the first buffer B1. The counter 36 counts the number of rising edges of the DI signal (for example, signal S1 and the like), and outputs the count value to the decoder 35. The decoder 35 converts the input count value into the corresponding slave address and outputs it to the I2C circuit 34. The I2C circuit 34 communicates based on the input slave address.

The pulse detecting means 37 cuts off the first pulse PS of the DI signal, detects the rising edge and the falling edge once each, and then turns on SW1. When SW1 is turned ON, the output of the first buffer B1 is output to the DO terminal via the second buffer B2. That is, among the DI signals input to the first buffer B1, the first pulse PS is not output because SW1 is turned off, and after SW1 is turned on, the second and subsequent pulse PSs are displayed. It is output from the DO terminal.

A POR 38 is connected to the counter 36 and the pulse detecting means 37, and the POR 38 resets the counter 36 and the pulse detecting means 37 when the power of the slave device 20 is turned on. After the power is turned on, the master device 10 can assign a unique slave address to each slave device 20 by setting the slave address before starting the I2C communication.

(Third Embodiment)
Next, the interface circuit according to the third embodiment of the present invention will be described with reference to the drawings. In the third embodiment, the components having substantially the same functions as those of the first embodiment and the second embodiment are designated by the same reference numerals and the description thereof will be omitted.

FIG. 5 is an explanatory diagram showing an example of a register map used in the interface circuit according to the third embodiment of the present invention.

In the interface circuit 1 according to the third embodiment of the present invention, the slave device 20 is set with a default slave address together with a unique slave address. In the following, for the sake of explanation, a unique slave address may be referred to as a multi-slave address. The default slave address is set in common in all slave devices 20 in advance. For example, when the default slave address is set to "0101001", the multi-slave address is an arbitrary 7-bit address and is set differently from the default slave address.

The register map shown in FIG. 5 is stored in advance in the storage area of the slave device 20. In the register map, a register address (ADDR) and a register (a column of BIT) are associated with each other. The register address "00h" is a register for common setting for a plurality of slave devices 20, and in the register map shown in FIG. 5, the register for setting the operation mode (COP2 to COP7) and the register for software reset (RST). ) And a multi-slave register (MLT_SLV) that sets the validity / invalidity of the multi-slave address.

When resetting after the power is turned on, the software reset register initializes the plurality of slave devices 20, and then the slave address is assigned by the address setting signal from the master device 10. Here, by changing the multi-slave register (valid register) from "0" to "1", the multi-slave address becomes valid in the plurality of slave devices 20. That is, when the multi-slave register is set to "0", the multi-slave address is invalid.

Further, at the register address "01h", operation setting registers (OP0 to OP7) unique to each slave device 20 are arranged. The register address "02h" and the register address "03h" are read-only registers, and 16-bit digital information (RANGE0 to RANGE15) is stored. For example, when the slave device 20 is a distance measuring sensor, the digital information corresponds to the measured distance value. Regarding the access to the register (restricted register) corresponding to the register address "01h" to the register address "03h" described above, when the multi-slave register is "1", only the communication transmitted to the multi-slave address is performed. It is said to be accessible.

As described above, the slave device 20 has a register map including a preset valid register, and when a signal for the default slave address is received, the slave device 20 accesses the valid register to enable a unique slave address. It is said that. By setting the valid register in this way, it is possible to distinguish between the slave device 20 incorporated in the interface circuit 1 and the other devices. That is, by accessing the valid register and enabling the unique slave address, it is recognized as one of the plurality of slave devices 20, and bidirectional communication with the master device 10 is started.

The register map also includes preset limit registers. When the multi-slave address is enabled, the restriction register allows access only to the communication sent to the multi-slave address. Since the slave device 20 is set with two types, a multi-slave address and a default slave address, it is possible to retrieve the communication of a plurality of devices of the same type without collision. In addition, access to restricted registers can be restricted to avoid communication conflicts between multiple devices.

(Electronics)
The interface circuit according to the first to third embodiments of the present invention described above can be applied to an electronic device. Next, a robot vacuum cleaner, which is an example of an electronic device, will be described with reference to the drawings.

FIG. 6 is a schematic external view showing a robot vacuum cleaner which is an example of an electronic device.

The robot vacuum cleaner 50 is provided with five distance measuring sensors 60 centered on the front in the traveling direction. The robot vacuum cleaner 50 is self-propelled and cleans while detecting the distance to an obstacle by the distance measuring sensor 60. The distance measuring sensor 60 corresponds to the slave device 20 described above, and performs I2C communication. When the power of the robot vacuum cleaner 50 is turned on, by setting multi-slave addresses for the five distance measuring sensors 60, obstacles in five directions can be detected and data can be acquired via I2C communication.

It should be noted that the embodiments disclosed this time are examples in all respects and do not serve as a basis for a limited interpretation. Therefore, the technical scope of the present invention is not construed solely by the embodiments described above, but is defined based on the description of the scope of claims. It also includes all changes within the meaning and scope of the claims.

1 Interface circuit 2 Serial communication unit (example of communication means)
3 Address setting means 10 Master device 20 Slave device 50 Robot vacuum cleaner (an example of electronic equipment)
60 Distance measurement sensor 71 SCL line 72 SDA line

Claims (5)

An interface circuit in which a master device and a plurality of slave devices are connected by a two-wire communication means.
In the master device, the plurality of slave devices are sequentially connected to the communication means via an address setting means separately provided.
A unique slave address is set for each of the plurality of slave devices by a slave address setting signal transmitted from the master device via the address setting means, and the plurality of slave devices are shared with each other together with the unique slave address. The default slave address is set,
The slave device is
It has a register map containing preset valid registers and
Upon receiving a signal for the default slave address, access the valid register to enable the unique slave address.
An interface circuit featuring. The interface circuit according to claim 1 .
The register map contains preset limit registers.
The restriction register is an interface circuit characterized in that when the unique slave address is enabled, access is permitted only to the communication transmitted to the unique slave address. The interface circuit according to claim 1 or 2 .
The slave address setting signal is a waveform in which a plurality of pulses are combined.
The plurality of slave devices are an interface circuit characterized in that the number of the pulses is counted and the unique slave address is set. The interface circuit according to claim 3 .
The slave device is an interface circuit characterized in that, with respect to an input slave address setting signal, a slave address setting signal in which the number of pulses is changed is output to the next connected slave device. An electronic device provided with the interface circuit according to any one of claims 1 to 4 .

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