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JP7087328B2 - Electronic devices and manufacturing methods for electronic devices - Google Patents
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JP7087328B2 - Electronic devices and manufacturing methods for electronic devices - Google Patents

Electronic devices and manufacturing methods for electronic devices Download PDF

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JP7087328B2
JP7087328B2 JP2017193421A JP2017193421A JP7087328B2 JP 7087328 B2 JP7087328 B2 JP 7087328B2 JP 2017193421 A JP2017193421 A JP 2017193421A JP 2017193421 A JP2017193421 A JP 2017193421A JP 7087328 B2 JP7087328 B2 JP 7087328B2
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wiring board
electrodes
insulating wall
solder
electronic component
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JP2019067975A (en
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泰紀 上村
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Fujitsu Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps

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  • Wire Bonding (AREA)

Description

本願は、電子装置、及び電子装置の製造方法に関する。 The present application relates to an electronic device and a method for manufacturing the electronic device.

電子装置は、小型化の一途を辿っている。電子装置の小型化に対応するため、近年では、例えば、半導体チップの実装構造についても各種の形態が提案されている(例えば、特許文献1-5を参照)。 Electronic devices are becoming smaller and smaller. In recent years, in order to cope with the miniaturization of electronic devices, various forms have been proposed for mounting structures of semiconductor chips, for example (see, for example, Patent Document 1-5).

特開2005-340738号公報Japanese Unexamined Patent Publication No. 2005-340738 特開2008-147317号公報Japanese Unexamined Patent Publication No. 2008-147317 特開2015-149314号公報Japanese Unexamined Patent Publication No. 2015-149314 特許第4022139号公報Japanese Patent No. 4022139 特許第5443849号公報Japanese Patent No. 5443489

電子装置が処理する情報量の増大に伴い、例えば、半導体チップ等の電子部品の実装に用いられるはんだボール数は増大の一途を辿っている。また、電子装置が処理する情報量の増加に伴って電子部品の消費電力も増大しており、半導体チップ等の電子部品の実装に用いられるはんだボールは、許容される電流密度を上回らない程度の大きさが求められる。よって、電子部品の実装に用いられるはんだボール間のピッチは、不可避的に狭小化している。 As the amount of information processed by electronic devices increases, the number of solder balls used for mounting electronic components such as semiconductor chips is steadily increasing. In addition, as the amount of information processed by electronic devices increases, the power consumption of electronic components also increases, and the solder balls used for mounting electronic components such as semiconductor chips do not exceed the allowable current density. Size is required. Therefore, the pitch between the solder balls used for mounting electronic components is inevitably narrowed.

はんだボール間のピッチが狭小化すると、電気回路のショートを生じる可能性が高まる。よって、BGAパッケージ基板に備わるはんだボールは、互いに離間した状態でBGAパッケージ基板に融着されることが求められる。しかし、電極のピッチの微細化の進展に伴い、はんだボール同士の接触を回避することが困難になりつつある。 When the pitch between the solder balls is narrowed, the possibility of short-circuiting the electric circuit increases. Therefore, the solder balls provided on the BGA package substrate are required to be fused to the BGA package substrate in a state of being separated from each other. However, with the progress of miniaturization of the electrode pitch, it is becoming difficult to avoid contact between the solder balls.

そこで、本発明は、電極同士の接続部のショートを抑制する技術を提供することを課題とする。 Therefore, it is an object of the present invention to provide a technique for suppressing a short circuit between electrodes.

1つの態様では、電子装置は、複数の電極が表面に配列されている配線基板と、複数の電極が配列されている部位を覆うはんだを介して配線基板に接合される電子部品と、はんだを複数の電極間で仕切る絶縁壁と、を備える。 In one embodiment, the electronic device comprises a wiring board in which a plurality of electrodes are arranged on the surface, an electronic component bonded to the wiring board via a solder covering a portion in which the plurality of electrodes are arranged, and solder. It is provided with an insulating wall partitioning between a plurality of electrodes.

1つの側面として、電極同士の接続部のショートを抑制することができる。 As one aspect, it is possible to suppress a short circuit in the connection portion between the electrodes.

図1は、実施形態に係る電子装置の内部構造を示した図である。FIG. 1 is a diagram showing an internal structure of an electronic device according to an embodiment. 図2は、電子部品の製造方法の一例を示した第1の図である。FIG. 2 is a first diagram showing an example of a method for manufacturing an electronic component. 図3は、電子部品の一例を示した斜視図である。FIG. 3 is a perspective view showing an example of an electronic component. 図4は、電子部品の実装方法の一例を示した第1の図である。FIG. 4 is a first diagram showing an example of a mounting method of electronic components. 図5は、電子部品の実装方法の一例を示した第2の図である。FIG. 5 is a second diagram showing an example of a mounting method of electronic components. 図6は、電子部品の実装方法の一例を示した第3の図である。FIG. 6 is a third diagram showing an example of a mounting method of electronic components. 図7は、配線基板の製造方法の一例を示した第1の図である。FIG. 7 is a first diagram showing an example of a method for manufacturing a wiring board. 図8は、電子装置の変形例および比較例を示した図である。FIG. 8 is a diagram showing a modified example and a comparative example of the electronic device. 図9は、配線基板の製造方法の一例を示した第2の図である。FIG. 9 is a second diagram showing an example of a method for manufacturing a wiring board. 図10は、配線基板の製造方法の一例を示した第3の図である。FIG. 10 is a third diagram showing an example of a method for manufacturing a wiring board. 図11は、電子部品の製造方法の一例を示した第2の図である。FIG. 11 is a second diagram showing an example of a method for manufacturing an electronic component. 図12は、比較例を示した第1の図である。FIG. 12 is a first diagram showing a comparative example. 図13は、比較例を示した第2の図である。FIG. 13 is a second diagram showing a comparative example.

以下、実施形態について説明する。以下に示す実施形態は、単なる例示であり、本開示の技術的範囲を以下の態様に限定するものではない。 Hereinafter, embodiments will be described. The embodiments shown below are merely examples, and the technical scope of the present disclosure is not limited to the following aspects.

図1は、実施形態に係る電子装置の内部構造を示した図である。電子装置1は、電子部品2と配線基板3とを備える電子装置である。電子装置1の具体例としては、例えば、コンピュータ、通信装置、携帯端末、医療機器、産業用機器、その他の様々な電子装置が挙げられる。 FIG. 1 is a diagram showing an internal structure of an electronic device according to an embodiment. The electronic device 1 is an electronic device including an electronic component 2 and a wiring board 3. Specific examples of the electronic device 1 include computers, communication devices, mobile terminals, medical devices, industrial devices, and various other electronic devices.

電子部品2は、はんだ4によって配線基板3に接合されている。はんだ4としては、例えば、Snを主成分とするSnAgはんだ、SnAgCuはんだ、またはInSnはんだが挙げられる。電子部品2は、板状の形態を有する電子部品本体2Aと、電子部品本体2Aの表面に縦横に配列される電極2Bと、電子部品本体2Aの表面に形成された絶縁壁2Cとを有する。電子部品本体2Aは、微細な配線構造を有する電子部品である。電子部品本体2Aの具体例としては、例えば、微細な回路が集積された半導体装置が挙げられる。電極2Bは、微細な配線構造を有する電子部品本体2Aの表面に形成されているため、電子部品本体2Aの配線構造と同様に微細な電極である。 The electronic component 2 is joined to the wiring board 3 by the solder 4. Examples of the solder 4 include SnAg solder containing Sn as a main component, SnAgCu solder, and InSn solder. The electronic component 2 has an electronic component body 2A having a plate-like shape, electrodes 2B arranged vertically and horizontally on the surface of the electronic component body 2A, and an insulating wall 2C formed on the surface of the electronic component body 2A. The electronic component main body 2A is an electronic component having a fine wiring structure. Specific examples of the electronic component main body 2A include a semiconductor device in which fine circuits are integrated. Since the electrode 2B is formed on the surface of the electronic component main body 2A having a fine wiring structure, it is a fine electrode similar to the wiring structure of the electronic component main body 2A.

絶縁壁2Cは、電子部品本体2Aの表面に形成された絶縁材料の構造体である。絶縁壁2Cは、電子部品本体2Aの表面から立設するように形成された壁状の構造体である。絶縁壁2Cは、縦横に配列された各電極2B間に壁状のものを形成する構造体であるため、絶縁壁2C全体を俯瞰して見た場合、後述するように格子状の形態を呈する。 The insulating wall 2C is a structure of an insulating material formed on the surface of the electronic component main body 2A. The insulating wall 2C is a wall-shaped structure formed so as to stand upright from the surface of the electronic component main body 2A. Since the insulating wall 2C is a structure that forms a wall-like structure between the electrodes 2B arranged vertically and horizontally, when the entire insulating wall 2C is viewed from a bird's-eye view, it exhibits a grid-like shape as described later. ..

配線基板3は、板状の形態を有する基材3Aと、基材3Aの表面に縦横に配列される電極3Bとを有する。基材3Aは、電極3Bを表面に形成するための基材であり、例えば、樹脂や繊維状の素材を固めた板状の部品を適用可能である。電極3Bは、基材3Aの表面の電子部品2が実装される部位に形成される。電極3Bは、電子部品2の各電極2Bに対応する位置に配置されている。すなわち、電極3Bは、電極2Bと同様、基材3Aの表面に縦横に配列されている。 The wiring board 3 has a base material 3A having a plate-like shape and electrodes 3B arranged vertically and horizontally on the surface of the base material 3A. The base material 3A is a base material for forming the electrode 3B on the surface, and for example, a plate-shaped component obtained by solidifying a resin or a fibrous material can be applied. The electrode 3B is formed on the surface of the base material 3A at a portion where the electronic component 2 is mounted. The electrodes 3B are arranged at positions corresponding to the respective electrodes 2B of the electronic component 2. That is, the electrodes 3B are arranged vertically and horizontally on the surface of the base material 3A, like the electrodes 2B.

ところで、はんだ4は、基材3Aの表面のうち、複数の電極3Bが配列されている部位全体を覆うようにシート状に配置される。しかし、はんだ4は、絶縁壁2Cによって電極3B間で仕切られている。また、絶縁壁2Cの配線基板3側の先端が、基材3Aに埋まっているとき、絶縁壁2Cの配線基板3側の先端と、先端を挟む2つの側面とは、基材3Aと接している。そして、はんだ4を電極3B間で仕切る絶縁壁2Cは、図1に示されるように、配線基板3側の先端が、各電極3Bの間の部分で基材3Aに埋まっている(突き刺さっていると捉えることもできる)。すなわち、はんだ4は、複数の電極3Bが配列されている部位全体を覆うように配置されているものの、各電極3B間を仕切る絶縁壁2Cにより、はんだ4を通じた各電極3B間の電気的な導通が遮断されている。したがって、各電極3Bは、はんだ4の部分を通じた電気的な経路については絶縁壁2Cによって互いに絶縁されている。各電極2Bも電極3Bと同様、はんだ4の部分を通じた電気的な経路に
ついては絶縁壁2Cによって互いに絶縁されている。
By the way, the solder 4 is arranged in a sheet shape so as to cover the entire portion of the surface of the base material 3A where the plurality of electrodes 3B are arranged. However, the solder 4 is partitioned between the electrodes 3B by the insulating wall 2C. Further, when the tip of the insulating wall 2C on the wiring board 3 side is buried in the base material 3A, the tip of the insulating wall 2C on the wiring board 3 side and the two side surfaces sandwiching the tip are in contact with the base material 3A. There is. As shown in FIG. 1, the insulating wall 2C that partitions the solder 4 between the electrodes 3B has the tip on the wiring board 3 side embedded in the base material 3A at the portion between the electrodes 3B (pierced). It can also be regarded as). That is, although the solder 4 is arranged so as to cover the entire portion where the plurality of electrodes 3B are arranged, the insulating wall 2C partitioning the electrodes 3B provides electrical electrical between the electrodes 3B through the solder 4. The continuity is cut off. Therefore, the electrodes 3B are insulated from each other by the insulating wall 2C for the electrical path through the portion of the solder 4. Like the electrode 3B, the electrodes 2B are also insulated from each other by the insulating wall 2C with respect to the electrical path through the portion of the solder 4.

図2は、電子部品2の製造方法の一例を示した第1の図である。電子部品2は、例えば、次のような方法で製造することができる。すなわち、本製造方法においては、まず、絶縁壁2Cを形成するための穴10Aを形成したフィルム10が用意される(図2(A)を参照)。穴10Aは、例えば、レーザー加工で形成することができる。レーザー加工であれば、底部側が先細り状の穴を形成することができる。次に、穴10A内に絶縁材料が充填され、穴10A内に絶縁壁2Cが形成される(図2(B)を参照)。絶縁壁2Cは、例えば、熱硬化性樹脂を穴10A内に充填し、加熱して硬化させることにより形成可能である。次に、穴10A内に形成された絶縁壁2Cが各2B間に位置するようにフィルム10が電子部品本体2Aに搭載され、絶縁壁2Cが電子部品本体2Aに接合される(図2(C)を参照)。次に、フィルム10が電子部品本体2Aの表面から除去される(図2(D)を参照)。フィルム10が電子部品本体2Aの表面から除去されることにより、絶縁壁2Cが電子部品本体2Aの表面に形成された電子部品2が完成する。 FIG. 2 is a first diagram showing an example of a method for manufacturing the electronic component 2. The electronic component 2 can be manufactured, for example, by the following method. That is, in the present manufacturing method, first, a film 10 having holes 10A for forming the insulating wall 2C is prepared (see FIG. 2A). The hole 10A can be formed, for example, by laser machining. In the case of laser processing, it is possible to form a tapered hole on the bottom side. Next, the insulating material is filled in the hole 10A, and the insulating wall 2C is formed in the hole 10A (see FIG. 2B). The insulating wall 2C can be formed, for example, by filling the hole 10A with a thermosetting resin and heating to cure it. Next, the film 10 is mounted on the electronic component body 2A so that the insulating wall 2C formed in the hole 10A is located between each 2B, and the insulating wall 2C is joined to the electronic component body 2A (FIG. 2 (C). ). Next, the film 10 is removed from the surface of the electronic component body 2A (see FIG. 2D). By removing the film 10 from the surface of the electronic component body 2A, the electronic component 2 in which the insulating wall 2C is formed on the surface of the electronic component body 2A is completed.

図3は、電子部品2の一例を示した斜視図である。上記した電子部品2の製造方法において、例えば、絶縁壁2Cを形成するための穴10Aを格子状に形成したフィルム10が用いられる場合、図3に示されるように、電子部品本体2Aの表面に絶縁壁2Cが格子状に形成された電子部品2が完成することになる。 FIG. 3 is a perspective view showing an example of the electronic component 2. In the above-mentioned manufacturing method of the electronic component 2, for example, when the film 10 in which the holes 10A for forming the insulating wall 2C are formed in a grid pattern is used, as shown in FIG. 3, on the surface of the electronic component main body 2A. The electronic component 2 in which the insulating wall 2C is formed in a grid pattern is completed.

上記の方法で製造された電子部品2は、例えば、次のようにして配線基板3へ実装される。図4は、電子部品2の実装方法の一例を示した第1の図である。電子部品2は、例えば、図4に示されるように、電極3Bを基材3Aの表面に縦横に配列した配線基板3に実装される。このような配線基板3に電子部品2が実装される際は、例えば、以下のような方法で電子部品2の実装が行われる。 The electronic component 2 manufactured by the above method is mounted on the wiring board 3 as follows, for example. FIG. 4 is a first diagram showing an example of a mounting method of the electronic component 2. As shown in FIG. 4, for example, the electronic component 2 is mounted on a wiring board 3 in which electrodes 3B are arranged vertically and horizontally on the surface of the base material 3A. When the electronic component 2 is mounted on such a wiring board 3, for example, the electronic component 2 is mounted by the following method.

図5は、電子部品2の実装方法の一例を示した第2の図である。配線基板3への電子部品2の実装に際しては、例えば、基材3Aの表面の電極3Bが配列されている部位を覆う状態でシート状のはんだ4が配置される。そして、絶縁壁2Cが配線基板3の方へ向く状態で電子部品2がはんだ4に載置される。 FIG. 5 is a second diagram showing an example of a mounting method of the electronic component 2. When mounting the electronic component 2 on the wiring board 3, for example, the sheet-shaped solder 4 is arranged so as to cover the portion of the surface of the base material 3A where the electrodes 3B are arranged. Then, the electronic component 2 is placed on the solder 4 with the insulating wall 2C facing toward the wiring board 3.

図6は、電子部品2の実装方法の一例を示した第3の図である。絶縁壁2Cが配線基板3の方へ向く状態で電子部品2がはんだ4に載置された後は、はんだ4が加熱されながら、電子部品2が配線基板3側へ押下される(図6(A)を参照)。はんだ4が加熱によって溶融すると、電子部品2の絶縁壁2Cがはんだ4を掻き分けながら降下し、やがて絶縁壁2Cの先端が配線基板3に接触する(図6(B)を参照)。そして、加熱の停止によってはんだ4が硬化し、はんだ4の体積が温度降下によって熱収縮すると、電子部品2が配線基板3側に引き寄せられる。電子部品2が配線基板3側に引き寄せられると、絶縁壁2Cの先端が各電極3B間で基材3Aに食い込む(図6(C)を参照)。はんだ4が熱収縮すると、電子部品2が配線基板3側に引き寄せられるため、はんだ4内にボイドが生じる可能性は低い。なお、はんだ4にはBiが含有されていてもよいが、はんだ4の熱収縮特性に鑑みると、Biの体積比率は40%以下であることが望ましい。Biの体積比率は40%以下のはんだ4であれば、はんだ4が凝固時に十分な熱収縮を生ずるため、絶縁壁2Cの先端が各電極3B間で基材3Aに十分に食い込む。 FIG. 6 is a third diagram showing an example of a mounting method of the electronic component 2. After the electronic component 2 is placed on the solder 4 with the insulating wall 2C facing toward the wiring board 3, the electronic component 2 is pushed toward the wiring board 3 while the solder 4 is heated (FIG. 6 (FIG. 6). See A)). When the solder 4 is melted by heating, the insulating wall 2C of the electronic component 2 descends while scraping the solder 4, and eventually the tip of the insulating wall 2C comes into contact with the wiring board 3 (see FIG. 6B). Then, when the solder 4 is cured by stopping the heating and the volume of the solder 4 is thermally shrunk due to the temperature drop, the electronic component 2 is attracted to the wiring board 3 side. When the electronic component 2 is attracted to the wiring board 3 side, the tip of the insulating wall 2C bites into the base material 3A between the electrodes 3B (see FIG. 6C). When the solder 4 is thermally shrunk, the electronic component 2 is attracted to the wiring board 3 side, so that the possibility of voids occurring in the solder 4 is low. Although Bi may be contained in the solder 4, it is desirable that the volume ratio of Bi is 40% or less in view of the heat shrinkage characteristics of the solder 4. If the volume ratio of Bi is 40% or less, the solder 4 causes sufficient heat shrinkage at the time of solidification, so that the tip of the insulating wall 2C sufficiently bites into the base material 3A between the electrodes 3B.

絶縁壁2Cの先端が基材3Aに食い込むと、各電極3Bは、はんだ4の部分を通じた電気的な経路については絶縁壁2Cで互いに絶縁された状態になる。また、各電極2Bも電極3Bと同様、はんだ4の部分を通じた電気的な経路については絶縁壁2Cで互いに絶縁された状態になる。電子部品2が上記方法で配線基板3に実装されることにより、電子装置1が完成する。 When the tip of the insulating wall 2C bites into the base material 3A, the electrodes 3B are in a state of being insulated from each other by the insulating wall 2C with respect to the electrical path through the portion of the solder 4. Further, like the electrode 3B, each electrode 2B is also in a state of being insulated from each other by the insulating wall 2C with respect to the electrical path through the portion of the solder 4. The electronic device 1 is completed by mounting the electronic component 2 on the wiring board 3 by the above method.

なお、絶縁壁2Cの先端が基材3Aに食い込むためには、基材3Aが絶縁壁2Cより柔軟な材料で形成されていることが好ましい。基材3Aに用いられる柔軟な材料は、絶縁壁2Cの弾性率よりも低い弾性率を有する材料である。材料の弾性率は、ナノインデンテーション法によって得られる荷重に対応する押し込み深さの値から導くことが可能である。基材3Aが絶縁壁2Cより柔軟な材料で形成されていれば、絶縁壁2Cの先端が電極3B間で基材3Aに食い込みやすい。絶縁壁2Cの先端が電極3B間で基材3Aに食い込みやすくするには、基材3A全体が絶縁壁2Cより柔軟な材料で形成される形態のみならず、例えば、以下の方法で製造される形態であってもよい。 In order for the tip of the insulating wall 2C to bite into the base material 3A, it is preferable that the base material 3A is made of a material more flexible than the insulating wall 2C. The flexible material used for the base material 3A is a material having an elastic modulus lower than the elastic modulus of the insulating wall 2C. The modulus of elasticity of the material can be derived from the value of the indentation depth corresponding to the load obtained by the nanoindentation method. If the base material 3A is made of a material that is more flexible than the insulating wall 2C, the tip of the insulating wall 2C easily bites into the base material 3A between the electrodes 3B. In order for the tip of the insulating wall 2C to easily bite into the base material 3A between the electrodes 3B, not only the entire base material 3A is formed of a material more flexible than the insulating wall 2C, but also, for example, it is manufactured by the following method. It may be in the form.

図7は、配線基板3の製造方法の一例を示した第1の図である。本製造方法においては、樹脂や繊維状の素材を固めた絶縁性の板材である基材3A1の表面に、基材3A1よりも柔軟な樹脂材料11が搭載される(図7(A)を参照)。次に、樹脂材料11に電極3Bを形成するためのパターニングが施される(図7(B)を参照)。パターニングが施された樹脂材料11は、軟質部3A2を形成する。次に、樹脂材料11のパターニングされた部位に導電性の材料が埋め込まれ、電極3Bが形成される(図7(C)を参照)。以上により、各電極3B間に軟質部3A2を有する配線基板3が完成する。 FIG. 7 is a first diagram showing an example of a method for manufacturing the wiring board 3. In the present manufacturing method, the resin material 11 which is more flexible than the base material 3A1 is mounted on the surface of the base material 3A1 which is an insulating plate material obtained by solidifying a resin or a fibrous material (see FIG. 7A). ). Next, the resin material 11 is patterned to form the electrode 3B (see FIG. 7B). The patterned resin material 11 forms the soft portion 3A2. Next, the conductive material is embedded in the patterned portion of the resin material 11 to form the electrode 3B (see FIG. 7C). As described above, the wiring board 3 having the soft portion 3A2 between the electrodes 3B is completed.

各電極3B間に軟質部3A2を有する配線基板3が完成した後は、図6を使って説明したのと同様の方法が行われる。すなわち、基材3A1の表面の電極3Bが配列されている部位を覆う状態でシート状のはんだ4が配置される(図7(D)を参照)。そして、絶縁壁2Cが配線基板3の方へ向く状態で電子部品2がはんだ4に載置される。そして、はんだ4が加熱されながら、電子部品2が配線基板3側へ押下される(図7(E)を参照)。はんだ4が加熱によって溶融すると、電子部品2の絶縁壁2Cがはんだ4を掻き分けながら降下し、やがて絶縁壁2Cの先端が配線基板3に接触する。そして、加熱の停止によってはんだ4が硬化し、はんだ4の体積が温度降下によって収縮すると、電子部品2が配線基板3側に引き寄せられる。電子部品2が配線基板3側に引き寄せられると、絶縁壁2Cの先端が各電極3B間で軟質部3A2に食い込む(図7(F)を参照)。 After the wiring board 3 having the soft portion 3A2 between the electrodes 3B is completed, the same method as described with reference to FIG. 6 is performed. That is, the sheet-shaped solder 4 is arranged so as to cover the portion of the surface of the base material 3A1 where the electrodes 3B are arranged (see FIG. 7D). Then, the electronic component 2 is placed on the solder 4 with the insulating wall 2C facing toward the wiring board 3. Then, while the solder 4 is heated, the electronic component 2 is pushed toward the wiring board 3 (see FIG. 7E). When the solder 4 is melted by heating, the insulating wall 2C of the electronic component 2 descends while scraping the solder 4, and the tip of the insulating wall 2C comes into contact with the wiring board 3. Then, when the solder 4 is hardened by stopping the heating and the volume of the solder 4 shrinks due to the temperature drop, the electronic component 2 is attracted to the wiring board 3 side. When the electronic component 2 is attracted to the wiring board 3 side, the tip of the insulating wall 2C bites into the soft portion 3A2 between the electrodes 3B (see FIG. 7F).

各電極3B間に軟質部3A2を有する配線基板3であれば、絶縁壁2Cの先端が軟質部3A2に食い込みやすい。よって、各電極3Bについて、はんだ4の部分を通じた電気的な経路を絶縁壁2Cで互いにより確実に絶縁された状態にすることができる。各電極2Bにおけるはんだ4の部分を通じた互いの電気的な経路の絶縁状態についても、電極3Bと同様である。 If the wiring board 3 has the soft portion 3A2 between the electrodes 3B, the tip of the insulating wall 2C easily bites into the soft portion 3A2. Therefore, for each electrode 3B, the electrical path through the portion of the solder 4 can be more reliably isolated from each other by the insulating wall 2C. The insulation state of each other's electrical paths through the portion of the solder 4 in each electrode 2B is the same as that of the electrode 3B.

また、電子装置1は、上記の形態に限定されるものではない。図8は、電子装置1の変形例および比較例を示した図である。図8(A)は、上記実施形態の電子装置1に相当する。一方、図8(B)は、電子装置1の第1比較例を示した図である。また、図8(C)は、電子装置1の第2比較例を示した図である。図8(D)は、電子装置1の変形例を示した図である。 Further, the electronic device 1 is not limited to the above-mentioned form. FIG. 8 is a diagram showing a modified example and a comparative example of the electronic device 1. FIG. 8A corresponds to the electronic device 1 of the above embodiment. On the other hand, FIG. 8B is a diagram showing a first comparative example of the electronic device 1. Further, FIG. 8C is a diagram showing a second comparative example of the electronic device 1. FIG. 8D is a diagram showing a modified example of the electronic device 1.

図8(B)に示す第1比較例の電子装置201は、上記実施形態の電子装置1と同様、電子部品202と配線基板203とを備えた電子装置であり、電子部品202がはんだ204で配線基板203に接合されている。そして、電子部品202の電子部品本体202Aに設けられている電極202Bと、配線基板203の基材203Aに設けられている電極203Bとを電気的に接続するはんだ204は、絶縁壁202Cで仕切られている。絶縁壁202Cの配線基板203側の先端は、基材203Aの凹部203A3に接している。 The electronic device 201 of the first comparative example shown in FIG. 8B is an electronic device including an electronic component 202 and a wiring board 203, as in the electronic device 1 of the above embodiment, and the electronic component 202 is made of solder 204. It is joined to the wiring board 203. The solder 204 that electrically connects the electrode 202B provided on the electronic component main body 202A of the electronic component 202 and the electrode 203B provided on the base material 203A of the wiring board 203 is partitioned by the insulating wall 202C. ing. The tip of the insulating wall 202C on the wiring board 203 side is in contact with the recess 203A3 of the base material 203A.

図8(C)に示す第2比較例の電子装置201も、図8(B)に示す第1比較例の電子
装置201とほぼ同様であるが、絶縁壁202Cの配線基板203側の先端が基材203Aの凹部203A4に嵌っている点が相違する。
The electronic device 201 of the second comparative example shown in FIG. 8C is almost the same as the electronic device 201 of the first comparative example shown in FIG. 8B, but the tip of the insulating wall 202C on the wiring board 203 side is The difference is that it fits into the recess 203A4 of the base material 203A.

上記第1比較例と第2比較例の電子装置201においても、上記実施形態の電子装置1と同様、電極202Bと電極203Bとを電気的に接続するはんだ204が、電極202B間に壁状に形成される絶縁壁202Cによって仕切られているが、絶縁壁202Cが基材203Aに触れているだけなので、絶縁壁202Cの絶縁機能が十分に発揮されない可能性がある。一方、上記実施形態の電子装置1では、絶縁壁2Cの先端が基材3Aに埋まっているため、電子装置1の反り等による絶縁壁2Cの絶縁機能の低下の可能性が低い。 In the electronic devices 201 of the first comparative example and the second comparative example, the solder 204 that electrically connects the electrode 202B and the electrode 203B is formed in a wall shape between the electrodes 202B as in the electronic device 1 of the above embodiment. Although it is partitioned by the insulating wall 202C to be formed, since the insulating wall 202C only touches the base material 203A, the insulating function of the insulating wall 202C may not be fully exhibited. On the other hand, in the electronic device 1 of the above embodiment, since the tip of the insulating wall 2C is embedded in the base material 3A, there is a low possibility that the insulating function of the insulating wall 2C is deteriorated due to the warp of the electronic device 1.

もっとも、絶縁壁2Cが先細り状の形態でない場合であっても、凹部3A4を設けることなく絶縁壁2Cの先端を基材3Aに埋めることは可能である。電極3B間の基材3Aの柔軟性によっては、例えば、図8(D)に示されるように、凹部3A4の無い基材3Aに対しても、先細り状の形態ではない絶縁壁2Cを埋め込むことが可能である。 However, even when the insulating wall 2C does not have a tapered shape, it is possible to bury the tip of the insulating wall 2C in the base material 3A without providing the recess 3A4. Depending on the flexibility of the base material 3A between the electrodes 3B, for example, as shown in FIG. 8D, the insulating wall 2C having no tapered shape may be embedded in the base material 3A having no recess 3A4. Is possible.

なお、図8(B)に示した第1比較例の電子装置201では、絶縁壁202Cの配線基板203側の先端が基材203Aの凹部203A3に触れているのみであり、絶縁壁202Cの配線基板203側の先端が基材203Aに埋まらない旨を上述したが、以下のような形態であれば絶縁壁の配線基板側の先端を基材の凹部に埋めることができる。図9は、配線基板3の製造方法の一例を示した第2の図である。すなわち、基材3A1の表面に、基材3A1よりも柔軟な樹脂材料11と、樹脂材料11よりは硬質な樹脂材料12が搭載される(図9(A)を参照)。次に、樹脂材料11と樹脂材料12に電極3Bを形成するためのパターニングが施される(図9(B)を参照)。パターニングが施された樹脂材料11(本願でいう「第2材料」の一例である)は軟質部3A2を形成する。また、パターニングが施された樹脂材料12(本願でいう「第1材料」の一例である)は硬質部3A5を形成する。次に、樹脂材料11と樹脂材料12のパターニングされた部位に導電性の材料が埋め込まれ、電極3Bが形成される(図9(C)を参照)。次に、硬質部3A5に凹部3A3が形成される(図9(D)を参照)。凹部3A3は、例えば、硬質部3A5の間隔と同程度の間隔を持つ剣山状の治具或いはレーザー光を、硬質部3A5に当てながらスライドすることにより形成することができる。以上により、各電極3B間に凹部3A3を有する配線基板3が完成する。樹脂材料12が樹脂材料11より硬質なため、凹部3A3の底部は側部より柔軟になる。 In the electronic device 201 of the first comparative example shown in FIG. 8B, the tip of the insulating wall 202C on the wiring board 203 side only touches the recess 203A3 of the base material 203A, and the wiring of the insulating wall 202C. As described above, the tip of the substrate 203 side is not buried in the base material 203A, but the tip of the insulating wall on the wiring board side can be buried in the recess of the base material in the following form. FIG. 9 is a second diagram showing an example of a method for manufacturing the wiring board 3. That is, a resin material 11 that is more flexible than the base material 3A1 and a resin material 12 that is harder than the resin material 11 are mounted on the surface of the base material 3A1 (see FIG. 9A). Next, the resin material 11 and the resin material 12 are patterned to form the electrode 3B (see FIG. 9B). The patterned resin material 11 (which is an example of the "second material" in the present application) forms the soft portion 3A2. Further, the patterned resin material 12 (which is an example of the "first material" in the present application) forms the hard portion 3A5. Next, the conductive material is embedded in the patterned portions of the resin material 11 and the resin material 12, and the electrode 3B is formed (see FIG. 9C). Next, the recess 3A3 is formed in the hard portion 3A5 (see FIG. 9D). The recess 3A3 can be formed, for example, by sliding a sword-shaped jig or a laser beam having a spacing similar to that of the hard portion 3A5 while irradiating the hard portion 3A5. As described above, the wiring board 3 having the recesses 3A3 between the electrodes 3B is completed. Since the resin material 12 is harder than the resin material 11, the bottom portion of the recess 3A3 becomes more flexible than the side portion.

各電極3B間に凹部3A3を有する配線基板3が完成した後は、図6を使って説明したのと同様の方法が行われる。すなわち、基材3A1の表面の電極3Bが配列されている部位を覆う状態ではんだ4が配置される(図9(E)を参照)。そして、絶縁壁2Cが配線基板3の方へ向く状態で電子部品2がはんだ4に載置される。そして、はんだ4が加熱されながら、電子部品2が配線基板3側へ押下される(図9(F)を参照)。はんだ4が加熱によって溶融すると、電子部品2の絶縁壁2Cがはんだ4を掻き分けながら降下し、やがて絶縁壁2Cの先端が配線基板3に接触する。そして、絶縁壁2Cの先端が凹部3A3内に案内されることによって、配線基板3に対する電子部品2の相対的な位置合わせが行われる(図9(G)を参照)。加熱の停止によってはんだ4が硬化し、はんだ4の体積が温度降下によって収縮すると、電子部品2が配線基板3側に引き寄せられ、絶縁壁2Cの先端が各電極3B間で軟質部3A2に食い込む。 After the wiring board 3 having the recesses 3A3 between the electrodes 3B is completed, the same method as described with reference to FIG. 6 is performed. That is, the solder 4 is arranged so as to cover the portion of the surface of the base material 3A1 where the electrodes 3B are arranged (see FIG. 9E). Then, the electronic component 2 is placed on the solder 4 with the insulating wall 2C facing toward the wiring board 3. Then, while the solder 4 is heated, the electronic component 2 is pushed toward the wiring board 3 (see FIG. 9F). When the solder 4 is melted by heating, the insulating wall 2C of the electronic component 2 descends while scraping the solder 4, and the tip of the insulating wall 2C comes into contact with the wiring board 3. Then, by guiding the tip of the insulating wall 2C into the recess 3A3, the relative alignment of the electronic component 2 with respect to the wiring board 3 is performed (see FIG. 9 (G)). When the solder 4 is hardened by stopping the heating and the volume of the solder 4 shrinks due to the temperature drop, the electronic component 2 is attracted to the wiring board 3 side, and the tip of the insulating wall 2C bites into the soft portion 3A2 between the electrodes 3B.

なお、図9に示した配線基板3の製造方法は、例えば、以下のように変形してもよい。図10は、配線基板3の製造方法の一例を示した第3の図である。すなわち、基材3A1の表面に樹脂材料11と樹脂材料12が搭載され(図10(A)を参照)、樹脂材料11と樹脂材料12にパターニングが施された後(図10(B)を参照)、樹脂材料11と樹脂材料12のパターニングされた部位に導電性の材料が埋め込まれ、隆起部3B1を有す
る電極3Bが形成される(図10(C)を参照)。次に、硬質部3A5に凹部3A3が形成される(図10(D)を参照)。以上により、隆起部3B1を有する電極3B、及び凹部3A3を有する配線基板3が完成する。
The method for manufacturing the wiring board 3 shown in FIG. 9 may be modified as follows, for example. FIG. 10 is a third diagram showing an example of a method for manufacturing the wiring board 3. That is, after the resin material 11 and the resin material 12 are mounted on the surface of the base material 3A1 (see FIG. 10A) and the resin material 11 and the resin material 12 are patterned (see FIG. 10B). ), The conductive material is embedded in the patterned portion of the resin material 11 and the resin material 12, and the electrode 3B having the raised portion 3B1 is formed (see FIG. 10C). Next, the recess 3A3 is formed in the hard portion 3A5 (see FIG. 10D). As described above, the electrode 3B having the raised portion 3B1 and the wiring board 3 having the concave portion 3A3 are completed.

各電極3B間に凹部3A3を有する配線基板3が完成した後は、図6を使って説明したのと同様の方法が行われる。すなわち、基材3A1の表面の電極3Bが配列されている部位を覆う状態でシート状のはんだ4が配置される(図10(F)を参照)。そして、絶縁壁2Cが配線基板3の方へ向く状態で電子部品2がはんだ4に載置される。そして、はんだ4が加熱されながら、電子部品2が配線基板3側へ押下される(図10(F)を参照)。はんだ4が加熱によって溶融すると、電子部品2の絶縁壁2Cがはんだ4を掻き分けながら降下し、やがて絶縁壁2Cの先端が配線基板3に接触する。そして、絶縁壁2Cの先端が隆起部3B1によって凹部3A3内に案内され、配線基板3に対する電子部品2の相対的な位置合わせが行われる(図10(G)を参照)。加熱の停止によってはんだ4が硬化し、はんだ4の体積が温度降下によって収縮すると、電子部品2が配線基板3側に引き寄せられ、絶縁壁2Cの先端が各電極3B間で軟質部3A2に食い込む。 After the wiring board 3 having the recesses 3A3 between the electrodes 3B is completed, the same method as described with reference to FIG. 6 is performed. That is, the sheet-shaped solder 4 is arranged so as to cover the portion of the surface of the base material 3A1 where the electrodes 3B are arranged (see FIG. 10F). Then, the electronic component 2 is placed on the solder 4 with the insulating wall 2C facing toward the wiring board 3. Then, while the solder 4 is heated, the electronic component 2 is pressed toward the wiring board 3 (see FIG. 10F). When the solder 4 is melted by heating, the insulating wall 2C of the electronic component 2 descends while scraping the solder 4, and the tip of the insulating wall 2C comes into contact with the wiring board 3. Then, the tip of the insulating wall 2C is guided into the recess 3A3 by the raised portion 3B1, and the relative alignment of the electronic component 2 with respect to the wiring board 3 is performed (see FIG. 10 (G)). When the solder 4 is hardened by stopping the heating and the volume of the solder 4 shrinks due to the temperature drop, the electronic component 2 is attracted to the wiring board 3 side, and the tip of the insulating wall 2C bites into the soft portion 3A2 between the electrodes 3B.

上記したように、凹部3A3や隆起部3B1が配線基板3に設けられていれば、配線基板3に対する電子部品2の位置合わせが容易に行われる。 As described above, if the recess 3A3 and the raised portion 3B1 are provided on the wiring board 3, the alignment of the electronic component 2 with respect to the wiring board 3 can be easily performed.

図11は、電子部品2の製造方法の一例を示した第2の図である。電子部品2は、例えば、次のような方法で製造することもできる。すなわち、本製造方法においては、まず、電極2Bを表面に配列した電子部品本体2Aにフィルム13が貼着される(図11(A)を参照)。次に、フィルム13に絶縁壁2Cを形成するための穴13Aが形成される(図11(B)を参照)。穴13Aは、例えば、レーザー加工によって形成される。次に、穴13A内に絶縁材料が充填され、穴13A内に絶縁壁2Cが形成される(図11(C)を参照)。絶縁壁2Cは、例えば、熱硬化性の樹脂を穴13A内に充填し、加熱することで形成可能である。次に、フィルム13が電子部品本体2Aの表面から除去され、洗浄が行われる(図11(D)を参照)。フィルム13が電子部品本体2Aの表面から除去されることにより、先端が先細りでない絶縁壁2Cが電子部品本体2Aの表面に形成された電子部品2が完成する。 FIG. 11 is a second diagram showing an example of a method for manufacturing the electronic component 2. The electronic component 2 can also be manufactured by, for example, the following method. That is, in the present manufacturing method, first, the film 13 is attached to the electronic component main body 2A in which the electrodes 2B are arranged on the surface (see FIG. 11A). Next, a hole 13A for forming the insulating wall 2C is formed in the film 13 (see FIG. 11B). The hole 13A is formed by, for example, laser processing. Next, the insulating material is filled in the hole 13A, and the insulating wall 2C is formed in the hole 13A (see FIG. 11C). The insulating wall 2C can be formed, for example, by filling the hole 13A with a thermosetting resin and heating it. Next, the film 13 is removed from the surface of the electronic component body 2A, and cleaning is performed (see FIG. 11D). By removing the film 13 from the surface of the electronic component body 2A, the electronic component 2 in which the insulating wall 2C having a non-tapered tip is formed on the surface of the electronic component body 2A is completed.

図12は、比較例を示した第1の図である。例えば、図12に示されるように、配線基板103の電極103Bにはんだボール104が設けられる場合、リフロー開始前にはんだボール104が所定の位置に整列されていても(図12(A1)を参照)、リフロー中はフラックス105の粘度低下によりタッキング力が低下し、フラックス105の流動に追従してはんだボール104が電極103B上を動き回る(図12(B1)を参照)。そして、はんだボール104が正常にリフローされれば、各はんだボール104は各電極103Bに溶着する(図12(C1)を参照)。しかし、基材103Aの表面に配列される電極103Bが微細化されると、電極103B同士の間隔が狭くなる。電極103B同士の間隔が狭いと、リフロー開始前にはんだボール104が所定の位置に整列されていても(図12(A2)を参照)、リフロー中に動き回るはんだボール104同士が接触する可能性が高まる(図12(B2)を参照)。リフロー中にはんだボール104同士が接触すると、はんだボール104は、例えば、隣のはんだボール104と一体化した状態で硬化する(図12(C2)に示す符号Aを参照)。隣のはんだボール104と一体化した状態で硬化すると、電極103B同士が短絡することになる。はんだボール104同士が接触する可能性を抑制するために小径のはんだボール104を使うなど、接合部のはんだ量を減らすことは、接続部における電気抵抗の増大や接続部の信頼性低下、伝熱性の低下に繋がる。 FIG. 12 is a first diagram showing a comparative example. For example, as shown in FIG. 12, when the solder balls 104 are provided on the electrodes 103B of the wiring board 103, even if the solder balls 104 are aligned at predetermined positions before the start of reflow (see FIG. 12 (A1)). ), The tacking force decreases due to the decrease in the viscosity of the flux 105 during the reflow, and the solder ball 104 moves around on the electrode 103B following the flow of the flux 105 (see FIG. 12 (B1)). Then, if the solder balls 104 are normally reflowed, each solder ball 104 is welded to each electrode 103B (see FIG. 12 (C1)). However, when the electrodes 103B arranged on the surface of the base material 103A are miniaturized, the distance between the electrodes 103B becomes narrower. If the distance between the electrodes 103B is narrow, even if the solder balls 104 are aligned in a predetermined position before the start of reflow (see FIG. 12A2), the solder balls 104 moving around during the reflow may come into contact with each other. Increase (see FIG. 12 (B2)). When the solder balls 104 come into contact with each other during reflow, the solder balls 104 are cured, for example, in a state of being integrated with the adjacent solder balls 104 (see reference numeral A shown in FIG. 12 (C2)). If the electrodes 103B are cured in a state of being integrated with the adjacent solder balls 104, the electrodes 103B will be short-circuited. Reducing the amount of solder in the joint, such as using a small-diameter solder ball 104 to suppress the possibility of the solder balls 104 coming into contact with each other, increases the electrical resistance at the connection, reduces the reliability of the connection, and has heat transfer properties. Leads to a decline in.

図13は、比較例を示した第2の図である。はんだボール104同士の接触は、配線基
板103上におけるリフロー時のみならず、例えば、図13に示されるように、電子部品102を配線基板103に実装する場合にも生じ得る。すなわち、電極102Bにはんだボール104が正常に溶着した電子部品102が用意されていても、電子部品102を配線基板103へ実装する際のリフローにおいて、例えば、電子部品102の自重ではんだボール104が押し広げられれば、図13において符号Bで示されるように、はんだボール104同士が接触する場合もある。
FIG. 13 is a second diagram showing a comparative example. Contact between the solder balls 104 can occur not only during reflow on the wiring board 103, but also when the electronic component 102 is mounted on the wiring board 103, for example, as shown in FIG. That is, even if the electronic component 102 in which the solder ball 104 is normally welded is prepared on the electrode 102B, in the reflow when the electronic component 102 is mounted on the wiring board 103, for example, the solder ball 104 is generated by the weight of the electronic component 102. When expanded, the solder balls 104 may come into contact with each other, as indicated by reference numeral B in FIG.

この点、上記実施形態や各変形例の電子装置1であれば、電極2Bと電極3Bとを電気的に接続するはんだ4が、電極2B間に壁状に形成される絶縁壁2Cによって仕切られるため、はんだボール104のように隣り合う電極のはんだ同士が接触することが無い。よって、電極2Bや電極3Bが微細化されていても、電極間同士の短絡が抑制される。また、接合部に十分なはんだ量を確保することができるため、接合部における電気抵抗を可及的に抑制することができる。また、接合部に十分なはんだ量を確保することができるため、伝熱性を確保することができる。また、はんだ間に絶縁壁があるため、近接するはんだ間における電界強度に起因するマイグレーションに耐えることができる。 In this respect, in the case of the electronic device 1 of the above embodiment and each modification, the solder 4 that electrically connects the electrodes 2B and the electrodes 3B is partitioned by the insulating wall 2C formed in a wall shape between the electrodes 2B. Therefore, unlike the solder balls 104, the solders of the adjacent electrodes do not come into contact with each other. Therefore, even if the electrodes 2B and 3B are miniaturized, short circuits between the electrodes are suppressed. Further, since a sufficient amount of solder can be secured in the joint portion, the electric resistance in the joint portion can be suppressed as much as possible. Further, since a sufficient amount of solder can be secured at the joint portion, heat transferability can be ensured. Further, since there is an insulating wall between the solders, it is possible to withstand migration due to the electric field strength between the adjacent solders.

1,201・・電子装置:2,102,202・・電子部品:2A,202A・・電子部品本体:2B,102B,202B・・電極:2C,202C・・絶縁壁:3,103,203・・配線基板:3A,3A1,103A,203A・・基材:3A2・・軟質部:3A3,3A4,203A3,203A4・・凹部:3A5・・硬質部:3B,103B・・電極:3B1・・隆起部:4,204・・はんだ:10,13・・フィルム:10A,13A・・穴:11,12・・樹脂材料:104・・はんだボール:105・・フラックス 1,201 ... Electronic device: 2,102,202 ... Electronic component: 2A, 202A ... Electronic component body: 2B, 102B, 202B ... Electrode: 2C, 202C ... Insulation wall: 3,103,203 ...・ Wiring board: 3A, 3A1,103A, 203A ・ ・ Base material: 3A2 ・ ・ Soft part: 3A3,3A4,203A3,203A4 ・ ・ Recessed part: 3A5 ・ ・ Hard part: 3B, 103B ・ ・ Electrode: 3B1 ・ ・ Uplift Part: 4,204 ... Solder: 10,13 ... Film: 10A, 13A ... Holes: 11,12 ... Resin material: 104 ... Solder ball: 105 ... Flux

Claims (14)

複数の電極が表面に配列されている配線基板と、
前記複数の電極が配列されている部位を覆うはんだを介して前記配線基板に接合される電子部品と、
前記はんだを前記複数の電極間において前記はんだに接触した状態の絶縁材料で仕切ることにより、前記はんだを通じた各電極間の電気的な導通を遮断する、前記配線基板側の先端が前記配線基板の前記複数の電極間の材料に埋まっている絶縁壁と、を備える、
電子装置。
A wiring board with multiple electrodes arranged on the surface,
An electronic component bonded to the wiring board via solder covering a portion where the plurality of electrodes are arranged, and
By partitioning the solder between the plurality of electrodes with an insulating material in contact with the solder, electrical conduction between the electrodes through the solder is cut off, and the tip on the wiring board side is the wiring board. An insulating wall embedded in a material between the plurality of electrodes.
Electronic device.
前記配線基板の前記複数の電極間の材料は、前記絶縁壁の材料の弾性率よりも低い弾性率を有する、
請求項1に記載の電子装置。
The material between the plurality of electrodes of the wiring board has an elastic modulus lower than the elastic modulus of the material of the insulating wall.
The electronic device according to claim 1.
前記配線基板は、前記複数の電極間に凹部を有する、
請求項1または2に記載の電子装置。
The wiring board has a recess between the plurality of electrodes.
The electronic device according to claim 1 or 2.
前記配線基板は、前記凹部の側部を形成する第1材料と、前記凹部の底面を形成し、前記第1材料の弾性率よりも弾性率の低い第2材料とを有する、
請求項3に記載の電子装置。
The wiring board has a first material that forms a side portion of the recess and a second material that forms the bottom surface of the recess and has a modulus of elasticity lower than that of the first material.
The electronic device according to claim 3.
前記複数の各電極は、中央部分が隆起している、
請求項1から4の何れか一項に記載の電子装置。
Each of the plurality of electrodes has a raised central portion.
The electronic device according to any one of claims 1 to 4.
前記絶縁壁は、前記電子部品の表面に格子状に形成されている、
請求項1から5の何れか一項に記載の電子装置。
The insulating wall is formed in a grid pattern on the surface of the electronic component.
The electronic device according to any one of claims 1 to 5.
複数の電極が表面に配列されている配線基板に、前記複数の電極が配列されている部位を覆う状態ではんだを配置する工程と、
前記はんだを前記複数の電極間で仕切る絶縁壁を表面に有する電子部品を、前記絶縁壁の前記配線基板側の先端が前記配線基板の前記複数の電極間の材料に埋まるように前記配
線基板に接合する工程と、を有する、
電子装置の製造方法。
A process of arranging solder on a wiring board in which a plurality of electrodes are arranged on the surface in a state of covering the portion where the plurality of electrodes are arranged, and a process of arranging the solder.
An electronic component having an insulating wall for partitioning the solder between the plurality of electrodes is placed on the wiring board so that the tip of the insulating wall on the wiring board side is embedded in the material between the plurality of electrodes of the wiring board. Has a step of joining,
Manufacturing method of electronic device.
前記接合する工程では、前記複数の電極が配列されている部位を覆う状態で配置されたはんだを加熱溶融させた状態において、前記絶縁壁が前記配線基板に押し当てられるように前記電子部品が前記配線基板に接合される、
請求項7に記載の電子装置の製造方法。
In the joining step, the electronic component is subjected to the electronic component so that the insulating wall is pressed against the wiring board in a state where the solder arranged so as to cover the portion where the plurality of electrodes are arranged is heated and melted. Joined to the wiring board,
The method for manufacturing an electronic device according to claim 7.
前記配置する工程では、Snを含み、Biの含有率が40%以下のはんだが前記配線基板に配置される、
請求項7または8に記載の電子装置の製造方法。
In the arranging step, solder containing Sn and having a Bi content of 40% or less is arranged on the wiring board.
The method for manufacturing an electronic device according to claim 7.
前記配線基板の前記複数の電極間の材料は、前記絶縁壁の材料の弾性率よりも低い弾性率を有し、
前記接合する工程では、前記絶縁壁の前記配線基板側の先端が前記配線基板の前記複数の電極間の材料に接触する、
請求項7から9の何れか一項に記載の電子装置の製造方法。
The material between the plurality of electrodes of the wiring board has an elastic modulus lower than the elastic modulus of the material of the insulating wall.
In the joining step, the tip of the insulating wall on the wiring board side comes into contact with the material between the plurality of electrodes of the wiring board.
The method for manufacturing an electronic device according to any one of claims 7 to 9.
前記配線基板は、前記複数の電極間に凹部を有し、
前記接合する工程では、前記絶縁壁の前記配線基板側の先端が前記凹部に入る、
請求項7から10の何れか一項に記載の電子装置の製造方法。
The wiring board has a recess between the plurality of electrodes, and the wiring board has a recess.
In the joining step, the tip of the insulating wall on the wiring board side enters the recess.
The method for manufacturing an electronic device according to any one of claims 7 to 10.
前記配線基板は、前記凹部の側部を形成する第1材料と、前記凹部の底面を形成し、前記第1材料の弾性率よりも弾性率の低い第2材料とを有し、
前記接合する工程では、前記絶縁壁の前記配線基板側の先端が前記凹部の底面の前記第2材料に接触する、
請求項11に記載の電子装置の製造方法。
The wiring board has a first material that forms a side portion of the recess and a second material that forms the bottom surface of the recess and has a modulus of elasticity lower than that of the first material.
In the joining step, the tip of the insulating wall on the wiring board side comes into contact with the second material on the bottom surface of the recess.
The method for manufacturing an electronic device according to claim 11 .
前記複数の各電極は、中央部分が隆起しており、
前記接合する工程では、前記絶縁壁の前記配線基板側の先端が、前記各電極の隆起によって前記凹部へ案内される、
請求項11または12に記載の電子装置の製造方法。
Each of the plurality of electrodes has a raised central portion.
In the joining step, the tip of the insulating wall on the wiring board side is guided to the recess by the ridges of the electrodes.
The method for manufacturing an electronic device according to claim 11 or 12 .
前記絶縁壁は、前記電子部品の表面に格子状に形成されており、
前記接合する工程では、前記絶縁壁の格子が前記複数の電極間に位置するように前記電子部品を前記配線基板に接合する、
請求項8から13の何れか一項に記載の電子装置の製造方法。
The insulating wall is formed in a grid pattern on the surface of the electronic component.
In the joining step, the electronic component is joined to the wiring board so that the lattice of the insulating wall is located between the plurality of electrodes.
The method for manufacturing an electronic device according to any one of claims 8 to 13.
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