JP7092555B2 - Arithmetic logic unit and interruption method - Google Patents

Description

The present invention relates to an arithmetic unit and an interruption method.

Conventionally, measures have been taken to prevent abnormal processing by the arithmetic unit. As an example of such a technique, there is known a technique for preventing runaway by prohibiting reading of numerical data after a branch instruction when a microprocessor executes an abnormal branch instruction.

Japanese Unexamined Patent Publication No. 11-21428

"Mechanism of FPGA and software and hardware used for development", Masahiko Tange <Internet> http://toragi.cqpub.co.jp/Portals/0/backnumber/2009/03/p096-097.pdf (May 2018) Search on the 1st of the month)

However, the above-mentioned technique may not be able to appropriately prevent abnormal processing.

For example, in the technique described above, the operation of the microphone processor is monitored by using a digital circuit. However, if such a digital circuit is manipulated by a virus or a hacker, it will not be possible to properly monitor the operation of the microprocessor.

The present application has been made in view of the above, and an object thereof is to more appropriately prevent abnormal processing by an arithmetic unit.

The arithmetic unit according to the present application has a first arithmetic unit capable of executing a predetermined process by changing a combination of logic circuits including an analog circuit, and a second arithmetic unit capable of executing a predetermined instruction set. The first arithmetic unit satisfies a predetermined condition in the monitoring process for monitoring the process executed by the second arithmetic unit and the process executed by the second arithmetic unit by combining the logic circuits. If this is the case, it is characterized in that an interruption process for interrupting the execution of the process by the second arithmetic unit is executed.

According to one aspect of the embodiment, it is possible to more appropriately prevent the abnormal processing by the arithmetic unit.

FIG. 1 is a diagram showing an example of an arithmetic unit according to an embodiment. FIG. 2 is a diagram showing a configuration example of the arithmetic unit according to the embodiment. FIG. 3 is a flowchart illustrating an example of the flow of processing according to the embodiment.

Hereinafter, an embodiment for carrying out the arithmetic unit and the interruption method according to the present application (hereinafter, referred to as “embodiment”) will be described in detail with reference to the drawings. It should be noted that this embodiment does not limit the arithmetic unit and the interruption method according to the present application. Further, in each of the following embodiments, the same parts are designated by the same reference numerals, and duplicate explanations are omitted.

[1-1. Example of arithmetic unit]
First, an example of an arithmetic unit will be described with reference to FIG. FIG. 1 is a diagram showing an example of an arithmetic unit according to an embodiment.

The arithmetic unit 100 is an arithmetic unit that executes the arithmetic processing described below. Here, the arithmetic unit 100 is an integrated circuit in which a user can define or change an internal logic circuit after manufacturing, and is a so-called PLD (Programmable Logic Device).

For example, the arithmetic unit 100 has a processor 110 capable of executing a predetermined instruction set and an FPGA (Field-Programmable Gate Array) 150. The processor 110 is a processor included in the arithmetic unit 100, and is, for example, a processor or a microprocessor that employs an ARM architecture or a POWER architecture. That is, the processor 110 is composed of a digital circuit. Then, the processor 110 executes various arithmetic processes in cooperation with the FPGA.

For example, the processor 110 has a processor core 111 and a cache memory 112. The processor core 111 is a so-called core that realizes logical operations and four rules operations, and is realized by an arithmetic logic unit composed of an ALU (Arithmetic Logic Unit). The cache memory 112 is an auxiliary storage device included in the processor 110. More specifically, the cache memory 112 is a storage device that can be accessed by the processor core 111 at a higher speed than the main storage device 200 (see, for example, FIG. 2) that can be accessed by the arithmetic unit 100, and is a so-called cache memory. Is.

The FPGA 150 is an arithmetic unit whose circuit configuration can be changed according to an instruction from the external device OA. For example, FPGAs include analog circuit elements. For example, an FPGA has a plurality of logic blocks that are programmable logic components, a logic block composed of an analog circuit, or a logic block in which an analog circuit and a digital circuit are combined, and is logical. The blocks are interconnected by reconfigurable wiring. Then, the FPGA 150 can realize various processes by hardware by changing the connection of such wiring by the hardware description language (HDL: Hardware Description Language) received from the external device OA.

That is, the arithmetic unit 100 is an FPGA 150 which is a first arithmetic unit that can execute a predetermined process by changing a combination of logic circuits including an analog circuit, and a second arithmetic unit that can execute a predetermined instruction set. It has a processor 110.

[1-2. Example of interruption processing]
Here, in the arithmetic unit including the conventional processor and the FPGA, the processor side composed of the digital circuit executes the control on the FPGA side composed of the analog circuit. However, when the control side is configured by a digital circuit, it is easily affected by hacking and viruses. As a result, when the processor side executes the control on the FPGA side, the runaway of the processing on the FPGA side cannot be prevented, and as a result, the runaway of the processing by the arithmetic unit 100 may be allowed.

Therefore, the arithmetic unit 100 controls the processor 110 configured by the digital circuit by the FPGA 150 configured by the analog circuit. More specifically, the FPGA 150 satisfies a predetermined condition in the monitoring process for monitoring the process executed by the processor 110 and the process executed by the processor 110 by configuring the circuit according to the HDL received from the external device OA. In that case, the interruption process for suspending the execution of the process by the processor 110 is executed. For example, the FPGA 150 monitors the execution of processing by the processor 110. Then, when the content of the process executed by the processor 110 is different from the normal process, the FPGA 150 interrupts the execution of the process by the processor 110.

Further, the FPGA 150 executes a change process for changing the combination of logic circuits for executing the monitoring process and the interruption process when the process executed by the processor 110 satisfies a predetermined condition by combining the logic circuits. do. For example, the FPGA 150 changes the combination of logic circuits every time the process executed by the processor 110 satisfies a predetermined condition. That is, when the content of the process executed by the processor 110 is different from the normal process, the FPGA 150 interrupts the process executed by the processor 110 and changes the circuit configuration of the FPGA 150 as a one-time password.

In this way, the arithmetic unit 100 controls the processor 110 configured by the digital circuit by the FPGA 150 configured by the analog circuit. Here, analog circuits are less susceptible to hacking and viruses than digital circuits. As a result, the arithmetic unit 100 can more appropriately prevent the execution of abnormal processing.

[1-3. Example of processing flow]
Hereinafter, an example of the processing executed by the arithmetic unit 100 will be described with reference to FIG. First, the arithmetic unit 100 receives a predetermined content from the external device OA (step S1). In such a case, the FPGA 150 configures a combination of logic circuits so as to execute the following processing. First, the FPGA 150 configures a process to be executed by the processor 110 (step S2). Then, the FPGA 150 causes the processor 110 to execute the process (step S3). In such a case, the processor 110 executes the process received from the FPGA 150 (step S4).

Here, the FPGA 150 monitors the processing status by the processor 110 at predetermined time intervals (step S5). Then, the FPGA 150 determines whether or not a process different from the process assumed by the processor 110 is being executed (step S6). For example, the FPGA 150 determines whether or not a process different from a predetermined process is executed as a normal process. Then, when the FPGA 150 determines that the processing different from the processing assumed by the processor 110 is being executed, the FPGA 150 outputs a processing interruption instruction to the processor 110 (step S7). For example, the FPGA 150 interrupts the processing by outputting an interrupt instruction instructing the processor 110 to end the processing.

Then, when the processing is interrupted, the FPGA 150 changes the circuit configuration (step S8). That is, when the processor 110 executes an abnormal process, the FPGA 150 minimizes the influence of hacking and viruses by changing the circuit configuration. By executing such processing, the arithmetic unit 100 can more appropriately prevent abnormal processing.

[2. Arithmetic logic unit configuration]
Hereinafter, an example of the functional configuration of the arithmetic unit 100 that realizes the above-mentioned arithmetic processing will be described. FIG. 2 is a diagram showing a configuration example of the arithmetic unit according to the embodiment.

For example, the arithmetic unit 100 includes a processor 110, an input / output device 120, a memory controller 130, and an FPGA 150. Further, the processor 110 has a processor core 111 and a cache memory 112.

The input / output device 120 is a device that relays communication between the arithmetic unit 100 and the external device OA, and is a so-called I / O (Input Output) device. For example, the input / output device 120 includes USB (Universal Serial Bus), Ethernet, SD (Secure Digital), UART (Universal Asynchronous Receiver / Transmitter), SPI (Serial Peripheral Interface), I2C, GPIO (General-purpose input / output). ) Etc., which is realized by various input / output devices that control communication with the external device OA according to various communication standards.

The memory controller 130 controls the memory access to the main storage device 200 by the arithmetic unit 100. More specifically, the memory controller 130 reads and writes data stored in the main storage device 200 by a paging method. The main storage device 200 is realized by a storage device such as a semiconductor memory element such as a RAM (Random Access Memory) or a flash memory (Flash Memory).

The FPGA 150 realizes the following functions by changing the combination of logic circuits composed of analog circuits according to the HDL received from the external device OA. Then, the FPGA 150 controls the arithmetic processing by the processor 110 by exerting the following functions.

For example, the FPGA 150 combines a logic circuit together with the reception unit 151 and the change unit 152 so as to form the control unit 160. Further, the control unit 160 includes an arithmetic control unit 161, a monitoring unit 162, and an interruption unit 163. For example, the FPGA 150 combines logic circuits so as to constitute a reception unit 151, a change unit 152, an arithmetic control unit 161, a monitoring unit 162, and an interruption unit 163 according to the HDL received from the external device OA.

The reception unit 151 receives a process to be executed by the processor 110. For example, the reception unit 151 receives from the external device OA the processing to be executed by the processor 110, that is, the processing information indicating the content of the arithmetic processing. In such a case, the reception unit 151 delivers the received processing information to the calculation control unit 161.

When the process executed by the processor 110, which is the second arithmetic unit, satisfies a predetermined condition, the change unit 152 executes a change process for changing the combination of logic circuits for executing the monitor process and the interruption process. .. Further, the change unit 152 changes the combination of logic circuits every time the process executed by the processor 110, which is the second calculation unit, satisfies a predetermined condition.

For example, when the execution of the process by the processor 110 is interrupted by the interruption unit 163, the change unit 152 releases the combination of the logic circuits constituting the control unit 160. More specifically, the changing unit 152 disconnects the connection between the logic circuits constituting the control unit 160. Then, the changing unit 152 sets the connection between the logic circuits so as to form a combination of logic circuits constituting the control unit 160 and different from the previous combination. The change unit 152 may have the processor 110 specify such a new connection, or the external device OA may specify it.

The arithmetic control unit 161 causes the processor 110 to execute a predetermined arithmetic processing. For example, when the arithmetic control unit 161 receives the processing information indicating the content of the arithmetic processing to be executed from the reception unit 151, the arithmetic control unit 161 causes the processor 110 to execute the arithmetic processing indicated by the processing information.

The monitoring unit 162 monitors the processing executed by the processor 110, which is the second arithmetic unit. For example, the monitoring unit 162 collects the values stored in the predetermined registers among the registers of the processor core 111 and the information registered in the cache memory 112 at predetermined time intervals. The monitoring target by the monitoring unit 162 may be appropriately changed according to the content of the arithmetic processing to be executed by the arithmetic control unit 161 in the processor 110. For example, the arithmetic control unit 161 sets the address of the register to be monitored and the address of the data held in the cache memory 112 (so-called virtual address) based on the processing content indicated by the processing information. Then, the monitoring unit 162 may target the register of the address set by the arithmetic control unit 161 as a monitoring target, and among the data registered in the cache memory 112, the monitoring unit 162 monitors the data of the address set by the arithmetic control unit 161. May be.

When the process executed by the processor 110, which is the second arithmetic unit, satisfies a predetermined condition, the interrupt unit 163 suspends the execution of the process by the processor 110. For example, the interruption unit 163 acquires the data registered in the register to be monitored by the monitoring unit 162 and the data held in the cache memory 112. Then, the interruption unit 163 determines whether or not the acquired data satisfies a predetermined condition. That is, the interruption unit 163 determines whether or not the acquired data satisfies a predetermined condition, thereby determining whether or not the processor 110 is executing a process different from the expected process. For example, the interruption unit 163 determines whether or not the transition of the periodically acquired data satisfies a predetermined condition.

Then, when the acquired data satisfies a predetermined condition, the interruption unit 163 suspends the execution of the process by the processor 110. For example, the interruption unit 163 outputs an interrupt instruction for interrupting the processing to the processor 110. As a result, the processor 110 can interrupt the execution of an unexpected process, that is, an abnormal process.

As the condition used for the determination by the interruption unit 163, any condition can be set according to the content of the process to be executed by the processor 110. For example, the arithmetic control unit 161 sets the information regarding the change of the data registered in the register to be monitored and the change of the data held in the cache memory 112 as a condition based on the content of the process indicated by the process information. .. Then, the interruption unit 163 may determine whether or not the data to be monitored satisfies the condition set by the calculation control unit 161.

To give a more specific example, the arithmetic control unit 161 indicates that the data held in the register indicated by the first address changes and the data held in the register indicated by the second address does not change. Set as a condition. In such a case, the monitoring unit 162 acquires the data held in the register indicated by the first address and the data held in the register indicated by the second address at predetermined time intervals. Further, the interruption unit 163 refers to the data acquired by the monitoring unit 162 at a predetermined time interval, changes the data held in the register indicated by the first address, and holds the data in the register indicated by the second address. It is determined whether or not the data to be generated has changed. Then, the interruption unit 163 performs an abnormal process when the data held in the register indicated by the first address has not changed or when the data held in the register indicated by the second address has changed. May be interrupted by the processor 110, assuming that is being executed.

[3. An example of the flow of processing executed by the arithmetic unit]
Next, an example of the flow of processing executed by the FPGA 150 will be described with reference to FIG. FIG. 3 is a flowchart illustrating an example of the flow of processing according to the embodiment.

First, the FPGA 150 receives the processing content from the external device OA (step S101). In such a case, the FPGA 150 configures a process to be executed by the processor 110 (step S102), and causes the processor 110 to execute the process (step S103). Here, the FPGA 150 determines whether or not an unexpected process is being executed (step S104), and if an unexpected process is being executed (step S104: Yes), the processor 110 is stopped. (Step S105). Subsequently, the FPGA 150 changes the circuit configuration of the control unit 160 (step S106), and ends the process.

On the other hand, the FPGA 150 determines whether or not the processing by the processor 110 is completed (step S107) when the unexpected processing is not executed (step 104: No), and when the processing is completed (step S107). : Yes), the processing result is output (step S108). after that. The FPGA 150 executes step S106. On the other hand, if the processing is not completed (step S107: No), the FPGA 150 executes step S103.

[4. others〕
Of each of the processes described in the above embodiments, all or part of the processes described as being automatically performed may be performed manually, or all or part of the processes described as being performed manually. Some can be done automatically by a known method. In addition, the processing procedure, specific name, and information including various data and parameters shown in the above text and drawings can be arbitrarily changed unless otherwise specified. For example, the various information shown in each figure is not limited to the information shown in the figure.

Further, each component of each of the illustrated devices is a functional concept, and does not necessarily have to be physically configured as shown in the figure. That is, the specific form of distribution / integration of each device is not limited to the one shown in the figure, and all or part of them may be functionally or physically distributed / physically in any unit according to various loads and usage conditions. Can be integrated and configured.

In addition, the above-described embodiments can be appropriately combined as long as the processing contents do not contradict each other.

[5. effect〕
As described above, the arithmetic unit 100 has a first arithmetic unit (for example, FPGA 150) capable of executing a predetermined process by changing a combination of logic circuits including an analog circuit, and a first arithmetic unit capable of executing a predetermined instruction set. In the arithmetic unit 100 having two arithmetic units (for example, a processor 110), the first arithmetic unit is a monitoring process for monitoring the process executed by the second arithmetic unit by combining logic circuits, and a second arithmetic unit. When the process executed by the unit satisfies a predetermined condition, the execution of the process by the second arithmetic unit is interrupted.

Further, the first arithmetic unit included in the arithmetic unit 100 combines logic circuits to execute logic for executing monitoring processing and interruption processing when the processing executed by the second arithmetic unit satisfies a predetermined condition. Change the circuit combination. For example, the first arithmetic unit changes the combination of logic circuits every time the processing executed by the second arithmetic unit satisfies a predetermined condition.

As a result of these processes, the arithmetic unit 100 can control the arithmetic processing by the processor 110 by, for example, an analog circuit less affected by hacking or a virus, so that it is possible to more appropriately prevent abnormal processing. ..

Although some of the embodiments of the present application have been described in detail with reference to the drawings, these are examples, and various modifications are made based on the knowledge of those skilled in the art, including the embodiments described in the disclosure column of the invention. It is possible to carry out the present invention in other modified forms.

Further, the above-mentioned "section, module, unit" can be read as "means" or "circuit". For example, the generation unit can be read as a generation means or a generation circuit.

100 Arithmetic logic unit 110 Processor 111 Processor core 112 Cache memory 120 Input / output device 130 Memory controller 150 FPGA
151 Reception unit 152 Change unit 160 Control unit 161 Arithmetic control unit 162 Monitoring unit 163 Interruption unit 200 Main storage device OA External device

Claims (4)

The first arithmetic unit, which is an FPGA (Field-Programmable Gate Array) that can execute predetermined processing by changing the combination of logic circuits including analog circuits, and the second arithmetic unit, which is a processor that can execute a predetermined instruction set. It is an arithmetic unit having a unit and
The first arithmetic unit can be combined with the logic circuit.
A monitoring process for monitoring the process executed by the second arithmetic unit, and
When the process executed by the second arithmetic unit is different from the predetermined process as a normal process, it is assumed that an abnormal process is being executed, and the execution of the process being executed by the second arithmetic unit is interrupted. An arithmetic unit characterized by performing interruption processing and execution. The first arithmetic unit can be combined with the logic circuit.
When the process executed by the second arithmetic unit satisfies a predetermined condition, the claim is characterized in that a change process for changing the combination of the logic circuit for executing the monitoring process and the interruption process is executed. Item 1. The arithmetic unit according to Item 1. The arithmetic unit according to claim 2, wherein the change processing changes the combination of the logic circuits each time the processing executed by the second arithmetic unit satisfies a predetermined condition. The first arithmetic unit, which is an FPGA (Field-Programmable Gate Array) that can execute predetermined processing by changing the combination of logic circuits including analog circuits, and the second arithmetic unit, which is a processor that can execute a predetermined instruction set. It is an interruption method executed by the arithmetic unit having the unit by combining the logic circuit possessed by the first arithmetic unit.
A monitoring process for monitoring the processing executed by the second arithmetic unit, and
When the process executed by the second arithmetic unit is different from the predetermined process as a normal process, it is assumed that an abnormal process is being executed, and the execution of the process being executed by the second arithmetic unit is interrupted. A method of interruption, characterized in that it comprises an interruption step.

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