JP7093673B2 - Semiconductor equipment - Google Patents

Description

One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Alternatively, one aspect of the invention relates to semiconductor wafers, modules, and electronic devices.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. A semiconductor circuit, an arithmetic unit, and a storage device, including a semiconductor element such as a transistor, are one aspect of a semiconductor device. Display devices (liquid crystal display devices, light emission display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, image pickup devices, electronic devices, etc. may be said to have semiconductor devices. ..

It should be noted that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter).

In recent years, the development of semiconductor devices has been promoted, and LSIs, CPUs, and memories are mainly used. A CPU is an aggregate of semiconductor elements having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and having electrodes as connection terminals formed therein.

Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, for example, printed wiring boards, and are used as one of various electronic device components.

Further, a technique for forming a transistor by using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also referred to simply as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

Further, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, a low power consumption CPU that applies the characteristic that the leakage current of a transistor using an oxide semiconductor is low is disclosed (see Patent Document 1).

Further, a method of manufacturing a transistor using an oxide semiconductor by embedding a gate electrode in an opening is disclosed (see Patent Document 2).

Further, in recent years, with the miniaturization and weight reduction of electronic devices, there is an increasing demand for integrated circuits in which transistors and the like are integrated at high density. Further, it is required to improve the productivity of semiconductor devices including integrated circuits.

Japanese Unexamined Patent Publication No. 2012-257187 JP-A-2017-05530

One aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration. One aspect of the present invention is to provide a semiconductor device having good electrical characteristics. One aspect of the present invention is to provide a semiconductor device having good frequency characteristics. One of the problems of one aspect of the present invention is to provide a semiconductor device having good reliability. One aspect of the present invention is to provide a highly productive semiconductor device.

One of the problems of one aspect of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. One aspect of the present invention is to provide a semiconductor device having a high information writing speed. One aspect of the present invention is to provide a semiconductor device having a high degree of freedom in design. One aspect of the present invention is to provide a semiconductor device capable of suppressing power consumption. One aspect of the present invention is to provide a novel semiconductor device.

The description of these issues does not preclude the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. Issues other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. Is.

One aspect of the present invention is an oxide, a first conductor provided on the oxide at a distance from each other, a second conductor, a first conductor on the oxide, and a first conductor. A third conductor having a region overlapping the region between the two conductors, a first insulator on the third conductor, an oxide, and a third conductor. The first on the second insulator, the first insulator, and the second insulator, which are arranged so as to cover the side surface of the third conductor and in contact with the side surface of the first insulator. And a third insulator having a second opening, a fourth conductor that electrically connects to the first conductor through the first opening, and a second through the second opening. It has a fifth conductor that electrically connects to the second conductor, and at least one of the first opening and the second opening is the first insulator and at least one of the second insulators. It is a semiconductor device having a region that overlaps with one of them.

In the above, it is preferable that the first insulator and the second insulator contain metal and oxygen, respectively, and the third insulator contains silicon and oxygen, respectively.

In the above, the semiconductor device includes a fourth insulator covering the upper surface and side surface of the first conductor, the upper surface and side surface of the second conductor, and the side surface of the oxide, and the fourth insulator and the fourth insulator. It may have a fifth insulator between the three insulators.

In the above, it is preferable that the fourth insulator contains metal and oxygen, and the fifth insulator contains silicon and oxygen.

In the above, the sixth insulator may be provided on the first insulator, and the sixth insulator is preferably a nitride containing silicon.

One aspect of the present invention is an oxide, a first conductor provided on the oxide at a distance from each other, a second conductor, and between the first conductor and the second conductor. On a third conductor provided in, a fourth conductor having a region on the oxide and overlapping with a region between the first conductor and the third conductor, and on the fourth conductor. First insulator, oxide, and fourth conductor, which are arranged so as to cover the side surface of the fourth conductor and to be in contact with the side surface of the first insulator. A third insulation on the second conductor, a fifth conductor having a region on the oxide and overlapping the region between the second conductor and the third conductor, and a third conductor on the fifth conductor. A fourth insulator arranged between the body, the oxide, and the fifth conductor, covering the side surface of the fifth conductor and in contact with the side surface of the third insulator. , A fifth insulator with an opening on a first insulator, a second insulator, a third insulator, and a fourth insulator, and an electrical conductor and a third conductor through the opening. With a sixth conductor connected to, the opening has a region that overlaps with at least one of the first, second, third, and fourth insulators. It is a semiconductor device.

In the above, the first insulator, the second insulator, the third insulator, and the fourth insulator may contain metal and oxygen, respectively, and the fifth insulator may contain silicon and oxygen. preferable.

In the above, the semiconductor device covers the upper surface and side surface of the first conductor, the upper surface and side surface of the second conductor, the upper surface and side surface of the third conductor, and the side surface of the oxide. It may have an insulator and a seventh insulator between the sixth insulator and the fifth insulator.

In the above, it is preferable that the sixth insulator contains metal and oxygen, and the seventh insulator contains silicon and oxygen.

In the above, the eighth insulator is on the first insulator, the ninth insulator is on the third insulator, the eighth insulator, and the ninth insulator are. , Each is preferably a nitride containing silicon.

In the above, the metal is preferably one selected from aluminum, hafnium, magnesium, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, tungsten, titanium, tantalum, and nickel.

In the above, the oxide preferably contains In, the element M (M is Al, Ga, Y, or Sn), and Zn.

According to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. According to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. According to one aspect of the present invention, a semiconductor device having good frequency characteristics can be provided. INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a semiconductor device having good reliability. According to one aspect of the present invention, a highly productive semiconductor device can be provided.

Alternatively, it is possible to provide a semiconductor device capable of retaining data for a long period of time. Alternatively, it is possible to provide a semiconductor device having a high data writing speed. Alternatively, it is possible to provide a semiconductor device having a high degree of freedom in design. Alternatively, it is possible to provide a semiconductor device capable of suppressing power consumption. Alternatively, a new semiconductor device can be provided.

The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not have to have all of these effects. It should be noted that the effects other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.

Top view and sectional view of the semiconductor device according to one aspect of the present invention. Sectional drawing of the semiconductor device which concerns on one aspect of this invention. Sectional drawing of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the storage device according to one aspect of the present invention. The circuit diagram of the storage device which concerns on one aspect of this invention. The schematic diagram of the storage device which concerns on one aspect of this invention. The schematic diagram of the storage device which concerns on one aspect of this invention. The cross-sectional view which shows the structure of the storage device which concerns on one aspect of this invention. The block diagram which shows the structural example of the storage device which concerns on one aspect of this invention. The circuit diagram which shows the structural example of the storage device which concerns on one aspect of this invention. The figure explaining an example of the electronic component which concerns on one aspect of this invention. The figure explaining an example of the electronic device which concerns on one aspect of this invention. The figure explaining the application example of the storage device which concerns on one aspect of this invention.

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that embodiments can be implemented in many different embodiments and that the embodiments and details can be varied in various ways without departing from the spirit and scope thereof. To. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but they may be omitted for ease of understanding. Further, in the drawings, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted. Further, when referring to the same function, the hatch pattern may be the same and no particular reference numeral may be added.

Further, in order to facilitate understanding of the invention, in particular, in a top view (also referred to as a “plan view”) or a perspective view, the description of some components may be omitted. In addition, some hidden lines may be omitted.

Further, in the present specification and the like, the ordinal numbers attached as the first, second, etc. are used for convenience, and do not indicate the process order or the stacking order. Therefore, for example, the "first" can be appropriately replaced with the "second" or "third" for explanation. In addition, the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

Further, in the present specification and the like, words and phrases indicating arrangements such as "above" and "below" are used for convenience in order to explain the positional relationship between the configurations with reference to the drawings. Further, the positional relationship between the configurations changes appropriately depending on the direction in which each configuration is depicted. Therefore, it is not limited to the words and phrases explained in the specification, and can be appropriately paraphrased according to the situation.

For example, in the present specification and the like, when it is explicitly stated that X and Y are directly connected and that X and Y are connected, X and Y are electric. It is assumed that the case where X and Y are functionally connected and the case where X and Y are functionally connected are disclosed in the present specification and the like. Therefore, it is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, and other than the connection relationship shown in the figure or text, it is assumed that the connection relationship is also described in the figure or text.

Here, it is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

Further, the functions of the source and the drain may be switched when transistors having different polarities are adopted or when the direction of the current changes in the circuit operation. Therefore, in the present specification and the like, the terms source and drain may be used interchangeably.

In the present specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter, also referred to as “effective channel width”) and the channel width shown in the top view of the transistor. (Hereinafter, also referred to as "apparent channel width") and may be different. For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a transistor that is fine and has a gate electrode covering the side surface of the semiconductor, the ratio of the channel forming region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.

Further, in the present specification, when simply described as a channel width, it may refer to an apparent channel width. Alternatively, in the present specification, the term "channel width" may refer to an effective channel width. The values of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like.

The semiconductor impurities are, for example, other than the main components constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. The inclusion of impurities may result in, for example, an increase in DOS (Density of States) of the semiconductor, a decrease in crystallinity, and the like. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, Group 1 element, Group 2 element, Group 13 element, Group 14 element, Group 15 element, and oxide semiconductor. There are transition metals other than the main components of the above, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of oxide semiconductors, water may also function as an impurity. Further, in the case of an oxide semiconductor, oxygen deficiency may be formed, for example, by mixing impurities. When the semiconductor is silicon, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements excluding oxygen and hydrogen, Group 2 elements, Group 13 elements, Group 15 elements and the like.

In the present specification and the like, silicon oxide has a higher oxygen content than nitrogen as its composition. Further, silicon nitride oxide has a higher nitrogen content than oxygen in its composition.

Further, in the present specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

In the present specification, the barrier membrane is a membrane having a function of suppressing the permeation of impurities such as hydrogen and oxygen, and when the barrier membrane has conductivity, it is referred to as a conductive barrier membrane. There is.

In the present specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when it is described as an OS FET or an OS transistor, it can be rephrased as a transistor having an oxide or an oxide semiconductor.

Further, in the present specification and the like, normally off means that when a potential is not applied to the gate or a ground potential is applied to the gate, the current per 1 μm of the channel width flowing through the transistor is 1 × 10 ^-20 at room temperature. A or less, 1 × 10 ^-18 A or less at 85 ° C, or 1 × 10 ^-16 A or less at 125 ° C.

(Embodiment 1)
Hereinafter, an example of a semiconductor device having the transistor 200 according to one aspect of the present invention will be described.

<Semiconductor device configuration example>
1 (A), 1 (B), and 1 (C) are a top view and a cross-sectional view of the transistor 200 according to one aspect of the present invention and the periphery of the transistor 200.

FIG. 1A is a top view of a semiconductor device having a transistor 200. Further, FIGS. 1B and 1C are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Further, FIG. 1C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. In the top view of FIG. 1 (A), some elements are omitted for the sake of clarity of the figure.

The semiconductor device of one aspect of the present invention includes a transistor 200, an insulator 210 that functions as an interlayer film, an insulator 212, an insulator 280, and an insulator 281. Further, the conductor 203 (conductor 203a and conductor 203b) that is electrically connected to the transistor 200 and functions as wiring, and the conductor 240 (conductor 240a, conductor 240b, and conductor 240c) that functions as a plug. ) And.

The transistor 200 has a transistor 200a and a transistor 200b in one semiconductor layer. Further, one of the source and drain of the transistor 200a is shared with one of the source and drain of the transistor 200b. Therefore, as compared with the case where the transistor 200a and the transistor 200b are formed, the number of plugs and the like connected to the transistor 200 can be reduced, and the area of the transistor 200 can be reduced. Here, in the present embodiment, one of the transistor 200a and the transistor 200b may be mainly described as a detailed description of the transistor 200, but the transistor 200a and the transistor 200b have the same configuration unless otherwise specified. The other description of the transistor 200a and the transistor 200b will be omitted. Further, in the present specification, the transistor 200 may refer to one or both of the transistor 200a and the transistor 200b.

The conductor 203 is in contact with the inner wall of the opening of the insulator 212 to form the conductor 203a, and the conductor 203b is further formed inside. Here, the height of the upper surface of the conductor 203 and the height of the upper surface of the insulator 212 can be made equal to each other. Although the transistor 200 shows a configuration in which the conductor 203a and the conductor 203b are laminated, the present invention is not limited to this. For example, the conductor 203 may be provided as a single layer or a laminated structure having three or more layers. When the structure has a laminated structure, an ordinal number may be given in the order of formation to distinguish them.

Further, the conductor 240 is provided in the opening of the insulator 280 and the insulator 281 via the insulator 241 in contact with the inner wall of the opening. The first conductor of the conductor 240 is formed in contact with the insulator 241, and the second conductor of the conductor 240 is further formed inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be made equal to each other. In the transistor 200, the configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are laminated is shown, but the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a laminated structure having three or more layers. When the structure has a laminated structure, an ordinal number may be given in the order of formation to distinguish them.

[Transistor 200]
As shown in FIG. 1, the conductor 200 is attached to an insulator 214 arranged on a substrate (not shown), an insulator 216 arranged on the insulator 214, and an insulator 214 and an insulator 216. Conductors 205 arranged to be embedded (conductors 205a and 205b), insulators 216 and insulators 222 placed on conductors 205, and insulation placed on insulators 222. The body 224, the oxide 230a arranged on the insulator 224, the oxide 230b arranged on the oxide 230a, and the conductor 242 arranged on the oxide 230b (conductor 242a, conductive). The body 242b and the conductor 242c), the insulator 244 covering the insulator 224, the oxide 230a, the oxide 230b, and the conductor 242, and the insulator 280 arranged on the insulator 244 and having an opening. In the opening, the upper surface and the side surface of the oxide 230b, the side surface of the oxide 230a, the side surface of the conductor 242, the side surface of the insulator 244, and the side surface of the insulator 280 are provided so as to be in contact with each other. The oxide 230c, the insulator 250a provided inside the oxide 230c, the insulator 250b provided inside the insulator 250a, the conductor 260a provided inside the insulator 250b, and the conductor 260a. A conductor 260b provided so as to be embedded inside the conductor, an insulator 272 provided on the conductor 260a and the conductor 260b, which is in contact with the inside of the insulator 250b, and an insulator 272 provided inside the insulator 272. It has an insulator 273 and the like.

Insulator 281 is provided on the insulator 280, the oxide 230c, the insulator 250a, the insulator 250b, the insulator 272, and the insulator 273, and the insulator 281, the insulator 280, and the insulator 244 have openings. The upper surface and side surface of the oxide 230c, the upper surface of the insulator 250a, the upper surface of the insulator 250b, and the upper surface or the side surface of the insulator 272 are exposed inside the opening, and the side surface of the opening is insulated. A conductor 240 is provided inside the opening provided with the body 241 and the insulator 241.

In the transistor 200, the oxide 230 is composed of three layers of the oxide 230a, the oxide 230b, and the oxide 230c in the region where the channel is formed (hereinafter, also referred to as the channel formation region) and the vicinity thereof. Although the structure having a laminated structure is shown, the present invention is not limited to this. For example, the oxide 230 has a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a laminated structure of four or more layers. May be good. Further, the oxide 230a, the oxide 230b, and the oxide 230c may each have a laminated structure of two or more layers. FIG. 2 is an enlarged view of the vicinity of the channel formation region of the transistor 200a. FIG. 2 shows an example in which the oxide 230c has a laminated structure consisting of two layers of the oxide 230c1 and the oxide 230c2 on the oxide 230c1. Although only the enlarged view of the transistor 200a is shown in FIG. 2, the transistor 200b has the same configuration. Further, in the transistor 200, the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a laminated structure of three or more layers.

Here, the conductor 260 functions as a gate electrode of the transistor, and the conductor 242a, the conductor 242b, and the conductor 242c function as a source electrode or a drain electrode, respectively. As described above, the conductor 260 has an oxide 230c or an oxide 230c in the opening of the insulator 280 and the region sandwiched between the conductor 242a and the conductor 242c, or the region sandwiched between the conductor 242b and the conductor 242c. It is formed so as to be embedded via an insulator 250 or the like. Here, the arrangement of the conductor 260, the conductor 242a, the conductor 242b, and the conductor 242c is self-aligned with respect to the opening of the insulator 280. That is, in the transistor 200, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 260 can be formed without providing the alignment margin, the occupied area of the transistor 200 can be reduced. As a result, the semiconductor device can be miniaturized and highly integrated.

Further, since the conductor 260 is formed in a region between the conductor 242a and the conductor 242c or a region between the conductor 242b and the conductor 242c in a self-aligned manner, the conductor 260 is formed in the region between the conductor 242a and the conductor 242a. It does not have a region that overlaps with the conductor 242b or the conductor 242c. This makes it possible to reduce the parasitic capacitance formed between the conductor 260 and the conductors 242a, 242b, and 242c. Therefore, the switching speed of the transistor 200 can be improved and a high frequency characteristic can be provided.

Further, the transistor 200 has a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor in the oxide 230 (oxide 230a, oxide 230b, and oxide 230c) containing a channel forming region. It is preferable to use it.

Since the transistor 200 using the oxide semiconductor in the channel forming region has an extremely small leakage current in the non-conducting state, it is possible to provide a semiconductor device having low power consumption. Further, since the oxide semiconductor can be formed into a film by a sputtering method or the like, it can be used for the transistor 200 constituting the highly integrated semiconductor device.

For example, as the oxide 230, an In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodym). , Hafnium, tantalum, tungsten, magnesium, etc. (one or more) and the like may be used. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.

Here, in the presence of impurities such as hydrogen, nitrogen, and metal elements, the oxide 230 may have an increased carrier density and a low resistance. Further, when the oxygen concentration contained in the oxide 230 decreases, the carrier density increases and the resistance may decrease.

When the conductor 242 (conductor 242a, conductor 242b, and conductor 242c) provided in contact with the oxide 230 and functioning as a source electrode or a drain electrode has a function of absorbing oxygen of the oxide 230. Or, when the oxide 230 has a function of supplying an impurity such as hydrogen, nitrogen, or a metal element, the oxide 230 has a region 231 (region 231a, region 231b, and region 231c) as a partially low resistance region. ) May be formed.

The insulator 244 is provided to suppress the oxidation of the conductor 242. Therefore, if the conductor 242 is an oxidation-resistant material or a material whose conductivity does not significantly decrease even if oxygen is absorbed, the insulator 244 does not necessarily have to be provided. Further, when the insulator 244 covers the side surfaces of the oxide 230a and the oxide 230b and comes into contact with the insulator 224 or the insulator 222, impurities such as hydrogen and water are added to the oxide 230a and the oxide 230b. Contamination and release of oxygen from oxides 230a and 230b can be suppressed.

The insulator 250b is provided to prevent contact between the conductor 260 and the conductor 240. Further, the insulator 250b may have a function of suppressing the oxidation of the conductor 260, and it is preferable to use a material in which oxygen does not easily permeate. On the other hand, if the conductor 260 does not significantly reduce the conductivity even if it absorbs an oxidation resistant material or oxygen, the insulator 250b does not need to have a function of suppressing the oxidation of the conductor 260.

The insulator 272 and the insulator 273 function as an etching stopper when forming an opening for exposing the conductor 242. The insulator 272 and the insulator 273 can form an opening for exposing the conductor 242 in a self-aligned manner, and the conductor 242 and the conductor 240 can be electrically connected to each other. The opening formed by such a structure, the opening, and the method of forming the conductor may be referred to as a self-aligned contact.

As shown in FIG. 1, a conductor 242 is provided so as to be in contact with the oxide 230, and a region 231 (region 231a, Regions 231b and 231c) are formed. Further, the oxide 230 has a region 234 (region 234a and region 234b) that functions as a channel forming region of the transistor 200. The region 234a and the region 234b function as a channel forming region of the transistor 200a and the transistor 200b, respectively.

Region 231 functions as a source region or a drain region. Further, the region 231 has a lower oxygen concentration than the region 234, or contains a large amount of impurities such as hydrogen, nitrogen, and metal elements, so that the carrier concentration is increased and the resistance is lowered. That is, the region 231 has a higher carrier density and a lower resistance than the region 234. Further, the region 234 functioning as the channel forming region is a high resistance region having a lower carrier density because the oxygen concentration is higher or the impurity concentration is lower than the region 231.

When the region 231 which is a low resistance region contains a metal element, the region 231 includes aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, in addition to the metal element contained in the oxide 230. It is preferable to have one or more metal elements selected from metal elements such as molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum. ..

Further, in FIG. 1B, the region 231 is formed in the vicinity of the interface of the oxide 230b with the conductor 242 in the film thickness direction of the oxide 230b, but the present invention is not limited to this. For example, the region 231 may have substantially the same thickness as the film thickness of the oxide 230b, or may be formed on the oxide 230a as well.

Further, in the oxide 230, it may be difficult to clearly detect the boundary of each region. The concentrations of metal elements detected in each region and impurity elements such as hydrogen and nitrogen are not limited to gradual changes in each region, but also continuously change (also referred to as gradation) in each region. You may. That is, the closer the region is to the channel formation region, the lower the concentration of the metal element and the impurity elements such as hydrogen and nitrogen is sufficient.

To selectively reduce the resistance of the oxide 230, the conductor 242 may be, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, etc. It is preferable to use a material containing at least one of metal elements such as manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum which enhances conductivity, and impurities. Alternatively, in the formation of the conductive film 242A to be the conductor 242, if an impurity such as an element forming an oxygen deficiency or an element captured by the oxygen deficiency is injected into the oxide 230, a film forming method, or the like is used. good. For example, examples of the element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and rare gas. Typical examples of rare gas elements include helium, neon, argon, krypton, xenon and the like.

Here, in a transistor using an oxide semiconductor, if impurities and oxygen deficiencies are present in the region where a channel is formed in the oxide semiconductor, the electrical characteristics are liable to fluctuate and the reliability may be deteriorated. Further, if oxygen deficiency is contained in the region where the channel is formed in the oxide semiconductor, the transistor tends to have a normally-on characteristic. Therefore, it is preferable that oxygen deficiency in the region 234 where the channel is formed is reduced as much as possible.

In order to suppress normalization of the transistor, it is preferable that the insulator 250 in the vicinity of the oxide 230 contains more oxygen (also referred to as excess oxygen) than oxygen satisfying the stoichiometric composition. The oxygen contained in the insulator 250 diffuses into the oxide 230, the oxygen deficiency of the oxide 230 can be reduced, and the normalization of the transistor can be suppressed.

That is, the oxygen contained in the insulator 250 diffuses into the region 234 of the oxide 230, so that the oxygen deficiency in the region 234 of the oxide 230 can be reduced.

Further, in order to suppress the diffusion of oxygen contained in the oxide 230 and the insulator 250 to the outside from the transistor 200, an insulator 222, an insulator 244, an insulator 273, an insulator 272, an insulator 250b and the like are used. It is preferable to be provided. As these insulators, it is preferable to use a material that does not easily allow oxygen to permeate. For example, an oxide containing one of aluminum and hafnium, a nitride of silicon, and the like can be used. Further, it is preferable that these insulating films are made of a material in which impurities such as hydrogen, water, nitrogen and metal elements are difficult to permeate. By using such a material, it is possible to suppress the mixing of impurities into the transistor 200 from the outside of the transistor 200.

Further, since the oxide semiconductor can be formed into a film by a sputtering method or the like, it can be used for a transistor constituting a highly integrated semiconductor device. Further, since the transistor using the oxide semiconductor in the channel forming region has an extremely small leakage current (off current) in the non-conducting state, it is possible to provide a semiconductor device having low power consumption.

From the above, it is possible to provide a semiconductor device having a transistor having a large on-current. Alternatively, it is possible to provide a semiconductor device having a transistor having a small off-current. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

Hereinafter, a detailed configuration of the semiconductor device having the transistor 200 according to one aspect of the present invention will be described.

As shown in FIGS. 1A and 1C, the conductor 203 is extended in the channel width direction and functions as a wiring for applying a potential to the conductor 205. The conductor 203 is preferably provided by being embedded in the insulator 212.

The conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. Further, the conductor 205 may be provided in contact with the conductor 203. Further, it is preferable that the conductor 205 is embedded in the insulator 214 and the insulator 216.

Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, it is possible to make the Vth of the transistor 200 larger than 0V and reduce the off-current. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when it is not applied.

Further, by providing the conductor 205 on the conductor 203, it is possible to appropriately design the distance between the conductor 260 having a function as a first gate electrode and wiring and the conductor 203. That is, by providing the insulator 214 and the insulator 216 between the conductor 203 and the conductor 260, the parasitic capacitance between the conductor 203 and the conductor 260 is reduced, and the conductor 203 and the conductor 260 The withstand voltage between them can be increased.

Further, by reducing the parasitic capacitance between the conductor 203 and the conductor 260, the switching speed of the transistor 200 can be improved, and the transistor can be made into a transistor having high frequency characteristics. Further, the reliability of the transistor 200 can be improved by increasing the withstand voltage between the conductor 203 and the conductor 260. Therefore, it is preferable to increase the film thickness of the insulator 214 and the insulator 216. The stretching direction of the conductor 203 is not limited to this, and may be stretched in the channel length direction of the transistor 200, for example.

As shown in FIG. 1A, the conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. Further, the conductor 205 may be provided larger than the region 234 in the oxide 230. In particular, as shown in FIG. 1C, it is preferable that the conductor 205 is also stretched in a region outside the end of the region 234 of the oxide 230 intersecting the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on each other via the insulator on the side surface of the oxide 230 in the channel width direction.

By having the above configuration, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a channel formed in the oxide 230. Can cover the area.

That is, the channel forming region of the region 234 can be electrically surrounded by the electric field of the conductor 260 having the function as the first gate electrode and the electric field of the conductor 205 having the function as the second gate electrode. .. In the present specification, the structure of the transistor that electrically surrounds the channel forming region by the electric fields of the first gate electrode and the second gate electrode is referred to as a curved channel (S-channel) structure.

Further, the conductor 205 is in contact with the inner wall of the opening of the insulator 214 and the insulator 216 to form the conductor 205a, and the conductor 205b is further formed inside. Here, the height of the upper surface of the conductor 205a and the conductor 205b can be made the same as the height of the upper surface of the insulator 216. The transistor 200 shows a configuration in which the conductor 205a and the conductor 205b are laminated, but the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or a laminated structure having three or more layers. When the structure has a laminated structure, an ordinal number may be given in the order of formation to distinguish them.

Here, the conductor 205a or the conductor 203a diffuses impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules _{(N2O, NO, NO 2 ,} etc.), and copper atoms. It is preferable to use a conductive material having a function of suppressing (the above impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule) (the above oxygen is difficult to permeate). In the present specification, the function of suppressing the diffusion of impurities or oxygen is the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

Since the conductor 205a or the conductor 203a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 205b or the conductor 203b from being oxidized and the conductivity from being lowered. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used. Therefore, as the conductor 205a or the conductor 203a, the conductive material may be a single layer or a laminated material. This makes it possible to prevent impurities such as hydrogen and water from diffusing toward the transistor 200 through the conductor 203 and the conductor 205.

Further, as the conductor 205b, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Although the conductor 205b is shown as a single layer, it may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.

Further, since the conductor 203b functions as wiring, it is preferable to use a conductor having higher conductivity than the conductor 205b. For example, a conductive material containing copper or aluminum as a main component can be used. Further, the conductor 203b may have a laminated structure, and may be, for example, a laminated structure of titanium or titanium nitride and the conductive material.

In particular, it is preferable to use copper for the conductor 203b. Since copper has a small resistance, it is preferable to use it for wiring or the like. On the other hand, since copper is easily diffused, it may diffuse into the oxide 230 to deteriorate the electrical characteristics of the transistor 200. Therefore, for example, by using a material such as aluminum oxide or hafnium oxide having low copper permeability for the insulator 214, the diffusion of copper can be suppressed.

The conductor 205, the insulator 214, and the insulator 216 do not necessarily have to be provided. In that case, a part of the conductor 203 can function as a second gate electrode.

It is preferable that the insulator 210 and the insulator 214 function as a barrier insulating film that prevents impurities such as water and hydrogen from being mixed into the transistor 200 from the substrate side. Therefore, the insulator 210 and the insulator 214 diffuse impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ₍ N2O, NO, _NO2 , etc.) and copper atom. It is preferable to use an insulating material having a function of suppressing (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule) (the above oxygen is difficult to permeate).

For example, it is preferable to use aluminum oxide or the like as the insulator 210 and silicon nitride or the like as the insulator 214. This makes it possible to prevent impurities such as hydrogen and water from diffusing from the substrate side to the transistor 200 side of the insulator 210 and the insulator 214. Alternatively, it is possible to prevent oxygen contained in the insulator 224 or the like from diffusing toward the substrate side of the insulator 210 and the insulator 214.

Further, by stacking the conductor 205 on the conductor 203, the insulator 214 can be provided between the conductor 203 and the conductor 205. Here, even if a metal such as copper that is easily diffused is used for the second conductor of the conductor 203, the metal is diffused to the layer above the insulator 214 by providing silicon nitride or the like as the insulator 214. Can be suppressed.

Further, the insulator 212, the insulator 216, the insulator 280, and the insulator 281 that function as an interlayer film preferably have a lower dielectric constant than the insulator 210 or the insulator 214. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.

For example, as insulator 212, insulator 216, insulator 280, and insulator 281 include silicon oxide, silicon nitride nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead strontium titanate (PZT). ), Strontium titanate (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST) and other insulators can be used in a single layer or in a laminated manner. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon nitride, or silicon nitride may be laminated and used on the above-mentioned insulator.

The insulator 222, the insulator 224, and the insulator 250 have a function as a gate insulator.

Here, as the insulator 224, it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition. That is, it is preferable that the insulator 224 has an excess oxygen region. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen deficiency in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

As the insulator having an excess oxygen region, specifically, it is preferable to use an oxide material in which a part of oxygen is desorbed by heating. Oxides that desorb oxygen by heating are those whose oxygen desorption amount in terms of oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis. An oxide film of 0.0 × 10 ¹⁹ atoms / cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms / cm ³ , or 3.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.

Further, when the insulator 224 has an excess oxygen region, the insulator 222 has a function of suppressing the diffusion of at least one oxygen (for example, an oxygen atom, an oxygen molecule, etc.) (the oxygen is difficult to permeate). Is preferable.

Since the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, the oxygen contained in the oxide 230 does not diffuse to the insulator 216 side, which is preferable. Further, it is possible to suppress the conductor 205 from reacting with the oxygen contained in the insulator 224 and the oxide 230.

The insulator 222 is a so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconate oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST). -It is preferable to use an insulator containing a k material in a single layer or in a laminated manner. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for an insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing diffusion of impurities and oxygen (the oxygen is difficult to permeate). As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like. When the insulator 222 is formed by using such a material, the insulator 222 suppresses the release of oxygen from the oxide 230 and the mixing of impurities such as hydrogen from the peripheral portion of the transistor 200 into the oxide 230. Functions as a layer.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon nitride or silicon nitride may be laminated and used on the above-mentioned insulator.

The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.

The oxide 230 has an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. By having the oxide 230a under the oxide 230b, it is possible to suppress the diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b. Further, by having the oxide 230c on the oxide 230b, it is possible to suppress the diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b.

The oxide 230 preferably has a laminated structure due to oxides having different atomic number ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the atomic number ratio of the element M in the constituent elements is larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used in the oxide 230b. Is preferable. Further, in the metal oxide used for the oxide 230a, the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230b, the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 230a. Further, as the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.

Further, it is preferable that the energy at the lower end of the conduction band of the oxide 230a and the oxide 230c is higher than the energy at the lower end of the conduction band of the oxide 230b. In other words, it is preferable that the electron affinity of the oxide 230a and the oxide 230c is smaller than the electron affinity of the oxide 230b.

Here, at the junction of the oxide 230a, the oxide 230b, and the oxide 230c, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that the energy level at the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c is continuously changed or continuously bonded. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c.

Specifically, as the oxide 230a, a metal oxide having In: Ga: Zn = 1: 3: 4 [atomic number ratio] or 1: 1: 0.5 [atomic number ratio] may be used. Further, as the oxide 230b, a metal oxide having In: Ga: Zn = 4: 2: 3 [atomic number ratio] or 1: 1: 1 [atomic number ratio] may be used. Further, as the oxide 230c, In: Ga: Zn = 1: 3: 4 [atom number ratio], In: Ga: Zn = 4: 2: 3 [atom number ratio], Ga: Zn = 2: 1 [atom]. A metal oxide having a [number ratio] or Ga: Zn = 2: 5 [atomic number ratio] may be used. Further, as a specific example in the case where the oxide 230c has a laminated structure containing the oxide 230c1 and the oxide 230c2 on the oxide 230c1 as shown in FIG. 2, In: Ga: Zn = 4: as the oxide 230c1. Laminated structure of 2: 3 [atomic number ratio] and In: Ga: Zn = 1: 3: 4 [atomic number ratio] as oxide 230c2, In: Ga: Zn = 4: 2: 3 as oxide 230c1 A laminated structure of [atomic number ratio] and Ga: Zn = 2: 1 [atomic number ratio] as the oxide 230c2, and In: Ga: Zn = 4: 2: 3 [atomic number ratio] as the oxide 230c1. A laminated structure with Ga: Zn = 2: 5 [atomic number ratio] as the oxide 230c2, In: Ga: Zn = 4: 2: 3 [atomic number ratio] as the oxide 230c1, and gallium oxide as the oxide 230c2. The laminated structure of the above can be mentioned.

At this time, the main path of the carrier is the oxide 230b. By configuring the oxide 230a and the oxide 230c as described above, the defect level density at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 200 can obtain high on-current and high frequency characteristics. When the oxide 230c has a laminated structure, in addition to the effect of lowering the defect level density at the interface between the oxide 230b and the oxide 230c, the constituent elements of the oxide 230c are on the insulator 250 side. It is expected to suppress the spread to. More specifically, since the oxide 230c has a laminated structure and an oxide containing no In or having a reduced concentration of In is located above the laminated structure, In that can be diffused to the insulator 250 side is suppressed. can do. Since the insulator 250 functions as a gate insulator, if In is diffused, the characteristics of the transistor become poor. Therefore, by forming the oxide 230c in a laminated structure, it is possible to provide a highly reliable semiconductor device.

Further, by forming the oxide 230c in a laminated structure, the main path of the carrier may be the interface between the oxide 230b and the oxide 230c1 or its vicinity.

Further, since the oxide 230c1 is in contact with the side surface of the insulator 280, oxygen contained in the insulator 280 can be supplied to the channel forming region of the transistor 200 via the oxide 230c1. Further, it is preferable to use a material as the oxide 230c2, which is difficult for oxygen to permeate. By using the above-mentioned material, oxygen contained in the insulator 280 can be prevented from permeating through the oxide 230c2 and absorbed by the insulator 250 or the conductor 260, and oxygen can be efficiently transferred to the channel forming region. Can be supplied.

Further, the oxide 230 has a region 231 and a region 234. It should be noted that at least a part of the region 231 has a region in contact with the conductor 242.

When the transistor 200 is turned on, the region 231a, the region 231b, or the region 231c functions as a source region or a drain region. On the other hand, at least a part of the region 234 functions as a region where a channel is formed.

That is, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meets the requirements according to the circuit design.

As the oxide 230, it is preferable to use a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor. For example, as the metal oxide forming the region 234, it is preferable to use an oxide having a band gap of 2 eV or more, preferably 2.5 eV or more. As described above, by using a metal oxide having a large bandgap, the off-current of the transistor can be reduced.

Since a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state, it is possible to provide a semiconductor device having low power consumption. Further, since the oxide semiconductor can be formed into a film by a sputtering method or the like, it can be used for a transistor constituting a highly integrated semiconductor device.

A conductor 242 (conductor 242a, conductor 242b, and conductor 242c) that functions as a source electrode and a drain electrode is provided on the oxide 230b. As the conductor 242, it is preferable to use an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even if it absorbs oxygen.

By providing the conductor 242 so as to be in contact with the oxide 230, the oxygen concentration in the region 231 may be reduced. Further, a metal compound layer containing the metal contained in the conductor 242 and the component of the oxide 230 may be formed in the region 231. In such a case, the carrier density of the region 231 increases, and the region 231 becomes a low resistance region.

Here, the region between the conductor 242a and the conductor 242c and the region between the conductor 242b and the conductor 242c are formed so as to overlap with the opening of the insulator 280. As a result, the conductor 260 can be arranged in a self-aligned manner between the conductor 242a and the conductor 242c, and between the conductor 242b and the conductor 242c.

The insulator 244 is provided so as to cover the conductor 242 and suppresses the oxidation of the conductor 242. At this time, the insulator 244 may be provided so as to cover the side surface of the oxide 230 and be in contact with the insulator 224.

As the insulator 244, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like can be used. can.

In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both oxides of aluminum or hafnium. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the thermal history in a later step. If the conductor 242 is a material having oxidation resistance, or if the conductivity does not significantly decrease even if oxygen is absorbed, the insulator 244 is not an essential configuration. It may be appropriately designed according to the desired transistor characteristics.

An insulator 280 is provided on the insulator 244. The surface of the insulator 280 is preferably flattened.

As shown in FIGS. 1B and 1C, the oxide 230c is the upper surface of the oxide 230b, the side surface of the oxide 230b, the side surface of the oxide 230a, the side surface of the conductor 242, and the insulator 244. It is provided so as to be in contact with the side surface and the side surface of the insulator 280.

The insulator 250a and the insulator 250b function as a gate insulator. The insulator 250a is preferably arranged in contact with the inside (upper surface and side surface) of the oxide 230c. The insulator 250a is preferably formed by using an insulator that releases oxygen by heating. For example, in a heated desorption gas spectroscopy analysis (TDS analysis), the amount of oxygen desorbed in terms of oxygen molecules is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1.0 × 10 ¹⁹ . It is an oxide film having atoms / cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms / cm ³ , or 3.0 × 10 ²⁰ atoms / cm ³ . The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower.

Specifically, as the insulator 250a, silicon oxide having excess oxygen, silicon oxide, silicon oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, and silicon oxide to which carbon and nitrogen are added. , Silicon oxide having pores can be used. In particular, silicon oxide and silicon nitride nitride are preferable because they are heat-stable.

By providing an insulator that releases oxygen by heating as an insulator 250a in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied from the insulator 250a to the region 234 of the oxide 230b through the oxide 230c. Can be supplied. Further, as with the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250a is reduced. The film thickness of the insulator 250a is preferably 1 nm or more and 20 nm or less.

Further, the insulator 250 is provided not only between the oxide 230b and the conductor 260, but also between the conductor 242 and the conductor 260. If a parasitic capacitance is formed between the conductor 242 and the conductor 260 due to the film thickness required for the insulator 250, which adversely affects the characteristics of the transistor 200 or the semiconductor device, the conductor 242 and the conductor are conductive. It is preferable that the film thickness of the insulator 250 located between the bodies 260 is thicker than the film thickness of the insulator 250 located between the oxide 230b and the conductor 260. For that purpose, the insulator 250a located between the conductor 242 and the conductor 260 may have a two-layer structure, and the insulator 250a located between the oxide 230b and the conductor 260 may have a single-layer structure. For example, an insulating film to be the first insulator is formed inside the oxide film 230C to be the oxide 230c, anisotropic etching is performed on the insulating film, and the first is applied only to the inner wall of the oxide film 230C. Form an insulator. Subsequently, by forming an insulating film to be the second insulator, the insulator 250a located between the oxide 230b and the conductor 260 has a single-layer structure, and is located between the conductor 242 and the conductor 260. The insulator 250a has a two-layer structure. Therefore, the film thickness of the insulator 250a located between the conductor 242 and the conductor 260 can be made thicker than the film thickness of the insulator 250a located between the oxide 230b and the conductor 260.

When silicon oxide, silicon oxynitride, or the like is used for the insulator 250a, it is preferable to use a metal oxide which is a high-k material having a high relative permittivity for the insulator 250b. By forming the gate insulator into a laminated structure of the insulator 250a and the insulator 250b, it is possible to obtain a laminated structure that is stable against heat and has a high relative permittivity. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Further, it is possible to reduce the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

Specifically, the insulator 250b is a metal oxidation containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like. Things can be used.

In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both oxides of aluminum or hafnium. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the thermal history in a later step.

Further, the insulator 250b serves as an etching stopper (also referred to as a sidewall) for protecting the side wall of the conductor 260 when forming an opening for providing the conductor 240 in the insulator 281, the insulator 280, and the insulator 244. It also has the function of. By providing the insulator 250b, it is possible to prevent the conductor 260 from coming into contact with the conductor 240.

Further, by providing the insulator 250b between the insulator 250a and the conductor 260, oxygen contained in the insulator 250a may be efficiently supplied to the oxide 230. The insulator 250b preferably suppresses oxygen diffusion from the insulator 250a. By providing the insulator 250b that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250a to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 by oxygen.

The conductor 260 that functions as the first gate electrode is shown as a two-layer structure in FIG. 1, but may have a single-layer structure or a laminated structure of three or more layers. For example, when the conductor 260 has a two-layer structure, the conductor 260a has a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, and a nitrogen oxide molecule ₍ N2O, NO), similarly to the conductor 205a. , NO ₂ etc.), It is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule).

Since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from being lowered. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.

Further, as the conductor 260b, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductor 260 also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the conductive material.

Further, as shown in FIG. 1C, when the conductor 205 is stretched in a region outside the end portion intersecting the channel width direction of the oxide 230, the conductor 260 is in the region. It is preferable that they are superimposed via the insulator 250. That is, it is preferable that the conductor 205, the insulator 250, and the conductor 260 form a laminated structure on the outside of the side surface of the oxide 230.

By having the above configuration, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a channel formed in the oxide 230. Can cover the area.

That is, the channel forming region of the region 234 can be electrically surrounded by the electric field of the conductor 260 having the function as the first gate electrode and the electric field of the conductor 205 having the function as the second gate electrode. ..

Here, as shown in FIGS. 1B and 1C, it is preferable that the height of the upper surface of the oxide 230c and the insulator 250 substantially coincides with the height of the upper surface of the insulator 280. On the other hand, it is preferable that the upper surface of the conductor 260 is lower than the upper surface of the insulator 280, and the conductor 260 has a recess with respect to the insulator 280.

It is preferable to provide the insulator 272 on the conductor 260 in contact with the side surface of the insulator 250b, and to provide the insulator 273 inside the insulator 272. The insulator 272 and the insulator 273 function as an etching stopper when forming an opening for providing the conductor 240 in the insulator 281, the insulator 280, and the insulator 244. Metal oxidation containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like as the insulator 272 and the insulator 273. Things can be used. Alternatively, silicon nitride such as silicon nitride or silicon nitride can be used.

In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both oxides of aluminum or hafnium. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the thermal history in a later step. For example, aluminum oxide can be used as the insulator 272, and silicon nitride can be used as the insulator 273. Further, it is preferable that the heights of the upper surfaces of the insulator 272 and the insulator 273 substantially match the height of the upper surface of the insulator 280.

The insulator 280 is provided on the insulator 244. Like the insulator 224, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the membrane. The insulator 280 preferably has oxygen. For example, as the insulator 280, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores are used. , Or a resin or the like is preferable. In particular, silicon oxide and silicon nitride nitride are preferable because they are thermally stable.

If the insulator 244 is not provided, the insulator 280 is in contact with the side surfaces of the oxide 230a and the oxide 230b. At this time, oxygen contained in the insulator 280 may be supplied to the region 234 of the oxide 230 by heating. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced.

Further, it is preferable to provide an insulator 281 that functions as an interlayer film on the insulator 280. Like the insulator 224 and the insulator 280, the insulator 281 preferably has a reduced concentration of impurities such as water or hydrogen in the membrane.

Further, the conductor 240 (conductor 240a, conductor 240b, and conductor 240c) electrically connected to the conductor 242 is arranged in the openings formed in the insulator 281, the insulator 280, and the insulator 244. .. At this time, it is preferable to provide an insulator 241 on the side surface of the opening. The insulator 241 preferably has a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator 241, the same materials as the insulator 210, the insulator 214, the insulator 222, the insulator 244, the insulator 250b, the insulator 272, the insulator 273, and the like can be used. Further, as will be described later, in the channel width direction, the insulator 241 may also be formed on the side surfaces of the oxide 230a and the oxide 230b. By providing the insulator 241, oxidation of the conductor 240 can be suppressed. Further, it is possible to suppress the diffusion of hydrogen contained in the insulator 280 and the insulator 281 into the oxide 230 via the conductor 240.

A portion of the opening is formed to have a region overlapping the oxide 230c and the insulator 250. A part of the conductor 240 is in contact with the insulator 241. Further, the conductor 240 may be in contact with any one or more of the oxide 230c, the insulator 250, the insulator 272, and the insulator 273. The upper surface of the conductor 240 may be flush with the upper surface of the insulator 281.

The conductor 240 may have a laminated structure including a first conductor and a second conductor. In this case, the second conductor is provided on the first conductor connected to the conductor 242. Further, it is preferable that the first conductor is provided so as to cover the side surface of the second conductor.

To provide an opening in which the insulator 250b provided on the side surface of the conductor 260, the insulator 272 provided on the conductor 260, and the insulator 273 expose a part of the conductor 242, that is, the conductor 240. Since it functions as an etching stopper when forming the opening of the conductor 260, it is possible to prevent the conductor 260 from coming into contact with the conductor 240.

FIG. 3A shows an example in which the alignment of the mask in the lithography method is deviated in the A1 direction when forming an opening that exposes a part of the conductor 242. Even in such a case, since the insulator 250b, the insulator 272, and the insulator 273 function as etching stoppers, it is possible to prevent the conductor 260 from coming into contact with the conductor 240. Further, since the contact with the conductor 242c is formed in a self-aligned manner, even if the mask is misaligned as shown in FIG. 3A, the contact area between the conductor 242c and the conductor 240c is shown in FIG. The contact area between the conductor 242c and the conductor 240c shown in 1 (B) is equal to that of the conductor 240c, and the contact resistance does not decrease.

Here, FIG. 3B shows a cross-sectional view of the portion shown by the alternate long and short dash line of A5-A6 in FIG. 1A, that is, the source region or drain region of the transistor 200. As shown in FIG. 3B, the conductor 240a (conductor 240b, conductor 240c) is not covered by the insulator 241 and is formed on the upper surface and the side surface of the conductor 242a (conductor 242b, conductor 242c). Contact. Further, when the insulator 241 is not provided on the inner wall of the opening formed in the insulator 281, the insulator 280, and the insulator 244, or the insulator 241 is provided on the side surface of the oxide 230a and the side surface of the oxide 230b. If not, the conductor 240a (conductor 240b, conductor 240c) is in contact with the side surface of the oxide 230b and the side surface of the oxide 230a. Therefore, since the contact area between the conductor 240a (conductor 240b, conductor 240c) and the source region or drain region of the transistor 200 increases, the contact resistance can be reduced, which is preferable. Further, the conductor 240a (conductor 240b) may be configured to be in contact with the side surface on the A1 side (A2 side) on the side surface where the conductor 240a (conductor 240b) intersects the channel length direction of the oxide 230.

Further, FIG. 3C shows a case where the mask alignment in the lithography method is deviated in the A5 direction when forming an opening that exposes a part of the conductor 242a (conductor 242b, conductor 242c). An example is shown. By making the width of the opening larger than the widths of the conductors 242a (conductors 242b, conductors 242c), oxides 230b, and oxides 230a in the channel width direction, even if misalignment occurs, the conductors 242a (Conductor 242b, Conductor 242c) can be in contact with the upper surface and the side surface of the conductor 242a (conductor 242b, conductor 242c) which is not covered by the insulator 241, and good contact is obtained.

As the conductor 240a, the conductor 240b, and the conductor 240c, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor 240a, the conductor 240b, and the conductor 240c may have a laminated structure.

Further, when the conductor 240 has a laminated structure, the first contact with the insulator 230a, the oxide 230b, the conductor 242, the insulator 244, the insulator 280, and the insulator 281 via the insulator 241 or directly. As the conductor, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen, as in the case of the conductor 205a. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide and the like are preferably used. Further, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated manner. By using the conductive material, impurities such as hydrogen and water can be suppressed from being mixed into the oxide 230 from the layer above the insulator 281 through the conductor 240a and the conductor 240b. Further, as the second conductor provided inside the first conductor, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.

Further, although not shown, a conductor that functions as wiring may be arranged in contact with the upper surface of the conductor 240a, the upper surface of the conductor 240b, and the upper surface of the conductor 240c. As the conductor functioning as wiring, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material. The conductor may be formed so as to be embedded in an opening provided in the insulator, similarly to the conductor 203 and the like.

<Constituent materials for semiconductor devices>
Hereinafter, the constituent materials that can be used in the semiconductor device will be described.

<< Board >>
As the substrate on which the transistor 200 is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, and the like. Examples of the semiconductor substrate include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate and the like. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate and the like. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided in an insulator substrate, a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like. Alternatively, those on which an element is provided may be used. Elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.

Further, a flexible substrate may be used as the substrate. As a method of providing the transistor on the flexible substrate, there is also a method of forming the transistor on the inflexible substrate, peeling off the transistor, and transposing it to the substrate which is a flexible substrate. In that case, it is advisable to provide a release layer between the inflexible substrate and the transistor. Further, the substrate may have elasticity. Further, the substrate may have a property of returning to the original shape when bending or pulling is stopped. Alternatively, it may have a property that does not return to the original shape. The substrate has, for example, a region having a thickness of 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. By thinning the substrate, the weight of the semiconductor device having a transistor can be reduced. Further, by making the substrate thinner, it may have elasticity even when glass or the like is used, or it may have a property of returning to the original shape when bending or pulling is stopped. Therefore, it is possible to alleviate the impact applied to the semiconductor device on the substrate due to dropping or the like. That is, it is possible to provide a durable semiconductor device.

As the substrate which is a flexible substrate, for example, metal, alloy, resin or glass, fibers thereof, or the like can be used. Further, as the substrate, a sheet, a film, a foil or the like in which fibers are woven may be used. A substrate that is a flexible substrate is preferable because the lower the coefficient of linear expansion, the more the deformation due to the environment is suppressed. As the substrate which is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ^-3 / K or less, 5 × 10 ^-5 / K or less, or 1 × 10 ^-5 / K or less may be used. .. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic and the like. In particular, aramid has a low coefficient of linear expansion and is therefore suitable as a substrate that is a flexible substrate.

<< Insulator >>
Examples of the insulator include oxides having insulating properties, nitrides, nitride oxides, nitride oxides, metal oxides, metal oxide nitrides, metal nitride oxides and the like.

For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as a gate insulator, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material having a low relative permittivity for the insulator that functions as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. Therefore, the material may be selected according to the function of the insulator.

Examples of the insulator having a high specific dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, nitride oxides having aluminum and hafnium, oxides having silicon and hafnium, silicon and hafnium. There are nitrides having oxides, or nitrides having silicon and hafnium.

Examples of the insulator having a low relative permittivity include silicon oxide, silicon oxide, silicon oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and empty. There are silicon oxide with pores, resin, and the like.

In particular, silicon oxide and silicon nitride nitride are thermally stable. Therefore, for example, by combining with a resin, a laminated structure that is thermally stable and has a low relative permittivity can be obtained. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like. Further, for example, silicon oxide and silicon oxide nitride can be combined with an insulator having a high relative permittivity to form a laminated structure that is thermally stable and has a high relative permittivity.

Further, the transistor using the oxide semiconductor can stabilize the electrical characteristics of the transistor by surrounding the transistor with an insulator having a function of suppressing the permeation of impurities such as hydrogen and water and oxygen.

Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and water and oxygen include boron, carbon, nitrogen, oxygen, fluorine, phosphorus, chlorine, argon, silicon, aluminum, hafnium, magnesium, gallium, and germanium. Insulations containing, ittrium, zirconium, lanthanum, neodymium, tungsten, titanium, tantalum, or nickel may be used in a single layer or in a laminate. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, etc. Metal oxides such as tungsten oxide, titanium oxide, tantalum oxide, or nickel oxide, and silicon nitrides such as silicon nitride or silicon nitride can be used.

For example, as the insulator 250b, the insulator 272, and the insulator 273, one selected from aluminum, hafnium, magnesium, gallium, germanium, ittrium, zirconium, lantern, neodymium, tungsten, titanium, tantalum, or nickel, or A metal oxide containing two or more kinds can be used. Further, a nitride of silicon or a nitride of silicon containing oxygen, that is, silicon nitride, silicon nitride oxide, or the like can be used.

The insulator 250b, the insulator 272, and the insulator 273 act as an etching stopper when forming openings in the insulator 244, the insulator 280, and the insulator 281, so that the insulator 244, the insulator 280, and the insulator 280, It is preferable to use a material having an etching rate different from the etching rate in the processing of the insulator 281.

For example, the insulator 250a and the insulator 224 that function as a part of the gate insulator are preferably insulators having oxygen. For example, by forming the structure in which silicon oxide or silicon oxide having oxygen is in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated.

Further, for example, in the insulator 222 that functions as a part of the gate insulator, an insulator containing one or more oxides of aluminum, hafnium, and gallium can be used. In particular, as an insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and the like.

By adopting the above-mentioned laminated structure, it is possible to improve the on-current without weakening the influence of the electric field from the gate electrode. In addition, the physical thickness of the gate insulator keeps the distance between the gate electrode and the region where the channel is formed, so that the leakage current between the gate electrode and the channel formation region can be suppressed. ..

The insulator 212, the insulator 216, the insulator 280, and the insulator 281 preferably have a single layer or a laminate of insulators having a low relative permittivity. For example, the insulator 212, the insulator 216, the insulator 280, and the insulator 281 include silicon oxide, silicon oxide, silicon oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon, and the like. It is preferable to have silicon oxide to which nitrogen is added, silicon oxide having pores, a resin, or the like. Alternatively, the insulator 212, the insulator 216, the insulator 280, and the insulator 281 are silicon oxide, silicon oxide, silicon oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon, and the like. It is preferable to have a laminated structure of silicon oxide to which nitrogen is added, silicon oxide having pores, and a resin. Since silicon oxide and silicon oxide nitride are thermally stable, they can be combined with a resin to form a laminated structure that is thermally stable and has a low relative permittivity. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.

As the insulator 210, the insulator 214, the insulator 244, and the insulator 241, an insulator having a function of suppressing the permeation of impurities such as hydrogen and water and oxygen may be used. The insulator 210, the insulator 214, the insulator 244, and the insulator 241 include, for example, aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and oxidation. Metal oxides such as tungsten, titanium oxide, tantalum oxide, or nickel oxide, silicon nitride, silicon nitride, and the like may be used.

<< Conductor >>
Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, berylium, indium, ruthenium, iridium, strontium, and lanthanum. A material containing at least one kind of metal element selected from the above can be used. Further, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and a silicide such as nickel silicide may be used.

Further, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

When an oxide is used in the channel forming region of the transistor, a laminated structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined is used for the conductor functioning as a gate electrode. Is preferable. In this case, a conductive material containing oxygen may be provided on the channel forming region side. By providing the conductive material containing oxygen on the channel forming region side, oxygen separated from the conductive material can be easily supplied to the channel forming region.

In particular, as the conductor that functions as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed. Further, the above-mentioned conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium zinc oxide may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen mixed in from an outer insulator or the like.

The conductors 260, 203, 205, 242, and 240 include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, and niobium. , Manganese, magnesium, zirconium, berylium, indium, ruthenium, iridium, strontium, lanthanum, or an alloy containing the above-mentioned metal element as a component, or an alloy containing the above-mentioned metal element can be used. preferable. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even if it absorbs oxygen. Further, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and a silicide such as nickel silicide may be used.

<< Metal Oxide >>
As the oxide 230, it is preferable to use a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor. Hereinafter, the metal oxide applicable to the oxide 230 according to the present invention will be described.

The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, aluminum, gallium, yttrium, tin and the like are preferably contained. Further, one or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like may be contained.

Here, consider the case where the metal oxide is an In—M—Zn oxide having indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like. However, as the element M, a plurality of the above-mentioned elements may be combined in some cases.

In addition, in this specification and the like, a metal oxide having nitrogen may also be generically referred to as a metal oxide. Further, the metal oxide having nitrogen may be referred to as a metal oxynitride.

[Composition of metal oxide]
Hereinafter, the configuration of the CAC (Cloud-Aligned Company) -OS that can be used for the transistor disclosed in one aspect of the present invention will be described.

In addition, in this specification and the like, it may be described as CAAC (c-axis aligned composite) and CAC (Cloud-Aligned Composite). In addition, CAAC represents an example of a crystal structure, and CAC represents an example of a function or a composition of a material.

The CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in a part of the material, and a semiconductor function as a whole of the material. When CAC-OS or CAC-metal oxide is used for the semiconductor layer of the transistor, the conductive function is the function of flowing electrons (or holes) to be carriers, and the insulating function is the carrier. It is a function that does not allow electrons to flow. By making the conductive function and the insulating function act in a complementary manner, a switching function (on / off function) can be imparted to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

Further, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Further, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

Further, in CAC-OS or CAC-metal oxide, when the conductive region and the insulating region are dispersed in the material in a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively. There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In the case of this configuration, when the carrier is flown, the carrier mainly flows in the component having a narrow gap. Further, the component having a narrow gap acts complementarily to the component having a wide gap, and the carrier flows to the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel forming region of the transistor, a high current driving force, that is, a large on-current and a high field effect mobility can be obtained in the on state of the transistor.

That is, the CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[Structure of metal oxide]
Oxide semiconductors (metal oxides) are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (c-axis aligned crystal linear semiconductor), polycrystal oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudo-amorphous oxide semiconductor (a-lik). OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

CAAC-OS has a c-axis orientation and has a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have strain. The strain refers to a region where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned in the region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagonal shapes and may have non-regular hexagonal shapes. In addition, in distortion, it may have a lattice arrangement such as a pentagon and a heptagon. In CAAC-OS, it is difficult to confirm a clear grain boundary (also referred to as grain boundary) even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and that the bond distance between atoms changes due to the substitution of metal elements. Because.

Further, CAAC-OS is a layered crystal in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are laminated. It tends to have a structure (also called a layered structure). Indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as a (In, M, Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can also be expressed as a (In, M) layer.

CAAC-OS is a highly crystalline metal oxide. On the other hand, in CAAC-OS, it is difficult to confirm a clear grain boundary, so it can be said that the decrease in electron mobility due to the crystal grain boundary is unlikely to occur. Further, since the crystallinity of the metal oxide may be deteriorated due to the mixing of impurities or the generation of defects, CAAC-OS is a metal having few impurities and defects (oxygen deficiency (VO: _oxygen vacancy), etc.). It can also be called an oxide. Therefore, the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide having CAAC-OS is resistant to heat and has high reliability.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.

Indium-gallium-zinc oxide (hereinafter referred to as IGZO), which is a kind of metal oxide having indium, gallium, and zinc, may have a stable structure by forming the above-mentioned nanocrystals. be. In particular, since IGZO tends to have difficulty in crystal growth in the atmosphere, it is better to use smaller crystals (for example, the above-mentioned nanocrystals) than large crystals (here, a few mm crystal or a few cm crystal). However, it may be structurally stable.

The a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

Oxide semiconductors (metal oxides) have various structures, and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[Transistor with metal oxide]
Subsequently, a case where the metal oxide is used in the channel forming region of the transistor will be described.

By using the metal oxide in the channel forming region of the transistor, a transistor having high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.

Further, it is preferable to use a metal oxide having a low carrier density for the transistor. When the carrier density of the metal oxide film is lowered, the impurity concentration in the metal oxide film may be lowered to lower the defect level density. In the present specification and the like, a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, metal oxides have a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ^-9 /. It may be cm ³ or more.

Further, since the metal oxide film having high purity intrinsicity or substantially high purity intrinsicity has a low defect level density, the trap level density may also be low.

In addition, the charge captured at the trap level of the metal oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor having a metal oxide having a high trap level density in the channel forming region may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the metal oxide. Further, in order to reduce the impurity concentration in the metal oxide, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

[impurities]
Here, the influence of each impurity in the metal oxide will be described.

When silicon or carbon, which is one of the Group 14 elements, is contained in the metal oxide, a defect level is formed in the metal oxide. Therefore, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon near the interface with the metal oxide (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

Further, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal in the channel forming region tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

Further, in the metal oxide, when nitrogen is contained, electrons which are carriers are generated, the carrier density is increased, and it is easy to form an n-type. As a result, a transistor using a metal oxide containing nitrogen in the channel forming region tends to have a normally-on characteristic. Therefore, in the metal oxide, it is preferable that the nitrogen in the channel forming region is reduced as much as possible. For example, the nitrogen concentration in the metal oxide is 5 × 10 ¹⁹ atoms / cm ³ or less, preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and more preferably 1 × 10 18 atoms / cm 3 or less in SIMS. It is preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency. When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using a metal oxide containing hydrogen tends to have a normally-on characteristic.

Further, hydrogen contained in the metal oxide may form shallow defect levels (sDOS: shallow level Density of States) in the metal oxide. The shallow defect level refers to the interface state located near the lower end of the conduction band. It is presumed that the shallow defect level exists near the boundary between the high-density region and the low-density region in the metal oxide. Here, the high-density region and the low-density region in the metal oxide are distinguished by the amount of hydrogen contained in the region. That is, the high-density region is a region containing a larger amount of hydrogen as compared with the low-density region. In the vicinity of the boundary between the high-density region and the low-density region in the metal oxide, minute cracks are likely to occur due to the stress strain between the two regions, and oxygen deficiency and indium dungling bonds occur in the vicinity of the cracks. It is presumed that shallow defect levels are formed by the localization of impurities such as hydrogen or water.

Further, the high-density region in the metal oxide may have higher crystallinity than the low-density region. Further, the high-density region in the metal oxide may have a higher film density than the low-density region. When the metal oxide has a composition of indium, gallium, and zinc, the high-density region contains indium, gallium, and zinc, and the low-density region contains indium and zinc. May have. In other words, the low density region may have a lower percentage of gallium than the high density region.

The shallow defect level is presumed to be due to oxygen deficiency. It is estimated that as the oxygen deficiency in the metal oxide increases, the deep defect levels (dDOS: deep level Density of States) increase as well as the shallow defect levels. This is because the deep defect level is also considered to be due to oxygen deficiency. The deep defect level refers to a defect level located near the center of the band gap.

Therefore, by suppressing oxygen deficiency in the metal oxide, it is possible to reduce both the shallow defect level and the deep defect level. Further, the shallow defect level may be controlled to some extent by adjusting the temperature at the time of film formation of the metal oxide. Specifically, the shallow defect level can be reduced by setting the temperature at the time of film formation of the metal oxide to 170 ° C. or its vicinity, preferably 130 ° C. or its vicinity, and more preferably room temperature.

Further, the shallow defect level of the metal oxide affects the electrical characteristics of the transistor using the metal oxide in the semiconductor layer. That is, due to the shallow defect level, the change of the drain current Id with respect to the gate voltage Vg becomes gradual in the drain current-gate voltage (Id-Vg) characteristic of the transistor, and the rising or bad characteristics of the rising state of the transistor from the off state to the on state are good or bad. The S value (also referred to as Subthreshold Swing, SS), which is one of the criteria for the above, deteriorates. This is thought to be because the electrons were trapped in the shallow defect level.

Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in metal oxides, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . By using a metal oxide having sufficiently reduced impurities in the channel forming region of the transistor, stable electrical characteristics can be imparted.

<Method of manufacturing semiconductor devices>
Next, the manufacturing method of the semiconductor device having the transistor 200 according to the present invention will be described with reference to FIGS. 4 to 14. Further, in FIGS. 4 to 14, (A) in each figure shows a top view. Further, (B) in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200. Further, (C) in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200. In the top view of (A) in each figure, some elements are omitted for the purpose of clarifying the figure.

First, a substrate (not shown) is prepared, and an insulator 210 is formed on the substrate. The film formation of the insulator 210 is performed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or a pulsed laser deposition (PLD) method. It can be performed by using the (Atomic Layer Deposition) method or the like.

The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. .. Further, it can be divided into a metal CVD (Metal CVD) method and an organometallic CVD (MOCVD: Metalorganic CVD) method depending on the raw material gas used.

In particular, the ALD method has excellent step covering property and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively slow film forming speed, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming speed.

In the present embodiment, aluminum oxide is formed as the insulator 210 by a sputtering method. Further, the insulator 210 may have a multi-layer structure. For example, the structure may be such that aluminum oxide is formed by a sputtering method and aluminum oxide is formed on the aluminum oxide by an ALD method. Alternatively, the structure may be such that aluminum oxide is formed by the ALD method and aluminum oxide is formed on the aluminum oxide by the sputtering method.

Next, the insulator 212 is formed on the insulator 210. The film formation of the insulator 212 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxide or silicon oxide is formed as the insulator 212 by the CVD method.

Next, the insulator 212 is formed with an opening that reaches the insulator 210. The opening also includes, for example, a groove or a slit. Further, the area where the opening is formed may be referred to as an opening. Although a wet etching method may be used for forming the openings, it is preferable to use a dry etching method for microfabrication. Further, as the insulator 210, it is preferable to select an insulator that functions as an etching stopper when the insulator 212 is etched to form an opening. For example, when silicon oxide is used for the insulator 212 forming the opening, the insulator 210 may use silicon nitride, aluminum oxide, or hafnium oxide as the insulator that functions as an etching stopper.

After forming the opening, a conductive film to be a conductor 203a is formed. The conductive film preferably contains a conductor having a function of suppressing the permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride and the like can be used. Alternatively, it can be a laminated film with tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The film formation of the conductive film to be the conductor 203a can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In the present embodiment, as the conductive film to be the conductor 203a, tantalum nitride or a film in which titanium nitride is laminated on tantalum nitride is formed by a sputtering method. By using such a metal nitride as the conductor 203a, even if a metal such as copper, which is easily diffused, is used in the conductor 203b described later, it is possible to suppress the metal from diffusing out from the conductor 203a. ..

Next, a conductive film to be the conductor 203b is formed on the conductive film to be the conductor 203a. The film formation of the conductive film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, a low resistance conductive material such as copper is formed as a conductive film to be the conductor 203b.

Next, by performing the CMP treatment, a part of the conductive film to be the conductor 203a and a part of the conductive film to be the conductor 203b is removed, and the insulator 212 is exposed. As a result, the conductive film to be the conductor 203a and the conductive film to be the conductor 203b remain only in the opening. As a result, the conductor 203 including the conductor 203a and the conductor 203b having a flat upper surface can be formed (see FIG. 5). In addition, a part of the insulator 212 may be removed by the CMP treatment.

Next, the insulator 214 is formed on the insulator 212 and the conductor 203. The film formation of the insulator 214 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon nitride is formed as the insulator 214 by the CVD method. As described above, by using an insulator such as silicon nitride that is difficult for copper to permeate as the insulator 214, even if a metal that easily diffuses such as copper is used for the conductor 203b, the metal is a layer above the insulator 214. It can be suppressed from spreading to.

Next, the insulator 216 is formed on the insulator 214. The film formation of the insulator 216 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxide or silicon oxide is formed as the insulator 216 by the CVD method.

Next, an opening reaching the conductor 203 is formed in the insulator 214 and the insulator 216. Although a wet etching method may be used for forming the openings, it is preferable to use a dry etching method for microfabrication.

After forming the opening, a conductive film to be a conductor 205a is formed. The conductive film preferably contains a conductive material having a function of suppressing the permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride and the like can be used. Alternatively, it can be a laminated film with tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The film formation of the conductive film to be the conductor 205a can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In the present embodiment, tantalum nitride is formed as a conductive film to be the conductor 205a by a sputtering method.

Next, a conductive film to be the conductor 205b is formed on the conductive film to be the conductor 205a. The film formation of the conductive film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In the present embodiment, titanium nitride is formed as a conductive film to be the conductor 205b by the CVD method, and tungsten is formed on the titanium nitride by the CVD method.

Next, by performing the CMP treatment, a part of the conductive film to be the conductor 205a and a part of the conductive film to be the conductor 205b is removed, and the insulator 216 is exposed. As a result, the conductive film to be the conductor 205a and the conductor 205b remains only in the opening. As a result, the conductor 205 including the conductor 205a and the conductor 205b having a flat upper surface can be formed (see FIG. 5). In addition, a part of the insulator 216 may be removed by the CMP treatment.

Next, the insulator 222 is formed on the insulator 216 and the conductor 205. As the insulator 222, it is preferable to form an insulator containing an oxide of one or both of aluminum and hafnium. As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and the like. Insulators containing oxides of one or both of aluminum and hafnium have barrier properties against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 200 are suppressed from diffusing into the inside of the transistor 200 through the insulator 222. , The formation of oxygen deficiency in the oxide 230 can be suppressed.

The film formation of the insulator 222 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The film formed by using the ALD method has good coverage. On the other hand, it is preferable to use the sputtering method because a film having a reduced hydrogen concentration can be formed as compared with using other methods. It should be selected according to the characteristics required for the device.

Next, the insulator 224 is formed on the insulator 222. The film formation of the insulator 224 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxide is formed as the insulator 224 by using a sputtering method. Further, silicon oxide or silicon nitride may be formed into a film by a CVD method.

Subsequently, it is preferable to perform heat treatment. The heat treatment may be performed at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, and more preferably 320 ° C. or higher and 450 ° C. or lower. The heat treatment is carried out in an atmosphere of nitrogen or an inert gas, or an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more. Further, the heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas to supplement the desorbed oxygen after the heat treatment in a nitrogen or inert gas atmosphere. good.

In the present embodiment, as the heat treatment, after the film formation of the insulator 224 is formed, the treatment is performed in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour. By the heat treatment, impurities such as hydrogen and water contained in the insulator 224 can be removed.

Further, the heat treatment can also be performed after the film formation of the insulator 222 is performed. For the heat treatment, the above-mentioned heat treatment conditions can be used.

Here, in order to contain a large amount of oxygen in the insulator 224, plasma treatment containing oxygen may be performed in a reduced pressure state. For plasma treatment containing oxygen, for example, it is preferable to use an apparatus having a power source for generating high-density plasma using microwaves. Alternatively, a power source for applying RF (Radio Frequency) may be provided on the substrate side. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224. can. Alternatively, plasma treatment containing an inert gas may be performed using this apparatus, and then plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. By appropriately selecting the conditions for the plasma treatment, impurities such as hydrogen and water contained in the insulator 224 can be removed. In that case, the heat treatment may not be performed.

Next, the oxide film 230A and the oxide film 230B are sequentially formed on the insulator 224 (see FIG. 4). It is preferable that the oxide film is continuously formed without being exposed to the atmospheric environment. By forming the film without opening it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.

The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, when the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film formed can be increased. Further, when the above oxide film is formed by a sputtering method, for example, an In—M—Zn oxide target can be used.

In particular, it is preferable that the oxide film 230A contains more oxygen. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.

Further, when the oxide film 230B is formed by a sputtering method, if the ratio of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. It is formed. Transistors using oxygen-deficient oxide semiconductors in the channel formation region can obtain relatively high field-effect mobilities.

In the present embodiment, as the oxide film 230A, a film is formed by a sputtering method using a target of In: Ga: Zn = 1: 3: 4 or 1: 1: 0.5 [both have an atomic number ratio]. be able to. Further, the oxide film 230B is formed by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1, 5: 1: 6, or 1: 1: 1 [both have an atomic number ratio]. Can be filmed. Each oxide film may be formed according to the characteristics required for the oxide 230 by appropriately selecting the film forming conditions and the atomic number ratio.

Next, heat treatment may be performed. For the heat treatment, the above-mentioned heat treatment conditions can be used. By heat treatment, impurities such as hydrogen and water in the oxide film 230A and the oxide film 230B can be removed. In the present embodiment, after the treatment is performed in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour, the treatment is continuously performed in an oxygen atmosphere at a temperature of 400 ° C. for 1 hour.

Next, the conductive film 242A is formed on the oxide film 230B (see FIG. 4). The conductive film 242A contains aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, berylium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even if it absorbs oxygen. The conductive film 240A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the conductive film 242A is processed to form a hard mask for processing the oxide film 230A and the oxide film 230B.

The conductive film 242A may be processed by using a lithography method. Further, a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for microfabrication.

In the lithography method, the resist is first exposed through a mask. Next, the exposed area is removed or left with a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching the resist mask. For example, a resist mask may be formed by exposing the resist with KrF excimer laser light, ArF excimer laser light, UV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the above-mentioned light, an electron beam or an ion beam may be used. When an electron beam or an ion beam is used, the above-mentioned mask for resist exposure is not required because the drawing is performed directly on the resist. The resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process. ..

Next, a conductor 242B that functions as a hard mask is formed by etching the conductive film 242A using a resist mask (see FIG. 5). After forming the conductor 242B, the resist mask may be removed and then the oxide film may be processed, or the resist mask may be left as it is. In the latter case, the resist mask may disappear during etching.

As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate type electrodes can be used. The capacitive coupling type plasma etching apparatus having a parallel plate type electrode may be configured to apply a high frequency power source to one of the parallel plate type electrodes. Alternatively, a plurality of different high frequency power supplies may be applied to one of the parallel plate type electrodes. Alternatively, a high frequency power supply having the same frequency may be applied to each of the parallel plate type electrodes. Alternatively, a high frequency power supply having a different frequency may be applied to each of the parallel plate type electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

Next, using the conductor 242B as a hard mask, the oxide film 230A and the oxide film 230B are processed into an island shape to form the oxide 230a and the oxide 230b (see FIG. 5). In addition, a part of the insulator 224 may be removed by the processing. After etching the oxide film, the conductor 242B that functions as a hard mask may be removed by etching, but in the present embodiment, the conductor 242B is further processed to function as a source electrode and a drain electrode. The conductor 242B is not removed in order to form the conductor 242B.

Here, the oxide 230a and the oxide 230b are formed so that at least a part thereof overlaps with the conductor 205. Further, it is preferable that the side surfaces of the oxide 230a and the oxide 230b have a tapered shape with respect to the upper surface of the insulator 222 or the upper surface of the substrate. The side surfaces of the oxide 230a and the oxide 230b have a tapered shape with respect to the upper surface of the insulator 222 or the upper surface of the substrate, so that a film is formed on the side surfaces of the oxide 230a and the oxide 230b in a subsequent step. , Or the film formed on the side surface can be easily removed.

Further, it has a curved surface between the side surface of the oxide 230a, the oxide 230b, and the conductor 242B and the upper surface of the conductor 242B. That is, it is preferable that the end portion of the side surface and the end portion of the upper surface are curved (hereinafter, also referred to as a round shape). The curved surface has, for example, a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less at the end of the oxide 230b. By having no corners at the ends, the coverage of the film in the subsequent film forming process is improved.

For the processing of the oxide film, the conductor 242B can be used as a hard mask, and a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for microfabrication.

Further, by performing the above-mentioned dry etching or the like, impurities caused by the etching gas or the like may adhere to or diffuse to the side surface or the inside of the oxide 230a and the oxide 230b. Impurities include, for example, fluorine or chlorine.

Cleaning is performed to remove the above impurities and the like. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be appropriately combined.

As the wet cleaning, the cleaning treatment may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrogen peroxide solution, hydrofluoric acid or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning may be performed using pure water or carbonated water. In this embodiment, ultrasonic cleaning is performed using pure water or carbonated water.

Subsequently, heat treatment may be performed. As the heat treatment conditions, the above-mentioned heat treatment conditions can be used. However, when there is concern about oxidation of the conductor 242B due to the heat treatment, it is preferable that the heat treatment is performed in an atmosphere containing no oxygen. On the other hand, when the conductor 242B contains an oxidation resistant material, the heat treatment may be performed in an atmosphere containing oxygen.

Next, the insulator 244 is formed on the insulator 224, the oxide 230a, the oxide 230b, and the conductor 242B (see FIG. 6). The insulator 244 preferably functions as an insulating barrier, and includes aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tungsten oxide, and titanium oxide. It is preferable to form an insulator containing tantalum oxide, a metal oxide such as nickel oxide, silicon nitride or silicon nitride, and the like. Further, as an insulator containing both aluminum and hafnium, an oxide containing aluminum and hafnium (hafnium aluminate) or the like can be used. Oxidation of the conductor 242B can be suppressed by the insulator 244 having a barrier property. When the conductor 242B contains an oxidation resistant material, the insulator 244 does not necessarily have to be provided. The film of the insulator 244 can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the insulator 280 is formed on the insulator 244. The insulator 280 preferably has an insulator having a low relative permittivity. For example, silicon oxide, silicon oxide, silicon oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with carbon and nitrogen, silicon oxide with pores, or resin. It is preferable to have. Further, silicon oxide and silicon nitride nitride are preferable because they are thermally stable. The film formation of the insulator 280 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, it can be performed by using a spin coating method, a dip method, a droplet ejection method (inkjet method, etc.), a printing method (screen printing, offset printing, etc.), a doctor knife method, a roll coater method, a curtain coater method, or the like. .. In the present embodiment, silicon oxide is formed as an insulator 280 by a sputtering method. It is preferable to use the sputtering method because the hydrogen concentration in the insulator 280 can be reduced. Further, silicon oxide may be formed into a film by a CVD method. It is preferable to use the CVD method because the insulator 280 can be formed with good coverage.

The insulator 280 is preferably formed so that the upper surface has flatness. For example, the upper surface of the insulator 280 may have a flat surface immediately after the film is formed. Alternatively, for example, the insulator 280 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to the reference surface such as the back surface of the substrate after the film formation. Such a process may be referred to as a flattening process, and the obtained film may be referred to as a flattening film. The flattening treatment includes a CMP treatment, a dry etching treatment, and the like. In this embodiment, the CMP process is used as the flattening process. However, the upper surface of the insulator 280 does not necessarily have to have flatness.

Next, a hard mask 246 is formed on the insulator 280 (see FIG. 6). The hard mask 246 may function as a hard mask when etching the insulator 280, the insulator 244, and the conductor 242B in a subsequent step, and can be formed by the conductor or the insulator. In the present embodiment, since the hard mask 246 is etched and removed in the processing of the conductor 242B, the hard mask 246 is preferably a conductor, and is preferably made of the same material as the conductor 242B.

Next, using the hard mask 246, the insulator 280, the insulator 244, and the conductor 242B are processed so as to have a region overlapping with the conductor 205 at least, and an opening 245 is formed (FIG. 7). reference.). Although a wet etching method may be used for forming the openings, it is preferable to use a dry etching method because fine processing is possible and the side surface of the insulator 280 can be processed substantially vertically. Further, by processing the conductor 242B, the conductor 242 (conductor 242a, conductor 242b, and conductor 242c) is formed. The processing exposes the sides of the oxide 230a, the top and sides of the oxide 230b, and a portion of the surface of the insulator 224. In addition, a part of the insulator 224 may be etched by the processing, and a part of the insulator 222 may be exposed. It is also preferable that the hard mask 246 is also removed by the processing. On the other hand, the hard mask 246 may remain on the insulator 280, and in that case, it may be removed in the polishing step of the insulator 272A and the insulator 272B in the subsequent step.

The cross section of the surface where the conductor 242a and the conductor 242c, and the conductor 242b and the conductor 242c face each other may have a tapered shape. On the other hand, the cross section may have a substantially vertical shape.

The conductor 260 formed in the subsequent step is self-aligned in the opening 245.

Here, it is preferable to perform heat treatment. The heat treatment may be performed at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, and more preferably 320 ° C. or higher and 450 ° C. or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere. On the other hand, when the conductor 242 is a conductor having oxidation resistance, the heat treatment may be performed in an atmosphere containing oxygen. Further, the heat treatment may be performed in a reduced pressure state. For example, as a heat treatment, a treatment is performed in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour.

By the heat treatment, impurities such as hydrogen and water contained in the oxide 230a and the oxide 230b can be removed. Further, the damage caused to the oxide 230a or the oxide 230b by the dry etching in the above processing can be recovered. Further, when the heat treatment is performed in an atmosphere containing oxygen, oxygen can be added to the oxide 230a and the oxide 230b.

Further, by the heat treatment, the above-mentioned metal element may be diffused from the conductor 242 to the oxide 230, and the metal element may be added to the oxide 230. In addition, oxygen near the interface of the oxide 230 with the conductor 242 may be absorbed by the conductor 242. As a result, the vicinity of the interface of the oxide 230 with the conductor 242 becomes a metal compound, and the resistance is lowered. At that time, a part of the oxide 230 and the above-mentioned metal element may be alloyed. When a part of the oxide 230 and the metal element are alloyed, the metal element added to the oxide 230 becomes a relatively stable state, so that a highly reliable semiconductor device can be provided. In FIG. 7B, as an example of the low resistance region of the oxide 230, the region 231 (region 231a, region 231b, and region 231c) is shown by a dotted line.

The region 231 shows an example in which the oxide 230b is provided so as to diffuse in the depth direction and the horizontal direction in the vicinity of the conductor 242, but the present invention is not limited to this. The region 231 may be formed on the entire oxide 230b or may be formed on the oxide 230a in the depth direction. Further, the region 231 shows an example in which the region 231 is formed in a region diffused horizontally from the conductor 242 in the horizontal direction, but the present invention is not limited to this. The region 231 may be formed only in a region overlapping the conductor 242, or may be formed in a region overlapping a part of the conductor 260 formed in a later step.

Further, it is considered that the hydrogen in the oxide 230 diffuses into the region 231 and becomes a relatively stable state when it enters the oxygen deficiency existing in the region 231. Further, the hydrogen in the oxygen deficiency existing in the region 234 escapes from the oxygen deficiency by the heat treatment at 250 ° C. or higher, diffuses into the region 231 and enters the oxygen deficiency existing in the region 231 to be in a relatively stable state. It is considered to be. Therefore, it is considered that the region 231 has a lower resistance and the region 234 has a higher purity (reduction of impurities such as water and hydrogen) and a higher resistance by the heat treatment.

Further, after the heat treatment in a nitrogen or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of the oxidizing gas. The heat treatment may be performed at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, and more preferably 320 ° C. or higher and 450 ° C. or lower.

In the heat treatment after the film formation of the conductive film 242A or the formation of the conductor 242, the oxygen in the region 231 of the oxide 230 is absorbed by the conductive film 242A or the conductor 242, so that the region 231 becomes the region 231. Oxygen deficiency may occur. When hydrogen in the oxide 230 enters the oxygen deficiency, the carrier density of the region 231 increases. Therefore, the region 231 of the oxide 230 becomes n-type, and the resistance is reduced.

The oxygen concentration in region 231 may be lower than the oxygen concentration in region 234. Further, the hydrogen concentration in the region 231 may be higher than the oxygen concentration in the region 234.

Next, the insulation is provided so as to have a region in the opening 245 that is in contact with the side surface of the oxide 230a, the upper surface of the oxide 230b, and the side surface, the side surface of the conductor 242, the side surface of the insulator 244, and the side surface of the insulator 280. An oxide film 230C is formed on the body 280 (see FIG. 8).

The oxide film 230C can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C may be formed by using the same film forming method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide 230c. In the present embodiment, as the oxide film 230C, a film is formed by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 or 1: 3: 4 [both have an atomic number ratio]. be able to.

The oxide film 230C may be laminated. For example, by a sputtering method, a film is formed using a target of In: Ga: Zn = 4: 2: 4.1 [atomic number ratio], and In: Ga: Zn = 1: 3: 4 [atomic number ratio] is continuously formed. A film may be formed using a target of [number ratio].

Subsequently, an insulator 250A is formed on the oxide film 230C (see FIG. 8).

The insulator 250A can be formed into a film by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 250A, it is preferable to form silicon oxide nitride by a CVD method. The film forming temperature when forming the insulator 250A is preferably 350 ° C. or higher and lower than 450 ° C., particularly preferably around 400 ° C. By forming the insulator 250A at 400 ° C., it is possible to form an insulator having few impurities.

By exciting oxygen with microwaves to generate high-density oxygen plasma and exposing the insulator 250A to the oxygen plasma, oxygen can be introduced into the insulator 250A.

Moreover, you may perform heat treatment. For the heat treatment, the above-mentioned heat treatment conditions can be used. By the heat treatment, the water concentration and the hydrogen concentration of the insulator 250A can be reduced.

Next, the insulator 250B is formed on the insulator 250A (see FIG. 8). The insulator 250b obtained by processing the insulator 250B functions as an etching stopper when forming openings in the insulator 281, the insulator 280, and the like in a later step. Further, the insulator 250B preferably functions as an insulating barrier. As the insulator 250B, metal oxides such as aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tungsten oxide, titanium oxide, tantalum oxide, or nickel oxide, It is advisable to form an insulator containing silicon nitride oxide, silicon nitride, or the like. Further, as an insulator containing both aluminum and hafnium, an oxide containing aluminum and hafnium (hafnium aluminate) or the like can be used. By using an insulating barrier as the insulator 250B, it is possible to suppress the oxidation of the conductor 260 that functions as a gate electrode, which is formed in a later step. On the other hand, if the conductor 260 is made of an oxidation-resistant material, or if it is a material whose conductivity does not significantly decrease even if it absorbs oxygen, the insulator 250B needs to have an insulating barrier function. There is no.

Here, as a means for forming the insulator 250B, oxygen can be introduced into the insulator 250A while forming the insulator 250B by forming the film in an oxygen gas atmosphere using a sputtering device. can. Alternatively, the insulator 250B may be formed on the side surface of the insulator 250A by using the ALD method having good coverage.

Subsequently, the conductive film 260A and the conductive film 260B are sequentially formed (see FIG. 8). The conductive film 260A and the conductive film 260B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Titanium nitride may be formed as the conductive film 260A, and tungsten may be formed as the conductive film 260B.

As the conductive film 260A, a metal nitride may be formed by a CVD method or a sputtering method. By using a metal nitride for the conductive film 260A, it is possible to prevent the conductive film 260B from being oxidized by the oxygen contained in the insulator 250A or the insulator 250B and the conductivity from being lowered.

Further, by laminating a low resistance metal film as the conductive film 260B, it is possible to provide a transistor having a small drive voltage.

Subsequently, heat treatment can be performed. For the heat treatment, the above-mentioned heat treatment conditions can be used. In some cases, the heat treatment may not be performed. By this heat treatment, oxygen is added from the insulator 250B to the insulator 250A, and the oxygen concentration contained in the insulator 250A can be increased. Further, the present heat treatment may form a low resistance region (region 231) in the oxide 230b.

When the conductive film 260B is formed by using a CVD method (metal CVD method), the conductive film 260B may have irregularities (roughness) on its surface. Therefore, it is preferable to perform a flattening treatment on the surface of the conductive film 260B (see FIG. 9). For the flattening treatment, a method of polishing the conductive film 260B by the CMP method can be used. FIG. 9 shows an example in which only the surface of the conductive film 260B is polished and flattened, but the present invention is not limited to this. The conductive film 260B may be polished until the conductive film 260A is exposed, or the conductive film 260B and the conductive film 260A may be polished until the insulator 250B is exposed. Further, the conductor 260a and the conductor 260b may be formed as shown in the next step without performing the flattening treatment.

Next, the conductive film 260B and the conductive film 260A are processed to form the conductor 260 (conductor 260a and conductor 260b) (see FIG. 10). Dry etching or wet etching can be used for processing the conductive film 260B and the conductive film 260A. The processing is preferably performed until the upper surface of the conductor 260 is lower than the upper surface of the insulator 280.

At this time, the conductor 260 is formed so that at least a part thereof overlaps with the conductor 205, the oxide 230a, and the oxide 230b. The width of the conductor 260 in the channel length direction is determined by the width of the opening 245 provided in the insulator 280, the thickness of the oxide film 230C, the thickness of the insulator 250A, and the thickness of the insulator 250B. The width and thickness can be adjusted according to the performance required for the transistor 200 or the semiconductor device to form the conductor 260 having a desired width.

In this way, the conductor 260 is formed so as to be embedded in the opening 245. Since the conductor 260 is formed in a self-aligned manner without using a lithography method, it is not necessary to provide an alignment margin for the conductor 260. Therefore, the occupied area of the transistor 200 can be reduced, and the semiconductor device can be miniaturized and highly integrated. In addition, since the lithography process is not required, productivity can be expected to be improved by simplifying the process.

Further, in miniaturizing a semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 260 from being lowered. Therefore, if the film thickness of the conductor 260 is increased, the conductor 260 may have a shape having a high aspect ratio. In the present embodiment, since the conductor 260 is provided so as to be embedded in the opening 245, even if the conductor 260 has a shape having a high aspect ratio, it can be formed without collapsing the conductor 260 during the process.

Next, the insulator 272A and the insulator 273A are sequentially formed so as to cover the conductor 260 and the insulator 250 (see FIG. 11). Insulator 272A, and insulator 273A include one or more selected from aluminum, hafnium, magnesium, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, tungsten, titanium, tantalum, nickel and the like. Metal oxide can be used. Further, as the insulator 272A and the insulator 273A, a nitride of silicon or a nitride of silicon containing oxygen, that is, silicon nitride, silicon nitride oxide, or the like can be used. For example, as the insulator 272A, metal oxidation such as aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tungsten oxide, titanium oxide, tantalum oxide, or nickel oxide. Things can be used. Further, a nitride containing silicon can be used as the insulator 273A.

Further, the insulator 272A and the insulator 273A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The film formed by using the ALD method has good coverage. On the other hand, it is preferable to use the sputtering method because a film having a reduced hydrogen concentration can be formed as compared with using other methods. It should be selected according to the characteristics required for the device.

Next, the insulator 273A, the insulator 272A, the insulator 250B, the insulator 250A, and the oxide film 230C are polished until the insulator 280 is exposed, and the insulator 273, the insulator 272, the insulator 250b, and the insulator 250a are polished. , Oxide 230c is formed (see FIG. 12). The CMP method can be used for the polishing. By the polishing, it is preferable that the upper surfaces of the insulator 273, the insulator 272, the insulator 250b, the insulator 250a, and the oxide 230c substantially coincide with the upper surface of the insulator 280.

Here, heat treatment may be performed. For the heat treatment, the above-mentioned heat treatment conditions can be used. By the heat treatment, oxygen contained in an insulator such as an insulator 250a or an insulator 280 can be supplied to the oxide 230. Further, the damage of the oxide 230b due to the formation of the oxide 230c, the insulator 250, the conductor 260, the insulator 272, or the insulator 273 can be recovered. Further, the present heat treatment may form a low resistance region (region 231) in the oxide 230b.

Next, the insulator 281 is formed so as to cover the insulator 280, the insulator 272, the insulator 273, and the like (see FIG. 13). The insulator 281 can be formed by using the same device as the insulator 280 and using the same material. For example, a CVD method is used to form an insulator 281 containing silicon oxide.

Next, the insulator 281, the insulator 280, and the insulator 244 are processed by a lithography method to form an opening connecting to the conductor 242 (see FIG. 14). When forming the opening, the insulator 250b, the insulator 272, and the insulator 273 function as an etching stopper. Therefore, the opening may have a region that overlaps with at least one of the insulator 250b, the insulator 272, and the insulator 273. For example, the insulator 272 and the insulator 273 function as a hard mask, and the insulator 250b functions as a sidewall, so that the conductor 260 can be prevented from being exposed inside the opening. This makes it possible to prevent a short circuit between the conductor 240 and the conductor 260 formed in the subsequent process. At this time, it is preferable that the etching rates of the insulator 273, the insulator 272, and the insulator 250b are sufficiently smaller than the etching rates of the insulator 281 and the insulator 280. Further, it is more preferable that the etching rates of the insulator 250a and the oxide 230c are sufficiently smaller than the etching rates of the insulator 281 and the insulator 280.

FIG. 14 shows an example in which not only the insulator 250b but also the insulator 250a and the oxide 230c remain on the side surface of the conductor 260. As described above, it is preferable that the insulator 250a and the oxide 230c also function as sidewalls. The contact formed by providing the etching stopper on the upper surface and the side surface of the conductor 260 that functions as the gate electrode is referred to as a self-aligned contact (SAC), and the process of forming the SAC is referred to as a SAC process. be.

Next, an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241. The film formation of the conductive film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film to be the insulator 241, it is preferable to use an insulating film having a function of suppressing the permeation of oxygen. For example, it is preferable to form aluminum oxide or silicon nitride by the ALD method. Further, the anisotropic etching may be performed by, for example, a dry etching method. By having such a configuration on the side wall portion of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent the oxidation of the conductor 240a and the conductor 240b to be formed next. Further, it is possible to prevent impurities such as water and hydrogen from diffusing from the conductor 240a and the conductor 240b to the outside.

Next, a conductive film to be a conductor 240 (conductor 240a, conductor 240b, and conductor 240c) is formed. It is desirable that the conductive film to be the conductor 240 has a laminated structure including a conductor having a function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum nitride, titanium nitride and the like can be laminated with tungsten, molybdenum, copper and the like. The film formation of the conductive film to be the conductor 240 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, by performing the CMP treatment, a part of the conductive film to be the conductor 240 is removed, and the insulator 281 is exposed. As a result, the conductor 240 having a flat upper surface can be formed by the conductive film remaining only in the opening (see FIG. 1). In addition, a part of the insulator 281 may be removed by the CMP treatment.

In the present embodiment, since the SAC process is used to form the openings, the conductor 260 and the conductor 240 do not come into contact with each other, and the distance between them is kept constant.

From the above, the semiconductor device having the transistor 200 can be manufactured. As shown in FIGS. 4 to 14, the transistor 200 can be manufactured by using the method for manufacturing the semiconductor device shown in the present embodiment.

According to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a small off-current can be provided. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device having a large on-current. Alternatively, one aspect of the present invention can provide a highly reliable semiconductor device. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention can provide a highly productive semiconductor device.

As described above, the configurations and methods shown in the present embodiment can be appropriately combined with the configurations and methods shown in other embodiments and examples.

<Modification example 1 of semiconductor device>
Hereinafter, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention, which is different from the one shown in the above <constituent example of the semiconductor device>, will be described with reference to FIG.

FIG. 15A is a top view of the semiconductor device having the transistor 200. 15 (B) and 15 (C) are cross-sectional views of the semiconductor device. Here, FIG. 15B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 15A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Further, FIG. 15C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 15A, and is also a cross-sectional view of the transistor 200 in the channel width direction. In the top view of FIG. 15A, some elements are omitted for the sake of clarity of the figure.

In the semiconductor device shown in FIG. 15, the same reference numerals are added to the structures having the same functions as the structures constituting the semiconductor devices (see FIG. 1) shown in <Semiconductor device configuration example>.

Hereinafter, the configurations of the transistors 200 will be described with reference to FIGS. 15. Also in this item, as the constituent material of the transistor 200, the material described in detail in <Semiconductor device configuration example> can be used.

In the semiconductor device (see FIG. 1) shown in the above <Semiconductor device configuration example>, an example is shown in which the transistor 200 has two transistors (transistor 200a and transistor 200b) in one semiconductor layer. However, the present invention is not limited to this. As shown in FIG. 15, the transistor 200 may have one transistor (transistor 200a) in one semiconductor layer. Also in the transistor 200 shown in FIG. 15, the area of the transistor 200 can be reduced by using the SAC process. In the transistor 200, an insulator 250b that functions as an etching stopper on the side surface of the conductor 260 that functions as the first gate electrode of the transistor 200a, an insulator 272 that functions as an etching stopper on the upper surface of the conductor 260, and an insulator 273. Is provided. By providing these etching stoppers, even if the contact that exposes the conductor 242 is brought close to the side surface of the conductor 260, the conductor 260 and the conductor 240 are not connected, and the area of the transistor 200 can be reduced. can.

<Modification 2 of semiconductor device>
Hereinafter, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention, which is different from the one shown in the above <constituent example of the semiconductor device>, will be described with reference to FIG.

FIG. 16A is a top view of a semiconductor device having a transistor 200. 16 (B) and 16 (C) are cross-sectional views of the semiconductor device. Here, FIG. 16B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 16A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Further, FIG. 16C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 16A, and is also a cross-sectional view of the transistor 200 in the channel width direction. In the top view of FIG. 16A, some elements are omitted for the sake of clarity of the figure.

In the semiconductor device shown in FIG. 16, the same reference numerals are given to the structures having the same functions as the structures constituting the semiconductor devices (see FIG. 1) shown in <Semiconductor device configuration example>.

Hereinafter, the configurations of the transistors 200 will be described with reference to FIGS. 16. Also in this item, as the constituent material of the transistor 200, the material described in detail in <Semiconductor device configuration example> can be used.

The semiconductor device shown in FIG. 23 is different from the semiconductor device (see FIG. 1) shown in <Semiconductor device configuration example> in that the oxide 230c is provided on the upper surface of the oxide 230b and the conductor is provided on the upper surface of the oxide 230c. The difference is that 242 and the insulator 250 are provided.

In order to form the transistor 200 having such a configuration, the oxide film 230C may be formed after the oxide film 230B is formed, and the conductive film 242A may be formed on the oxide film C.

As described above, the configuration, structure, method and the like shown in the present embodiment can be appropriately combined with the configuration, structure, method and the like shown in other embodiments and examples.

(Embodiment 2)
In this embodiment, a form of a semiconductor device that functions as a storage device, which is different from the above-described embodiment, will be described with reference to FIGS. 17 to 20.

<Storage device 1>
17 (A) and 17 (B) show cells 600 constituting the storage device. The cell 600 has a transistor 200a, a transistor 200b, a capacitive element 100a, and a capacitive element 100b. FIG. 17A is a top view of the cell 600. Further, FIG. 17B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 17A. In the top view of FIG. 17A, some elements are omitted for the sake of clarity of the figure.

The cell 600 has a transistor 200a and a transistor 200b, has a capacitive element 100a superimposed on the transistor 200a, and has a capacitive element 100b superimposed on the transistor 200b. In the cell 600, the transistor 200a and the transistor 200b, and the capacitive element 100a and the capacitive element 100b may be arranged line-symmetrically. Therefore, it is preferable that the transistor 200a and the transistor 200b have the same configuration, and it is preferable that the capacitive element 100a and the capacitive element 100b have the same configuration.

The insulator 130 is provided on the transistor 200a and the insulator 281 on the transistor 200b, and the insulator 150 is provided on the insulator 130. Here, as the insulator 150, an insulator that can be used for the insulator 281 may be used.

Further, the conductor 160 is provided on the insulator 150. Further, the conductor 240 is provided so as to be embedded in the openings formed in the insulator 280, the insulator 281 and the insulator 130, and the insulator 150. The lower surface of the conductor 240 is in contact with the conductor 242b, and the upper surface of the conductor 240 is in contact with the conductor 160. Further, the conductor 240 is in contact with the upper surface and the side surface of the insulator 273 and is electrically connected to the conductor 242b.

As the transistor 200a and the transistor 200b, the transistor 200 shown in the above embodiment can be used. Therefore, the description of the transistor 200 can be taken into consideration for the configurations of the transistor 200a and the transistor 200b. Further, in FIGS. 17A and 17B, the reference numerals of the elements of the transistor 200a and the transistor 200b are omitted. The transistor 200a and the transistor 200b shown in FIGS. 17A and 17B are examples, and the transistor 200a and the transistor 200b are not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

Both the transistor 200a and the transistor 200b are formed of the oxide 230, and one of the source and drain of the transistor 200a and one of the source and drain of the transistor 200b are both in contact with the conductor 242c. Therefore, one of the source and drain of the transistor 200a and one of the source and drain of the transistor 200b are electrically connected to the conductor 240c via the conductor 242c. As a result, the contact portion of the transistor 200a and the transistor 200b is shared, and the number of plugs and contact holes can be reduced. In this way, by sharing the wiring electrically connected to one of the source and the drain, the occupied area of the memory cell array can be further reduced.

[Capacitive element 100a and capacitive element 100b]
As shown in FIGS. 25A and 25B, the capacitive element 100a is provided in a region overlapping with the transistor 200a. Similarly, the capacitive element 100b is provided in a region superimposing on the transistor 200b. The capacitive element 100b has a structure corresponding to that of the capacitive element 100a. Hereinafter, the detailed structure of the capacitive element 100a will be described, but unless otherwise specified, the description of the capacitive element 100a can be referred to for the capacitive element 100b.

The capacitive element 100a has a conductor 110, an insulator 130, and a conductor 120 on the insulator 130. Here, as the conductor 110 and the conductor 120, a conductor that can be used for the conductor 203, the conductor 205, the conductor 242, the conductor 260, or the like may be used.

The capacitive element 100a is provided on the insulator 281 and is electrically connected to the transistor 200a via the conductor 240a. The capacitive element 100a is provided on the insulator 281 and has a configuration in which a conductor 110 that functions as a lower electrode and a conductor 120 that functions as an upper electrode face each other with the insulator 130 that functions as a dielectric interposed therebetween. Here, the conductor 110 of the capacitive element 100a is formed in contact with the conductor 242a.

Further, it is preferable to use an insulator having a large dielectric constant as the insulator 130. For example, an insulator containing an oxide of one or both of aluminum and hafnium can be used. As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.

Further, the insulator 130 may have a laminated structure, for example, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like. Therefore, two or more layers may be selected to form a laminated structure. For example, it is preferable to form a film of hafnium oxide, aluminum oxide and hafnium oxide in order by the ALD method to form a laminated structure. The film thicknesses of hafnium oxide and aluminum oxide shall be 0.5 nm or more and 5 nm or less, respectively. With such a laminated structure, it is possible to obtain a capacitance element 100a having a large capacitance value and a small leakage current.

The conductor 110 or the conductor 120 may have a laminated structure. For example, the conductor 110 or the conductor 120 is a laminate of a conductive material containing titanium, titanium nitride, tantalum, or tantalum nitride as a main component and a conductive material containing tungsten, copper, or aluminum as a main component. It may be a structure. Further, the conductor 110 or the conductor 120 may have a single-layer structure or a laminated structure having three or more layers.

[Structure of cell array]
Next, an example of a cell array in which the above cells are arranged in a matrix or a matrix will be described with reference to FIGS. 18 to 20.

FIG. 18 is a circuit diagram showing a form in which the cells shown in FIG. 17 are arranged in a matrix. FIG. 19 is a schematic diagram showing a cross-sectional structure in the vicinity of the cell 600 in the circuit diagram shown in FIG. 18 and the cell 601 adjacent to the cell 600. FIG. 20 is a schematic diagram showing the layout of the wiring WL, the wiring BL, and the oxide 230 in the circuit diagram shown in FIG. In FIGS. 18 to 20, the extending direction of the wiring BL is the x direction, the extending direction of the wiring WL is the y direction, and the direction perpendicular to the xy plane is the z direction. Although FIGS. 18 and 20 show an example in which 3 × 3 cells are arranged, the present embodiment is not limited to this, and the number and arrangement of memory cells or wiring included in the cell array is not limited to this. May be set as appropriate. Further, in the top view of FIG. 20, for the sake of clarity of the figure, some elements shown in FIG. 18 are omitted.

As shown in FIG. 18, one of the source and drain of the transistor 200a and the transistor 200b constituting the cell is electrically connected to the common wiring BL (BL01, BL02, BL03). Further, the wiring BL is electrically connected to one of the source and drain of the transistor 200a and the transistor 200b of the cells 600 arranged in the x direction. On the other hand, the first gate of the transistor 200a and the first gate of the transistor 200b constituting the cell 600 are electrically connected to different wiring WLs (WL01 to WL06). Further, these wiring WLs are electrically connected to the first gate of the transistor 200a and the first gate of the transistor 200b of the cells 600 arranged in the y direction, respectively.

Further, one electrode of the capacitance element 100a and one electrode of the capacitance element 100b of the cell 600 are electrically connected to the wiring PL. For example, the wiring PL may be formed by extending in the y direction.

Further, the transistor 200a and the transistor 200b of each cell 600 may be provided with a second gate BG. The threshold value of the transistor can be controlled by the potential applied to the BG. The BG is connected to the transistor 400, and the potential applied to the BG can be controlled by the transistor 400.

For example, as shown in FIG. 19, the conductor 160 is stretched in the x direction to function as a wiring BL, the conductor 260 is stretched in the y direction to function as a wiring WL, and the conductor 120 is stretched in the y direction. Can function as a wiring PL. Further, the conductor 203 can be extended in the y direction to function as a wiring connected to the BG.

Further, as shown in FIG. 19, it is preferable that the conductor 120 that functions as one electrode of the capacitance element 100b of the cell 600 also serves as one electrode of the capacitance element 100a of the cell 601. Further, although not shown, the conductor 120 that functions as one electrode of the capacitance element 100a of the cell 600 also serves as one electrode of the capacitance element of the cell adjacent to the left side of the cell 600. The cell on the right side of cell 601 has the same configuration. Therefore, a cell array can be constructed. By configuring the cell array, the distance between adjacent cells can be reduced, so that the projected area of the cell array can be reduced, and high integration is possible.

Further, as shown in FIG. 20, by arranging the oxide 230 and the wiring WL in a matrix, the semiconductor device of the circuit diagram shown in FIG. 18 can be formed. Here, it is preferable that the wiring BL is provided in a layer different from the wiring WL and the oxide 230. In particular, by providing the capacitive element 100a and the capacitive element 100b in the lower layer than the wiring BL, it is possible to realize a layout in which the long side direction of the oxide 230 and the wiring BL are substantially parallel to each other. Therefore, the cell layout can be simplified, the degree of freedom in design can be improved, and the process cost can be reduced.

Further, in FIG. 20, the oxide 230 and the wiring WL are provided so that the long side of the oxide 230 is substantially orthogonal to the extending direction of the wiring WL, but the present invention is not limited to this. For example, the layout may be such that the long side of the oxide 230 is not orthogonal to the extending direction of the wiring WL and the long side of the oxide 230 is inclined with respect to the extending direction of the wiring WL. Preferably, the oxide 230 and the wiring WL may be provided so that the angle formed by the long side of the oxide 230 and the wiring WL is 20 ° or more and 70 ° or less, preferably 30 ° or more and 60 ° or less.

Further, the cellar array may be laminated not only on a flat surface but also on a flat surface. By stacking a plurality of cell array, cells can be integrated and arranged without increasing the occupied area of the cell array. That is, a 3D cell array can be configured.

As described above, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. Alternatively, one aspect of the present invention can provide a semiconductor device having good electrical characteristics. Alternatively, according to one aspect of the present invention, a semiconductor device having a small off-current can be provided. Alternatively, according to one aspect of the present invention, a transistor having a large on-current can be provided. Alternatively, one aspect of the present invention can provide a highly reliable semiconductor device. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention can provide a highly productive semiconductor device.

As described above, the configurations and methods shown in the present embodiment can be appropriately combined with the configurations and methods shown in other embodiments.

(Embodiment 3)
In this embodiment, a form of a semiconductor device that functions as a storage device, which is different from the above-described embodiment, will be described with reference to FIG. 21.

<Storage device 2>
The storage device shown in FIG. 21A includes a transistor 300, a transistor 200a, a transistor 200 having the transistor 200b, a capacitive element 100a, and a capacitive element 100b. FIG. 21A is a cross-sectional view of the transistor 200 and the transistor 300 in the channel length direction. FIG. 21B shows a cross-sectional view of the transistor 300 in the vicinity of the transistor 300 in the channel width direction. In the following description, a storage device including the transistor 300, the transistor 200a, and the capacitive element 100a will be described. On the other hand, in the transistor 200b included in the transistor 200, a storage device can be separately configured by a capacitive element 100b connected to the transistor 200b and a transistor (not shown), but duplicate description will be omitted unless otherwise specified.

The transistor 200a is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200a has a small off current, it is possible to retain the stored contents for a long period of time by using the transistor 200a as a storage device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.

In the storage device shown in FIG. 21A, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200a, the wiring 1004 is electrically connected to the top gate of the transistor 200a, and the wiring 1006 is electrically connected to the bottom gate of the transistor 200a. There is. The gate of the transistor 300 and the other of the source and drain of the transistor 200a are electrically connected to one of the electrodes of the capacitive element 100a, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitive element 100a. ..

The storage device shown in FIG. 21 (A) has a characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read out as shown below.

Writing and retaining information will be described. First, the potential of the wiring 1004 is set to the potential at which the transistor 200a is in the conductive state, and the transistor 200a is set to the conductive state. As a result, the potential of the wiring 1003 is given to the gate of the transistor 300 and the node SN electrically connected to one of the electrodes of the capacitive element 100a. That is, a predetermined charge is given to the gate of the transistor 300 (writing). Here, it is assumed that either of the charges that give two different potential levels (hereinafter, referred to as Low level charge and High level charge) is given. After that, the electric charge is held (retained) in the node SN by setting the potential of the wiring 1004 to the potential at which the transistor 200a is in the non-conducting state and putting the transistor 200a in the non-conducting state.

When the off current of the transistor 200a is small, the charge of the node SN is retained for a long period of time.

Next, reading information will be described. When a predetermined potential (constant potential) is applied to the wiring 1001 and an appropriate potential (reading potential) is applied to the wiring 1005, the wiring 1002 takes a potential corresponding to the amount of electric charge held in the node SN. This is because when the transistor 300 is an n-channel type, the apparent threshold voltage _{Vth_H} when the high level charge is given to the gate of the transistor 300 is the case where the low level charge is given to the gate of the transistor 300. This is because it is lower than the apparent threshold voltage V _{th_L} . Here, the apparent threshold voltage means the potential of the wiring 1005 required to make the transistor 300 in a conductive state. Therefore, by setting the potential of the wiring 1005 to the potential V ₀ between V _{th_H} and V _{th_L} , the electric charge given to the node SN can be discriminated. For example, in writing, when the node SN is given a high level charge, if the potential of the wiring 1005 becomes V ₀ (> V _{th_H} ), the transistor 300 is in a conductive state. On the other hand, when the low level charge is given to the node SN, the transistor 300 remains in the non-conducting state even if the potential of the wiring 1005 becomes V ₀ (<V _{th_L} ). Therefore, by discriminating the potential of the wiring 1002, the information held in the node SN can be read out.

When the memory cells are arranged in an array, the information of the desired memory cells must be read at the time of reading. For example, when the memory cell array has a NOR type configuration, only the information of a desired memory cell can be read out by setting the transistor 300 of the memory cell that does not read information into a non-conducting state. In this case, a potential that causes the transistor 300 to be in a non-conducting state regardless of the charge given to the node SN, that is, a potential lower than V _{th_H} , may be applied to the wiring 1005 connected to the memory cell that does not read information. .. Alternatively, for example, when the memory cell array has a NAND type configuration, only the information of a desired memory cell can be read out by making the transistor 300 of the memory cell that does not read information into a conductive state. In this case, a potential that causes the transistor 300 to be in a conductive state regardless of the charge given to the node SN, that is, a potential higher than _{Vth_L} may be applied to the wiring 1005 connected to the memory cell that does not read information.

<Structure of storage device 2>
As shown in FIG. 21A, the storage device of one aspect of the present invention includes a transistor 300, a transistor 200, a capacitive element 100a, and a capacitive element 100b. The transistor 200 has a transistor 200a and a transistor 200b, and is provided above the transistor 300. Further, the capacitive element 100a and the capacitive element 100b are provided above the transistor 300 and the transistor 200.

The transistor 300 is provided on the substrate 311 and has a semiconductor region 313 composed of a conductor 316, an insulator 315, and a part of the substrate 311, and a low resistance region 314a and a low resistance region 314b that function as a source region or a drain region. Have.

As shown in FIG. 21B, the transistor 300 is covered with the conductor 316 on the upper surface of the semiconductor region 313 and the side surface in the channel width direction via the insulator 315. As described above, by making the transistor 300 a Fin type, the on characteristic of the transistor 300 can be improved by increasing the effective channel width. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristic of the transistor 300 can be improved.

The transistor 300 may be either a p-channel type or an n-channel type.

It is preferable to include a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like. It preferably contains crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

In the low resistance region 314a and the low resistance region 314b, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity such as arsenic and phosphorus, or p-type conductivity such as boron are imparted. Contains elements that

The conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

Since the work function is determined by the material of the conductor, the Vth of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

The transistor 300 shown in FIG. 21 is an example, and the transistor 300 is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order so as to cover the transistor 300.

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, etc. are used. Just do it.

The insulator 322 may have a function as a flattening film for flattening a step generated by a transistor 300 or the like provided below the insulator 322. For example, the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.

Further, for the insulator 324, it is preferable to use a film having a barrier property so that hydrogen and impurities do not diffuse in the region where the transistor 200 is provided from the substrate 311 or the transistor 300.

As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by the CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 200, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.

The amount of hydrogen desorbed can be analyzed using, for example, a heated desorption gas analysis method (TDS). For example, the amount of hydrogen desorbed from the insulator 324 is the amount desorbed in terms of hydrogen atoms in the range of 50 ° C. to 500 ° C. in the surface temperature of the film in TDS analysis, which is converted into the area of the insulator 324. It may be 10 × 10 ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less.

The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, more preferably less than 3. Further, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less the relative permittivity of the insulator 324. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.

Further, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitive element 100a, a conductor 328 electrically connected to the transistor 200a, a conductor 330, and the like. The conductor 328 and the conductor 330 function as a plug or wiring. In addition, a conductor that functions as a plug or wiring may collectively assign a plurality of structures to the same reference numeral. Further, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is single-layered or laminated. Can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.

One or more wiring layers may be provided on the insulator 326 and the conductor 330. For example, in FIG. 21A, insulator 350 (insulator 350-1, insulator 350-2, insulator 350-3, insulator 350-4), insulator 352 (insulator 352-1, insulator). 352-2, insulator 352-3, insulator 352-4), and insulator 354 (insulator 354-1, insulator 354-2, insulator 354-3, insulator 354-4) are laminated in this order. It is provided. Further, a conductor 356 (conductor 356-1, conductor 356-2, conductor 356-3, conductor 356-4) is formed on the insulator 350, the insulator 352, and the insulator 354. .. The conductor 356 functions as a plug or wiring. The conductor 356 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 350, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 356 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 200 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

As the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen has a structure in contact with the insulator 350 having a barrier property against hydrogen.

FIG. 21A shows an example in which four wiring layers including a conductor 356 are laminated, but the storage device according to the present embodiment is not limited to this. The number of wiring layers including the conductor 356 may be 3 or less, or 5 or more.

An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are laminated on the insulator 354 in this order. As any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216, it is preferable to use a substance having a barrier property against oxygen and hydrogen.

Further, the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (conductor 205) constituting the transistor 200a, and the like. The conductor 218 has a function as a plug or wiring for electrically connecting to the capacitive element 100a or the transistor 300. The conductor 218 can be provided by using the same material as the conductor 328 and the conductor 330.

In particular, the conductor 210 and the conductor 218 in the region in contact with the insulator 214 are preferably conductors having a barrier property against oxygen, hydrogen, and water. With this configuration, the transistor 300 and the transistor 200 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

A transistor 200 is provided above the insulator 216. As the structure of the transistor 200, the transistor included in the semiconductor device described in the previous embodiment may be used. Further, the transistor 200 shown in FIG. 21A is an example, and the transistor 200 is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method.

An insulator 281 is provided above the transistor 200.

Further, a conductor 240, an insulator 241 and the like are embedded in the insulator 222, the insulator 224, the insulator 244, the insulator 280, and the insulator 281.

The conductor 240 functions as a plug or wiring that electrically connects to the capacitive element 100a, the transistor 200a, or the transistor 300. The conductor 240 can be provided by using the same material as the conductor 328 and the conductor 330.

A capacitive element 100a is provided above the transistor 200a. The capacitive element 100a has a conductor 110, a conductor 120, and an insulator 130.

The conductor 110 has a function as an electrode of the capacitive element 100a.

The conductor 110 is a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned elements as a component (tantal nitride film, (Titanium nitride film, molybdenum nitride film, tungsten nitride film) and the like can be used. Alternatively, add indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide. It is also possible to apply a conductive material such as indium-tin oxide.

In FIG. 21A, the conductor 110 has a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used. For example, a conductor having a barrier property and a conductor having a high adhesion to the conductor having a high conductivity may be formed between the conductor having the barrier property and the conductor having a high conductivity.

The conductor 120 is provided so as to overlap with the conductor 110 via the insulator 130. As the conductor 120, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When it is formed at the same time as other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which are low resistance metal materials, may be used.

An insulator 150 is provided on the conductor 120 and the insulator 130. The insulator 150 can be provided by using the same material as the insulator 320. Further, the insulator 150 may function as a flattening film that covers the uneven shape below the insulator 150.

Further, in the insulator 150 and the insulator 130, a conductor 112 that is electrically connected to the conductor 240 is embedded. Further, the conductor 160 may be provided on the conductor 112 and the insulator 150.

By using this structure, it is possible to suppress fluctuations in electrical characteristics and improve reliability in a semiconductor device using a transistor having an oxide semiconductor. Alternatively, it is possible to provide a transistor having an oxide semiconductor having a large on-current. Alternatively, it is possible to provide a transistor having an oxide semiconductor having a small off-current. Alternatively, it is possible to provide a semiconductor device with reduced power consumption. Alternatively, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved.

As described above, the configuration, structure, method and the like shown in the present embodiment can be appropriately combined with the configuration, structure, method and the like shown in other embodiments and examples.

(Embodiment 4)
In the present embodiment, using FIGS. 22 and 23, a transistor using an oxide as a semiconductor (hereinafter, may be referred to as an OS transistor) and a capacitive element according to one aspect of the present invention are applied. The storage device (hereinafter, may be referred to as an OS memory device) is described. The OS memory device is a storage device having at least a capacitance element and an OS transistor that controls charging / discharging of the capacitance element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory.

<Configuration example of storage device>
FIG. 22A shows an example of the configuration of the OS memory device. The storage device 1400 has a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. The wiring is the wiring connected to the memory cell of the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440. Further, the row circuit 1420 has, for example, a row decoder, a word line driver circuit, and the like, and the row to be accessed can be selected.

The storage device 1400 is supplied with a low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (SiO) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from the outside. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside. The address signal ADDR is input to the row decoder and column decoder, and WDATA is input to the write circuit.

The control logic circuit 1460 processes input signals (CE, WE, RE) from the outside to generate control signals for a row decoder and a column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.

The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one column, and the like. Further, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one row, and the like.

Although FIG. 22A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, the present embodiment is not limited to this. For example, as shown in FIG. 22B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap under the memory cell array 1470.

FIG. 23 describes an example of a memory cell configuration applicable to the above-mentioned memory cell MC.

[DOSRAM]
23 (A) to 23 (C) show an example of a circuit configuration of a DRAM memory cell. In the present specification and the like, a DRAM using a memory cell of a 1OS transistor and a 1-capacity element type may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 23 (A) has a transistor M1 and a capacitive element CA. The transistor M1 has a gate (sometimes referred to as a front gate) and a back gate.

The first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected. Is connected to the wiring BGL. The second terminal of the capacitive element CA is connected to the wiring CAL.

The wiring BIL functions as a bit line and the wiring WOL functions as a word line. The wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. It is preferable to apply a low level potential to the wiring CAL when writing and reading data. The wiring BGL functions as wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

Further, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL as in the memory cell 1472 shown in FIG. 23 (B). Further, for example, the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M1 having no back gate, as in the memory cell 1473 shown in FIG. 23 (C).

When the semiconductor device shown in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitive element 100 can be used as the capacitive element CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very low. That is, since the written data can be held for a long time by the transistor M1, the frequency of refreshing the memory cells can be reduced. Further, the refresh operation of the memory cell can be eliminated. Further, since the leak current is very low, it is possible to hold multi-valued data or analog data for the memory cell 1471, the memory cell 1472, and the memory cell 1473.

Further, in the DOSRAM, if the sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. As a result, the bit line capacity is reduced, and the holding capacity of the memory cell can be reduced.

[NOSRAM]
23 (D) to (H) show an example of a circuit configuration of a gain cell type memory cell having two transistors and one capacitance element. The memory cell 1474 shown in FIG. 23D has a transistor M2, a transistor M3, and a capacitive element CB. The transistor M2 has a front gate (sometimes referred to simply as a gate) and a back gate. In the present specification and the like, a storage device having a gain cell type memory cell using an OS transistor in the transistor M2 may be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

The first terminal of the transistor M2 is connected to the first terminal of the capacitive element CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2. Is connected to the wiring BGL. The second terminal of the capacitive element CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.

The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. It is preferable to apply a low level potential to the wiring CAL during data writing, data retention, and data reading. The wiring BGL functions as wiring for applying a potential to the back gate of the transistor M2. The threshold voltage of the transistor M2 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

Further, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be appropriately changed. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL as in the memory cell 1475 shown in FIG. 23 (E). Further, for example, the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M2 having no back gate, as in the memory cell 1476 shown in FIG. 23 (F). Further, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined as one wiring BIL, as in the memory cell 1477 shown in FIG. 23 (G).

When the semiconductor device shown in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitive element 100 can be used as the capacitive element CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made very low. As a result, the written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cells can be reduced. Further, the refresh operation of the memory cell can be eliminated. Further, since the leak current is very low, multi-valued data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

The transistor M3 may be a transistor having silicon in the channel forming region (hereinafter, may be referred to as a Si transistor). The conductive type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a readout transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be provided by stacking it on the transistor M3, so that the occupied area of the memory cell can be reduced and the storage device can be highly integrated.

Further, the transistor M3 may be an OS transistor. When an OS transistor is used for the transistors M2 and M3, the circuit can be configured by using only the n-type transistor in the memory cell array 1470.

Further, FIG. 23 (H) shows an example of a gain cell type memory cell having a 3-transistor and 1-capacity element. The memory cell 1478 shown in FIG. 23 (H) has transistors M4 to M6 and a capacitive element CC. The capacitive element CC is appropriately provided. The memory cell 1478 is electrically connected to the wiring BIL, RWL, WWL, BGL, and GNDL. Wiring GNDL is wiring that gives a low level potential. The memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.

The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. The back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not have to have a back gate.

The transistors M5 and M6 may be n-channel type Si transistors or p-channel type Si transistors, respectively. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured by using only n-type transistors.

When the semiconductor device shown in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitive element 100 can be used as the capacitive element CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made very low.

The configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in the present embodiment are not limited to the above. The arrangement or function of these circuits and the wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.

The configuration shown in this embodiment can be appropriately combined with the configuration shown in other embodiments and the like.

(Embodiment 5)
This embodiment shows an example of an electronic component and an electronic device incorporating a storage device or the like shown in the above embodiment.

<Electronic components>
First, an example of an electronic component incorporating the storage device shown in the above embodiment will be described with reference to FIGS. 24 (A) and 24 (B).

FIG. 24A shows a perspective view of the electronic component 700 and the substrate on which the electronic component 700 is mounted (mounting substrate 704). The electronic component 700 shown in FIG. 24 (A) is an IC chip and has a lead and a circuit unit 710. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such IC chips are combined and electrically connected to each other on the printed circuit board 702 to complete the mounting board 704.

In the circuit unit 710, various circuits shown in the above embodiment are provided on one die. As shown in the previous embodiment, the circuit unit 710 has a laminated structure and is roughly classified into a Si transistor layer 712, a wiring layer 714, and an OS transistor layer 716. Since the OS transistor layer 716 can be laminated on the Si transistor layer 712, the electronic component 700 can be easily miniaturized.

As the circuit unit 710 of the electronic component 700, the storage device shown in the above embodiment is provided. In FIG. 24A, QFP (Quad Flat Package) is applied to the package of the electronic component 700, but the mode of the package is not limited to this.

FIG. 24B shows a perspective view of the electronic component 730. The electronic component 730 is an example of SiP (System in package) or MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on the package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of circuit units 710 are provided on the interposer 731.

In the electronic component 730, an example is shown in which the storage device shown in the above embodiment is used as a wide band memory (HBM: High Bandwidth Memory) as the circuit unit 710. Further, as the semiconductor device 735, an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA can be used.

As the package substrate 732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer 731, a silicon interposer, a resin interposer, or the like can be used.

The interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. Multiple wirings are provided in a single layer or multiple layers. Further, the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrode provided on the package substrate 732. For these reasons, the interposer may be referred to as a "rewiring board" or an "intermediate board". Further, a through electrode may be provided on the interposer 731, and the integrated circuit and the package substrate 732 may be electrically connected using the through electrode. Further, in the silicon interposer, a TSV (Through Silicon Via) can be used as a through electrode.

It is preferable to use a silicon interposer as the interposer 731. Since it is not necessary to provide an active element in the silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with a resin interposer.

In HBM, it is necessary to connect many wires in order to realize a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as an interposer for mounting HBM.

Further, in SiP or MCM using a silicon interposer, the reliability is unlikely to be lowered due to the difference in the expansion coefficient between the integrated circuit and the interposer. Further, since the surface of the silicon interposer is high, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.

Further, a heat sink (heat sink) may be provided so as to be overlapped with the electronic component 730. When the heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 uniform. For example, in the electronic component 730 shown in the present embodiment, it is preferable that the heights of the circuit unit 710 and the semiconductor device 735 are the same.

In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732. FIG. 24B shows an example in which the electrode 733 is formed of a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. Further, the electrode 733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

The electronic component 730 can be mounted on another substrate by using various mounting methods, not limited to BGA and PGA. For example, SPGA (Stepgered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), QFN (QuadNeg, etc.) be able to.

<Electronic equipment>
Next, an example of an electronic device provided with the above electronic components will be described with reference to FIG. 25.

The robot 7100 includes an illuminance sensor, a microphone, a camera, a speaker, a display, various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, piezo sensor, optical sensor, gyro sensor, etc.), a moving mechanism, and the like. The electronic component 730 has a processor and the like, and has a function of controlling these peripheral devices. For example, the electronic component 700 has a function of storing data acquired by a sensor.

The microphone has a function of detecting an acoustic signal such as a user's voice and an environmental sound. In addition, the speaker has a function of emitting audio signals such as voice and horn. The robot 7100 can analyze an audio signal input via a microphone and emit a necessary audio signal from the speaker. In the robot 7100, it is possible to communicate with the user by using a microphone and a speaker.

The camera has a function of photographing the surroundings of the robot 7100. Further, the robot 7100 has a function of moving by using a moving mechanism. The robot 7100 can capture an image of the surroundings using a camera, analyze the image, and detect the presence or absence of an obstacle when moving.

The flying object 7120 has a propeller, a camera, a battery, and the like, and has a function of autonomously flying. The electronic component 730 has a function of controlling these peripheral devices.

For example, the image data taken by the camera is stored in the electronic component 700. The electronic component 730 can analyze the image data and detect the presence or absence of an obstacle when moving. Further, the remaining battery level can be estimated from the change in the storage capacity of the battery by the electronic component 730.

The cleaning robot 7140 has a display arranged on the upper surface, a plurality of cameras arranged on the side surface, a brush, an operation button, various sensors, and the like. Although not shown, the cleaning robot 7300 is provided with tires, suction ports, and the like. The cleaning robot 7300 is self-propelled, can detect dust, and can suck dust from a suction port provided on the lower surface.

For example, the electronic component 730 can analyze an image taken by a camera and determine the presence or absence of an obstacle such as a wall, furniture, or a step. Further, when an object that is likely to be entangled with the brush such as wiring is detected by image analysis, the rotation of the brush can be stopped.

The automobile 7160 has an engine, tires, brakes, a steering device, a camera, and the like. For example, the electronic component 730 controls to optimize the running state of the automobile 7160 based on data such as navigation information, speed, engine state, gear selection state, and brake usage frequency. For example, the image data taken by the camera is stored in the electronic component 700.

The electronic component 700 and / or the electronic component 730 can be incorporated into a TV device 7200 (television receiving device), a smartphone 7210, a PC7220 (personal computer), 7230, a game machine 7240, a game machine 7260, and the like.

For example, the electronic component 730 built into the TV device 7200 can function as an image engine. For example, the electronic component 730 performs image processing such as noise removal and resolution up-conversion.

The smartphone 7210 is an example of a mobile information terminal. The smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display unit. These peripherals are controlled by electronic components 730.

PC7220 and PC7230 are examples of notebook PCs and stationary PCs, respectively. A keyboard 7232 and a monitoring device 7233 can be connected to the PC 7230 wirelessly or by wire. The game machine 7240 is an example of a portable game machine. The game machine 7260 is an example of a stationary game machine. A controller 7262 is connected to the game machine 7260 wirelessly or by wire. Electronic components 700 and / or electronic components 730 can also be incorporated into the controller 7262.

This embodiment can be appropriately combined with the configurations described in other embodiments and the like.

(Embodiment 6)
In this embodiment, an application example of a storage device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device shown in the above embodiment is, for example, a storage device for various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording / playback device, a navigation system, etc.). Can be applied to. Here, the computer includes a tablet-type computer, a notebook-type computer, a desktop-type computer, and a large-scale computer such as a server system. Alternatively, the semiconductor device shown in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive). FIG. 26 schematically shows some configuration examples of the removable storage device. For example, the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.

FIG. 26A is a schematic diagram of the USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like of the substrate 1104.

FIG. 26B is a schematic diagram of the appearance of the SD card, and FIG. 26C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing the memory chip 1114 on the back surface side of the substrate 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 1113. As a result, the data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1114 or the like of the substrate 1113.

FIG. 26 (D) is a schematic diagram of the appearance of the SSD, and FIG. 26 (E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152 and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 on the back surface side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1154 or the like of the substrate 1153.

This embodiment can be appropriately combined with the configurations described in other embodiments and the like.

200 Insulator, 203 Insulator, 205 Insulator, 210 Insulator, 212 Insulator, 214 Insulator, 216 Insulator, 218 Insulator, 222 Insulator, 224 Insulator, 230 Oxide, 231 Region, 234 Region, 240 Conductor, 241 Insulator, 242 Insulator, 244 Insulator, 245 Opening, 246 Hard Mask, 250 Insulator, 260 Insulator, 272 Insulator, 273 Insulator, 280 Insulator, 281 Insulator

Claims (12)

With oxides
A first conductor and a second conductor provided on the oxide so as to be separated from each other,
A third conductor having a region on the oxide and overlapping with a region between the first conductor and the second conductor.
With the first insulator on the third conductor,
A second insulator arranged between the oxide and the third conductor, covering the side surface of the third conductor, and arranging so as to be in contact with the side surface of the first insulator. When,
A third insulator having a first opening and a second opening on the first insulator and the second insulator.
A fourth conductor that is electrically connected to the first conductor through the first opening.
It has a fifth conductor that is electrically connected to the second conductor through the second opening.
A semiconductor device having a region in which at least one of the first opening and the second opening overlaps with at least one of the first insulator and the second insulator. In claim 1,
A semiconductor device in which the first insulator and the second insulator contain metal and oxygen, respectively, and the third insulator contains silicon and oxygen, respectively. In claim 1 or 2,
The semiconductor device includes an upper surface and a side surface of the first conductor, an upper surface and a side surface of the second conductor, and a fourth insulator covering the side surface of the oxide.
A semiconductor device having a fifth insulator between the fourth insulator and the third insulator. In claim 3,
The fourth insulator contains metal and oxygen, and the fifth insulator contains silicon and oxygen, a semiconductor device. In any one of claims 1 to 4,
A sixth insulator is provided on the first insulator.
The sixth insulator is a semiconductor device which is a nitride containing silicon. With oxides
A first conductor, a second conductor, and a third conductor provided between the first conductor and the second conductor, which are provided on the oxide at a distance from each other. With the body
A fourth conductor having a region on the oxide and overlapping with a region between the first conductor and the third conductor.
With the first insulator on the fourth conductor,
A second insulator arranged between the oxide and the fourth conductor, covering the side surface of the fourth conductor and in contact with the side surface of the first insulator. When,
A fifth conductor having a region on the oxide and overlapping with a region between the second conductor and the third conductor.
With the third insulator on the fifth conductor,
A fourth insulator arranged between the oxide and the fifth conductor, covering the side surface of the fifth conductor and in contact with the side surface of the third insulator. When,
A fifth insulator with an opening on the first insulator, the second insulator, the third insulator, and the fourth insulator.
It has a sixth conductor that is electrically connected to the third conductor through the opening.
A semiconductor device in which the opening has a region that overlaps with at least one of the first insulator, the second insulator, the third insulator, and the fourth insulator. In claim 6,
The first insulator, the second insulator, the third insulator, and the fourth insulator contain metal and oxygen, respectively, and the fifth insulator contains silicon and oxygen, respectively. , Semiconductor device. In claim 6 or 7,
The semiconductor device covers the upper surface and side surface of the first conductor, the upper surface and side surface of the second conductor, the upper surface and side surface of the third conductor, and the side surface of the oxide. 6 insulators and
A semiconductor device having a seventh insulator between the sixth insulator and the fifth insulator. In claim 8,
The sixth insulator contains metal and oxygen, and the seventh insulator contains silicon and oxygen, a semiconductor device. In any one of claims 6 to 9,
An eighth insulator is provided on the first insulator.
A ninth insulator is provided on the third insulator.
A semiconductor device in which the eighth insulator and the ninth insulator are nitrides containing silicon, respectively. In any one of claims 2, claim 4, claim 7, and claim 9.
The metal is one selected from aluminum, hafnium, magnesium, gallium, germanium , ittrium, zirconium, lantern, neodymium, tungsten, titanium, tantalum, and nickel. In any one of claims 1 to 11 .
A semiconductor device in which the oxide has In, an element M (M is Al, Ga, Y, or Sn), and Zn.

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