JP7095615B2 - Semiconductor device - Google Patents

Description

The techniques disclosed herein relate to semiconductor devices.

Patent Document 1 discloses a semiconductor substrate and a semiconductor device having a plurality of wirings (for example, source wiring, gate wiring, drain wiring) provided on the semiconductor substrate. There is a gap between each wiring. At intervals between the wires, the top surface of the semiconductor substrate is covered with an oxide film. Further, each wiring and the surface of the oxide film are covered with a passivation film.

JP-A-2017-152655

In a semiconductor device as described above, an insulating resin may be used as a passivation film. When such a semiconductor device is used, thermal expansion occurs in each component such as wiring, oxide film, and insulating resin according to the temperature rise of the semiconductor substrate. Since the linear expansion coefficient of each component is different, the expansion rate of each component is different. Therefore, high stress is applied to each component. As a result, the insulating resin may be peeled from the oxide film in the vicinity of the wiring, and the metal may be extruded from the wiring in the peeled region. The metal extruded from the wiring extends along the interface between the insulating resin and the oxide film. A short circuit occurs when the metal extending along the interface between the insulating resin and the oxide film comes into contact with other wiring. The present specification provides a technique capable of suppressing a short circuit between wirings.

As a result of diligent studies by the present inventors, it has been found that the above-mentioned short circuit is likely to occur when the distance between the two wirings is 100 μm or less. In view of this situation, the semiconductor device disclosed in the present specification has the following configuration.

The semiconductor device disclosed in the present specification includes a SiC substrate, a first wiring, a second wiring, a groove portion, a silicon oxide film, and an insulating resin. The first wiring is arranged on the upper part of the SiC substrate and is composed of Al. The second wiring is arranged on the upper part of the SiC substrate, is composed of Al, and is separated from the first wiring. The groove is provided on the upper surface of the SiC substrate between the first wiring and the second wiring. The silicon oxide film covers the upper surface of the SiC substrate between the first wiring and the second wiring and the inner surface of the groove portion. The insulating resin covers the range straddling the first wiring, the silicon oxide film, and the second wiring. A part of the insulating resin is arranged in the groove portion and covers the surface of the silicon oxide film in the groove portion. The distance between the first wiring and the second wiring is 100 μm or less.

The first wiring may be in contact with the upper surface of the SiC substrate. Further, another layer may be arranged between the first wiring and the SiC substrate. Similarly, the second wiring may be in contact with the upper surface of the SiC substrate. Further, another layer may be arranged between the second wiring and the SiC substrate.

In the above semiconductor device, a groove is provided on the upper surface of the SiC substrate between the first wiring and the second wiring. Further, a part of the insulating resin is arranged in the groove portion and covers the surface of the silicon oxide film in the groove portion. Therefore, the interface between the insulating resin and the silicon oxide film extends along the groove. In this semiconductor device, consider a case where the metal extruded from the first wiring extends to the second wiring side along the interface between the insulating resin and the silicon oxide film due to stress. In this case, since the interface between the insulating resin and the silicon oxide film extends along the groove portion, the metal extruded from the first wiring extends along the interface (that is, following the groove portion). Therefore, in the above semiconductor device, the extension distance required for the metal extruded from the first wiring to reach the second wiring (that is, from the first wiring measured along the interface between the insulating resin and the silicon oxide film). The distance to the second wiring) is longer than the linear distance between the first wiring and the second wiring. Therefore, even if peeling occurs between the silicon oxide film and the insulating resin, a short circuit between the wirings is unlikely to occur.

Sectional drawing of the semiconductor device 10 of an embodiment. FIG. 1 is a cross-sectional view taken along the line II-II of FIG. The figure which shows the state when the peeling occurs between the silicon oxide film 20 and the insulating resin 22. The cross-sectional view corresponding to FIG. 2 of the semiconductor device of a modification.

The semiconductor device 10 of the present embodiment will be described with reference to the drawings. As shown in FIGS. 1 and 2, the semiconductor device 10 has a SiC substrate 12, a gate wiring 14, and two source wirings 16. Although not shown, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is formed inside the SiC substrate 12. In FIG. 1, for the sake of easy viewing, only the gate wiring 14 and the source wiring 16 formed on the upper surface 12a of the SiC substrate 12 are shown, and the insulating film and the like are not shown. The element structure formed inside the SiC substrate 12 is not limited to the MOSFET, and may be, for example, an IGBT (Insulated Gate Bipolar Transistor).

As shown in FIG. 1, each source wiring 16 is arranged in the center of the upper part of the SiC substrate 12. Each source wiring 16 has a rectangular shape in a plan view. Each source wiring 16 is made of Al (aluminum). A part of each source wiring 16 is in contact with the upper surface 12a of the SiC substrate 12.

The gate wiring 14 has an outer peripheral portion 14a and an extending portion 14b. The outer peripheral portion 14a is arranged on the upper portion of the SiC substrate 12 along the outer peripheral edge of the SiC substrate 12 so as to surround the two source wirings 16. The extending portion 14b extends along between the two source wires 16 and one end thereof is connected to the outer peripheral portion 14a. A part of the extending portion 14b is connected to a gate electrode (not shown) provided inside the SiC substrate 12. The gate wiring 14 is composed of Al. The distance D1 between the gate wiring 14 and the source wiring 16 is 100 μm or less.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. As shown in FIG. 2, a groove 18 is provided on the upper surface 12a of the SiC substrate 12. The groove portion 18 is provided on the upper surface 12a of the SiC substrate 12 between the gate wiring 14 and the source wiring 16. As shown in FIG. 1, the groove portion 18 is arranged between the outer peripheral portion 14a of the gate wiring 14 and the source wiring 16, and extends long along the outer peripheral portion 14a. That is, the groove portion 18 is formed in a region outside the two source wirings 16 and in a region inside the outer peripheral portion 14a of the gate wiring 14.

As shown in FIG. 2, a silicon oxide film 20 is formed on the upper surface 12a of the SiC substrate 12 and the inner surface of the groove 18. The silicon oxide film 20 covers a range extending from the inner surface of the groove 18 to the upper surface 12a of the SiC substrate 12.

The gate wiring 14 is arranged on the silicon oxide film 20. The gate wiring 14 is insulated from the SiC substrate 12 by the silicon oxide film 20. The source wiring 16 is arranged on the silicon oxide film 20. As described above, the source wiring 16 is in contact with the upper surface 12a of the SiC substrate 12 at a position (not shown). The entire surface of the SiC substrate 12 (that is, the upper surface 12a and the inner surface of the groove 18) located between the gate wiring 14 and the source wiring 16 is covered with the silicon oxide film 20.

The gate wiring 14, the silicon oxide film 20, and the source wiring 16 are covered with the insulating resin 22. The insulating resin 22 covers a range extending from the surface of the gate wiring 14 to the surface of the source wiring 16. The insulating resin 22 is also arranged inside the groove 18. The insulating resin 22 covers the surface of the silicon oxide film 20 inside the groove 18. That is, the insulating resin 22 covers the entire surface of the silicon oxide film 20 located between the gate wiring 14 and the source wiring 16. The insulating resin 22 is made of, for example, polyimide.

When the semiconductor device 10 is used, thermal expansion occurs in each component such as the gate wiring 14, the source wiring 16, the silicon oxide film 20, and the insulating resin 22 according to the temperature rise of the SiC substrate 12. Since the linear expansion coefficient of each component is different, the expansion rate of each component is different. In particular, the SiC substrate 12 used in this embodiment has a relatively high Young's modulus and is not easily deformed even if other constituent members thermally expand. Therefore, in the semiconductor device 10 of the present embodiment, high stress is likely to be applied to each component. Further, a higher stress is applied to the outer peripheral portion of the SiC substrate 12 as compared with the central portion of the SiC substrate 12. As a result, peeling is likely to occur at the interface between the insulating resin 22 having a relatively low adhesion and the silicon oxide film 20 on the outer peripheral portion of the SiC substrate 12. When the insulating resin 22 is peeled from the silicon oxide film 20 in the vicinity of the gate wiring 14 and the source wiring 16, the metal (that is, Al) constituting them may be extruded from the gate wiring 14 and the source wiring 16 to the peeled region. be.

In the semiconductor device 10 of the present embodiment, a groove 18 is provided on the upper surface 12a of the SiC substrate 12 between the outer peripheral portion 14a of the gate wiring 14 and the source wiring 16. Further, a part of the insulating resin 22 is arranged in the groove portion 18 and covers the surface of the silicon oxide film 20 in the groove portion 18. Therefore, the interface between the insulating resin 22 and the silicon oxide film 20 extends following the groove portion 18. In this semiconductor device 10, as shown in FIG. 3, the insulating resin 22 is peeled off from the silicon oxide film 20 at the portion S near the gate wiring 14, and the Al member 15 extruded from the gate wiring 14 is oxidized with the insulating resin 22. Consider a case where the silicon film 20 extends to the source wiring 16 side along the interface. In this case, since the interface between the insulating resin 22 and the silicon oxide film 20 extends along the groove portion 18, the Al member 15 extruded from the gate wiring 14 is along the interface (that is, as shown by arrow A). , Following the groove 18). Therefore, in the semiconductor device 10 of the present embodiment, the extension distance required for the Al member 15 extruded from the gate wiring 14 to reach the source wiring 16 (that is, along the interface between the insulating resin 22 and the silicon oxide film 20). The measured distance D2 from the gate wiring 14 to the source wiring 16 (see the thick line portion in FIG. 2) is longer than the linear distance between the gate wiring 14 and the source wiring 16 (that is, the distance D1 in FIG. 2). Therefore, in this semiconductor device 10, even if peeling occurs between the silicon oxide film 20 and the insulating resin 22, a short circuit between the wirings 14 and 16 is unlikely to occur. Similarly, when the insulating resin 22 is peeled off from the silicon oxide film 20 in the vicinity of the source wiring 16 and the Al extruded from the source wiring 16 extends toward the gate wiring 14, short circuit between the wirings 14 and 16 is suppressed. can do.

In the above-described embodiment, the gate wiring 14 and the source wiring 16 are provided on the upper surface 12a of the SiC substrate 12 via the silicon oxide film 20. However, as shown in FIG. 4, a groove 18 may be provided between the wiring 114 and the wiring 116 provided so as to be in direct contact with the upper surface 12a of the SiC substrate 12. Further, only one of the wiring 114 and the wiring 116 may be in direct contact with the upper surface 12a of the SiC substrate 12. Even with such a configuration, when the insulating resin 22 is peeled off from the silicon oxide film 20, a short circuit between the wirings 114 and 116 can be suppressed.

The relationship between the components of the above-described embodiment and the components of the claims will be described. The gate wiring 14 of the embodiment is an example of the "first wiring" or the "second wiring" of the claim, and the source wiring 16 is an example of the "second wiring" or the "first wiring" of the claim. ..

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples exemplified above. The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in the present specification or the drawings achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

10: Semiconductor device, 12: SiC substrate, 12a: Top surface, 14: Gate wiring, 16: Source wiring, 18: Groove, 20: Silicon oxide film, 22: Insulation resin

Claims (1)

With a SiC substrate
The first wiring, which is arranged on the upper part of the SiC substrate and is composed of Al,
The second wiring, which is arranged on the upper part of the SiC substrate, is composed of Al, and is separated from the first wiring, and
A groove provided on the upper surface of the SiC substrate between the first wiring and the second wiring, and
The upper surface of the SiC substrate between the first wiring and the second wiring, and the silicon oxide film covering the inner surface of the groove portion.
The first wiring, the silicon oxide film, and the insulating resin covering the range straddling the second wiring.
Have,
A part of the insulating resin is arranged in the groove portion and covers the surface of the silicon oxide film in the groove portion.
A semiconductor device in which the distance between the first wiring and the second wiring is 100 μm or less.

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