JP7098902B2 - Through Silicon Via Substrate - Google Patents

Description

The present disclosure relates to a through silicon via substrate.

In order to simplify the mounting of semiconductor chip components on a large wiring board (motherboard), they are integrated on a through silicon via board (also called a wiring board, multilayer wiring board, through silicon via board, interposer, etc.) that converts the terminal arrangement to a coarse pitch. A semiconductor device in which an element such as a circuit is attached is used. When a plurality of layers of wiring are formed on a substrate, an insulating film having a flat upper surface may be formed on the wiring (for example, Patent Documents 1 and 2).

Japanese Unexamined Patent Publication No. 2009-188379 Japanese Unexamined Patent Publication No. 2014-44785

The through silicon via substrate has a multilayer wiring layer. This multi-layer wiring layer contains elements as small as the upper layer. Therefore, the mounting portion side of the through silicon via substrate has a high-density wiring structure. Further, when the insulating material is applied on the wiring, the liquid insulating material may flow to the left and right due to the influence of gravity. In this case, the insulating film becomes thin near the end of the wiring, and the insulating film may be cracked. As described in Patent Documents 1 and 2, thickening the insulating film causes difficulty in forming a fine pattern, and is not suitable for application to a through silicon via substrate.

In view of such a problem, one of the objects in the embodiment of the present disclosure is to suppress the occurrence of cracking of the insulating film on the wiring in the through silicon via substrate.

The through electrode substrate, which is one of the embodiments of the present disclosure, includes a substrate having a first surface, a second surface, and a through hole penetrating the first surface and the second surface, and the through hole. The wiring layer is provided with a through electrode provided on the substrate and a wiring layer provided on the substrate and electrically connecting the through electrode and an element provided on the substrate, and the wiring layer is the first. A first insulating film having a first wiring provided on one surface and a step portion provided on the first wiring and the first surface and corresponding to an end portion of the first wiring in the first direction. And, it is provided on the first insulating film, and when viewed from the direction perpendicular to the first surface, at least a part thereof overlaps with the first wiring, and the distance between the ends in the first direction is the first. A second wiring different from the first wiring, and a second insulating film provided on the second wiring and the first insulating film and having a step portion corresponding to the end portion of the second wiring in the first direction. , Have.

In the through silicon via substrate of the present disclosure, the distance between the ends in the first direction may be larger in the second wiring than in the first wiring. The second wiring may be provided on the entire step portion of the first wiring and the first insulating film.

In the through silicon via substrate of the present disclosure, the distance between the ends in the first direction may be smaller in the second wiring than in the first wiring.

In the through silicon via substrate of the present disclosure, the first wiring and the second wiring may be electrically connected via an opening provided in the first insulating film.

In the through silicon via substrate of the present disclosure, at least one of the first wiring and the second wiring may be electrically connected to the element and the through electrode.

In the through electrode substrate of the present disclosure, the wiring layer is a first wiring layer for electrically connecting the through electrode and the first element provided on the first surface, and the through electrode and the first element are connected to each other. The second wiring layer further includes a second wiring layer for electrically connecting the second element provided on the two surfaces, and the second wiring layer includes the third wiring provided on the second surface and the second wiring. A third insulating film provided on the three wirings and the second surface and having a step portion corresponding to an end portion of the third wiring in the first direction, and a third insulating film provided on the third insulating film, said. The fourth wiring, which is at least partially overlapped with the third wiring when viewed from the direction perpendicular to the second surface, and the distance between the ends in the first direction is different from that of the third wiring, and the fourth wiring. And a fourth insulating film provided on the third insulating film and having a step portion corresponding to the end portion of the fourth wiring in the first direction may be provided.

The through electrode substrate of the present disclosure includes a substrate having a first surface, a second surface, a through hole penetrating the first surface and the second surface, and a through electrode provided in the through hole. A wiring layer provided on the substrate and electrically connecting the through electrode and an element provided on the substrate is provided, and the wiring layers are adjacent to each other on the first surface. The first wiring and the second wiring provided, and the step portion provided on the first wiring, the second wiring, and the first surface and corresponding to the end portion of the first wiring in the first direction. A first insulating film having a stepped portion corresponding to an end portion of the second wiring in the first direction, and a first insulating film provided on the first insulating film and viewed from a direction perpendicular to the first surface. A third wiring that overlaps with the first wiring and has a larger distance between the ends in the first direction than the first wiring, and a direction provided on the first insulating film and perpendicular to the first surface. The fourth wiring that overlaps with the second wiring and the distance between the ends in the first direction is smaller than that of the second wiring, and the third wiring, the fourth wiring, and the first insulating film. It has a second insulating film provided on the top of the third wiring and having a stepped portion corresponding to each end portion of the fourth wiring in the first direction.

In the through silicon via substrate of the present disclosure, when viewed in a direction perpendicular to the first surface, the end portion of the third wiring exists outside the end portion of the first wiring, and the end portion of the fourth wiring is described above. It may be inside the end of the second wire. When viewed from a direction perpendicular to the first surface, the first region including the first wiring and the third wiring and the second region including the second wiring and the fourth wiring are aligned in at least one direction. They may be arranged alternately. The first region and the second region may be alternately arranged along the first direction and the second direction intersecting the first direction when viewed from the direction perpendicular to the first surface.

It is a top view explaining the semiconductor device which concerns on 1st Embodiment of this disclosure. It is sectional drawing which follows the A1-A2 line of the semiconductor device shown in FIG. It is an enlarged cross section of a part of the wiring layer which concerns on 1st Embodiment of this disclosure. It is an enlarged cross section of a part of the wiring layer which concerns on 1st Embodiment of this disclosure. It is an enlarged cross section of a part of the wiring layer which concerns on 1st Embodiment of this disclosure. It is a top view which shows the wiring pattern which concerns on 1st Embodiment of this disclosure. It is an enlarged cross section of a part of the wiring layer which concerns on 1st Embodiment of this disclosure. It is a top view which shows the wiring pattern which concerns on 1st Embodiment of this disclosure. It is a top view which shows the wiring pattern which concerns on 1st Embodiment of this disclosure. It is a top view which shows the dummy pattern which concerns on 1st Embodiment of this disclosure. It is a top view which shows the dummy pattern which concerns on 1st Embodiment of this disclosure. It is a top view which shows the dummy pattern which concerns on 1st Embodiment of this disclosure. It is a top view which shows the dummy pattern which concerns on 1st Embodiment of this disclosure. It is sectional drawing along the A1-A2 line of the semiconductor device which concerns on 2nd Embodiment of this disclosure. It is an enlarged cross section of a part of the wiring layer which concerns on 2nd Embodiment of this disclosure. It is an enlarged cross section of a part of the wiring layer which concerns on 2nd Embodiment of this disclosure. It is an enlarged cross section of a part of the wiring layer which concerns on 2nd Embodiment of this disclosure. It is an enlarged cross section of a part of the wiring layer which concerns on 2nd Embodiment of this disclosure. It is an enlarged cross section of a part of the wiring layer which concerns on 2nd Embodiment of this disclosure. It is a figure which illustrates the cross-sectional structure when a plurality of wirings which concerns on 1st Embodiment of this disclosure are laminated with the same width.

Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings and the like. However, the present disclosure can be carried out in various aspects without departing from the gist thereof, and is not construed as being limited to the description contents of the embodiments exemplified below.

The drawings may schematically represent the width, thickness, shape, etc. of each part as compared to the actual embodiment in order to clarify the explanation, but this is merely an example and the interpretation of the present disclosure is limited. It's not something to do. In the present specification and each figure, elements having the same functions as those described with respect to the above-mentioned figures may be designated by the same reference numerals and duplicate explanations may be omitted.

In the present specification and the scope of patent claims, when expressing an aspect of arranging another structure on one structure, when the term "above" is simply used, the structure shall be used unless otherwise specified. It includes both the case where another structure is placed directly above the structure so as to be in contact with each other and the case where another structure is placed above one structure via another structure.

In the present specification and claims, the expression that one structure overlaps with another means that at least a part of these structures overlap in a plan view. In other words, it means that one of these structures is located above or below the other, and at least some of these structures overlap each other when viewed from above or below. do.

<First Embodiment>
FIG. 1 shows a top view showing an example of the semiconductor device 100 according to the first embodiment of the present disclosure. The semiconductor device 100 includes a printed circuit board 102, a through silicon via 104, and an integrated circuit 106. The through silicon via 104 electrically connects the integrated circuit 106 and the printed circuit board 102. Here, the through silicon via substrate 104 is an interposer that relays signals between the integrated circuits 106 having different terminal pitches and the printed circuit board 102.

The integrated circuit 106 is an element provided on the through silicon via substrate 104. The integrated circuit 106 is electrically connected to the through electrode substrate 104 via the wiring layer 116 and the through electrode 118. The through silicon via 104 is electrically connected to the printed circuit board 102 via the through electrode 118. The number of integrated circuits 106 arranged on the through electrode substrate 104 may be two or more.

The through silicon via board 104 is mounted on the printed circuit board 102. In the following description, the direction may be described using a right-handed XYZ Cartesian coordinate system. The X direction (first direction) and the Y direction (second direction) are directions along one side and the other side when the through silicon via 104 is viewed from the upper surface, respectively. The Z direction (third direction) is a direction perpendicular to the plane of the through silicon via substrate 104.

FIG. 2 shows a cross-sectional view taken along the line A1-A2 of FIG. The through electrode substrate 104 has a substrate 120, a through electrode 118, and a wiring layer 116. The substrate 120 is, for example, a glass substrate. The substrate 120 may be a silicon substrate, a substrate made of a flexible material such as FPC, or the like. The substrate 120 has a first surface 140A, a second surface 140B, and a through hole 126. The second surface 140B is a surface facing the first surface 140A. That is, the first surface 140A and the second surface 140B have an upper and lower relationship or a front and back relationship with respect to the through silicon via substrate 104.

The through hole 126 is a hole that penetrates the first surface 140A and the second surface 140B. The through electrode 118 is provided in the through hole 126. The through electrode 118 is formed, for example, by a plating method. As the material of the through electrode 118, for example, copper (Cu) is used, but other materials may be used. The through electrode 118 may be provided on the entire through hole 126, or may be provided only on the side wall surface of the through hole 126. The wiring layer 116 is a wiring layer that electrically connects the integrated circuit 106 and the through silicon via 118. The wiring layer 116 is provided on the first surface 140A of the substrate 120. The wiring layer 116 includes, for example, wirings 240 and 260 as wirings that electrically connect the integrated circuit 106 and the through silicon vias 118. The through electrode 118 is electrically connected to the bump 114. The through silicon via substrate 104 is electrically connected to the printed circuit board 102 via the bump 114.

Hereinafter, an example of the wiring structure included in the wiring layer 116 will be described.

(Configuration Example 1)
FIG. 3 shows an enlarged cross-sectional view of a part of the wiring layer 116. FIG. 3 shows a cross section around the connection point 500 between the integrated circuit 106 shown in FIG. 1 and the through silicon via substrate 104. The wiring 210 is provided on the first surface 140A of the substrate 120. The width of the wiring 210 in the X direction is W1. Assuming that the ends of the wiring 210 in the X direction are S1 and S2, the distance between the ends S1 and S2 in the X direction is W1. Here, the wiring 210 is an island-shaped wiring called a land connecting the through electrode 118 and each wiring. In the present embodiment, the material used for each wiring is not particularly limited, and examples thereof include copper (Cu), aluminum (Al), nickel (Ni), titanium (Ti), and tungsten (W).

The insulating film 310 is provided on the first surface 140A and the wiring 210. The insulating film 310 is provided on the first surface 140A and the wiring 210 so as to have a uniform or substantially uniform thickness. As the material of the insulating film, for example, a coating-type photosensitive insulating material or a thermosetting insulating material having a low temperature curability is used. The insulating film 310 has a stepped portion C1 corresponding to the end portion S1 of the wiring 210 in the X direction, and has a stepped portion C2 corresponding to the end portion S2. The step portions C1 and C2 are formed by flowing a liquid insulating material from above the wiring 210 onto the first surface 140A in the process of forming the insulating film 310. In this embodiment, the insulating film is formed by, for example, spin coating. When the insulating film is formed by spin coating, gravity causes the insulating material to flow in. Another reason for the inflow is that the melting point of the insulating material is relatively low. The upper surfaces of the step portions C1 and C2 are inclined so as to be lower in the direction away from the wiring 210 in the X direction. The shape and range of the stepped portion of the insulating material vary depending on the material, viscosity, method of forming the insulating film, and the like.

The insulating film 310 has an opening 312. The opening 312 penetrates the insulating film 310 in the Z direction on the wiring 210.

The wiring 220 is provided on the insulating film 310. The wiring 220 is a wiring having a width of W2 in the X direction. Assuming that the ends of the wiring 220 in the X direction are S3 and S4, the distance between the ends S3 and S4 in the X direction is W2. The wiring 220 is provided on the wiring 210 and is electrically connected to the wiring 210 via the opening 312. The width W2 of the wiring 220 is larger than the width W1 of the wiring 210. Therefore, the wiring 220 has a portion inclined along the upper surface of the step portions C1 and C2. The wiring 220 overlaps the wiring 210 and the entire stepped portions C1 and C2 when viewed in a direction perpendicular to the first surface 140A (that is, in the Z direction). The ends S3 and S4 do not overlap with the ends S1 and S2, respectively, when viewed in the Z direction. Here, the ends S3 and S4 of the wiring 220 in the X direction overlap with the lowest points of the stepped portions C1 and C2, that is, the boundaries between the stepped portions C1 and C2 and the flat portion, respectively, when viewed in the Z direction. There is. However, the ends S3 and S4 may each overlap a region closer to the wiring 210 in the X direction than the lowest point, or may overlap a region distant from the wiring 210 in the X direction from the lowest point.

The insulating film 320 is provided on the insulating film 310 and the wiring 220. The insulating film 320 is provided on the insulating film 310 and the wiring 220 so as to have a uniform or substantially uniform thickness. The insulating film 320 has stepped portions C3 and C4 corresponding to the end portions S3 and S4 of the wiring 220 in the X direction. The step portions C3 and C4 are formed by flowing a liquid insulating material from above the wiring 220 onto the upper surface of the insulating film 310 in the process of forming the insulating film 320. The upper surfaces of the step portions C3 and C4 are inclined so as to be lower in the direction away from the wiring 220 in the X direction. Further, the step portion C3 has a wider range in the X direction than the step portion C1. The step portion C4 has a wider range in the X direction than the step portion C2.

The insulating film 320 has an opening 322. The opening 322 penetrates the insulating film 320 in the Z direction on the wiring 220.

The wiring 230 is provided on the insulating film 320. The wiring 230 is a wiring having a width of W3 in the X direction. Assuming that the ends of the wiring 230 in the X direction are S5 and S6, the distance between the ends S5 and S6 in the X direction is W3. The wiring 230 is electrically connected to the wiring 220 via the opening 332. W3 is smaller than the width W2 of the wiring 220. Further, the width W3 is the same as the width W1 of the wiring 210 here, but may be different. The wiring 230 overlaps with the wiring 220 when viewed in the Z direction. However, the end portion S5 of the wiring 230 does not overlap with the end portion S3 when viewed in the Z direction. The end portion S6 of the wiring 230 does not overlap with the end portion S4 of the wiring 220 when viewed in the Z direction.

The insulating film 330 is provided on the insulating film 320 and the wiring 230. The insulating film 330 is provided on the insulating film 320 and the wiring 230 so as to have a uniform or substantially uniform thickness. The insulating film 330 has a stepped portion C5 corresponding to the end portion S5 of the wiring 230 in the X direction, and has a stepped portion C6 corresponding to the end portion S6. The step portions C5 and C6 are formed by flowing a liquid insulating material from above the wiring 230 onto the upper surface of the insulating film 320. The upper surfaces of the step portions C5 and C6 are inclined so as to be lower in the direction away from the wiring 230 in the X direction. Further, the step portion C5 has a wider range in the X direction than the step portion C3. The step portion C6 has a wider range in the X direction than the step portion C4.

The insulating film 330 has an opening 332. The opening 332 penetrates the insulating film 330 in the Z direction on the wiring 230. The integrated circuit 106 is provided on the insulating film 330. The integrated circuit 106 is electrically connected to the wiring 230 via the opening 332.

As described above, when the through silicon via 104 is viewed in the Z direction, the end portion of each wiring in the X direction does not overlap with the end portion of the wiring immediately below in the X direction. As a result, the occurrence of cracking of each insulating film, particularly the insulating film 330 which is the uppermost layer, is suppressed.

FIG. 20 is a diagram illustrating a cross-sectional structure when wiring 810, wiring 820, and wiring 830 are laminated with the same width W. The wirings are stacked in the order of wiring 810, wiring 820, and wiring 830 in the order of proximity to the substrate 120. The insulating film 910 is formed on the wiring 810 so as to have a constant thickness. The insulating film 910 has stepped portions C41 and C42 corresponding to the end portions in the X direction. The insulating film 920 is formed on the wiring 820 so as to have a constant thickness. The insulating film 920 has stepped portions C43 and C44 corresponding to the end portions in the X direction. The insulating film 930 is formed on the wiring 830 so as to have a constant thickness. The insulating film 930 has stepped portions C45 and C46 corresponding to the end portions in the X direction. As shown in FIG. 20, the ranges of the step portions C41, C43, and C45 in the X direction are substantially the same. Further, the ranges of the step portions C42, C44, and C46 in the X direction are almost the same. Therefore, the higher the insulating film, the steeper the step. Therefore, in the range R near the end of the wiring 830, the film thickness tends to be particularly thin. Therefore, cracks are likely to occur due to the shrinkage or expansion of the insulating film 930 at this location.

On the other hand, in the present embodiment, as shown in FIG. 3, when the through electrode substrate 104 is viewed in the Z direction, the end portion of each wiring in the X direction is at least the end portion of the wiring immediately below in the X direction. Do not overlap. That is, the range of the step portion in the X direction is deviated for each insulating layer. Therefore, the insulating film is less likely to become thin even near the end of the wiring on the uppermost layer. Therefore, it is possible to avoid the concentration of heat shrinkage and expansion near the end of the wiring, and the generation of cracks due to the shrinkage or expansion of the insulating film is suppressed at this location. Further, since the upper surface of each insulating film does not have to be flat, the film thickness of each insulating film can be reduced, and it is also suitable for forming a high-definition pattern on the through electrode substrate 104.

(Configuration Example 2)
FIG. 4 shows another example of an enlarged cross-sectional view of a part of the wiring layer 116. In the following description, the description of the content overlapping with the configuration example 1 will be omitted or simplified. A cross section around the connection point 600 between the integrated circuit 106 and the through silicon via substrate 104 shown in FIG. 1 is shown. The wiring 240 is provided on the first surface 140A. The wiring 240 extends in the X direction. The insulating film 310 is provided on the first surface 140A and the wiring 240. The upper surface of the insulating film 310 is flat. The insulating film 310 has an opening 314. The opening 314 penetrates the insulating film 310 in the Z direction.

Wiring 250 and wiring 260 are provided on the insulating film 310. The wiring 250 is electrically connected to the wiring 240 via the opening 314. Here, the ends S12 and S13 of the wiring 250 in the X direction do not overlap with the ends S11 of the wiring 240 in the X direction when viewed from the Z direction. The wiring 260 extends in the X direction. The end S14 of the wiring 260 in the X direction does not overlap with the end S11 of the wiring 240 in the X direction when viewed from the Z direction.

The insulating film 320 is provided on the insulating film 310, the wiring 250 and the wiring 260. The insulating film 320 has stepped portions C11 and C12 corresponding to the end portions S12 and S13 of the wiring 250 in the X direction. Further, the insulating film 320 has a stepped portion C13 corresponding to the end portion S14 in the X direction of the wiring 260. The insulating film 320 has openings 324 and 326. The opening 324 penetrates the insulating film 320 in the Z direction on the wiring 250. The opening 326 penetrates the insulating film 320 in the Z direction on the wiring 260.

The wiring 270 overlaps with the wiring 250 when viewed from the Z direction. The laminated structure of the wiring 250, the insulating film 320, and the wiring 270 is the same as the laminated structure of the wiring 210, the insulating film 310, and the wiring 220. That is, the wiring 270 has a larger width in the X direction than the wiring 250. Therefore, both ends S15 and S16 of the wiring 270 do not overlap with the ends S12 and S13 when viewed from the Z direction. The wiring 270 is inclined along the upper surface of the stepped portions C11 and C12. The wiring 270 overlaps the wiring 250 and the entire stepped portions C11 and C12 when viewed in the Z direction.

The wiring 280 overlaps with the wiring 260 when viewed from the Z direction. However, the ends S17 and S18 of the wiring 280 do not overlap with the ends S14 of the wiring 260 when viewed from the Z direction.

The insulating film 330 is provided on the insulating film 320, the wiring 270 and the wiring 280. The insulating film 330 has stepped portions C14 and C15 corresponding to the ends S15 and S16 of the wiring 270 in the X direction. The insulating film 330 has stepped portions C16 and C17 corresponding to the ends S17 and S18 of the wiring 280 in the X direction.

The insulating film 330 has openings 334 and 336. The opening 334 penetrates the insulating film 330 in the Z direction on the wiring 270. The opening 336 penetrates the insulating film 330 in the Z direction on the wiring 280. The integrated circuit 106 is electrically connected to the wirings 270 and 280 via the openings 334 and 336.

As described above, when the through silicon via 104 is viewed in the Z direction, the end portion of each wiring in the X direction does not overlap with the end portion of the wiring immediately below in the X direction. As a result, the occurrence of cracking of each insulating film, particularly the insulating film 330 which is the uppermost layer, is suppressed.

(Configuration Example 3)
FIG. 5 shows another example of an enlarged cross-sectional view of a part of the wiring layer 116. Here, a wiring structure other than the connection point between the integrated circuit 106 and the through silicon via substrate 104 will be described. The wiring 410 is provided on the first surface 140A. The wiring 410 is a wiring having a width of W4 in the X direction. Assuming that the ends of the wiring 410 in the X direction are S21 and S22, the distance between the ends S21 and S22 in the X direction is W4. The insulating film 340 is provided on the first surface 140A of the substrate 120 and the wiring 410. The insulating film 340 is provided on the wiring 410 so as to have a constant or substantially constant thickness. In the vicinity of the ends S21 and S22 of the wiring 410 in the X direction, the stepped portions C21 and C22 are generated by the liquid insulating material flowing from the top of the wiring 410 onto the insulating film 340. The width of the wiring 420 in the X direction is W5. Assuming that the ends of the wiring 420 in the X direction are S23 and S24, the distance between the ends S23 and S24 in the X direction is W5. The wiring 420 is provided on the insulating film 340. The wiring 420 overlaps with the wiring 410 when viewed in the Z direction. The width W5 of the wiring 420 is larger than the width W4 of the wiring 410. The wiring 420 overlaps with the wiring 410 when viewed in the Z direction. The ends S23 and S24 of the wiring 420 in the X direction exist outside the ends S21 and S22 of the wiring 410 in the X direction and do not overlap with the ends S21 and S22. The insulating film 350 is provided on the wiring 420 and the insulating film 340. The insulating film 350 is formed on the wiring 420 so as to have a constant or substantially constant thickness. Step portions C23 and C24 are generated in the vicinity of the ends S23 and S24 of the wiring 420 in the X direction.

The wiring pattern PA including the above-mentioned wiring 410 and the laminated structure of the wiring 420 may be arranged as shown in FIG. 6, for example. That is, a plurality of wiring patterns PA may be arranged in the X direction intersecting the Y direction, which is the extending direction thereof. The distance between adjacent wiring patterns PA may or may not be constant.

FIG. 7 shows an enlarged cross-sectional view of a part of the wiring layer 116. Wiring 430 is provided on the first surface 140A. The wiring 430 is a wiring having a width of W6 in the X direction. Assuming that the ends of the wiring 430 in the X direction are S25 and S26, the distance between the ends S25 and S26 in the X direction is W6. The insulating film 340 is provided on the first surface 140A of the substrate 120 and the wiring 410. The insulating film 340 is formed on the wiring 430 so as to have a constant or substantially constant thickness. In the vicinity of the ends S25 and S26 of the wiring 430 in the X direction, the stepped portions C25 and C26 are generated by the liquid insulating material flowing from the top of the wiring 430 onto the insulating film 340. Wiring 440 is provided on the insulating film 310. The width of the wiring 440 in the X direction is W7. Assuming that the ends of the wiring 440 in the X direction are S27 and S28, the distance between the ends S27 and S28 in the X direction is W7. The wiring 440 overlaps with the wiring 430 when viewed in the Z direction. The width W7 of the wiring 440 in the X direction is smaller than the width W6 of the wiring 430 in the X direction. For example, W6 = W5, W7 = W4. The wiring 440 overlaps with the wiring 430 when viewed in the Z direction. The ends S27 and S28 of the wiring 440 in the X direction exist inside the ends S25 and S26 of the wiring 430 in the X direction and do not overlap with the ends S25 and S26. The insulating film 350 is provided on the wiring 440 and the insulating film 340. The insulating film 350 is formed on the wiring 440 so as to have a constant or substantially constant thickness. Step portions C27 and C28 are generated in the vicinity of the ends S27 and S28 of the wiring 440 in the X direction.

The wiring pattern PB including the laminated structure of the wiring 430 and the wiring 440 as described above may be arranged as shown in FIG. 8, for example. That is, a plurality of wiring patterns PB may be arranged in the X direction intersecting the Y direction, which is the extending direction thereof. The distance between adjacent wiring patterns PB may or may not be constant.

Wiring patterns PA and PB may be used together in the through silicon via substrate 104. In FIG. 9, the wiring pattern PA and the wiring pattern PB are alternately arranged, for example, one by one in the X direction. The distance between the adjacent wiring patterns PA and PB may or may not be constant. The wiring pattern PA and the wiring pattern PB may not be alternately arranged one by one, but may be arranged alternately by two or more predetermined numbers.

(Configuration Example 4)
A dummy pattern may be configured using the wiring structure described with reference to FIGS. 5 and 7. The dummy pattern is a wiring pattern that is not electrically connected to the through electrode 118, and is a wiring pattern that is regularly arranged on the through electrode substrate 104. FIG. 10 shows a plan view of the dummy pattern as viewed in the Z direction. In this example, the dummy pattern DA (first region) having the structure described with reference to FIG. 5 and the dummy pattern DB (second region) having the structure described with reference to FIG. 7 are rectangular or square, respectively. Further, the end portion of the wiring 410 is inside the end portion of the wiring 420. The ends of the wiring 410 and the wiring 420 do not overlap when viewed in the Z direction. The end of the wiring 430 is outside the end of the wiring 440. The ends of the wiring 430 and the wiring 440 do not overlap when viewed in the Z direction. The distance between the adjacent dummy patterns DA and DB in which the dummy pattern DA and the dummy pattern DB are alternately arranged in each of the X direction and the Y direction may or may not be constant. May be good.

Generally, the dummy pattern is arranged to reduce the variation in the distribution of the wiring on the substrate. According to the arrangement of the dummy patterns DA and DB shown in FIG. 10, the variation in the wiring area for each layer is reduced, so that the stability of the pattern is improved. Further, since the variation in the amount of the inflow of the insulating material for each layer is reduced, the wiring patterning property is improved. The dummy pattern DA and the dummy pattern PB may not be alternately arranged one by one, but may be arranged alternately by two or more predetermined numbers.

11, 12, and 13 are plan views showing other examples of the dummy pattern. In FIG. 11, in the dummy pattern DA1, the wiring 410 has an elliptical shape when viewed in the Z direction. The wiring 420 overlaps with the wiring 410. However, the end of the wiring 420 is a rectangle or a square located outside the end of the wiring 410. In the dummy pattern DB1, the wiring 430 is a rectangle or a square when viewed in the Z direction. The wiring 440 overlaps with the wiring 430. However, the end portion of the wiring 440 is an elliptical shape located inside the end portion of the wiring 430.

FIG. 12 shows that in the dummy pattern DA2, the wiring 410 is rectangular or square when viewed in the Z direction. When viewed in the Z direction, the wiring 420 overlaps with the wiring 410. However, the end portion of the wiring 420 has an elliptical shape located outside the end portion of the wiring 410. In the dummy pattern DB2, the wiring 430 has an elliptical shape when viewed in the Z direction. The wiring 440 overlaps with the wiring 430. However, the end of the wiring 440 is a rectangle or a square located inside the end of the wiring 430.

FIG. 13 shows that in the dummy pattern DA3, the wiring 410 is rectangular or square when viewed in the Z direction. The wiring 420 overlaps with the wiring 410. However, the wiring 420 has an opening 428 in the center. The outer end of the wire 420 is a rectangle or square located outside the end of the wire 410. The inner end of the wire 420 (ie, the end of the opening 428) overlaps the wire 410 but does not overlap the end of the wire 410. In the dummy pattern DB3, the wiring 430 is a rectangle or a square when viewed in the Z direction. The wiring 440 overlaps with the wiring 430. However, the wiring 440 has an opening 448. The outer end of the wire 440 is a rectangle or square located inside the end of the wire 430. The inner end of the wire 440 (ie, the end of the opening 448) overlaps the wire 430 but does not overlap the end of the wire 430.

<Second Embodiment>
FIG. 14 shows a cross-sectional view of the semiconductor device 700 according to the second embodiment of the present disclosure when the semiconductor device 700 is cut in the same plane as the cross section shown in FIG. In the following description, the same elements as those described in the first embodiment are designated by the same reference numerals as those in the first embodiment.

The semiconductor device 700 includes a through electrode substrate 704 and integrated circuits 106A and 106B. The semiconductor device 700 does not have a printed circuit board 102. The through silicon via substrate 704 electrically connects the integrated circuits 106A and 106B. The integrated circuit 106A is a first element provided on the first surface 140A side of the through silicon via substrate 704. The integrated circuit 106B is a second element provided on the second surface 140B of the through silicon via substrate 704. The through silicon via substrate 704 has a substrate 120, a through silicon via 118, and wiring layers 116A and 116B. The wiring layer 116A is a first wiring layer provided on the first surface 140A and electrically connecting the integrated circuit 106A and the through electrode 118A. The wiring layer 116B is a second wiring layer provided on the second surface 140B and electrically connecting the integrated circuit 106B and the through electrode 118A. The positions of the integrated circuits 106A and 106B shown in FIG. 14 are examples. For example, the integrated circuit 106A and the integrated circuit 106B may face each other with the substrate 120 interposed therebetween.

Next, a configuration example of the wiring layer 116A and the wiring layer 116B will be described. In the following description, each element of the wiring layer 116A is represented by using a reference numeral having an "A" added to the end of the reference numeral of the corresponding element of the wiring layer 116 described in the first embodiment. Each element of the wiring layer 116B is represented by a reference numeral of which "B" is added to the end of the reference numeral of the corresponding element of the wiring layer 116.

15, FIG. 16, FIG. 17, FIG. 18 and FIG. 19 show an example of an enlarged cross section of a part of the wiring layer 116A and the wiring layer 116B, respectively. In the cross section shown in FIG. 15, the wiring layer 116A and the wiring layer 116B each have the same configuration as the wiring layer 116 described with reference to FIG. In the cross section shown in FIG. 16, the wiring layer 116A and the wiring layer 116B each have the same configuration as the wiring layer 116 described with reference to FIG. In FIG. 17, the wiring layer 116A and the wiring layer 116B each have the same configuration as the wiring layer 116 described with reference to FIG. In FIG. 18, the wiring layer 116A and the wiring layer 116B have the same configuration as the wiring layer 116 described with reference to FIG. 7, respectively. The configurations of the wiring layer 116A and the wiring layer 116B do not have to be the same. For example, as shown in FIG. 19, the configurations of the wiring layer 116A and the wiring layer 116B may be different. Further, at least one of the number of layers of wiring and the number of layers of insulating film may be different between the wiring layer 116A and the wiring layer 116B.

The structures of the through silicon vias 140 and 704 described above are only examples. For example, the number, shape, size, and number of layers of wiring may be changed as appropriate.

Instead of the integrated circuits 106, 106A, 106A, elements other than the integrated circuits may be applied. As the element of the present disclosure, for example, a semiconductor element such as a light emitting diode or a transistor may be used.

Each of the above-described embodiments as the embodiments of the present disclosure can be appropriately combined and implemented as long as they do not contradict each other. Further, as long as the gist of the present disclosure is provided, those skilled in the art who appropriately add, delete, or change the design based on each embodiment are also included in the scope of the present disclosure.

In addition, even if the effects are different from the effects brought about by each of the above-described embodiments, those that are clear from the description of the present specification or those that can be easily predicted by those skilled in the art are of course. It is understood to be brought about by this disclosure.

The through electrode substrate of the present disclosure can be used as a wiring board with a through electrode. For example, the penetrating electrode substrate of the present disclosure is used in a semiconductor device mounted on an electric device such as a notebook personal computer, a tablet terminal, a mobile phone, a smartphone, a digital video camera, and a digital camera. In addition to the above-mentioned electronic devices, the penetrating electrode substrate of the present disclosure can be widely used in semiconductor devices mounted on electronic devices such as LED lighting, digital signage, desktop personal computers, servers, and car navigation systems.

100, 700: Semiconductor device, 102: Printed circuit board, 104, 704: Through electrode board, 106, 106A, 106B: Integrated circuit, 114: Bump, 116: Wiring layer, 118: Through electrode, 120: Board, 126: Penetration Hole, 140: Through electrode substrate, 140A: 1st surface, 140B: 2nd surface, 210: Wiring, 220: Wiring, 230: Wiring, 240: Wiring, 250: Wiring, 260: Wiring, 270: Wiring, 280: Wiring, 310: Insulation film, 312: Opening, 314: Opening, 320: Insulation film, 322: Opening, 324: Opening, 326: Opening, 330: Insulating film, 332: Opening, 334: Opening 336: Opening, 340: Insulating film, 350: Insulating film, 410: Wiring, 420: Wiring, 428: Opening, 430: Wiring, 440: Wiring, 448: Opening, 500: Connection point, 600: Connection location, 810: wiring, 820: wiring, 830: wiring, 910: insulating film, 920: insulating film, 930: insulating film

Claims (8)

A substrate having a first surface, a second surface, and a through hole penetrating the first surface and the second surface.
Through electrodes provided in the through holes and
A wiring layer provided on the substrate and electrically connecting the through electrode and the element provided on the substrate,
Equipped with
The wiring layer is
The first wiring provided on the first surface and
A first insulating film provided on the first wiring and the first surface and having a first step portion corresponding to an end portion of the first wiring in the first direction.
The distance between the first wiring, the first step portion, and the end portion in the first direction, which is provided on the first insulating film and is viewed from a direction perpendicular to the first surface, is the first. The second wiring, which is larger than the first wiring,
A second insulating film provided on the second wiring and the first insulating film and having a second step portion corresponding to an end portion of the second wiring in the first direction.
A second wiring that is provided on the second insulating film, overlaps the second wiring when viewed from a direction perpendicular to the first surface, and the distance between the ends in the first direction is smaller than that of the second wiring. 3 wiring and
Through silicon via substrate. The through electrode substrate according to claim 1, wherein the first wiring and the second wiring are electrically connected to each other through an opening provided in the first insulating film. The through electrode substrate according to claim 1 or 2, wherein at least one of the first wiring and the second wiring electrically connects the element and the through electrode. A substrate having a first surface, a second surface, and a through hole penetrating the first surface and the second surface.
Through electrodes provided in the through holes and
A first wiring layer that electrically connects the through electrode and the first element provided on the first surface,
A second wiring layer that electrically connects the through electrode and the second element provided on the second surface, and
Equipped with
The first wiring layer is
The first wiring provided on the first surface and
A first insulating film provided on the first wiring and the first surface and having a first step portion corresponding to an end portion of the first wiring in the first direction.
The distance between the first wiring, the first step portion, and the end portion in the first direction, which is provided on the first insulating film and is viewed from a direction perpendicular to the first surface, is the first. The second wiring, which is larger than the first wiring,
A second insulating film provided on the second wiring and the first insulating film and having a second step portion corresponding to an end portion of the second wiring in the first direction.
Have,
The second wiring layer is
The third wiring provided on the second surface and
A third insulating film provided on the third wiring and the second surface and having a third step portion corresponding to the end portion of the third wiring in the first direction.
It is provided on the third insulating film, overlaps with the third wiring when viewed from a direction perpendicular to the second surface, and the distance between the ends in the first direction is smaller than that of the third wiring. 4th wiring and
A fourth insulating film provided on the fourth wiring and the third insulating film and having a fourth step portion corresponding to an end portion of the fourth wiring in the first direction.
Through silicon via substrate. A substrate having a first surface, a second surface, and a through hole penetrating the first surface and the second surface.
Through electrodes provided in the through holes and
A wiring layer provided on the substrate and electrically connecting the through electrode and the element provided on the substrate,
Equipped with
The wiring layer is
The first wiring and the second wiring provided adjacent to each other on the first surface,
A first step portion provided on the first wiring, the second wiring, and the first surface and corresponding to an end portion of the first wiring in the first direction, and a first step portion of the second wiring in the first direction. A first insulating film having a second step portion corresponding to an end portion,
The distance between the first wiring, the first step portion, and the end portion in the first direction, which is provided on the first insulating film and is viewed from a direction perpendicular to the first surface, is the first. The third wiring, which is larger than the first wiring,
A second wiring provided on the first insulating film, which overlaps with the second wiring when viewed from a direction perpendicular to the first surface, and the distance between the ends in the first direction is smaller than that of the second wiring. 4 wiring and
A third step portion provided on the third wiring, the fourth wiring, and the first insulating film and corresponding to an end portion in the first direction of the third wiring, and the first direction of the fourth wiring. A second insulating film having a fourth step portion corresponding to the end portion in the
The first is provided between the first surface and the first wiring, overlaps the first wiring when viewed from a direction perpendicular to the first surface, and has an end portion in the first direction. The fifth wiring, which is larger than the wiring,
Through silicon via substrate. When viewed from a direction perpendicular to the first surface, the end of the third wiring is outside the end of the first wiring, and the end of the fourth wiring is inside the end of the second wiring. The through silicon via substrate according to claim 5 , which is present in the above. When viewed from a direction perpendicular to the first surface, the first region including the first wiring and the third wiring and the second region including the second wiring and the fourth wiring are aligned in at least one direction. The through silicon via substrate according to claim 6 , which is arranged alternately. 7. Claim 7 in which the first region and the second region are alternately arranged along a second direction intersecting the first direction and the first direction when viewed from a direction perpendicular to the first surface. The through electrode substrate according to.

Images