JP7108932B2 - POWER CONVERTER, CONTROL METHOD, AND PROGRAM - Google Patents

Description

TECHNICAL FIELD The present disclosure generally relates to a power converter, a control method, and a program, and more particularly to a power converter having a flying capacitor circuit, a control method for the flying capacitor circuit, and a program.

2. Description of the Related Art Conventionally, there is an inverter device (power conversion device) equipped with a 3-level voltage generation circuit (flying capacitor circuit) (see, for example, Patent Document 1).

The three-level voltage generation circuit of Patent Document 1 has first to fourth switch elements (switching elements) and capacitors. The first to fourth switch elements are connected in series between the first input terminal and the second input terminal of the DC power supply. The capacitor has a first end connected to a connection point between the first switch element and the second switch element, and a second end connected to a connection point between the third switch element and the fourth switch element. . A connection point between the second switch element and the third switch element is used as an output terminal.

Japanese Patent No. 6123900

In the flying capacitor circuit, it is desired to control the voltage across the capacitor to a target value in order to improve the accuracy of the output voltage.

The present disclosure has been made in view of the above reasons, and an object thereof is to provide a power conversion device, a control method, and a program capable of adjusting the voltage across the capacitor of the flying capacitor circuit.

A power converter according to an aspect of the present disclosure includes two pairs of flying capacitor circuits, and a control circuit that controls the two pairs of flying capacitor circuits. Each pair of flying capacitor circuits included in the two pairs of flying capacitor circuits has a capacitor and a plurality of switching elements electrically connected to the capacitor. The pair of flying capacitor circuits are electrically connected between output terminals of a DC power supply. The control circuit is configured to output a plurality of control signals for individually controlling the plurality of switching elements to each of the pair of flying capacitor circuits. The control circuit has a normal mode and a delay mode as operation modes. In the normal mode, a control signal for a switching element among the plurality of switching elements for one flying capacitor circuit of the pair of flying capacitor circuits that switches on/off, and a control signal for the switching element for switching on/off of the plurality of switching elements for the other flying capacitor circuit. A control signal for a switching element that switches between on and off is output at the same timing. In the delay mode, a control signal for a switching element among the plurality of switching elements for switching on/off for at least one flying capacitor circuit of the pair of flying capacitor circuits is delayed from the output timing in the normal mode. output with a delay . The two sets of pairs of flying capacitor circuits include a set of a first flying capacitor circuit and a second flying capacitor circuit and a set of a third flying capacitor circuit and a fourth flying capacitor circuit. A series circuit of the first flying capacitor circuit on the high potential side and the fourth flying capacitor circuit on the low potential side, and the third flying capacitor circuit on the high potential side and the low potential side are provided between the output terminals of the DC power supply. and the second flying capacitor circuit are connected in parallel. A connection point between the first flying capacitor circuit and the fourth flying capacitor circuit is electrically connected to a connection point between the third flying capacitor circuit and the second flying capacitor circuit.

A control method according to an aspect of the present disclosure is a control method for two pairs of flying capacitor circuits included in a power converter. Each pair of flying capacitor circuits included in the two pairs of flying capacitor circuits has a capacitor and a plurality of switching elements electrically connected to the capacitor. The pair of flying capacitor circuits are electrically connected between output terminals of a DC power supply. The control method includes output control processing . The operation modes of the output control process include a normal mode and a delay mode . In the output control process, a plurality of control signals for individually controlling the plurality of switching elements are output to each of the pair of flying capacitor circuits. In the normal mode, a control signal for a switching element among the plurality of switching elements for one flying capacitor circuit of the pair of flying capacitor circuits that switches on/off, and a control signal for the switching element for switching on/off of the plurality of switching elements for the other flying capacitor circuit. A control signal for a switching element that switches between on and off is output at the same timing. In the delay mode , a control signal for a switching element among the plurality of switching elements for switching on/off for at least one flying capacitor circuit of the pair of flying capacitor circuits is delayed from the output timing in the normal mode. output with a delay. The two sets of pairs of flying capacitor circuits include a set of a first flying capacitor circuit and a second flying capacitor circuit and a set of a third flying capacitor circuit and a fourth flying capacitor circuit. A series circuit of the first flying capacitor circuit on the high potential side and the fourth flying capacitor circuit on the low potential side, and the third flying capacitor circuit on the high potential side and the low potential side are provided between the output terminals of the DC power supply. and the second flying capacitor circuit are connected in parallel. A connection point between the first flying capacitor circuit and the fourth flying capacitor circuit is electrically connected to a connection point between the third flying capacitor circuit and the second flying capacitor circuit.

A program according to one aspect of the present disclosure is a program for causing a computer system to execute the control method.

The present disclosure has the advantage of being able to adjust the voltage across the capacitor of the flying capacitor circuit.

FIG. 1 is a circuit diagram of a power converter according to an embodiment of the present disclosure. FIG. 2A is an explanatory diagram of a first switching pattern in the same power converter. FIG. 2B is an explanatory diagram of a second switching pattern in the same power converter. FIG. 3A is an explanatory diagram of a third switching pattern in the same power converter. FIG. 3B is an explanatory diagram of a fourth switching pattern in the same power converter. FIG. 4A is an explanatory diagram of a fifth switching pattern in the same power converter. FIG. 4B is an explanatory diagram of a sixth switching pattern in the same power converter. FIG. 5A is an explanatory diagram of a seventh switching pattern in the same power converter. FIG. 5B is an explanatory diagram of an eighth switching pattern in the same power converter. FIG. 6 is a block diagram of a control circuit in the same power converter. FIG. 7 is an operation explanatory diagram of delay processing in the power conversion device of the same.

The embodiments and modifications described below are merely examples of the present disclosure, and the present disclosure is not limited to the embodiments and modifications. Other than this embodiment and modifications, various modifications can be made according to the design and the like within the scope of the technical idea of the present disclosure.

(embodiment)
(1) Configuration FIG. 1 shows a circuit diagram of a power converter 1 according to this embodiment.

The power converter 1 of the present embodiment performs at least one of an operation of converting DC power into AC power and an operation of converting AC power into DC power. The power conversion device 1 includes a 5-level inverter circuit capable of outputting 5-level output voltages. In the following description, the operation when DC power is input and AC power is output will be mainly described. It is possible to

The power converter 1 is electrically connected to a DC power supply 101 and receives a DC input voltage Vi from the DC power supply 101 . In the following description, the voltage value of the input voltage Vi is assumed to be "E". The power converter 1 has a pair of input terminals P51 and P52. The input terminal P51 is electrically connected to the positive electrode of the DC power supply 101 and the input terminal P52 is electrically connected to the negative electrode of the DC power supply 101 .

The power converter 1 is also electrically connected to the load 102 and outputs an AC output voltage Vo to the load 102 . The power converter 1 has a pair of output terminals P61 and P62. A load 102 is electrically connected between the pair of output terminals P61 and P62. The load 102 is configured to operate with the output voltage Vo from the power converter 1 .

The power conversion device 1 includes four flying capacitor circuits (first flying capacitor circuit 10 to fourth flying capacitor circuit 40) and a control circuit 9. Each flying capacitor circuit includes one capacitor (flying capacitor) and multiple (four) switching elements. Hereinafter, the flying capacitor circuit may be abbreviated as an FC circuit.

Among the four FC circuits, the first FC circuit 10 and the second FC circuit 20 form a pair, and the third FC circuit 30 and the fourth FC circuit 40 form a pair. In other words, the power conversion device 1 includes two pairs of FC circuits. The two pairs of FC circuits include a first FC circuit 10 and a second FC circuit 20 set and a third FC circuit 30 and a fourth FC circuit 40 set.

A series circuit of the first FC circuit 10 and the fourth FC circuit 40 and a series circuit of the third FC circuit 30 and the second FC circuit 20 are electrically connected in parallel between the pair of input terminals P51 and P52.

Specifically, the first FC circuit 10 is electrically connected to the input terminal P51, and the fourth FC circuit 40 is electrically connected to the input terminal P52. The third FC circuit 30 is electrically connected to the input terminal P51, and the second FC circuit 20 is electrically connected to the input terminal P52. That is, the first FC circuit 10 and the third FC circuit 30 are FC circuits on the high potential side, and the fourth FC circuit 40 and the second FC circuit 20 are FC circuits on the low potential side.

The first FC circuit 10 includes four (first) switching elements Q11 to Q14 and one (first) capacitor C11.

As an example, each of the switching elements Q11 to Q14 is composed of a depletion type n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The switching elements Q11 to Q14 are connected in series in the order of switching elements Q11, Q12, Q13 and Q14 from the input terminal P51 side.

Specifically, the switching element Q11 has a drain electrically connected to the input terminal P51 and a source electrically connected to the drain of the switching element Q12. The switching element Q12 has a source electrically connected to the drain of the switching element Q13. The switching element Q13 has a source electrically connected to the switching element Q14. Switching element Q14 is electrically connected to fourth FC circuit 40 .

Switching elements Q11-Q14 are controlled by control signals S11-S14 output from control circuit 9, respectively.

Also, the switching elements Q11 to Q14 have parasitic diodes D11 to D14, respectively. Each of the parasitic diodes D11 to D14 is configured such that the anode is electrically connected to the source and the cathode is electrically connected to the drain.

The capacitor C11 is electrically connected between the connection point between the switching elements Q11 and Q12 and the connection point between the switching elements Q13 and Q14. In other words, the capacitor C11 is electrically connected in parallel with the series circuit of the switching element Q12 and the switching element Q13.

A connection point between the switching element Q12 and the switching element Q13 is the output end P11 of the first FC circuit 10 .

The capacitor C11 is precharged so that the voltage value of the voltage across it becomes "E/4". "E" is the voltage value of the input voltage Vi. In the first FC circuit 10, the switching elements Q11 to Q14 are controlled such that the capacitor C11 repeats charging and discharging around the voltage value "E/4". Therefore, the voltage value of the output voltage of the first FC circuit 10 has three levels of "E", "3E/4", and "E/2", which will be described in detail in the "Example of Operation" column. The output voltage of the first FC circuit 10 here is the potential of the output terminal P11 of the first FC circuit 10 with the potential of the negative electrode of the DC power supply 101 as a reference.

The fourth FC circuit 40 includes four (fourth) switching elements Q41 to Q44 and one (fourth) capacitor C41.

As an example, each of the switching elements Q41 to Q44 is composed of a depletion-type n-channel MOSFET. The switching elements Q41 to Q44 are connected in series in the order of switching elements Q41, Q42, Q43 and Q44 from the first FC circuit 10 side.

Specifically, the switching element Q41 has a drain electrically connected to the source of the switching element Q14 of the first FC circuit 10, and a source electrically connected to the drain of the switching element Q42. The switching element Q42 has a source electrically connected to the drain of the switching element Q43. The switching element Q43 has a source electrically connected to the switching element Q44. Switching element Q44 is electrically connected to input terminal P52.

That is, the switching elements Q11 to Q14 of the first FC circuit 10 and the switching elements Q41 to Q44 of the fourth FC circuit 40 are connected in series between the output terminals of the DC power supply 101 (between the pair of input terminals P51 and P52).

Switching elements Q41-Q44 are controlled by control signals S41-S44 output from control circuit 9, respectively.

Also, the switching elements Q41 to Q44 have parasitic diodes D41 to D44, respectively. Each of the parasitic diodes D41 to D44 is configured such that the anode is electrically connected to the source and the cathode is electrically connected to the drain.

The capacitor C41 is electrically connected between the connection point between the switching elements Q41 and Q42 and the connection point between the switching elements Q43 and Q44. In other words, the capacitor C41 is electrically connected in parallel with the series circuit of the switching element Q42 and the switching element Q43.

The connection point between the switching element Q42 and the switching element Q43 is the output terminal P41 of the fourth FC circuit 40. FIG.

The capacitor C41 is precharged so that the voltage value of the voltage across it becomes "E/4". In the fourth FC circuit 40, the switching elements Q41 to Q44 are controlled so that the capacitor C41 repeats charging and discharging around the voltage value "E/4". Therefore, the voltage value of the output voltage of the fourth FC circuit 40 has three levels of "E/2", "E/4", and "0", which will be described in detail in the section "Example of Operation". The output voltage of the fourth FC circuit 40 here is the potential of the output terminal P41 of the fourth FC circuit 40 with reference to the potential of the negative electrode of the DC power supply 101 .

The third FC circuit 30 includes four (third) switching elements Q31 to Q34 and one (third) capacitor C31.

As an example, each of the switching elements Q31 to Q34 is composed of a depletion-type n-channel MOSFET. The switching elements Q31 to Q34 are connected in series in the order of switching elements Q31, Q32, Q33 and Q34 from the input terminal P51 side.

Specifically, the switching element Q31 has a drain electrically connected to the input terminal P51 and a source electrically connected to the drain of the switching element Q32. The switching element Q32 has a source electrically connected to the drain of the switching element Q33. The switching element Q33 has a source electrically connected to the switching element Q34. Switching element Q34 is electrically connected to fourth FC circuit 40 .

Switching elements Q31-Q34 are controlled by control signals S31-S34 output from control circuit 9, respectively.

Also, the switching elements Q31 to Q34 have parasitic diodes D31 to D34, respectively. Each of the parasitic diodes D31 to D34 is configured such that the anode is electrically connected to the source and the cathode is electrically connected to the drain.

The capacitor C31 is electrically connected between a connection point between the switching elements Q31 and Q32 and a connection point between the switching elements Q33 and Q34. In other words, the capacitor C31 is electrically connected in parallel with the series circuit of the switching element Q32 and the switching element Q33.

A connection point between the switching element Q32 and the switching element Q33 is the output end P31 of the third FC circuit 30 .

The capacitor C31 is precharged so that the voltage value of the voltage across it becomes "E/4". In the third FC circuit 30, the switching elements Q31 to Q34 are controlled such that the capacitor C31 repeats charging and discharging around the voltage value "E/4". Therefore, the voltage value of the output voltage of the third FC circuit 30 has three levels of "E", "3E/4", and "E/2", which will be described in detail in the section "Example of Operation". The output voltage of the third FC circuit 30 referred to here is the potential of the output terminal P31 of the third FC circuit 30 with reference to the potential of the negative electrode of the DC power supply 101 .

The second FC circuit 20 includes four (second) switching elements Q21 to Q24 and one (second) capacitor C21.

As an example, each of the switching elements Q21 to Q24 is composed of a depletion-type n-channel MOSFET. The switching elements Q21 to Q24 are connected in series in the order of switching elements Q41, Q42, Q43 and Q44 from the first FC circuit 10 side.

Specifically, the switching element Q41 has a drain electrically connected to the source of the switching element Q34 of the third FC circuit 30, and a source electrically connected to the drain of the switching element Q22. The switching element Q22 has a source electrically connected to the drain of the switching element Q23. The switching element Q23 has a source electrically connected to the switching element Q24. Switching element Q24 is electrically connected to input terminal P52.

That is, the switching elements Q31 to Q34 of the third FC circuit 30 and the switching elements Q21 to Q24 of the second FC circuit 20 are connected in series between the output terminals of the DC power supply 101 (between the pair of input terminals P51 and P52).

Switching elements Q21-Q24 are controlled by control signals S21-S24 output from control circuit 9, respectively.

Also, the switching elements Q21 to Q24 have parasitic diodes D21 to D24, respectively. Each of the parasitic diodes D21 to D24 is configured such that the anode is electrically connected to the source and the cathode is electrically connected to the drain.

The capacitor C21 is electrically connected between the connection point between the switching elements Q21 and Q22 and the connection point between the switching elements Q23 and Q24. In other words, the capacitor C21 is electrically connected in parallel with the series circuit of the switching element Q22 and the switching element Q23.

A connection point between the switching element Q22 and the switching element Q23 is the output end P21 of the second FC circuit 20 .

The capacitor C21 is precharged so that the voltage value of the voltage across it becomes "E/4". In the second FC circuit 20, the switching elements Q21 to Q24 are controlled such that the capacitor C21 repeats charging and discharging around the voltage value "E/4". Therefore, the voltage value of the output voltage of the second FC circuit 20 has three levels of "E/2", "E/4", and "0", which will be described in detail in the "Example of Operation" column. The output voltage of the second FC circuit 20 referred to here is the potential of the output terminal P21 of the second FC circuit 20 with reference to the potential of the negative electrode of the DC power supply 101 .

A connection point between the first FC circuit 10 and the fourth FC circuit 40 and a connection point between the third FC circuit 30 and the second FC circuit 20 are electrically connected. Specifically, the connection point of the source of the switching element Q14 of the first FC circuit 10 and the drain of the switching element Q41 of the fourth FC circuit 40, the source of the switching element Q34 of the third FC circuit 30 and the switching element Q21 of the second FC circuit 20 is electrically connected to the connection point of the drain of the .

In the first to fourth FC circuits 10 to 40, the capacitors C11, C21, C31 and C41 have the same capacitance. The "same capacity" as used herein does not have to be strictly the same value, and may differ within a range of error (for example, about 10%).

The power converter 1 further includes capacitors C1 and C2.

The capacitors C1 and C2 are connected in series between the output terminals of the DC power supply 101 (between the pair of input terminals P51 and P52). The capacitor C1 has one end electrically connected to the input terminal P51 and the other end electrically connected to the input terminal P52 via the capacitor C2. The capacitor C1 and the capacitor C2 are capacitors with the same capacity. Therefore, the voltage value of the voltage across each of the capacitors C1 and C2 is "E/2". Note that the capacitances of the capacitors C1 and C2 do not have to be strictly the same value, and may differ within a margin of error (for example, about 10%).

A connection point between the capacitor C1 and the capacitor C2 is electrically connected to a connection point between the first FC circuit 10 and the fourth FC circuit 40 and a connection point between the third FC circuit 30 and the second FC circuit 20 . That is, the capacitor C1 is electrically connected in parallel with the first FC circuit 10 and the third FC circuit 30, and the capacitor C2 is electrically connected in parallel with the fourth FC circuit 40 and the second FC circuit 20. FIG.

The power converter 1 further includes first to fourth output switch circuits 50-80.

The first output switch circuit 50 has switching elements Q51 and Q52 connected in series. The second output switch circuit 60 has switching elements Q61 and Q62 connected in series. The third output switch circuit 70 has switching elements Q71 and Q72 connected in series. The fourth output switch circuit 80 has switching elements Q81 and Q82 connected in series.

As an example, each of the switching elements Q51, Q52, Q61, Q62, Q71, Q72, Q81, Q82 is composed of a depletion-type n-channel MOSFET.

The first output switch circuit 50 and the fourth output switch circuit 80 are electrically connected in series between the output terminal P11 of the first FC circuit 10 and the output terminal P41 of the fourth FC circuit 40 . Specifically, the switching element Q51 of the first output switch circuit 50 has a drain electrically connected to the connection point of the switching element Q12 and the switching element Q13 in the first FC circuit 10, and a source electrically connected to the drain of the switching element Q52. properly connected. The switching element Q52 has a source electrically connected to the drain of the switching element Q81 in the fourth output switch circuit 80 . The switching element Q81 has a source electrically connected to the drain of the switching element Q82. The switching element Q82 has a drain electrically connected to a connection point between the switching element Q42 and the switching element Q43 in the fourth FC circuit 40 .

The third output switch circuit 70 and the second output switch circuit 60 are electrically connected in series between the output terminal P31 of the third FC circuit 30 and the output terminal P21 of the second FC circuit 20 . Specifically, the switching element Q71 of the third output switch circuit 70 has a drain electrically connected to the connection point of the switching element Q32 and the switching element Q33 in the third FC circuit 30, and a source electrically connected to the drain of the switching element Q72. properly connected. The switching element Q72 has a source electrically connected to the drain of the switching element Q61 in the second output switch circuit 60 . The switching element Q61 has a source electrically connected to the drain of the switching element Q62. The switching element Q62 has a drain electrically connected to a connection point between the switching element Q22 and the switching element Q23 in the second FC circuit 20 .

Switching elements Q51, Q52, Q61, Q62, Q71, Q72, Q81 and Q82 are controlled by control signals S51, S52, S61, S62, S71, S72, S81 and S82 output from control circuit 9, respectively.

A connection point between the first output switch circuit 50 and the second output switch circuit 60 is electrically connected through the filter circuit 90 to the output terminal P61 (first output terminal). A connection point between the third output switch circuit 70 and the fourth output switch circuit 80 is electrically connected through the filter circuit 90 to the output terminal P62 (second output terminal).

The filter circuit 90 includes inductors L91 and L92 and a capacitor C91. The inductor L91 has one end electrically connected to the connection point of the first output switch circuit 50 and the second output switch circuit 60, and the other end electrically connected to the output terminal P61. The inductor L92 has one end electrically connected to the connection point of the third output switch circuit 70 and the fourth output switch circuit 80, and the other end electrically connected to the output terminal P62. The capacitor C91 is electrically connected between the connection point between the inductor L91 and the output terminal P61 and the connection point between the inductor L92 and the output terminal P62.

The control circuit 9 is composed of a microcomputer having a processor and memory. That is, the control circuit 9 is realized by a computer system having a processor and memory. The computer system functions as the control circuit 9 by the processor executing appropriate programs. The program may be prerecorded in a memory, or may be provided by being recorded in a non-temporary recording medium such as a memory card or through an electric communication line such as the Internet.

The control circuit 9 is configured to control the first to fourth FC circuits 10-40. Specifically, the control circuit 9 outputs to the first FC circuit 10 control signals S11 to S14 for driving the switching elements Q11 to Q14, respectively. The control circuit 9 outputs to the second FC circuit 20 control signals S21 to S24 for driving the switching elements Q21 to Q24, respectively. The control circuit 9 outputs to the third FC circuit 30 control signals S31 to S34 for driving the switching elements Q31 to Q34, respectively. The control circuit 9 outputs to the fourth FC circuit 40 control signals S41 to S44 for driving the switching elements Q41 to Q44, respectively.

The control circuit 9 is further configured to control the first to fourth output switch circuits 50-80. Specifically, the control circuit 9 outputs to the first output switch circuit 50 control signals S51 and S52 for driving the switching elements Q51 and Q52, respectively. The control circuit 9 outputs to the second output switch circuit 60 control signals S61 and S62 for driving the switching elements Q61 and Q62, respectively. The control circuit 9 outputs to the third output switch circuit 70 control signals S71 and S72 for driving the switching elements Q71 and Q72, respectively. The control circuit 9 outputs control signals S81 and S82 to the fourth output switch circuit 80 to drive the switching elements Q81 and Q82, respectively.

(2) Operation Example (2.1) Basic Operation Next, the operation of the power converter 1 will be described with reference to FIGS. 2A to 5B. In the following description, voltages are appropriately labeled with "+" or "-" in order to clearly indicate the polarity of the output voltage Vo. The output voltage Vo is the voltage between the pair of output terminals P61 and P62. More specifically, the output voltage Vo is the potential of the output terminal P62 with reference to the potential of the output terminal P61. The polarity of the output voltage Vo is "+" when the potential of the output terminal P61 is higher than the potential of the output terminal P62, and "-" when the potential of the output terminal P61 is lower than the potential of the output terminal P62. . However, when neither "+" nor "-" is attached, "+" is indicated unless otherwise specified.

There are first to eighth patterns as switching patterns of the switching elements of the first to fourth FC circuits 10 to 40 and the first to fourth output switch circuits 50 to 80 (see Tables 1 and 2). The control circuit 9 performs output control processing for switching the switching pattern to any one of the first to eighth switching patterns so that the output voltage Vo becomes an AC voltage.

2A and 2B show the circuit states in the case of the first switching pattern and the second switching pattern, respectively. 3A and 3B show circuit states in the case of the third switching pattern and the fourth switching pattern, respectively. 4A and 4B show circuit states in the case of the fifth switching pattern and the sixth switching pattern, respectively. 5A and 5B show circuit states in the case of the seventh switching pattern and the eighth switching pattern, respectively. In FIGS. 2A to 5B, paths through which the current I does not flow are indicated by broken lines in order to clearly show the circuit state. 2A to 5B, the switching elements are illustrated in a simplified manner, and the illustration of the filter circuit 90 is omitted.

The first switching pattern (see FIG. 2A) is a switching pattern for setting the voltage value of the output voltage Vo to "+E". As shown in Table 1, in the first switching pattern, the switching elements Q11 and Q12 of the first FC circuit 10 are turned on, the switching elements Q13 and Q14 are turned off, and the switching elements Q51 and Q52 of the first output switch circuit 50 are turned on. do. In the first switching pattern, the switching elements Q23 and Q24 of the second FC circuit 20 are turned on, the switching elements Q21 and Q22 are turned off, and the switching elements Q61 and Q62 of the second output switch circuit 60 are turned on.

In the first switching pattern, the potential of the output terminal P61 is "+E" and the potential of the output terminal P62 is "0", so the voltage value of the output voltage Vo is "+E".

Further, in the first switching pattern, the path of the current I flowing through the load 102 does not include the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 . Therefore, the capacitors C11 and C21 are not charged or discharged, and the charges are maintained. Also, in the first switching pattern, the capacitor C31 of the third FC circuit 30 and the capacitor C41 of the fourth FC circuit 40 are not charged or discharged, and the charges are maintained.

The second switching pattern (see FIG. 2B) is a switching pattern for setting the voltage value of the output voltage Vo to "+E/2". As shown in Table 1, in the second switching pattern, the switching elements Q11 and Q13 of the first FC circuit 10 are turned on, the switching elements Q12 and Q14 are turned off, and the switching elements Q51 and Q52 of the first output switch circuit 50 are turned on. do. In the second switching pattern, the switching elements Q22 and Q24 of the second FC circuit 20 are turned on, the switching elements Q21 and Q23 are turned off, and the switching elements Q61 and Q62 of the second output switch circuit 60 are turned on.

Assuming that the voltage value of the voltage Vc11 across the capacitor C11 is "E/4", the potential of the output terminal P61 is "3E/4". Further, if the voltage value of the voltage Vc21 across the capacitor C21 is "E/4", the potential of the output terminal P62 is "E/4". Therefore, in the second switching pattern, the voltage value of the output voltage Vo is "+E/2".

Also, in the second switching pattern, the path of the current I flowing through the load 102 includes the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 . Current I flows in the direction of charging capacitors C11 and C21. Therefore, in the second switching pattern, the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 are charged simultaneously. Further, in the second switching pattern, the capacitor C31 of the third FC circuit 30 and the capacitor C41 of the fourth FC circuit 40 are not charged or discharged, and the charges are maintained.

The third switching pattern (see FIG. 3A) is a switching pattern for setting the voltage value of the output voltage Vo to "+E/2". As shown in Table 1, in the third switching pattern, the switching elements Q12 and Q14 of the first FC circuit 10 are turned on, the switching elements Q11 and Q13 are turned off, and the switching elements Q51 and Q52 of the first output switch circuit 50 are turned on. do. In the third switching pattern, the switching elements Q21 and Q23 of the second FC circuit 20 are turned on, the switching elements Q22 and Q24 are turned off, and the switching elements Q61 and Q62 of the second output switch circuit 60 are turned on.

If the voltage value of the voltage Vc11 across the capacitor C11 is "E/4", the voltage Vc2 across the capacitor C2 is "E/2", so the potential of the output terminal P61 is "3E/4". If the voltage value of the voltage Vc21 across the capacitor C21 is "E/4", the voltage Vc2 across the capacitor C2 is "E/2", so the potential of the output terminal P62 is "E/4". Therefore, in the third switching pattern, the voltage value of the output voltage Vo is "+E/2".

Also, in the third switching pattern, the path of the current I flowing through the load 102 includes the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 . Current I flows in the direction of discharging capacitors C11 and C21. Therefore, in the third switching pattern, the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 are discharged simultaneously. Further, in the third switching pattern, the capacitor C31 of the third FC circuit 30 and the capacitor C41 of the fourth FC circuit 40 are not charged or discharged, and the charges are maintained.

The fourth switching pattern (see FIG. 3B) is a switching pattern for setting the voltage value of the output voltage Vo to "+0". As shown in Table 1, in the fourth switching pattern, the switching elements Q13 and Q14 of the first FC circuit 10 are turned on, the switching elements Q11 and Q12 are turned off, and the switching elements Q51 and Q52 of the first output switch circuit 50 are turned on. do. In the fourth switching pattern, the switching elements Q21 and Q22 of the second FC circuit 20 are turned on, the switching elements Q23 and Q24 are turned off, and the switching elements Q61 and Q62 of the second output switch circuit 60 are turned on.

Since the voltage Vc2 across the capacitor C2 is "+E/2", the potential of the output terminal P61 is "+E/2" and the potential of the output terminal P62 is "+E/2". Therefore, in the fourth switching pattern, the voltage value of the output voltage Vo is "+0".

Further, in the fourth switching pattern, the path of the current I flowing through the load 102 does not include the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 . Therefore, the capacitors C11 and C21 are not charged or discharged, and the charges are maintained. Also, in the fourth switching pattern, the capacitor C31 of the third FC circuit 30 and the capacitor C41 of the fourth FC circuit 40 are not charged or discharged, and the charges are maintained.

A fifth switching pattern (see FIG. 4A) is a switching pattern for setting the voltage value of the output voltage Vo to "-E". As shown in Table 2, in the fifth switching pattern, the switching elements Q31 and Q32 of the third FC circuit 30 are turned on, the switching elements Q33 and Q34 are turned off, and the switching elements Q71 and Q72 of the third output switch circuit 70 are turned on. do. In the fifth switching pattern, the switching elements Q43 and Q44 of the fourth FC circuit 40 are turned on, the switching elements Q41 and Q42 are turned off, and the switching elements Q81 and Q82 of the fourth output switch circuit 80 are turned on.

In the fifth switching pattern, the potential of the output terminal P62 is "E" and the potential of the output terminal P61 is "0", so the voltage value of the output voltage Vo is "-E".

In addition, in the fifth switching pattern, the path of the current I flowing through the load 102 does not include the capacitor C31 of the third FC circuit 30 and the capacitor C41 of the fourth FC circuit 40 . Therefore, the capacitors C31 and C41 are not charged or discharged, and the charges are maintained. Also, in the fifth switching pattern, the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 are not charged or discharged, and the charges are maintained.

The sixth switching pattern (see FIG. 4B) is a switching pattern for setting the voltage value of the output voltage Vo to "-E/2". As shown in Table 2, in the sixth switching pattern, the switching elements Q31 and Q33 of the third FC circuit 30 are turned on, the switching elements Q32 and Q34 are turned off, and the switching elements Q71 and Q72 of the third output switch circuit 70 are turned on. do. In the sixth switching pattern, the switching elements Q42 and Q44 of the fourth FC circuit 40 are turned on, the switching elements Q41 and Q43 are turned off, and the switching elements Q81 and Q82 of the fourth output switch circuit 80 are turned on.

Assuming that the voltage value of the voltage Vc31 across the capacitor C31 is "E/4", the potential of the output terminal P62 is "3E/4". Further, when the voltage value of the voltage Vc41 across the capacitor C41 is "E/4", the potential of the output terminal P61 is "E/4". Therefore, in the sixth switching pattern, the voltage value of the output voltage Vo is "-E/2".

Also, in the sixth switching pattern, the path of the current I flowing through the load 102 includes the capacitor C31 of the third FC circuit 30 and the capacitor C41 of the fourth FC circuit 40 . Current I flows in the direction of charging capacitors C31 and C41. Therefore, in the sixth switching pattern, the capacitor C31 of the third FC circuit 30 and the capacitor C41 of the fourth FC circuit 40 are charged simultaneously. In addition, in the sixth switching pattern, the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 are not charged or discharged, and the charges are maintained.

The seventh switching pattern (see FIG. 5A) is a switching pattern for setting the voltage value of the output voltage Vo to "-E/2". As shown in Table 2, in the seventh switching pattern, the switching elements Q32 and Q34 of the third FC circuit 30 are turned on, the switching elements Q31 and Q33 are turned off, and the switching elements Q71 and Q72 of the third output switch circuit 70 are turned on. do. In the seventh switching pattern, the switching elements Q41 and Q43 of the fourth FC circuit 40 are turned on, the switching elements Q42 and Q44 are turned off, and the switching elements Q81 and Q82 of the fourth output switch circuit 80 are turned on.

If the voltage value of the voltage Vc31 across the capacitor C31 is "E/4", the voltage Vc2 across the capacitor C2 is "E/2", so the potential of the output terminal P62 is "3E/4". If the voltage value of the voltage Vc41 across the capacitor C41 is "E/4", the voltage Vc2 across the capacitor C2 is "E/2", so the potential of the output terminal P61 is "E/4". Therefore, in the seventh switching pattern, the voltage value of the output voltage Vo is "-E/2".

Further, in the seventh switching pattern, the path of the current I flowing through the load 102 includes the capacitor C31 of the third FC circuit 30 and the capacitor C41 of the fourth FC circuit 40 . Current I flows in the direction of discharging capacitors C31 and C41. Therefore, in the seventh switching pattern, the capacitor C31 of the third FC circuit 30 and the capacitor C41 of the fourth FC circuit 40 are discharged simultaneously. Further, in the seventh switching pattern, the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 are not charged or discharged, and the charges are maintained.

The eighth switching pattern (see FIG. 5B) is a switching pattern for setting the voltage value of the output voltage Vo to "-0". As shown in Table 2, in the eighth switching pattern, the switching elements Q33 and Q34 of the third FC circuit 30 are turned on, the switching elements Q31 and Q32 are turned off, and the switching elements Q71 and Q72 of the third output switch circuit 70 are turned on. do. In the eighth switching pattern, the switching elements Q41 and Q42 of the fourth FC circuit 40 are turned on, the switching elements Q43 and Q44 are turned off, and the switching elements Q81 and Q82 of the fourth output switch circuit 80 are turned on.

Since the voltage Vc2 across the capacitor C2 is "+E/2", the potential of the output terminal P62 is "+E/2" and the potential of the output terminal P61 is "+E/2". Therefore, in the fourth switching pattern, the voltage value of the output voltage Vo is "-0".

In addition, in the eighth switching pattern, the path of the current I flowing through the load 102 does not include the capacitor C31 of the third FC circuit 30 and the capacitor C41 of the fourth FC circuit 40 . Therefore, the capacitors C31 and C41 are not charged or discharged, and the charges are maintained. Also, in the eighth switching pattern, the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 are not charged or discharged, and the charges are maintained.

As described above, the switching patterns of the switching elements of the first to fourth FC circuits 10 to 40 and the first to fourth output switch circuits 50 to 80 are switched according to the first to eighth switching patterns. As a result, the voltage value of the output voltage Vo becomes five levels of "-E", [-E/2], "0", "+E/2", and "+E".

When the polarity of the output voltage Vo is positive (+), the control circuit 9 switches the switching pattern among the first to fourth switching patterns (see Table 1 and FIGS. 2A to 3B). Further, when the polarity of the output voltage Vo is negative (-), the control circuit 9 switches the switching pattern among the fifth to eighth switching patterns (see Table 2 and FIGS. 4A to 5B).

The control circuit 9 sets the output voltage Vo to a sine wave and equalizes the charging and discharging times of the capacitors C11, C21, C31, and C41 of the first to fourth FC circuits 10 to 40, respectively. It adjusts the ratio of the length of time the pattern is executed. Specifically, the control circuit 9 generates a PWM (Pulse Width Modulation) signal using two carriers (a first carrier and a second carrier) and a modulation signal, and converts the PWM signal into control signals S11 to S11. Output as S14, S21 to S24, S31 to S34, and S41 to S44.

The first carrier wave and the second carrier wave are triangular waves and are 180° out of phase with each other. The modulation signal is a signal for PWM-controlling the switching element, and the amplitude value is adjusted according to the target voltage value of the output voltage Vo.

The control circuit 9 generates a first signal S1 and a fourth signal S4, which are PWM signals, by comparing the first carrier wave and the modulated signal. The first signal S1 is high (Hi) when the amplitude value of the first carrier wave is less than the amplitude value of the modulating signal, and is low (Low) when the amplitude value of the first carrier wave is greater than or equal to the amplitude value of the modulating signal. It is a square wave that becomes The fourth signal S4 is high (Hi) when the amplitude value of the first carrier wave is greater than or equal to the amplitude value of the modulating signal, and is low (Low) when the amplitude value of the first carrier wave is less than the amplitude value of the modulating signal. It is a square wave that becomes That is, the first signal S1 and the fourth signal S4 are rectangular waves in which high and low are inverted.

The control circuit 9 also generates a second signal S2 and a third signal S3, which are PWM signals, by comparing the second carrier wave and the modulated signal. The second signal S2 is high (Hi) when the amplitude value of the second carrier wave is less than the amplitude value of the modulating signal, and is low (Low) when the amplitude value of the second carrier wave is greater than or equal to the amplitude value of the modulating signal. It is a square wave that becomes The third signal S3 is high (Hi) when the amplitude value of the second carrier wave is greater than or equal to the amplitude value of the modulating signal, and is low (Low) when the amplitude value of the second carrier wave is less than the amplitude value of the modulating signal. It is a square wave that becomes That is, the second signal S2 and the third signal S3 are rectangular waves in which high and low are inverted.

The control circuit 9 outputs the first signal S1 to the switching element Q11 of the first FC circuit 10 and the switching element Q41 of the fourth FC circuit 40 as control signals S11 and S41. The control circuit 9 outputs signals obtained by inverting the first signal S1 to the switching element Q31 of the third FC circuit 30 and the switching element Q21 of the second FC circuit 20 as control signals S31 and S21.

Further, the control circuit 9 outputs the second signal S2 to the switching element Q12 of the first FC circuit 10 and the switching element Q42 of the fourth FC circuit 40 as control signals S12 and S42. The control circuit 9 outputs signals obtained by inverting the second signal S2 to the switching element Q32 of the third FC circuit 30 and the switching element Q22 of the second FC circuit 20 as control signals S32 and S22.

The control circuit 9 also outputs the third signal S3 to the switching element Q13 of the first FC circuit 10 and the switching element Q43 of the fourth FC circuit 40 as control signals S13 and S43. The control circuit 9 outputs signals obtained by inverting the third signal S3 to the switching element Q33 of the third FC circuit 30 and the switching element Q23 of the second FC circuit 20 as control signals S33 and S23.

Further, the control circuit 9 outputs the fourth signal S4 to the switching element Q14 of the fourth FC circuit 40 and the switching element Q44 of the fourth FC circuit 40 as control signals S14 and S44. The control circuit 9 outputs signals obtained by inverting the fourth signal S4 to the switching element Q34 of the third FC circuit 30 and the switching element Q24 of the second FC circuit 20 as control signals S34 and S24.

In this way, the control circuit 9 generates the first to fourth signals S1 to S4 using the two phase-inverted carrier waves (the first half-transmission wave and the second carrier wave) and the modulation signal, and the switching element Q11-Q14, Q21-Q24, Q31-Q34, and Q41-Q44 are PWM-controlled. Therefore, it is possible to equalize the time during which the capacitors C11 and C21 are charged in the second switching pattern and the time during which the capacitors C11 and C21 are discharged in the third switching pattern. In addition, it is possible to equalize the time during which the capacitors C31 and C41 are charged in the fifth switching pattern and the time during which the capacitors C31 and C41 are discharged in the sixth switching pattern.

Furthermore, the control circuit 9 is configured to adjust the charging and discharging times of the capacitors C11, C21, C31 and C41 by correcting the modulation signal. The control circuit 9 receives detection results of voltages Vc11, Vc21, Vc31, and Vc41 across the capacitors C11, C21, C31, and C41, respectively. The control circuit 9 compares the voltage values of the voltages Vc11, Vc21, Vc31, Vc41 across the voltages Vc11, Vc21, Vc31, Vc41 with a target value (for example, "E/4"), and increases or decreases the amplitude value of the modulation signal so as to reduce the difference value. For example, assume that the voltage values of the voltages Vc11 and Vc21 across the capacitors C11 and C21 are lower than the target values. In this case, the control circuit 9 corrects the amplitude value of the modulation signal so that the charging time of the capacitors C11 and C21 becomes longer. This increases the amount of charge in the capacitors C11 and C21, thereby reducing the difference between the voltage values of the voltages Vc11 and Vc21 across the terminals and the target values. Similarly, for capacitors C31 and C41, the difference between the voltage values of both-end voltages Vc31 and Vc41 and the target value is reduced by correcting the amplitude value of the modulation signal.

(2.2) Delay Processing As described above, in the second switching mode, the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 are charged simultaneously. In the third switching mode, the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 are discharged simultaneously. Also, in the fifth switching mode, the capacitor C31 of the third FC circuit 30 and the capacitor C41 of the fourth FC circuit 40 are charged simultaneously. In the sixth switching mode, the capacitor C31 of the third FC circuit 30 and the capacitor C41 of the fourth FC circuit 40 are discharged simultaneously.

Therefore, when the charge/discharge time is adjusted by correcting the modulation signal, both the charge/discharge time of the pair of capacitors C11 and C21 change. Similarly, when the charge/discharge time is adjusted by correcting the modulation signal, the charge/discharge time of the pair of capacitors C31 and C41 both change. Therefore, in the correction process of the modulated signal, the voltage across one of the pair of capacitors cannot be raised and the voltage across the other capacitor can be lowered. For example, the voltage Vc11 across the capacitor C11 may be higher than the target value, and the voltage Vc21 across the capacitor C21 may be lower than the target value. In such a case, in the above modulation signal correction process, only the voltage value across one of the capacitors C11 and C21 is reduced in difference from the target value, and the voltage across the other capacitor is reduced. The value will increase the difference from the target value.

Therefore, the control circuit 9 of this embodiment has a delay mode as an operation mode. In the delay mode, the control circuit 9 adjusts the voltage value of the voltage across one of the pair of capacitors by performing delay processing for delaying a portion of the control signal in addition to the correction processing described above. Here, the delay processing for increasing the voltage Vc21 across the capacitor C21 of the pair of capacitors C11 and C21 will be described.

The control circuit 9 compares the voltage value of the voltage Vc21 across the capacitor C21 of the second FC circuit 20 with a target value (for example, "E/4"). When the voltage value of the voltage Vc21 between both ends is lower than the target value, the control circuit 9 controls part of the control signals S11 to S14 output to the switching elements Q11 to Q14 in the first FC circuit 10 paired with the second FC circuit 20. Delay the signal. Specifically, the control circuit 9 controls the output to the switching element Q12 electrically connected between the high potential side terminal of the capacitor C11 and the output end of the first FC circuit 10 among the switching elements Q11 to Q14. Delay the signal S12. "Delaying the control signal" means that the timing at which the level (high and low) of the control signal switches is delayed compared to the normal time when the control signal is not delayed. In other words, in the delay mode, some control signals are delayed compared to when the operation mode is the normal mode. In the normal mode, when the switching pattern is switched, a control signal is output so that the switching elements that are switched on/off among the plurality of switching elements are switched on/off at the same timing. The term "same timing" as used herein does not have to be strictly simultaneous, and the on/off timings may deviate within a margin of error due to control delays, individual differences in switching elements, and the like. For example, when switching from the first switching pattern to the second switching pattern, the switching element Q12 of the first FC circuit 10 and the switching element Q23 of the second FC circuit 20 are switched from ON to OFF. In the normal mode, the switching element Q12 and the switching element Q23 are switched from on to off at the same timing. When the control signal output to the switching element Q12 is delayed in the delay mode, the switching element Q12 switches from on to off at a timing later than that of the switching element Q23 .

As shown in FIG. 6 , the control circuit 9 includes a signal generator 91 , a delay circuit 92 and a signal selector 93 .

The signal generation unit 91 generates and outputs control signals S11 to S14, S21 to S24, S31 to S34, and S41 to S44 from the first to fourth signals S1 to S4. 6, only the control signals S11 to S14 are shown, and the control signals S21 to S24, S31 to S34, and S41 to S44 are omitted. Of the control signals S11 to S14 generated by the signal generator 91, only the control signal S12 is output to the delay circuit 92 and the signal selector 93. FIG.

The delay circuit 92 outputs to the signal selector 93 a control signal (delayed control signal S12d) obtained by delaying the input control signal S12. The delay circuit 92 may be, for example, an analog delay circuit including a capacitor or the like, or may be a digital delay circuit.

The signal selection unit 93 is a multiplexer and receives the control signal S12 and the delay control signal S12d. The signal selection unit 93 selects one of the control signal S12 and the delay control signal S12d and outputs the selected control signal to the switching element Q12. When the voltage value of the voltage Vc21 across the capacitor C21 of the second FC circuit 20 is lower than the target value, the signal selector 93 outputs the delayed delay control signal S12d to the switching element Q12. Further, when the voltage value of the voltage Vc21 across the capacitor C21 of the second FC circuit 20 is the target value (or higher than the target value), the signal selection unit 93 outputs the non-delayed control signal S12 to the switching element Q12. Output. That is, in this case, among the control signals output to the switching elements Q11 to Q14 of the first FC circuit 10, only the control signal output to the switching element Q12 is delayed.

An example in which the switching pattern switches between the first switching pattern (see FIG. 2A) and the second switching pattern (see FIG. 2B) will be described below with reference to FIG. Here, only the first FC circuit 10 and the second FC circuit 20 will be focused on and explained.

As described above, in the first switching pattern, the switching elements Q11 and Q12 of the first FC circuit 10 are turned on, and the switching elements Q13 and Q14 are turned off. Also, the switching elements Q23 and Q24 of the second FC circuit 20 are turned on, and the switching elements Q21 and Q22 are turned off.

In the second switching pattern, the switching elements Q11 and Q13 of the first FC circuit 10 are turned on, and the switching elements Q12 and Q14 are turned off. The switching elements Q22 and Q24 of the second FC circuit 20 are turned on, and the switching elements Q21 and Q23 are turned off.

That is, in switching from the first switching pattern to the second switching pattern, the switching element Q12 of the first FC circuit 10 is switched from ON to OFF, and the switching element Q13 is switched from OFF to ON. Also, the switching element Q22 of the second FC circuit 20 is switched from off to on, and the switching element Q23 is switched from on to off.

The control circuit 9 sets a dead time for a plurality of switching elements so that the circuit is not short-circuited when switching the switching pattern. The dead time is a period before and after switching of the switching pattern in which all of the switching elements that are switched on/off among the plurality of switching elements are turned off. In switching from the first switching pattern to the second switching pattern, switching elements Q12 and Q13 of the first FC circuit 10 and switching elements Q22 and Q23 of the second FC circuit 20 are switched on/off. Therefore, during the dead time T15 between the period T10 in which the first switching pattern is executed and the period T20 in which the second switching pattern is executed, the switching elements Q12 and Q13 of the first FC circuit 10 and the second FC circuit 20 Switching elements Q22 and Q23 are turned off. As a result, short-circuiting between both ends of the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 is suppressed.

Although detailed description is omitted, dead time is also set when switching to another switching pattern. For example, when switching from the first switching pattern (see FIG. 2A) to the third switching pattern (see FIG. 3A), the switching elements Q11 and Q14 of the first FC circuit 10 and the switching elements Q21 and Q24 of the second FC circuit 20 are turned on. / off is switched. Therefore, during the dead time between the period in which the first switching pattern is executed and the period in which the third switching pattern is executed, the switching elements Q11 and Q14 of the first FC circuit 10 and the switching element Q21 of the second FC circuit 20 , Q24 are turned off. Similarly, during the dead time between the period in which the second switching pattern is executed and the period in which the third switching pattern is executed, the switching elements Q11 to Q14 of the first FC circuit 10 and the switching element Q21 of the second FC circuit 20 ~Q24 is turned off.

Here, a delayed control signal (delayed control signal S12d) is output to the switching element Q12. Therefore, in the dead time T15 when switching from the first switching pattern to the second switching pattern, only the switching element Q12 is turned on during the delay time Td. The delay time Td is the time the delay circuit 92 delays the control signal. Here, the delay time Td is the time difference between the non-delayed control signal S12 and the delayed control signal S12d delayed by the delay circuit 92. FIG. The time length of the delay time Td is shorter than the time length of the dead time T15. This suppresses the short circuit across the circuit, specifically across the capacitor C11.

During the period T10 during which the first switching pattern is executed, the current I does not flow through the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20, so the capacitors C11 and C21 are neither charged nor discharged.

During the delay time Td in the dead time T15, the switching element Q12 is turned on by the delay control signal S12d, and the switching elements Q13, Q22, Q23 are turned off. Therefore, the current I does not flow through the capacitor C11 in the first FC circuit 10 during the delay time Td. In the second FC circuit 20, the switching elements Q22 and Q23 are off, but the current I flows through the capacitor C21 through the parasitic diode D22 of the switching element Q22, thereby charging the capacitor C21. That is, during the delay time Td, the capacitor C11 of the first FC circuit 10 is not charged, but the capacitor C21 of the second FC circuit 20 is charged. During the delay time Td, the potential of the output terminal P61 is "+E" and the potential of the output terminal P62 is "+E/4", so the voltage value of the output voltage Vo is "+3E/4".

When the delay time Td elapses, the switching element Q12 is turned off, so that the capacitor C11 is charged by the current I passing through the parasitic diode D13 of the switching element Q13.

During the period T20 in which the second switching pattern is executed, both the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 are charged as described above.

When switching from the second switching pattern to the first switching pattern, the switching element Q12 is turned off during the delay time Td in the period T10 during which the first switching pattern is executed. Therefore, during this delay time Td, the capacitor C11 of the first FC circuit 10 is charged and the capacitor C21 of the second FC circuit 20 is neither charged nor discharged.

That is, only the capacitor C21 of the capacitors C11 and C21 is charged during the delay time Td when switching from the first switching pattern to the second switching pattern. During the delay time Td when switching from the second switching pattern to the first switching pattern, only the capacitor C11 of the capacitors C11 and C21 is charged.

Here, as described above, the voltage value of the output voltage Vo is "+E" in the first switching pattern, and the voltage value of the output voltage Vo is "+E/2" in the second switching pattern. Therefore, when the switching pattern switches between the first switching pattern and the second switching pattern, the current value of the current I increases in the first switching pattern. Also, in the second switching pattern, the current value of the current I changes so as to decrease.

Therefore, the charge amount of the capacitor C21 charged during the delay time Td immediately after the period T10 during which the first switching pattern is executed is equal to the capacitor charged during the delay time Td at the start of the period T20 during which the second switching pattern is executed. It becomes larger than the charge amount of C11. As a result, the voltage Vc21 across the capacitor C21 of the second FC circuit 20 rises.

For example, assume that the voltage value of the voltage Vc11 across the capacitor C11 of the first FC circuit 10 is higher than the target value, and the voltage value of the voltage Vc21 across the capacitor C21 of the second FC circuit 20 is lower than the target value. In this case, the control circuit 9 performs the above-described correction processing of the modulated signal so that the voltage Vc11 across the capacitor C11, whose voltage value is higher than the target value, matches the target value. Only by correcting the modulated signal, the voltage value of the voltage Vc21 across the capacitor C21 will further decrease. Therefore, the control circuit 9 performs delay processing for delaying the control signal to be output to the switching element Q12 in addition to correction processing of the modulated signal. As a result, the voltage Vc21 across the capacitor C21 rises.

That is, the control circuit 9 performs both the correction processing of the modulated signal and the delay processing of the control signal so that the voltages Vc11, Vc11, Vc11, Vc11, Vc11, Vc11, Vc21 can be brought closer to the target value.

In the example described above, the voltage Vc21 across the capacitor C21 of the second FC circuit 20 is increased by the delay processing for delaying the control signal output to the switching element Q12 of the first FC circuit 10. FIG. When increasing the voltage value of the voltage Vc11 across the capacitor C11 of the first FC circuit 10, the control circuit 9 performs delay processing to delay the control signal output to the switching element Q23 of the second FC circuit 20. FIG. This increases the voltage Vc11 across the capacitor C11. That is, in the delay mode, the control circuit 9 performs delay processing for delaying the control signal output to the switching element Q12 of the first FC circuit 10 and delay processing for delaying the control signal output to the switching element Q23 of the second FC circuit 20. , or

In addition, although the set of the first FC circuit 10 and the second FC circuit 20 has been described as an example, the set of the third FC circuit 30 and the fourth FC circuit 40 is also similarly controlled by delay processing of the control signal. Voltages Vc31 and Vc41 can be controlled individually. When increasing the voltage value of the voltage Vc41 across the capacitor C41 of the fourth FC circuit 40, the control circuit 9 performs delay processing to delay the control signal output to the switching element Q32 of the third FC circuit 30. FIG. Further, when increasing the voltage value of the voltage Vc31 across the capacitor C31 of the third FC circuit 30, delay processing is performed to delay the control signal output to the switching element Q43 of the fourth FC circuit 40. FIG. That is, in the delay mode, the control circuit 9 performs delay processing for delaying the control signal output to the switching element Q32 of the third FC circuit 30 and delay processing for delaying the control signal output to the switching element Q43 of the fourth FC circuit 40. , or

The control circuit 9 includes a delay circuit 92 and a signal selector 93 corresponding to the switching elements Q12, Q23, Q32, Q43. Thereby, the control circuit 9 can individually delay the control signals output to the switching elements Q12, Q23, Q32, Q43. Note that FIG. 6 shows only the delay circuit 92 and the signal selector 93 corresponding to the switching element Q12.

Thus, in the delay mode, when the control circuit 9 adjusts the voltage across the capacitor of one FC circuit of the pair of FC circuits, it outputs to a part of the plurality of switching elements of the other FC circuit. Delay processing is performed to delay the control signal.

In other words, in the delay processing, the switching elements between the output terminals (P11, P31) in the high potential side FC circuits (first FC circuit 10, third FC circuit 30) and the high potential side terminals of the capacitors (C11, C31) Delay the control signal output to (Q12, Q32). As a result, the voltage across the capacitors (C21, C41) of the paired FC circuits (second FC circuit 20, fourth FC circuit 40) on the low potential side rises.

In addition, in the delay processing, switching elements ( The control signal output to Q23, Q43) is delayed. As a result, the voltage across the capacitors (C11, C31) of the paired high potential side FC circuits (the first FC circuit 10 and the third FC circuit 30) rises.

Due to the above delay processing, the charge/discharge amounts of the capacitors C11, C21, C31, and C41 are changed, and the voltages Vc11, Vc21, Vc31, and Vc41 can be individually adjusted.

The target values of the voltages Vc11, Vc21, Vc31, and Vc41 across the capacitors C11, C21, C31, and C41 are not limited to "E/4", and may be other values or different values. good too.

(4) Modifications (4.1) First Modification In the example described above, the control circuit 9 delays the control signals output to the switching elements Q12, Q23, Q32, and Q43. The output control signal may be delayed.

For example, the control circuit 9 may perform delay processing for delaying the control signal output to the switching element Q11 among the switching elements Q11 to Q14 of the first FC circuit 10. FIG. In this case, the capacitor C11 of the first FC circuit 10 discharges more than the capacitor C21 of the second FC circuit 20 due to the delay of the control signal output to the switching element Q11. For example, when switching from the third switching pattern (see FIG. 3A) to the first switching pattern (see FIG. 2A), only the capacitor C11 is discharged during the delay time when the switching element Q11 is turned off, and the capacitor C21 is charged and discharged. is not performed. During this delay time, the potential of the output terminal P61 is "+E/4" and the potential of the output terminal P62 is "0", so the voltage value of the output voltage Vo is "+E/4".

As a result, the discharge amount of the capacitor C11 becomes larger than the discharge amount of the capacitor C21. Therefore, the voltage Vc11 across the capacitor C11 drops.

Similarly, the control circuit 9 reduces the voltage Vc21 across the capacitor C21 of the second FC circuit 20 by delaying the control signal output to the switching element Q24 of the second FC circuit 20. FIG. In addition, the control circuit 9 reduces the voltage Vc31 across the capacitor C31 of the third FC circuit 30 by delaying the control signal output to the switching element Q31 of the third FC circuit 30 . Further, the control circuit 9 reduces the voltage Vc41 across the capacitor C41 of the fourth FC circuit 40 by delaying the control signal output to the switching element Q44 of the fourth FC circuit 40. FIG.

Thus, in the delay mode, when the control circuit 9 adjusts the voltage across the capacitor of one of the pair of FC circuits, it outputs to some of the switching elements of one of the FC circuits. Delay processing is performed to delay the control signal.

In other words, in the delay processing, switching elements (Q11, Q31 ) is delayed. As a result, the voltage across the capacitors (C11, C31) of the high potential side FC circuit (first FC circuit 10, third FC circuit 30) drops.

Further, in the delay processing, the switching elements (Q24, Q44) between the low potential side terminals of the capacitors (C21, C41) of the low potential side FC circuits (the second FC circuit 20, the fourth FC circuit 40) and the DC power supply 101 delays the control signal output to As a result, the voltage across the capacitors (C21, C41) of the FC circuits (second FC circuit 20, fourth FC circuit 40) on the low potential side drops.

Due to the above delay processing, the charge/discharge amounts of the capacitors C11, C21, C31, and C41 are changed, and the voltages Vc11, Vc21, Vc31, and Vc41 can be individually adjusted.

Note that the control circuit 9 may perform delay processing for delaying the control signals to be output to the plurality of switching elements in the FC circuit. For example, among the switching elements Q11 to Q14 of the first FC circuit 10, the control signal output to both switching elements Q11 and Q12 may be delayed. In this case, the voltage Vc11 across the capacitor C11 of the first FC circuit 10 drops, and the voltage Vc21 across the capacitor C21 of the second FC circuit 20 rises. Similarly, the control circuit 9 delays the control signals output to the switching elements Q23 and Q24 of the second FC circuit 20, the switching elements Q31 and Q32 of the third FC circuit 30, and the switching elements Q43 and Q44 of the fourth FC circuit 40. good too. This makes it possible to increase the change in the charge/discharge amount of the capacitor due to the delay processing.

Further, the control circuit 9 may delay the control signal output to the switching elements Q13 and Q14 of the first FC circuit 10. FIG. Similarly, the control circuit 9 delays the control signals output to the switching elements Q21 and Q22 of the second FC circuit 20, the switching elements Q33 and Q34 of the third FC circuit 30, and the switching elements Q41 and Q42 of the fourth FC circuit 40. good too. However, when these switching elements Q13, Q14, etc. are on, current flows from the source to the drain in any one of the first to eighth switching patterns. Therefore, even if a normally ON state is turned OFF due to delay processing, a current flows through the parasitic diode. Therefore, the change in the charge/discharge amount of the capacitor due to delay processing is relatively small. However, when the power factor is changed, there is a period in which current flows from the drain to the source. change becomes larger.

Further, in the delay mode, the control circuit 9 may perform delay processing for delaying the control signal for both of the pair of FC circuits, and adjust the voltages across the capacitors of both of the pair of FC circuits. For example, the control circuit 9 performs delay processing to delay the control signal output to the switching element Q12 of the first FC circuit 10 and the control signal output to the switching element Q23 of the second FC circuit 20. FIG. As a result, the voltages Vc11 and Vc22 across the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 can be increased. Further, the control circuit 9 performs delay processing to delay the control signal output to the switching element Q11 of the first FC circuit 10 and the control signal output to the switching element Q24 of the second FC circuit 20. FIG. As a result, the voltages Vc11 and Vc22 across the capacitor C11 of the first FC circuit 10 and the capacitor C21 of the second FC circuit 20 can be lowered. Similarly, in the delay mode, the control circuit 9 may perform delay processing for delaying control signals for both the third FC circuit 30 and the fourth FC circuit 40 .

(4.2) Second Modification The control circuit may be configured to change the delay time of the control signal. For example, the control circuit may change the delay time according to the magnitude of the voltage difference between the voltage across the capacitor and the target value. As a result, it is possible to reduce the time required for the voltage across the capacitor to match the target value.

(4.3) Other Modifications The above embodiment is just one of various embodiments of the present disclosure. The above-described embodiment can be modified in various ways according to design and the like, as long as the object of the present disclosure can be achieved. Also, functions similar to those of the control circuit 9 may be embodied by a control method, a computer program, a recording medium recording the program, or the like.

A control method according to one aspect is a control method for a pair of flying capacitor circuits (a set of a first FC circuit 10 and a second FC circuit 20, a set of a third FC circuit 30 and a fourth FC circuit 40) of a power converter. Each of the pair of flying capacitor circuits has a capacitor and a plurality of switching elements electrically connected to the capacitor. A pair of flying capacitor circuits are electrically connected in parallel between output terminals of the DC power supply. The control method includes output control processing and delay processing. In the output control process, a plurality of control signals for individually controlling a plurality of switching elements are output to each of the pair of flying capacitor circuits. In the delay processing, some control signals among the plurality of control signals are delayed with respect to at least one flying capacitor circuit of the pair of flying capacitor circuits.

A program according to one aspect is a program for causing a computer system to execute the control method described above.

The control circuit 9 of the power converter 1 in the present disclosure includes a computer system. A computer system is mainly composed of a processor and a memory as hardware. The function of the control circuit 9 of the power converter 1 in the present disclosure is realized by the processor executing a program recorded in the memory of the computer system. The program may be recorded in advance in the memory of the computer system, may be provided through an electric communication line, or may be recorded in a non-temporary recording medium such as a computer system-readable memory card, optical disk, or hard disk drive. may be provided. A processor in a computer system consists of one or more electronic circuits, including semiconductor integrated circuits (ICs) or large scale integrated circuits (LSIs). The integrated circuit such as IC or LSI referred to here is called differently depending on the degree of integration, and includes integrated circuits called system LSI, VLSI (Very Large Scale Integration), or ULSI (Ultra Large Scale Integration). In addition, a field-programmable gate array (FPGA) that is programmed after the LSI is manufactured, or a logic device capable of reconfiguring the bonding relationship inside the LSI or reconfiguring the circuit partitions inside the LSI may also be adopted as the processor. can be done. A plurality of electronic circuits may be integrated into one chip, or may be distributed over a plurality of chips. A plurality of chips may be integrated in one device, or may be distributed in a plurality of devices. A computer system, as used herein, includes a microcontroller having one or more processors and one or more memories. Accordingly, the microcontroller also consists of one or more electronic circuits including semiconductor integrated circuits or large scale integrated circuits.

In the example described above, the power conversion device 1 is configured to output single-phase AC power. may be configured.

(summary)
A power conversion device (1) according to a first aspect includes a pair of flying capacitor circuits (a set of a first flying capacitor circuit 10 and a second flying capacitor circuit 20, a set of a third flying capacitor circuit 30 and a fourth flying capacitor circuit 40). ) and a control circuit (9) for controlling a pair of flying capacitor circuits. Each of the pair of flying capacitor circuits includes capacitors (C11, C21, C31, C41) and a plurality of switching elements (Q11 to Q14, Q21 to Q24) electrically connected to the capacitors (C11, C21, C31, C41). , Q31 to Q34, Q41 to Q44). A pair of flying capacitor circuits are electrically connected in parallel between output terminals of a DC power supply (101). A control circuit (9) outputs a plurality of control signals (S11 , S14, S21-S24, S31-S34, S41-S44). The control circuit (9) applies a plurality of control signals (S11 to S14, S21 to S24, S31 to S34, S41 to S44 ) has a delay mode for delaying some of the control signals.

According to this aspect, by delaying some of the control signals, the charge/discharge amount of the capacitor of the flying capacitor circuit is changed, and the voltage across the capacitor can be adjusted.

A power conversion device (1) according to a second aspect includes two sets of a pair of flying capacitor circuits in the first aspect. The two pairs of flying capacitor circuits are a set of a first flying capacitor circuit (10) and a second flying capacitor circuit (20) and a third flying capacitor circuit (30) and a fourth flying capacitor circuit (40). and a set of A series circuit of a first flying capacitor circuit (10) on the high potential side and a fourth flying capacitor circuit (40) on the low potential side, and a third flying capacitor on the high potential side, between output terminals of a DC power supply (101). A series circuit of the circuit (30) and the second flying capacitor circuit (20) on the low potential side is connected in parallel. A connection point between the first flying capacitor circuit (10) and the fourth flying capacitor circuit (40) is electrically connected to a connection point between the third flying capacitor circuit (30) and the second flying capacitor circuit (20) ing.

According to this aspect, the voltage across the capacitor in each flying capacitor circuit can be individually adjusted.

A power conversion device (1) according to a third aspect is, in the second aspect, a first output switch circuit (50), a second output switch circuit (60), a third output switch circuit (70), and a fourth an output switch circuit (80). The first output switch circuit (50) is electrically connected between the output end (P11) of the first flying capacitor circuit (10) and the first output terminal (P61). The second output switch circuit (60) is electrically connected between the output end (P21) of the second flying capacitor circuit (20) and the second output terminal (P22). The third output switch circuit (70) is electrically connected between the output terminal (P31) of the third flying capacitor circuit (30) and the second output terminal (P22). The fourth output switch circuit (80) is electrically connected between the output terminal (P41) of the fourth flying capacitor circuit (40) and the first output terminal (P61).

According to this aspect, the output of each flying capacitor circuit can be controlled.

In the power conversion device (1) according to the fourth aspect, in any one of the first to third aspects, the control circuit (9) has, in the delay mode, at least one flying capacitor circuit of the pair of flying capacitor circuits Some control signals are delayed based on the voltages (Vc11, Vc21, Vc31, Vc41) across the capacitors (C11, C21, C31, C41).

According to this aspect, by delaying the control signal, the voltage across the capacitor can be controlled to match the target value.

In the power converter (1) according to the fifth aspect, in any one of the first to fourth aspects, the delay time (Td) of some of the control signals is shorter than the dead time of the plurality of switching elements.

According to this aspect, short-circuiting of the circuit due to the delay of the control signal is suppressed.

In the power converter (1) according to the sixth aspect, in any one of the first to fifth aspects, the control circuit (9) is configured to be able to change the delay time of some of the control signals.

According to this aspect, the adjustment amount of the voltage across the capacitor can be increased or decreased.

In the power conversion device (1) according to the seventh aspect, in any one of the first to sixth aspects, the control circuit (9), in the delay mode, provides a plurality of control signals to both the pair of flying capacitor circuits delay some of the control signals.

According to this aspect, by delaying some of the control signals, the charge/discharge amount of the capacitor of the flying capacitor circuit is changed, and the voltage across the capacitor can be adjusted.

In the power conversion device (1) according to the eighth aspect, in any one of the first to sixth aspects, the control circuit (9), in the delay mode, controls only one flying capacitor circuit of the pair of flying capacitor circuits. , some of the plurality of control signals are delayed.

According to this aspect, by delaying some of the control signals, the charge/discharge amount of the capacitor of the flying capacitor circuit is changed, and the voltage across the capacitor can be adjusted.

A control method according to a ninth aspect includes a pair of flying capacitor circuits (a set of a first flying capacitor circuit 10 and a second flying capacitor circuit 20, a set of a first flying capacitor circuit 10 and a second flying capacitor circuit 20, a third flying capacitor circuit 30 and a fourth flying capacitor A set of circuits 40). Each of the pair of flying capacitor circuits includes capacitors (C11, C21, C31, C41) and a plurality of switching elements (Q11 to Q14, Q21 to Q24) electrically connected to the capacitors (C11, C21, C31, C41). , Q31 to Q34, Q41 to Q44). A pair of flying capacitor circuits are electrically connected in parallel between output terminals of a DC power supply (101). The control method includes output control processing and delay processing. In the output control process, a plurality of control signals for individually controlling a plurality of switching elements are output to each of the pair of flying capacitor circuits. In the delay processing, some of the plurality of control signals are delayed with respect to at least one flying capacitor circuit of the pair of flying capacitor circuits.

According to this aspect, by delaying some of the control signals, the charge/discharge amount of the capacitor of the flying capacitor circuit is changed, and the voltage across the capacitor can be adjusted.

A program according to the tenth aspect causes a computer system to execute the control method according to the ninth aspect.

According to this aspect, by delaying some of the control signals, the charge/discharge amount of the capacitor of the flying capacitor circuit is changed, and the voltage across the capacitor can be adjusted.

1 power converter 10 first flying capacitor circuit (flying capacitor circuit)
20 second flying capacitor circuit (flying capacitor circuit)
30 third flying capacitor circuit (flying capacitor circuit)
40 fourth flying capacitor circuit (flying capacitor circuit)
50 first output switch circuit 60 second output switch circuit 70 third output switch circuit 80 fourth output switch circuit C11, C21, C31, C41 capacitors Q11 to Q14, Q21 to Q24, Q31 to Q34, Q41 to Q44 switching element S11 ~S14, S21~S24, S31~S34, S41~S44 Control signals P11, P21, P31, P41 Output terminal P61 Output terminal (first output terminal)
P62 output terminal (second output terminal)

Claims (9)

two sets of a pair of flying capacitor circuits;two sets ofa control circuit that controls a pair of flying capacitor circuits,
included in the two sets of paired flying capacitor circuits each of the pair of flying capacitor circuits has a capacitor and a plurality of switching elements electrically connected to the capacitor;
The pair of flying capacitor circuits are electrically connected between the output terminals of the DC power supply.in contact withis continued,
The control circuit is
configured to output a plurality of control signals for individually controlling the plurality of switching elements to each of the pair of flying capacitor circuits,
As an operating mode,
A control signal for a switching element among the plurality of switching elements for one flying capacitor circuit of the pair of flying capacitor circuits to switch on/off, and a control signal for switching on/off among the plurality of switching elements for the other flying capacitor circuit. A normal mode in which the control signal for the switching element to be switched is output at the same timing;
for at least one of the pair of flying capacitor circuitsA control signal for a switching element that switches ON/OFF among the plurality of switching elements to be switched from the output timing in the normal modedelayto outputdelay modeandYes death,
The two sets of paired flying capacitor circuits are:
a set of a first flying capacitor circuit and a second flying capacitor circuit;
a third flying capacitor circuit and a set of fourth flying capacitor circuits;
A series circuit of the first flying capacitor circuit on the high potential side and the fourth flying capacitor circuit on the low potential side, and the third flying capacitor circuit on the high potential side and the low potential side are provided between the output terminals of the DC power supply. A series circuit with the second flying capacitor circuit of is connected in parallel,
A connection point between the first flying capacitor circuit and the fourth flying capacitor circuit and a connection point between the third flying capacitor circuit and the second flying capacitor circuit are electrically connected,
Power converter. a first output switch circuit electrically connected between an output terminal of the first flying capacitor circuit and a first output terminal;
a second output switch circuit electrically connected between the output terminal of the second flying capacitor circuit and a second output terminal;
a third output switch circuit electrically connected between the output terminal of the third flying capacitor circuit and the second output terminal;
a fourth output switch circuit electrically connected between the output terminal of the fourth flying capacitor circuit and the first output terminal;
The power converter according to claim 1. In the delay mode, the control circuit controls at least one flying capacitor of the pair of flying capacitor circuits based on a voltage across the capacitor of at least one of the pair of flying capacitor circuits. delaying a control signal for a switching element that switches on/off among the plurality of switching elements for the circuit;
The power converter according to claim 1 or 2. A delay time of a control signal for a switching element that switches on/off among the plurality of switching elements for at least one flying capacitor circuit of the pair of flying capacitor circuits is shorter than a dead time of the plurality of switching elements. ,
The power converter according to any one of claims 1 to 3. The control circuit is configured to be able to change a delay time of a control signal for a switching element among the plurality of switching elements for switching ON/OFF for at least one flying capacitor circuit of the pair of flying capacitor circuits. ,
The power converter according to any one of claims 1 to 4. In the delay mode, the control circuit delays, among the plurality of control signals, a control signal for a switching element that switches ON/OFF among the plurality of switching elements for both of the pair of flying capacitor circuits. ,
The power converter according to any one of claims 1 to 5. In the delay mode, the control circuit switches ON/OFF of the plurality of switching elements among the plurality of control signals for only one flying capacitor circuit of the pair of flying capacitor circuits. delaying the control signal to the switching element;
The power converter according to any one of claims 1 to 5. A control method for two pairs of flying capacitor circuits included in a power conversion device,
each of the pair of flying capacitor circuits included in the two pairs of flying capacitor circuits has a capacitor and a plurality of switching elements electrically connected to the capacitor;
The pair of flying capacitor circuits are electrically connected between output terminals of a DC power supply,
output control processing for outputting a plurality of control signals for individually controlling the plurality of switching elements for each of the pair of flying capacitor circuits;
The operation mode of the output control process is
A control signal for a switching element among the plurality of switching elements for one flying capacitor circuit of the pair of flying capacitor circuits to switch on/off, and a control signal for switching on/off among the plurality of switching elements for the other flying capacitor circuit. A normal mode in which the control signal for the switching element to be switched is output at the same timing;
A delay mode in which a control signal for a switching element that switches on/off among the plurality of switching elements for at least one flying capacitor circuit of the pair of flying capacitor circuits is output with a delay from the output timing in the normal mode. and including
The two sets of paired flying capacitor circuits are:
a set of a first flying capacitor circuit and a second flying capacitor circuit;
a third flying capacitor circuit and a set of fourth flying capacitor circuits;
A series circuit of the first flying capacitor circuit on the high potential side and the fourth flying capacitor circuit on the low potential side, and the third flying capacitor circuit on the high potential side and the low potential side are provided between the output terminals of the DC power supply. A series circuit with the second flying capacitor circuit of is connected in parallel,
A connection point between the first flying capacitor circuit and the fourth flying capacitor circuit and a connection point between the third flying capacitor circuit and the second flying capacitor circuit are electrically connected,
control method. A program for causing a computer system to execute the control method according to claim 8.

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