JP7111019B2 - unit parallel inverter - Google Patents

Description

The present invention relates to a unit parallel inverter in which two chopper circuits are connected in parallel, and more particularly to an interleave gate instruction generation method.

In order to reduce the size and weight of the step-up/step-down chopper, there is a method called an interleave method in which a plurality of chopper circuits are connected in parallel. FIG. 5 is a diagram showing a unit parallel inverter in which two chopper circuits are connected in parallel. In the interleave method, the switching cycles of the two chopper circuits connected in parallel are shifted and the two chopper circuits are operated in opposite phases to reduce the ripple current of the capacitor and reduce the size of the capacitor.

Further, Non-Patent Document 1 discloses a method of integrating two cores into one by coupling two reactors for a chopper circuit. By adopting such a configuration, the number of parts is reduced, and the size of the reactor is reduced by reducing the current ripple due to mutual induction.

As a method for generating gate commands for the two chopper circuits connected in parallel, as shown in FIGS. 6 and 7, a carrier signal is generated for each chopper circuit and the phase of each carrier signal is shifted by 180°. is common. Gate commands S _A1 and S _B1 are generated by comparing the carrier signal with the duty signal of the A-phase first unit and the duty signal of the B-phase second unit. As a method for generating the gate commands S _A1 and S _B1 , Patent Documents 1 and 2 describe that the phase difference between the carrier signals of n parallel chopper circuits should be 360°/n.

Japanese Unexamined Patent Application Publication No. 2011-061901 JP 2013-220028 A

"Characteristic Analysis and Design of Automotive Boost Chopper Circuit Using Coupled Inductors", Journal of Power Electronics Society, Vol. 39 (2014.3)

However, this method of generating carrier signals for each chopper circuit and setting the phase difference of each carrier signal may not be possible depending on the configuration of the control circuit. For example, when using an existing control circuit and using the PWM function of a microcomputer, the function to generate two carrier signals and invert the sign of one of the carrier signals is not installed, or the carrier generation unit is an ASIC ( Application Specific Integrated Circuit), and the logic circuit may not be changed.

Due to the above problems, Patent Documents 1 and 2 describe a gate command generation method when three or more chopper circuits are connected in parallel. The production method is not described.

From the above, it is a subject to propose a gate instruction generation method in a unit parallel inverter that performs interleaved driving in which two chopper circuits are connected in parallel.

The present invention has been devised in view of the conventional problems described above, and one aspect thereof has a first unit having two switching elements connected in series, and two switching elements connected in series, A second unit connected in parallel with the first unit, a first reactor having one end connected to a connection point of two switching elements of the first unit, and a connection point of the two switching elements of the second unit and a second reactor having one end connected and the other end connected to the other end of the first reactor, the unit parallel inverter performing interleaved driving, wherein a carrier signal common to the first and second units is and an inverting unit that inverts the duty signal of the second unit to a symmetrical value based on an intermediate value between the upper limit value and the lower limit value of the carrier signal and outputs it as a corrected duty signal. a first PWM operation section that performs PWM control by comparing the duty signal of the first unit and the carrier signal and outputs a gate command of the first unit; the corrected duty signal of the second unit and the carrier signal; and a logic inversion unit that logically inverts the output of the second PWM calculation unit and outputs it as a gate command for the second unit. .

Further, as one aspect thereof, when the upper limit value and the lower limit value of the carrier signal are positive/negative symmetrical values, the inverting section converts the sign of the duty signal of the second unit to the corrected duty signal. It is characterized by outputting.

Further, as another aspect, when the upper limit value and the lower limit value of the carrier signal are not positive and negative symmetrical values, the inverting section calculates the duty signal of the second unit from a value obtained by adding the upper limit value and the lower limit value of the carrier signal. is output as the corrected duty signal.

According to the present invention, it is possible to generate a gate command in a unit parallel inverter that performs interleaved driving in which two chopper circuits are connected in parallel.

4 is a control block diagram of the unit parallel inverter in Embodiment 1. FIG. 4 is a time chart showing each signal in the first embodiment; FIG. 10 is a control block diagram of a unit parallel inverter according to the second embodiment; 4 is a time chart showing each signal in the second embodiment; The figure which shows the unit parallel inverter which connected two chopper circuits in parallel. FIG. 2 is a control block diagram of a conventional unit parallel inverter; A time chart showing each signal of a conventional unit parallel inverter.

Embodiments 1 and 2 of the unit parallel inverter according to the present invention will be described in detail below with reference to FIGS. 1 to 5. FIG.

[Embodiment 1]
First, based on FIG. 5, the main circuit of the unit parallel inverter in the first embodiment will be described. Embodiments 1 and 2 assume a unit parallel inverter in which two chopper circuits are connected in parallel, and do not assume a configuration in which three or more chopper circuits are connected in parallel.

As shown in FIG. 5, in the unit parallel inverter in Embodiment 1, two first and second units A and B of A phase and B phase are connected in parallel. In the first unit A, a first switching element A1 and a second switching element A2 are connected in series. Similarly, in the second unit B, the first switching element B1 and the second switching element B2 are connected in series.

One end of a first reactor L1 is connected to the connection point between the A-phase first switching element A1 and the second switching element A2, and the connection point between the B-phase first switching element B1 and the second switching element B2 is connected to the _first reactor L1. One end of the _two reactors L2 is connected. The other ends of the first and second reactors L ₁ and L ₂ are connected.

The voltage between the connection point of the first and second reactors L ₁ and L ₂ and the connection point of the second switching elements A 2 and B 2 is defined as the low voltage side voltage detection value V _low . Also, the voltage between the connection point of the first switching elements A1 and B1 and the connection point of the second switching elements A2 and B2 is defined as the _high voltage side voltage detection value Vhigh.

Let I _L be the current on the low voltage side V _low side of the connection point of the first and second reactors L ₁ and L ₂ , let IL be the current flowing through the first reactor L ₁ , and let I _L1 be the current flowing through the second reactor L ₂ . be I _L2 . Also, let S _A1 , S _A2 , S _B1 , and S _B2 be the gate commands for the switching elements A1, A2, B1, and B2.

FIG. 1 shows a control block configuration of a unit parallel inverter according to the first embodiment. In the first embodiment, the case where the upper limit value and the lower limit value of the carrier signal are positive/negative symmetrical values such as 1 and -1 will be described.

The DC voltage control unit 1 performs voltage control so that the _high voltage side voltage detection value Vhigh follows the DC voltage command value, and outputs it as a current command value _{IL_ref} . The current command value I _{L_ref} is the current command value of the current I _L to flow to the low voltage side voltage detection value V _low side. The multiplication unit 2 outputs half the value of the current command value I _{L_ref} as the first reactor current command value and the second reactor current command value to flow through the first and second reactors L ₁ and L ₂ of each phase.

The first current control unit 3 inputs the detected value of the current I _L1 and the first reactor current command value, performs current control, and outputs it as a duty signal for the first unit. The second current control unit 4 inputs the detected value of the current I _L2 and the second reactor current command value, performs current control, and outputs it as a duty signal for the second unit. A carrier signal generator 6 generates a carrier signal common to the A-phase and B-phase first and second units.

The inverting unit 5 inverts the duty signal of the second unit to a symmetrical value based on an intermediate value between the upper limit value and the lower limit value of the carrier signal, and outputs it as a corrected duty signal. In the first embodiment, a value obtained by inverting the sign of the duty signal of the second unit is used as the corrected duty signal.

When the upper and lower limits of the carrier signal are positive and negative symmetrical values, the intermediate value is 0. Therefore, the value obtained by inverting the symmetrical value with respect to 0 is the value with the sign inverted. Therefore, in the first embodiment, the value obtained by inverting the sign of the duty signal of the second unit in the inverter 5 is used as the corrected duty signal.

The first PWM calculator 7 performs PWM control by comparing the duty signal of the first unit and the carrier signal, and outputs gate commands S _A1 and S _A2 . A second PWM calculation unit 8 performs PWM control by comparing the corrected duty signal and the carrier signal. A logical inversion unit 9 logically inverts the output of the second PWM operation unit 8 and outputs it as gate commands S _B1 and S _B2 .

Thus, in the first embodiment, the outputs of the first and second current controllers 3 and 4 are input to the first and second PWM calculators 7 and 8. , second unit) is inverted in sign and input to the first and second PWM calculation units 7 and 8 . Then, the PWM operation output whose sign is inverted is logically inverted to generate a final gate command. In FIG. 1, the sign of the duty signal of the second unit is inverted.

FIG. 2 is a time chart showing each signal of the unit parallel inverter in the first embodiment. As shown in FIG. 2, in the first embodiment, the carrier signal is shared between the first and second units. PWM control is performed by comparing the duty signal of the first unit (phase A) and the carrier signal, and the gate command S _A1 is output.

Further, the duty signal of the second unit (phase B) is generated by the inverter 5 with the intermediate value (0.0) between the upper limit value (1.0) and the lower limit value (-1.0) of the carrier signal as a reference, Flips to symmetrical values. If the duty signal of the second unit (phase B) is set to 0.6 and is symmetrically inverted with respect to the intermediate value 0.0, the corrected duty signal will be -0.6. In the first embodiment, when the duty signal of the second unit (phase B) is 0.6, the sign is inverted to output -0.6 as the corrected duty signal.

In the second PWM operation section 8, PWM control is performed by comparing the corrected duty signal and the carrier signal, and the output of the second PWM operation section 8 is logically inverted to generate the gate command S _B1 .

As described above, according to the first embodiment, it is possible to generate a gate command in a unit parallel inverter that performs interleaved driving in which two chopper circuits are connected in parallel.

Depending on the hardware configuration, it may not be possible to generate two carrier signals having a phase difference of 180° when generating a gate command for two-phase interleaving. For example, if an existing control circuit is used and the PWM function of a microcomputer is used, the function to generate two carrier signals and invert the sign of one carrier signal is not installed, or the carrier generation unit is an ASIC. configured and the logic circuit may not be changed.

In the first embodiment, it is possible to generate a gate command for two-phase interleaving by adding a process of inverting the duty signal used for the PWM calculation and a process of inverting the gate command after the PWM calculation.

Compared to generating two carrier signals with a 180° phase difference, the hardware configuration can be simplified and there are fewer restrictions, making it easier to generate gate commands for interleaving. is also easy to use.

For example, since the duty signal input to the PWM calculation is the result of calculation by a CPU, etc., correction such as sign inversion can be easily realized without depending on the hardware. is often installed as a standard function.

[Embodiment 2]
In the second embodiment, the case where the upper limit value and the lower limit value of the carrier signal are not positive/negative symmetrical values such as 1 and 0 will be described.

FIG. 3 shows the control block configuration of the unit parallel inverter in the second embodiment. As shown in FIG. 3, in the second embodiment, as in the first embodiment, voltage control is performed such that the high-side voltage detection value V _high follows the DC voltage command value, and is output as the current command value _{IL_ref} . The multiplier 2 outputs half the current command value _{IL_ref} as a first reactor current command value and a second reactor current command value to flow through the first and second reactors L ₁ and L ₂ of each phase.

The first current control unit 3 inputs the detected value of the current I _L1 and the first reactor current command value, performs current control, and outputs it as a duty signal for the first unit. The second current control unit 4 inputs the detected value of the current I _L2 and the second reactor current command value, performs current control, and outputs it as a duty signal for the second unit.

The inverting unit 5 inverts the duty signal of the second unit to a symmetrical value with respect to an intermediate value between the upper limit value and the lower limit value of the carrier signal, and outputs it as a corrected duty signal. In the second embodiment, it is assumed that the upper and lower limits of the carrier signal are not symmetrical about positive and negative.

The inverting section 5 of the second embodiment includes an adding section 10 and a subtracting section 11 . The adder 10 adds the upper limit value and the lower limit value of the carrier signal. Subtraction section 11 subtracts the output of second current control section 4 (the duty signal of the second unit) from the output of addition section 10 . The subsequent operations of the first and second PWM calculation units 7 and 8 and the logic inversion unit 9 are the same as in the first embodiment.

As an example, FIG. 4 shows a case where the upper limit value of the carrier signal is 1, the lower limit value is 0, and the output of the second current control section 4 (duty signal of the second unit) is 0.8. If the upper limit value of the carrier signal is 1 and the lower limit value is 0, the intermediate value is 0.5. When the duty signal 0.8 of the second unit is inverted to a symmetrical value with respect to the intermediate value 0.5, the corrected duty signal becomes 0.2.

In the second embodiment, the corrected duty signal of the second unit is calculated by the following formula.
Corrected duty signal = Upper limit of carrier signal + Lower limit of carrier signal - Duty signal of second unit
= 1.0 + 0.0 - 0.8
= 0.2
As described above, according to the second embodiment, the same effects as those of the first embodiment are obtained. In addition, even when the configuration of the carrier signal is not positive and negative symmetrical about 0, it is possible to generate the correction duty signal, and the gate command can be generated by using the carrier signal of the two chopper circuits in common.

In the case where the carrier signal is positive and negative symmetrical with respect to zero as in the first embodiment, it is also possible to deal with it by inverting the sign of the carrier signal. However, there are cases where the carrier signal is not positive/negative symmetrical, in which case the sign inversion of the carrier signal cannot generate a gate command for the unit parallel inverter in which two chopper circuits are connected in parallel. It is necessary to prepare carrier signals whose phases are shifted by 180° while synchronizing two phases of carrier signals, which makes the configuration more complicated.

On the other hand, in the second embodiment, compared to the case of generating two carrier signals having a phase difference of 180°, the hardware configuration can be simplified and there are fewer restrictions, so generation of gate commands for interleaving can be simplified. easier to do. Moreover, it is easy to divert to the existing control circuit.

Although the present invention has been described in detail only with respect to the specific examples described above, it is obvious to those skilled in the art that various modifications and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are, of course, covered by the claims.

In the specification, the method of generating the duty signal of the first unit and the duty signal of the second unit using the DC voltage control section 1 and the first and second current control sections 3 and 4 is described. The duty signal of the unit and the duty signal of the second unit may be generated by other methods.

1: DC voltage control unit 2: Multiplication unit 3: First current control unit 4: Second current control unit 5: Inversion unit 6: Carrier signal generation unit 7: First PWM operation unit 8: Second PWM operation unit 9: Logic inversion Section 10: Addition Section 11: Subtraction Section

Claims (1)

a first unit having two switching elements connected in series;
a second unit having two switching elements connected in series and connected in parallel with the first unit;
a first reactor having one end connected to a connection point between two switching elements of the first unit;
and a second reactor having one end connected to a connection point of two switching elements of the second unit and the other end connected to the other end of the first reactor, wherein the unit parallel inverter performs interleaved driving, ,
a carrier signal generator that generates a carrier signal common to the first and second units;
an inverting unit that inverts the duty signal of the second unit to a symmetrical value with respect to an intermediate value between the upper limit value and the lower limit value of the carrier signal and outputs it as a corrected duty signal;
a first PWM operation unit that performs PWM control by comparing the duty signal of the first unit and the carrier signal and outputs a gate command of the first unit;
a second PWM calculation section that performs PWM control by comparing the corrected duty signal of the second unit and the carrier signal;
a logical inverting unit that logically inverts the output of the second PWM operation unit and outputs it as a gate command for the second unit;
with
The upper limit value and the lower limit value of the carrier signal are positive and negative symmetrical values ,
The unit parallel inverter, wherein the inverter outputs a value obtained by inverting the sign of the duty signal of the second unit as the corrected duty signal.

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