JP7117367B2 - Protective elements and semiconductor devices - Google Patents

Description

The present disclosure relates to protection elements and semiconductor devices.

In a semiconductor device such as an IC (Integrated Circuit) chip, the internal circuit of the semiconductor device is protected from a sudden surge current caused by electrostatic discharge (ESD) or the like in the vicinity of pads that are electrodes for external connection. An ESD protection device is provided.

As the ESD protection element, for example, a diode-based or MOS (Metal-Oxide-Semiconductor) transistor-based protection element or the like can be used as described in Patent Document 1 below. In the invention described in Patent Document 1, a diode-based protection element and a MOS transistor-based protection element are provided in parallel to provide high protection against both forward and reverse surge currents. is realized.

JP 2013-48209 A

However, in the ESD protection element described in Patent Document 1, different protection elements are provided according to the direction of the surge current, so the area of the ESD protection element is large. Therefore, in the IC chip mounted with the ESD protection element described in Patent Document 1, the area of the chip increases, and the manufacturing cost increases.

Therefore, there has been a demand for a protective element that has a high ability to pass a surge current in any direction and that can be formed in a smaller area.

According to the present disclosure, an element region of a first conductivity type provided in a semiconductor substrate, a plurality of finger electrodes provided on the element region with a gate insulating film interposed therebetween and arranged at predetermined intervals; a gate electrode having a connection electrode that connects the plurality of finger electrodes; and a second conductivity type source region and a drain region alternately provided in the element region between the finger electrodes, and the drain region. is electrically connected to a power source or an I/O wiring, the gate electrode and the source region are electrically connected to a ground wiring, and at least one of the source region and the drain region arranged in one direction The termination is the drain region, and the element region outside sandwiching the finger electrode with the termination drain region is electrically connected to the ground wiring and has a first conductivity type higher in concentration than the element region. A protection element is provided in which a body contact region is provided that is

Further, according to the present disclosure, an internal circuit and a protective element connected in parallel with the internal circuit are provided, and the protective element includes a first conductivity type element region provided on a semiconductor substrate and the element between each of the finger electrodes and a gate electrode provided above the region with a gate insulating film interposed therebetween and having a plurality of finger electrodes arranged at predetermined intervals and a connecting electrode connecting the plurality of finger electrodes; a source region and a drain region of a second conductivity type alternately provided in the element region of, the drain region being electrically connected to a power supply or an I/O wiring, and the gate electrode and the source region being At least one of the source region and the drain region, which are electrically connected to a ground line and arranged in one direction, is the drain region, and the finger electrode is located outside the drain region sandwiching the finger electrode. A semiconductor device is provided in which a body contact region, which is electrically connected to the ground wiring and has a higher concentration than the element region and is of the first conductivity type, is provided in the element region.

According to the present disclosure, a protection element can be formed by integrating a portion functioning as a GGMOS (Gate Grounded MOS) and a portion functioning as a PN junction diode.

As described above, according to the present disclosure, it is possible to provide a protection element and a semiconductor device that have a high ability to flow surge current in any direction and can be formed in a smaller area.

In addition, the above effects are not necessarily limited, and in addition to the above effects or instead of the above effects, any of the effects shown in this specification, or other effects that can be grasped from this specification may be played.

1 is a schematic circuit diagram illustrating a protective element to which technology according to the present disclosure is applied; FIG. 1 is a plan view showing a planar configuration of a protective element according to an embodiment of the present disclosure; FIG. FIG. 3 is a cross-sectional view showing a cross-sectional configuration of the protective element taken along line A-AA of FIG. 2; FIG. 3 is a cross-sectional view showing a cross-sectional configuration of the protection element taken along line B-BB of FIG. 2; It is a circuit diagram showing an equivalent circuit of the protection element according to the same embodiment. FIG. 5 is a schematic cross-sectional view for explaining the operation of the protective element according to the same embodiment when a surge current flows in the anti-ground direction. FIG. 4 is a schematic cross-sectional view for explaining the operation of the protective element according to the same embodiment when a surge current flows in the ground direction. It is a typical top view and sectional drawing explaining 1 process which manufactures the protection element which concerns on the same embodiment. It is a typical top view and sectional drawing explaining 1 process which manufactures the protection element which concerns on the same embodiment. It is a typical top view and sectional drawing explaining 1 process which manufactures the protection element which concerns on the same embodiment. It is a typical top view and sectional drawing explaining 1 process which manufactures the protection element which concerns on the same embodiment. It is a typical top view explaining the structure of the protection element which concerns on a 1st modification. It is a typical sectional view explaining composition of a protection element concerning the 2nd modification. FIG. 11 is a schematic cross-sectional view illustrating the configuration of a protective element according to a third modified example; It is a typical sectional view explaining composition of a protection element concerning the 4th modification. It is a typical sectional view explaining composition of a protection element concerning the 5th modification. It is an external view which shows an example of the electronic device which can mount the protection element which concerns on the same embodiment. It is an external view which shows an example of the electronic device which can mount the protection element which concerns on the same embodiment. It is an external view which shows an example of the electronic device which can mount the protection element which concerns on the same embodiment.

Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the present specification and drawings, constituent elements having substantially the same functional configuration are denoted by the same reference numerals, thereby omitting redundant description.

In addition, description shall be performed in the following order.
1. Background 2. Configuration example of protection element 3 . Operation example of protection element 4 . 4. Method for manufacturing protective element; Modification 5.1. First modification 5.2. Second modification 5.3. Third modification 5.4. Fourth modification 5.5. Fifth modification 6. Application example

<1. Background>
First, the background of the technology according to the present disclosure will be described with reference to FIG. FIG. 1 is a schematic circuit diagram illustrating a protection element 10 to which technology according to the present disclosure is applied.

As shown in FIG. 1, the semiconductor device 1 includes an internal circuit 20, a power supply or I/O wiring 30, a ground wiring 40, and a protection element 10. As shown in FIG.

The internal circuit 20 is a main circuit that implements the functions of the semiconductor device 1 . The power supply or I/O wiring 30 is electrically connected to a power supply (VDD) or I/O (Input/Output) terminal. A power supply or I/O wiring 30 electrically connected to a power supply (VDD) provides a power supply voltage from the power supply (VDD) to the internal circuit 20 . A power source or I/O wiring 30 electrically connected to the I/O terminals inputs and outputs signals to and from the I/O terminals. The ground wiring 40 is electrically connected to the ground (GND) and provides the internal circuit 20 with a reference potential.

The protection element 10 is connected in parallel with the internal circuit 20 between the power supply or I/O wiring 30 and the ground wiring 40 . The protection element 10 protects the internal circuit 20 from the surge current by causing the surge current to bypass the internal circuit 20 between the power supply or I/O wiring 30 and the ground wiring 40 . A surge current is a large current that instantaneously flows beyond a steady state. Therefore, the protection element 10 is configured to be conductive only for a surge current that is a large current, for example. A surge current can preferentially flow through the wiring provided with 10 . Thereby, the protection element 10 can prevent a surge current from flowing into the internal circuit 20 .

Here, the surge current refers to a direction from the power supply (VDD) or the I/O terminal to the ground (GND) (in this specification, it is referred to as the ground direction for convenience) depending on the polarity of the surge voltage that causes the surge current. ), and from the ground (GND) toward the power supply (VDD) or I/O terminal (referred to herein as the anti-ground direction for convenience). Therefore, the protective element 10 is required to efficiently flow surge current in both the ground direction and the anti-ground direction between the power supply or I/O wiring 30 and the ground wiring 40 .

Moreover, the protective element 10 is provided separately from the internal circuit 20 that implements the functions of the semiconductor device 1 . Therefore, in order to suppress the manufacturing cost of the semiconductor device 1, the protection element 10 is required to be provided in a smaller area.

The protective element 10 according to the present embodiment has been made in view of the above requirements. The protection element 10 according to the present embodiment has a high ability to pass a surge current in both the ground direction and the anti-ground direction, and can be formed in a smaller area. A specific configuration of the protective element 10 according to the present embodiment will be described below with reference to the drawings and the like.

In addition, in each drawing referred to in the following description, for convenience of description, the size of some of the constituent members may be exaggerated. Therefore, the relative sizes of the constituent members illustrated in each drawing do not necessarily accurately represent the actual size relationship between the constituent members. Further, in the following description, the stacking direction of the substrate and the layers is expressed as the vertical direction, the direction in which the substrate exists is expressed as the downward direction, and the direction opposite to the downward direction is expressed as the upward direction.

<2. Configuration example of protective element>
First, a configuration example of the protective element 10 according to the present embodiment will be described with reference to FIGS. 2 to 4. FIG. FIG. 2 is a plan view showing the planar configuration of the protection element 10 according to the present embodiment, and FIG. 3 is a cross-sectional view showing the cross-sectional configuration of the protection element 10 taken along line A-AA in FIG. 4 is a cross-sectional view showing a cross-sectional configuration of the protective element 10 taken along line B-BB in FIG.

As shown in FIG. 2, in a plan view, the protective element 10 includes a gate electrode 120 provided in a ladder shape on the element region of the first conductivity type (for example, P type) and a gate electrode 120 between the gate electrodes 120. A source region 110S and a drain region 110D of a second conductivity type (for example, N type) are alternately provided in the element regions of the first region, and a first region is provided around the source region 110S and the drain region 110D with the gate electrode 120 interposed therebetween. and a body contact region 110B of conductivity type (for example, P-type).

Note that the gate electrode 120 is provided on the element region via the gate insulating film. The gate electrode 120 is electrically connected to the ground wiring 40, the source region 110S is electrically connected to the ground wiring 40 by the source contact 130S, and the drain region 110D is connected to the power or I/O wiring 30 by the drain contact 130D. is electrically connected to In addition, each body contact region 110B is electrically connected to the ground wiring 40 by a body contact 130B.

On the other hand, as shown in FIG. 3, in the A-AA cross section, the protective element 10 has a first conductivity type element region 110 provided on the semiconductor substrate 100, and a gate insulator 110 on the element region 110 at a predetermined interval. A gate electrode 120 provided via a film 125, a second conductivity type source region 110S and a drain region 110D alternately provided in the element region 110 between the gate electrodes 120, and drain regions 110D at both ends. A body contact region 110B of the first conductivity type provided in the element region 110 so as to sandwich the gate electrode 120 therebetween, and source contacts 130S provided respectively on the source region 110S, the drain region 110D and the body contact region 110B. , the drain contact 130D and the body contact 130B, the source electrode 140S, the drain electrode 140D and the body electrode 140B respectively provided on the source contact 130S, the drain contact 130D and the body contact 130B, and the insulation embedding each configuration of the protection element 10 a layer 150;

Further, as shown in FIG. 4, in the B-BB cross section, the protective element 10 includes a first conductivity type element region 110 provided in the semiconductor substrate 100 and a second conductivity type drain provided in the element region 110. A gate electrode 120 is provided on the element region 110 with a gate insulating film 125 interposed therebetween so as to sandwich the region 110D and the region where the drain region 110D is provided, and the gate electrode 120 is sandwiched between the drain region 110D. a body contact region 110B of the first conductivity type provided in the element region 110, a drain contact 130D and a body contact 130B provided respectively on the drain region 110D and the body contact region 110B, and a drain contact 130D and a body contact 130B a drain electrode 140</b>D and a body electrode 140</b>B respectively provided thereon;

The element region 110 is a first conductivity type region formed in the semiconductor substrate 100 . Specifically, the element region 110 can be formed by introducing a P-type impurity such as boron (B) or aluminum (Al) into the semiconductor substrate 100 . The semiconductor substrate 100 may be, for example, a silicon (Si) substrate or a semiconductor substrate 100 such as germanium (Ge), or a compound semiconductor substrate such as gallium arsenide (GaAs), gallium nitride (GaN), or silicon carbide (SiC). may be

The device regions 110 are electrically isolated from each other by an insulating device isolation layer (not shown) formed on the semiconductor substrate 100 . Accordingly, the device isolation layer can electrically isolate each device including the protection device 10 formed on the semiconductor substrate 100 . The element isolation layer may be formed, for example, by embedding an insulating material in an opening provided from the surface of the semiconductor substrate 100 toward the inside. Specifically, the element isolation layer is formed by removing a predetermined region of the semiconductor substrate 100 by etching or the like using the STI (Shallow Trench Isolation) method, and then removing silicon oxide (SiO _x ) or silicon nitride from the formed opening. It may be formed by embedding with an insulating material such as (SiN _x ) or silicon oxynitride (SiON). Alternatively, the element isolation layer may be formed by converting a predetermined region of the semiconductor substrate 100 into an insulating oxide by thermal oxidation using a LOCOS (Local Oxidation of Silicon) method.

The gate electrode 120 is provided on the element region 110 with a gate insulating film 125 interposed therebetween in a ladder-like planar shape. Specifically, the gate electrode 120 includes a plurality of finger electrodes 123 arranged at predetermined intervals and a connecting electrode 121 connecting each of the plurality of finger electrodes 123 . Specifically, the connecting electrodes 121 are provided in a pair of linear shapes extending in the first direction and parallel to each other. A plurality of finger electrodes 123 are provided between the connecting electrodes 121 so as to extend in a second direction perpendicular to the first direction. That is, the plurality of finger electrodes 123 are provided so as to bridge between the connecting electrodes 121 provided in a pair of straight lines parallel to each other at a predetermined interval. Therefore, the gate electrode 120 has a planar shape that divides the device region 110 between the connecting electrodes 121 parallel to each other into a plurality of rectangular regions by the plurality of finger electrodes 123 . Rectangular regions divided by a plurality of finger electrodes alternately become source regions 110S and drain regions 110D, as will be described later. Thus, the gate electrode 120 can function as a field effect transistor with the source region 110S and the drain region 110D provided with the finger electrodes 123 interposed therebetween.

At least three finger electrodes 123 are provided in order to provide at least one source region 110S and at least one drain region 110D. As the number of finger electrodes 123 increases, the number of source regions 110S and drain regions 110D provided between the connection electrodes 121 can be increased, and the number of field effect transistors formed inside the protection device 10 can be increased. . According to this, since the protection element 10 can disperse|distribute and flow a surge current in more field effect transistors, it can improve the capability with respect to a surge current.

However, if the number of finger electrodes 123 is excessively large, the area of protection element 10 increases, and the manufacturing cost of semiconductor device 1 including protection element 10 increases. Moreover, since the number of transistors inside the protection element 10 increases, the parasitic capacitance inside the protection element 10 increases. Therefore, the number of finger electrodes 123 may be 3 or more and 51 or less so that the number of field effect transistors inside the protective element 10 is about 2 to 50.

Gate electrode 120 is formed of a conductive material. Specifically, the gate electrode 120 may be made of silicon or metal. For example, the gate electrode 120 may be formed of polysilicon, titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), niobium (Nb), nickel (Ni), zirconium (Zr). , gold (Au), silver (Ag), aluminum (Al) or copper (Cu), or a compound of these metals. The gate electrode 120 may be formed of a single layer of any of the above materials, or may be formed by laminating a plurality of layers of any of the above materials.

The gate insulating film 125 is formed of an insulating material and provided between the semiconductor substrate 100 provided with the element region 110 and the gate electrode 120 . Specifically, the gate insulating film 125 is provided under the gate electrode 120 in the same planar shape as the gate electrode 120 . The gate insulating film 125 may be made of an insulating material such as silicon oxide (SiO _x ), silicon nitride (SiN _x ), or silicon oxynitride (SiON). Alternatively, the gate insulating film 125 may be made of a high dielectric material such as hafnium oxide (HfO ₂ ) or a ferroelectric material.

The source region 110S and the drain region 110D are alternately provided as the regions of the second conductivity type in the element regions 110 of each rectangular region separated by the gate electrode 120 . Specifically, the source region 110S and the drain region 110D are alternately provided in rectangular regions obtained by dividing the device region 110 between the connecting electrodes 121 parallel to each other by a plurality of finger electrodes 123 . That is, the source region 110S and the drain region 110D are provided on both sides of the finger electrode 123, respectively. The source region 110S and the drain region 110D may be formed by introducing an N-type impurity such as phosphorus (P) or arsenic (As) into a predetermined region of the element region 110 at a higher concentration than the element region 110. .

The body contact region 110B is provided in the element region 110 surrounding the source region 110S and the drain region 110D as a first conductivity type region having a higher concentration than the element region 110. As shown in FIG. Specifically, the body contact region 110B is provided in the element region 110 opposite to the source region 110S and the drain region 110D with the gate electrode 120 interposed therebetween so as to surround the alternately arranged source region 110S and drain region 110D. be done. Body contact region 110B may be formed by additionally introducing a P-type impurity such as boron (B) or aluminum (Al) into a predetermined region of device region 110 . Thereby, the body contact region 110B is provided as a region of the first conductivity type having a higher concentration than the element region 110. FIG.

In the protection element 10 according to this embodiment, at least one end of the source region 110S and the drain region 110D alternately arranged with the finger electrodes 123 interposed therebetween is provided to be the drain region 110D. Thereby, the terminal drain region 110D can form a PN junction diode with the body contact region 110B provided so as to surround the source region 110S and the drain region 110D. Therefore, the protective element 10 can increase the ability to flow a surge current in the ground direction in the PN junction diode between the terminal drain region 110D and the body contact region 110B.

The ends of both the source region 110S and the drain region 110D alternately arranged with the finger electrodes 123 interposed therebetween may be provided so as to form the drain region 110D. According to this, the protective element 10 forms a PN junction diode at each end of both the alternately arranged source regions 110S and drain regions 110D. As a result, the protective element 10 can further increase the ability to flow a surge current in the ground direction. Note that when both the alternately arranged source regions 110S and the drain regions 110D terminate at the drain region 110D, the number of the alternately arranged source regions 110S and the drain regions 110D is an odd number, and the number of the finger electrodes is an even number. becomes.

Source contact 130S, drain contact 130D and body contact 130B are provided of a conductive material over source region 110S, drain region 110D and body contact region 110B, respectively. For example, the source contact 130S, the drain contact 130D, and the body contact 130B are made of a low resistance metal such as titanium (Ti) or tungsten (W), or a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN). may The source contact 130S, the drain contact 130D, and the body contact 130B may be formed of a single layer of the material described above, or may be formed by laminating a plurality of layers of the material described above.

An alloy (so-called silicide) of a metal such as Ni and silicon is formed on the surfaces of the source region 110S, the drain region 110D, and the body contact region 110B that are in contact with the source contact 130S, the drain contact 130D, and the body contact 130B, respectively. good too. According to this configuration, the source region 110S, the drain region 110D and the body contact region 110B can reduce the contact resistance between the source contact 130S, the drain contact 130D and the body contact 130B.

A source electrode 140S, a drain electrode 140D and a body electrode 140B are provided of a conductive material over the source contact 130S, the drain contact 130D and the body contact 130B respectively. For example, the source electrode 140S, the drain electrode 140D, and the body electrode 140B are made of titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), niobium (Nb), nickel (Ni), zirconium (Zr), It may be formed of a metal such as gold (Au), silver (Ag), aluminum (Al) or copper (Cu), or a compound of these metals. The source electrode 140S, the drain electrode 140D, and the body electrode 140B may be formed of a single layer of the material described above, or may be formed by laminating a plurality of layers of the material described above. The source electrode 140S and the body electrode 140B are electrically connected to the ground wiring 40 by wiring (not shown). The drain electrode 140D is electrically connected to the power supply or I/O wiring 30 by wiring (not shown).

The insulating layer 150 is provided on the semiconductor substrate 100 with an insulating material and embeds each component of the protection element 10 . Specifically, the insulating layer 150 is formed on the semiconductor substrate 100 provided with the element region 110 so as to bury the source contact 130S, the drain contact 130D, the body contact 130B, the source electrode 140S, the drain electrode 140D and the body electrode 140B. provided over the entire surface. For example, insulating layer 150 may be formed of an insulating material such as silicon oxide (SiO _x ), silicon nitride (SiN _x ), or silicon oxynitride (SiON).

<3. Operation example of protective element>
Next, an operation example of the protective element 10 according to the present embodiment will be described with reference to FIGS. 5 to 7. FIG. FIG. 5 is a circuit diagram showing an equivalent circuit of the protective element 10 according to this embodiment. FIG. 6 is a schematic cross-sectional view illustrating the operation of the protective element 10 when a surge current flows in the anti-ground direction, and FIG. 7 illustrates the operation of the protective element 10 when a surge current flows in the ground direction. FIG. 2 is a schematic cross-sectional view.

The protection element 10 functions as an N-type field effect transistor with the P-type element region 110, the gate electrode 120, the P-type body contact region 110B, the N-type source region 110S and the N-type drain region 110D. In addition, the gate electrode 120, the source region 110S, and the body contact region 110B are electrically connected to ground (GND), and the drain region 110D is electrically connected to a power supply (VDD) or an I/O terminal. ing. Therefore, the protection element 10 functions as a so-called GGMOS (Gate Grounded MOS).

In addition, in the protection element 10, the drain region 110D at the end of the alternately arranged source regions 110S and drain regions 110D forms a PN junction diode with the body contact region 110B.

Therefore, the protection element 10 can be regarded as equivalent to a circuit in which the GGMOS 11 and the PN junction diode 12 are connected in parallel, as shown in FIG. In such a protection element 10, the GGMOS 11 allows a surge current in the anti-ground direction to flow from the power supply (VDD) to the ground (GND), and the PN junction diode 12 allows the surge current in the ground direction to flow from the ground (GND) to the power supply (VDD). ) or to the I/O terminal.

Here, with reference to FIG. 6, the operation of the protective element 10 when a surge current flows in the anti-ground direction will be described. As shown in FIG. 6, when a surge current flows in the protection element 10 in the anti-ground direction, a positive voltage is applied to the drain electrode 140D and the drain region 110D, thereby causing the N-type drain region 110D and the P-type Avalanche breakdown occurs between the element region 110 of the . As a result, a current flows from the drain electrode 140D to the element region 110 of the semiconductor substrate 100. As shown in FIG. On the other hand, in the protection element 10, an NPN bipolar transistor is formed as a parasitic transistor having the source region 110S as the emitter, the body contact region 110B and the element region 110 as the base, and the drain region 110D as the collector. Therefore, when the current flowing through the element region 110 increases and a potential difference occurs between the element region 110, which is the base, and the source region 110S, which is the emitter, the NPN bipolar transistor is turned on. As a result, the protective element 10 can allow a large current to flow from the drain region 110D to the source region 110S, so that a surge current can flow in the anti-ground direction from the drain electrode 140D to the source electrode 140S.

Also, with reference to FIG. 7, the operation of the protective element 10 when a surge current flows in the ground direction will be described. As shown in FIG. 7, when a surge current in the ground direction flows through the protective element 10, a PN junction diode formed between the P-type element region 110 and the body contact region 110B and the N-type drain region 110D Thus, a surge current in the ground direction can flow from the source electrode 140S to the drain electrode 140D.

In the protective element 10 according to this embodiment, there is no source region 110S or element isolation layer between the P-type element region 110 and the body contact region 110B and the N-type drain region 110D. Therefore, the protection element 10 can reduce the resistance component of the PN junction diode. In addition, in the protection element 10, a PN junction diode is formed on each side of the body contact region 110B provided so as to surround the alternately arranged source regions 110S and drain regions 110D. As a result, in the protective element 10, a plurality of PN junction diodes that allow surge currents to flow in the ground direction are formed, so that the ability to cope with surge currents in the ground direction can be greatly improved.

The ability of the PN junction diode formed between the element region 110, the body contact region 110B, and the drain region 110D to flow a surge current in the ground direction depends on the gate electrode 120 sandwiched between the body contact region 110B and the drain region 110D. width can be adjusted. Specifically, by increasing the width of the gate electrode 120 provided between the body contact region 110B and the drain region 110D and increasing the distance between the body contact region 110B and the drain region 110D, the resistance to the surge current in the ground direction is increased. can be increased. However, when the width of the gate electrode 120 provided between the body contact region 110B and the drain region 110D is excessively large, the PN junction diode formed between the body contact region 110B and the drain region 110D has a resistance component. It is not preferable because the tolerance is rather reduced by the occurrence.

In addition, the protection element 10 according to the present embodiment can be formed by forming the GGMOS 11 and the PN junction diode 12 as an integrated element instead of forming the GGMOS 11 and the PN junction diode 12 as separate elements. can. Therefore, according to this embodiment, the protection element 10 can be formed in a smaller area, so that the area of the semiconductor device 1 including the protection element 10 can be reduced, and the manufacturing cost can be reduced.

In addition, the protection element 10 according to the present embodiment can prevent a surge current in the anti-ground direction from entering the PN junction diode 12 and destroying the PN junction diode 12 . Specifically, in the protection element in which the GGMOS 11 and the PN junction diode 12 are connected in parallel, if the surge current is a fast pulse, the surge current enters the PN junction diode 12 before the GGMOS 11 is turned on, and the PN junction Diode 12 may be destroyed. In the protective element 10 according to this embodiment, the GGMOS 11 and the PN junction diode 12 are integrally formed, so that the anti-ground surge current does not enter the PN junction diode 12 . Therefore, the protection element 10 according to the present embodiment can prevent the PN junction diode 12 from being destroyed by the anti-ground surge current.

As described above, the protective element 10 according to the present embodiment has a high ability to pass surge current in both the ground direction and the anti-ground direction, and can be formed in a smaller area.

<4. Method for manufacturing protective element>
Next, a method for manufacturing the protective element 10 according to this embodiment will be described with reference to FIGS. 8A to 8D. 8A to 8D are schematic plan views and cross-sectional views for explaining each step of manufacturing the protective element 10 according to this embodiment.

First, as shown in FIG. 8A, a gate insulating film 125 is formed on a semiconductor substrate 100 having an isolation layer formed thereon, and then a gate electrode 120 is formed on the gate insulating film 125 .

Specifically, first, in a desired region of the semiconductor substrate 100, ion implantation is performed to implant boron (B) as P− at 50 keV at 1.0×10 ¹² atoms/cm ² to 1.0×10 ¹³ atoms/cm 2 . /cm ² and a dose of 1.0×10 ¹¹ atoms/cm ² to 1.0×10 ¹² atoms/cm ² at 20 keV to form the device region 110 . Thereafter, using CVD (Chemical Vapor Deposition) or the like, a silicon oxide film is formed to a thickness of 5 nm to 50 nm on the semiconductor substrate 100 made of silicon or the like. After that, using CVD or the like, a polysilicon film is formed on the silicon oxide to a thickness of 100 nm to 200 nm, and a WSi film is formed on the polysilicon to a thickness of 100 nm to 200 nm. After that, by patterning these laminated films into a desired planar shape using lithography or the like, a laminated structure of the gate insulating film 125 and the gate electrode 120 is formed. For example, the gate electrode 120 having a laminated structure of polysilicon and WSi may be formed to have a sheet resistance of several Ω/□ and a gate width of 0.1 μm to 0.5 μm.

Next, as shown in FIG. 8B, a source region 110S, a drain region 110D and a body contact region 110B are formed.

Specifically, in a desired region of the semiconductor substrate 100, ion implantation is performed to implant phosphorus (P) as N− at 1.0×10 ¹³ atoms/cm ² to 5.0×10 ¹³ atoms/cm at 120 keV. ² , and arsenic (As) as N+ is implanted at 50 keV with a dose of 1.0×10 ¹⁵ atoms/cm ² to 5.0×10 ¹⁵ atoms/cm ² to form the source region 110S. and a drain region 110D. For example, the source region 110S and the drain region 110D may be formed with a width of 0.5 μm to 3.0 μm.

Further, in a desired region of the semiconductor substrate 100, boron (B) is implanted as P+ at a dose of 1.0×10 ¹⁵ atoms/cm ² to 5.0×10 ¹⁵ atoms/cm ² at 50 keV. to form the body contact region 110B. For example, the body contact region 110B may be formed at a distance of 0.1 μm to 0.5 μm from the gate electrode 120. FIG.

Subsequently, as shown in FIG. 8C, a source contact 130S, a drain contact 130D and a body contact 130B are formed on the source region 110S, the drain region 110D and the body contact region 110B.

Specifically, after forming the insulating layer 151 on the semiconductor substrate 100 by CVD or the like, openings are formed at positions corresponding to the source region 110S, the drain region 110D and the body contact region 110B by etching or the like. prepare. Furthermore, by forming a film of tungsten (W) or the like on the insulating layer 151 by using CVD or the like, the openings formed in the insulating layer 151 are filled with a conductive material, and the source contact 130S, the drain contact 130D and the body contact are formed. Form 130B. Tungsten or the like remaining on the insulating layer 151 can be removed by CMP (Chemical Mechanical Polishing) or the like.

Here, phosphorus (P) is implanted into the surfaces of the source region 110S and the drain region 110D at a dose of 1.0×10 ¹⁵ atoms/cm ² to 5.0×10 ¹⁵ atoms/cm ² at 20 keV. good too. Boron (B) may be implanted into the surface of the body contact region 110B at a dose of 1.0×10 ¹⁵ atoms/cm ² to 5.0×10 ¹⁵ atoms/cm ² at 20 keV. According to this process, the contact resistance between the source region 110S, the drain region 110D and the body contact region 110B and the source contact 130S, the drain contact 130D and the body contact 130B can be reduced.

Next, as shown in FIG. 8D, a source electrode 140S, a drain electrode 140D and a body electrode 140B are formed on the source contact 130S, the drain contact 130D and the body contact 130B.

Specifically, after forming an insulating layer 150 on the insulating layer 151 by using CVD or the like to form the insulating layer 150, etching or the like is used to form the source contact 130S, the drain contact 130D, and the body contact 130B. Apertures are provided at corresponding locations. Furthermore, by using CVD or the like to form a film of copper (Cu) or the like on the insulating layer 150, the openings formed in the insulating layer 150 are filled with a conductive material to form the source electrode 140S, the drain electrode 140D, and the body electrode. Form 140B. Copper or the like remaining on the insulating layer 150 can be removed by CMP (Chemical Mechanical Polishing) or the like. Furthermore, the source electrode 140S and the body electrode 140B are connected to the ground wiring 40, and the drain electrode 140D is connected to the power supply or I/O wiring 30.

Although not shown in FIGS. 8A to 8D, contacts are formed on the gate electrode 120 in the same steps as those shown in FIGS. 8C and 8D, and wiring to the ground wiring 40 is formed.

According to the above steps, the protective element 10 according to the present embodiment can be formed.

<5. Variation>
Modifications of the protective element 10 according to the present embodiment will be described below with reference to FIGS. 9A to 9E.

(5.1. First modification)
First, with reference to FIG. 9A, a protective element 10A according to a first modified example will be described. FIG. 9A is a schematic plan view illustrating the configuration of a protection element 10A according to the first modification.

As shown in FIG. 9A, in the protection element 10A according to the first modification, an additional drain region 111D and an additional body contact region 111B are provided in the element region 110 further outside the body contact region 110B.

Specifically, an additional drain region 111D of the second conductivity type (for example, N type) is provided on the opposite side of the body contact region 110B to the side on which the drain region 110D is provided, with the finger electrode 123 interposed therebetween. be done. As with the drain region 110D, the additional drain region 111D is provided with an additional drain contact 131D, and the additional drain region 111D is electrically connected to the power supply or I/O wiring 30 by electrodes and wirings (not shown).

Further, on the side of the additional drain region 111D opposite to the side on which the body contact region 110B is provided, the additional body contact region 111B of the first conductivity type (for example, P type) is provided with the finger electrode 123 interposed therebetween. . An additional body contact 131B is provided in the additional body contact region 111B, similarly to the body contact region 110B, and the additional body contact region 111B is electrically connected to the ground wiring 40 by electrodes and wiring (not shown).

That is, in the protection element 10A according to the first modification, in addition to the PN junction diode formed of the drain region 110D and the body contact region 110B, the PN junction diode formed of the additional drain region 111D and the additional body contact region 111B Junction diodes would also be provided in series. The configurations of the source region 110S, the drain region 110D, and the body contact region 110B are substantially the same as those of the protection element 10 shown in FIGS.

In the protection element 10A according to the first modification, the number of PN junction diodes is increased compared to the protection element 10 shown in FIGS. be able to. Note that FIG. 9A shows a configuration in which one PN junction diode is added by adding one additional drain region 111D and one additional body contact region 111B on both sides of the protection element 10A. Examples are not limited to such illustrations. For example, the number of additional drain regions 111D and additional body contact regions 111B added to both sides of the protection element 10A may be two or more.

(5.2. Second modification)
Next, a protection element 10B according to a second modification will be described with reference to FIG. 9B. FIG. 9B is a schematic cross-sectional view illustrating the configuration of a protective element 10B according to the second modification.

As shown in FIG. 9B, in a protective element 10B according to the second modification, a so-called PD-SOI (Partially Depleted Silicon On Insulator) substrate is used as a semiconductor substrate 100B.

Specifically, in the protection element 10B, instead of the semiconductor substrate 100 made of silicon or the like, a silicon oxide film 102 is provided on a support substrate 101, and a silicon oxide film 102 is formed on the silicon oxide film 102. A substrate provided with a semiconductor layer is used. The support substrate 101 may be made of any material, and may be made of, for example, silicon, which is the same as the semiconductor layer.

Element region 110, gate electrode 120, source region 110S and drain region 110D, body contact region 110B, source contact 130S, drain contact 130D and body contact 130B, source electrode 140S and drain electrode are formed on semiconductor substrate 100B. 140D, the body electrode 140B, and the insulating layer 150 are substantially the same as those of the protection element 10 shown in FIGS.

In the protection element 10B according to the second modification, by using the PD-SOI substrate as the semiconductor substrate 100B, it is possible to reduce the parasitic capacitance of the field effect transistor or the like formed in the semiconductor substrate 100B.

(5.3. Third modification)
Next, a protection element 10C according to a third modification will be described with reference to FIG. 9C. FIG. 9C is a schematic cross-sectional view illustrating the configuration of a protective element 10C according to the third modification.

As shown in FIG. 9C, a so-called FD-SOI (Fully Depleted Silicon On Insulator) substrate is used as a semiconductor substrate 100C in a protective element 10C according to the third modification.

Specifically, in the protection element 10C, instead of the semiconductor substrate 100 made of silicon or the like, a silicon oxide film 102 is provided on a support substrate 101, and a silicon oxide film 102 is formed on the silicon oxide film 102. A substrate provided with a semiconductor layer is used. The support substrate 101 may be made of any material, and may be made of, for example, silicon, which is the same as the semiconductor layer.

Element region 110, gate electrode 120, source region 110S and drain region 110D, body contact region 110B, source contact 130S, drain contact 130D and body contact 130B, source electrode 140S and drain electrode are formed on semiconductor substrate 100B. 140D, the body electrode 140B, and the insulating layer 150 are substantially the same as those of the protection element 10 shown in FIGS.

Here, the thickness of the semiconductor layer formed on the silicon oxide film 102 is approximately the depth at which the source region 110S and the drain region 110D are formed. In the FD-SOI substrate used in the third modified example, the thickness of the semiconductor layer in which the source region 110S and the drain region 110D are formed is extremely thin compared to the PD-SOI substrate used in the second modified example. The difference is that they are controlled.

In the protection element 10C according to the third modification, by using the FD-SOI substrate as the semiconductor substrate 100C, a parasitic capacitance such as a field effect transistor formed in the semiconductor substrate 100C is reduced to the protection element 10B according to the second modification. can be reduced even further than

(5.4. Fourth modification)
Subsequently, a protection element 10D according to a fourth modification will be described with reference to FIG. 9D. FIG. 9D is a schematic cross-sectional view illustrating the configuration of a protection element 10D according to the fourth modification.

As shown in FIG. 9D, a protection element 10D according to the fourth modification uses a PD-SOI substrate or an FD-SOI substrate with a polysilicon layer 103 added as a semiconductor substrate 100D.

Specifically, in the protection element 10D, instead of the semiconductor substrate 100 made of silicon or the like, a polysilicon layer 103 is provided on the support substrate 101, and a silicon oxide film 102 is provided on the polysilicon layer 103. A substrate in which a semiconductor layer made of silicon or the like is provided on a silicon oxide film 102 is used. The support substrate 101 may be made of any material, and may be made of, for example, silicon, which is the same as the semiconductor layer.

Element region 110, gate electrode 120, source region 110S and drain region 110D, body contact region 110B, source contact 130S, drain contact 130D and body contact 130B, source electrode 140S and drain electrode are formed on semiconductor substrate 100D. 140D, the body electrode 140B, and the insulating layer 150 are substantially the same as those of the protection element 10 shown in FIGS.

In the protection element 10D according to the fourth modification, the polysilicon layer traps carriers generated inside the semiconductor substrate 100D when, for example, a high frequency is applied, thereby preventing the substrate capacitance from varying due to the carriers. can do. Therefore, in the protective element 10D according to the fourth modification, it is possible to improve the high frequency characteristics more than the protective elements 10B and 10C according to the second and third modifications.

(5.5. Fifth modification)
Next, a protection element 10E according to a fifth modification will be described with reference to FIG. 9E. FIG. 9E is a schematic cross-sectional view illustrating the configuration of a protection element 10E according to the fifth modification.

As shown in FIG. 9E, a protection element 10E according to the fifth modification uses a so-called SOS (Silicon On Sapphire) substrate as a semiconductor substrate 100E.

Specifically, in the protection element 10E, instead of the semiconductor substrate 100 made of silicon or the like, a substrate in which a semiconductor layer made of silicon or the like is provided on a sapphire substrate 104 is used.

Element region 110, gate electrode 120, source region 110S and drain region 110D, body contact region 110B, source contact 130S, drain contact 130D and body contact 130B, source electrode 140S and drain electrode are formed on semiconductor substrate 100E. 140D, the body electrode 140B, and the insulating layer 150 are substantially the same as those of the protection element 10 shown in FIGS.

In the protection element 10E according to the fifth modification, by using the SOS substrate as the semiconductor substrate 100E, parasitic capacitance such as a field effect transistor formed on the semiconductor substrate 100E is reduced as in the case of the PD-SOI substrate or the FD-SOI substrate. can be reduced.

<6. Application example>
The protective element 10 according to this embodiment can be mounted in circuits mounted in various electronic devices. Next, examples of electronic devices to which the protective element 10 according to the present embodiment can be applied will be described with reference to FIGS. 10A to 10C. 10A to 10C are external views showing an example of an electronic device in which the protective element 10 according to this embodiment can be mounted.

For example, the protective element 10 according to this embodiment can be mounted on electronic devices such as smartphones. As shown in FIG. 10A, a smartphone 900 includes a display unit 901 that displays various information, and an operation unit 903 that includes buttons and the like for receiving operation input by the user. Here, the protection element 10 according to the present embodiment may be mounted in a control circuit that controls various operations of the smartphone 900 .

For example, the protective element 10 according to this embodiment can be mounted on electronic equipment such as a digital camera. As shown in FIGS. 10B and 10C, a digital camera 910 includes a main body (camera body) 911, an interchangeable lens unit 913, a grip 915 held by the user when shooting, and a monitor for displaying various information. and an EVF (Electronic View Finder) 919 that displays a through-the-lens image observed by the user at the time of shooting. 10B is an external view of the digital camera 910 viewed from the front (that is, the subject side), and FIG. 10C is an external view of the digital camera 910 viewed from the rear (that is, the photographer side). Here, a control circuit that controls various operations of the digital camera 910 may include the protective element 10 according to the present embodiment.

In addition, the electronic device in which the protective element 10 according to the present embodiment is mounted is not limited to the above example. The protective element 10 according to this embodiment can be mounted on electronic equipment in all fields. Examples of such electronic devices include glasses-type wearable devices, HMDs (Head Mounted Displays), television devices, electronic books, PDAs (Personal Digital Assistants), notebook personal computers, video cameras, game devices, and the like. be able to.

Although the preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is obvious that those who have ordinary knowledge in the technical field of the present disclosure can conceive of various modifications or modifications within the scope of the technical idea described in the claims. is naturally within the technical scope of the present disclosure.

Also, the effects described herein are merely illustrative or exemplary, and are not limiting. In other words, the technology according to the present disclosure can produce other effects that are obvious to those skilled in the art from the description of this specification in addition to or instead of the above effects.

Note that the following configuration also belongs to the technical scope of the present disclosure.
(1)
a first conductivity type element region provided on a semiconductor substrate;
a gate electrode provided above the element region via a gate insulating film and having a plurality of finger electrodes arranged at predetermined intervals and a connecting electrode connecting the plurality of finger electrodes;
a second conductivity type source region and a drain region alternately provided in the element region between each of the finger electrodes;
with
the drain region is electrically connected to a power source or an I/O wiring, the gate electrode and the source region are electrically connected to a ground wiring;
At least one end of the source region and the drain region arranged in one direction is the drain region, and the element region outside sandwiching the finger electrode with the drain region at the end is electrically connected to the ground wiring. and a body contact region of the first conductivity type having a higher concentration than the element region.
(2)
Both ends of the source region and the drain region arranged in one direction are the drain regions, respectively, and the body contact is provided in the outer element region sandwiching the finger electrode with each of the drain regions at the both ends. The protective element according to (1), wherein each region is provided.
(3)
The connecting electrodes are provided as a pair of parallel straight lines extending in a first direction,
The plurality of finger electrodes extend in a second direction orthogonal to the first direction, and are provided so as to bridge between a pair of parallel straight lines of the connecting electrode (1) or (2). Protective element described in .
(4)
The protective element according to (3), wherein the source region and the drain region are provided in the element region surrounded by the gate electrode.
(5)
The protection according to (4) above, wherein the element regions surrounding the source region and the drain region are provided with the body contact regions electrically connected to the ground wiring with the gate electrode interposed therebetween. element.
(6)
the element regions are electrically isolated from each other by an element isolation layer;
The protective element according to any one of (1) to (5), wherein the body contact region is provided in the same element region as the source region and the drain region.
(7)
An additional drain region of a second conductivity type is further provided across the finger electrodes in the element region further outside the body contact region,
An additional body contact region of a first conductivity type is further provided in the element region outside the additional drain region with the finger electrodes interposed therebetween,
Any one of (1) to (6) above, wherein the additional drain region is electrically connected to the power supply or I/O wiring, and the additional body contact region is electrically connected to the ground wiring. Protection element as described in item.
(8)
The protective element according to any one of (1) to (7), wherein the body contact region forms a PN junction with the terminal drain region.
(9)
The protective element according to any one of (1) to (8), wherein the semiconductor substrate is a substrate in which a silicon oxide film and a semiconductor layer are sequentially laminated on a support substrate.
(10)
The protection element according to (9), wherein the semiconductor substrate is a PD-SOI substrate or an FD-SOI substrate.
(11)
The protective element according to (9) or (10), further comprising a polysilicon layer between the supporting substrate and the silicon oxide film.
(12)
The protective element according to any one of (1) to (8), wherein the semiconductor substrate is a substrate in which a semiconductor layer is laminated on a sapphire substrate.
(13)
an internal circuit;
a protective element connected in parallel with the internal circuit;
with
The protective element is
a first conductivity type element region provided on a semiconductor substrate;
a gate electrode provided on the element region via a gate insulating film and having a plurality of finger electrodes arranged at predetermined intervals and a connecting electrode connecting the plurality of finger electrodes;
a second conductivity type source region and a drain region alternately provided in the element region between each of the finger electrodes;
with
the drain region is electrically connected to a power source or an I/O wiring, the gate electrode and the source region are electrically connected to a ground wiring;
At least one end of the source region and the drain region arranged in one direction is the drain region, and the element region outside sandwiching the finger electrode with the drain region at the end is electrically connected to the ground wiring. and a body contact region of the first conductivity type having a higher concentration than the element region.

1 semiconductor device 10 protection element 11 GGMOS
12 PN junction diode 20 internal circuit 30 power supply or I/O wiring 40 ground wiring 100 semiconductor substrate 110 element region 110B body contact region 110D drain region 110S source region 120 gate electrode 121 coupling electrode 123 finger electrode 125 gate insulating film 130B body contact 130D Drain contact 130S Source contact 140B Body electrode 140D Drain electrode 140S Source electrode 150 Insulating layer

Claims (13)

a first conductivity type element region provided on a semiconductor substrate;
a gate electrode provided above the element region via a gate insulating film and having a plurality of finger electrodes arranged at predetermined intervals and a connecting electrode connecting the plurality of finger electrodes;
a second conductivity type source region and a drain region alternately provided in the element region between each of the finger electrodes;
with
the drain region is electrically connected to a power source or an I/O wiring, the gate electrode and the source region are electrically connected to a ground wiring;
At least one end of the source region and the drain region arranged in one direction is the drain region, and the element region outside sandwiching the finger electrode with the drain region at the end is electrically connected to the ground wiring. and a body contact region of the first conductivity type having a higher concentration than the element region. Both ends of the source region and the drain region arranged in one direction are the drain regions, respectively, and the body contact is provided in the outer element region sandwiching the finger electrode with each of the drain regions at the both ends. 2. The protection element of claim 1, wherein each region is provided. The connecting electrodes are provided as a pair of parallel straight lines extending in a first direction,
2. The protective element according to claim 1, wherein the plurality of finger electrodes extend in a second direction orthogonal to the first direction, and are provided so as to bridge between a pair of parallel straight lines of the connecting electrode. . 4. The protective element according to claim 3, wherein said source region and said drain region are respectively provided in said element region surrounded by said gate electrode. 5. The protective element according to claim 4, wherein the element area surrounding the source area and the drain area is provided with the body contact area electrically connected to the ground wiring with the gate electrode interposed therebetween. . the element regions are electrically isolated from each other by an element isolation layer;
2. The protection device according to claim 1, wherein said body contact region is provided in said device region same as said source region and said drain region. An additional drain region of a second conductivity type is further provided across the finger electrodes in the element region further outside the body contact region,
An additional body contact region of a first conductivity type is further provided in the element region outside the additional drain region with the finger electrodes interposed therebetween,
2. The protection device according to claim 1, wherein said additional drain region is electrically connected to said power supply or I/O wiring, and said additional body contact region is electrically connected to said ground wiring. 2. The protection device of claim 1, wherein said body contact region forms a PN junction with said terminal drain region. 2. The protective element according to claim 1, wherein said semiconductor substrate is a substrate in which a silicon oxide film and a semiconductor layer are sequentially laminated on a support substrate. 10. The protection device according to claim 9, wherein the semiconductor substrate is a PD-SOI substrate or an FD-SOI substrate. 10. The protection device of claim 9, further comprising a polysilicon layer between the support substrate and the silicon oxide film. The protection element according to claim 1, wherein the semiconductor substrate is a substrate in which a semiconductor layer is laminated on a sapphire substrate. an internal circuit;
a protective element connected in parallel with the internal circuit;
with
The protective element is
a first conductivity type element region provided on a semiconductor substrate;
a gate electrode provided above the element region via a gate insulating film and having a plurality of finger electrodes arranged at predetermined intervals and a connecting electrode connecting the plurality of finger electrodes;
a second conductivity type source region and a drain region alternately provided in the element region between each of the finger electrodes;
with
the drain region is electrically connected to a power source or an I/O wiring, the gate electrode and the source region are electrically connected to a ground wiring;
At least one end of the source region and the drain region arranged in one direction is the drain region, and the element region outside sandwiching the finger electrode with the drain region at the end is electrically connected to the ground wiring. and a body contact region of the first conductivity type having a higher concentration than the element region.

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