JP7120886B2 - Method for manufacturing switching element - Google Patents

Description

The technology disclosed in this specification relates to a method for manufacturing a switching element.

Patent Document 1 discloses a trench gate type switching element. In this switching element, the body layer has an electric field relaxation layer extending below the bottom surface of the trench. By providing the electric field relaxation layer in the body layer, the electric field applied to the gate insulating film in the vicinity of the bottom surface of the trench can be relaxed, and the breakdown voltage of the switching element can be improved.

JP 2015-138958 A

In the switching element of Patent Document 1, each semiconductor layer is made of SiC (silicon carbide). The electric field relaxation layer is formed by ion-implanting a p-type impurity into the drift layer made of SiC.

In recent years, development of switching elements made of GaN (gallium nitride) based semiconductors has progressed. A GaN-based semiconductor is a semiconductor whose main material is a compound of gallium and nitrogen. GaN-based semiconductors include GaN, AlGaN, AlInGaN, and the like. It is extremely difficult to form a p-type layer of a GaN-based semiconductor by ion implantation, and the p-type layer of a GaN-based semiconductor is generally formed by epitaxial growth. Therefore, when providing an electric field relaxation layer in a switching element having a GaN-based semiconductor, it is not possible to employ a process such as that described in Patent Document 1 (that is, a process of forming an electric field relaxation layer by ion implantation of a p-type impurity). Have difficulty. Therefore, this specification proposes a technique for forming an electric field relaxation layer in a switching element having a GaN-based semiconductor.

The manufacturing method of the switching element disclosed in this specification has a body layer growing process, a trench forming process, a bottom layer forming process, a gate forming process, and a source layer forming process. In the body layer growth step, a p-type body layer made of a GaN-based semiconductor is epitaxially grown on an n-type drift layer made of a GaN-based semiconductor. In the trench forming step, a trench having a bottom surface located within the body layer is formed on the surface of the body layer. In the bottom layer forming step, an n-type bottom layer distributed from the bottom surface of the trench to the drift layer is formed in the body layer by implanting an n-type impurity into the bottom surface of the trench. In the gate forming step, a gate insulating film and a gate electrode are formed in the trench. The source layer forming step forms an n-type source layer separated from the bottom layer by the body layer and in contact with the gate insulating film.

Note that the source layer forming step may be performed at any time after the body layer is formed. For example, the source layer may be formed before the gate insulating film or after the gate insulating film. That is, as long as the source layer is in contact with the gate insulating film when both the source layer and the gate insulating film are formed, either the source layer or the gate insulating film may be formed first.

In this manufacturing method, a trench whose bottom surface is located in the body layer is formed on the surface of the body layer, and then n-type impurities are implanted into the bottom surface of the trench. As a result, the body layer near the bottom of the trench is made n-type, forming an n-type bottom layer distributed from the bottom of the trench to the drift layer. The body layer remaining without becoming n-type has a portion (main body layer) located above the bottom surface of the trench and a portion (electric field relaxation layer) located below the bottom surface of the trench. After that, a gate formation process and a source layer formation process are performed. By performing each step in this manner, a structure is obtained in which the electric field relaxation layer extends below the bottom surface of the trench (that is, the bottom end of the gate structure). When the potential of the gate electrode is increased to the gate threshold value or higher, a channel is formed in the main body layer in the range in contact with the gate insulating film. A connection is then established between the source layer and the drift layer through the channel and the bottom layer, turning on the switching element. When the potential of the gate electrode is lowered below the gate threshold, the channel disappears and the switching element is turned off. At this time, the depletion layer spreads from the electric field relaxation layer to the bottom layer, so that the electric field applied to the gate insulating film near the bottom of the trench is relaxed. Thus, according to this manufacturing method, it is possible to manufacture a switching element capable of relaxing the electric field in the vicinity of the bottom surface of the trench by the electric field relaxation layer. Moreover, in this manufacturing method, the body layer including the electric field relaxation layer is formed by epitaxial growth, so the p-type electric field relaxation layer made of a GaN-based semiconductor can be preferably formed.

Sectional drawing of the switching element of embodiment. Explanatory drawing of the manufacturing method of the switching element of embodiment. Explanatory drawing of the manufacturing method of the switching element of embodiment. Explanatory drawing of the manufacturing method of the switching element of embodiment. Explanatory drawing of the manufacturing method of the switching element of embodiment.

The switching element 10 of the embodiment shown in FIG. 1 is a MOSFET (metal-oxide-semiconductor field effect transistor). The switching element 10 has a semiconductor substrate 12 made of GaN. A trench 20 is formed in a surface (upper surface) 12 a of the semiconductor substrate 12 . A gate insulating film 22 and a gate electrode 24 are arranged in the trench 20 . A gate insulating film 22 covers the inner surface of the trench 20 . Gate electrode 24 is insulated from semiconductor substrate 12 by gate insulating film 22 . The surface of the gate electrode 24 is covered with an interlayer insulating film 26 . A source electrode 30 is arranged on the surface 12 a of the semiconductor substrate 12 . The source electrode 30 is insulated from the gate electrode 24 by an interlayer insulating film 26 . A drain electrode 32 is arranged on the back surface 12 b of the semiconductor substrate 12 .

The semiconductor substrate 12 has a source layer 40 , a body layer 42 , a bottom layer 46 , a heavily doped layer 48 , a drift layer 50 and a drain layer 52 .

Source layer 40 is an n-type layer and is in contact with source electrode 30 . The source layer 40 is in contact with the gate insulating film 22 at the upper end of the trench 20 .

The body layer 42 is a p-type layer and is arranged on the sides and below the source layer 40 . Body layer 42 separates source layer 40 from bottom layer 46 , high concentration layer 48 , drift layer 50 , and drain layer 52 . The body layer 42 has a body contact layer 42a, a main body layer 42b, and an electric field relaxation layer 42c.

The body contact layer 42a has a higher p-type impurity concentration than the main body layer 42b and the electric field relaxation layer 42c. Body contact layer 42 a is arranged on the side of source layer 40 and is in contact with source electrode 30 .

The main body layer 42b is arranged below the source layer 40 and the body contact layer 42a. The main body layer 42 b is a portion of the body layer 42 located within the depth range between the bottom surface of the trench 20 and the source layer 40 . The main body layer 42 b is in contact with the gate insulating film 22 below the source layer 40 .

The electric field relaxation layer 42c is arranged below the main body layer 42b. The electric field relaxation layer 42 c is a portion of the body layer 42 located below the bottom surface of the trench 20 . The electric field relaxation layer 42c has substantially the same p-type impurity concentration as the main body layer 42b. The electric field relaxation layer 42 c does not exist directly below the trench 20 .

Bottom layer 46 is an n-type layer and is located directly below trench 20 . Bottom layer 46 contacts gate insulating film 22 at the bottom of trench 20 . The bottom layer 46 is arranged between the two field relief layers 42c.

Dense layer 48 is an n-type layer and is located directly below bottom layer 46 . High concentration layer 48 has a higher n-type impurity concentration than bottom layer 46 and drift layer 50 .

The drift layer 50 is an n-type layer and is arranged below the high-concentration layer 48 and the electric field relaxation layer 42c.

The drain layer 52 is an n-type layer and is arranged below the drift layer 50 . The drain layer 52 has a higher n-type impurity concentration than the drift layer 50 . The drain layer 52 is in contact with the drain electrode 32 .

When the switching element 10 is used, a potential higher than that of the source electrode 30 is applied to the drain electrode 32 . When the potential of the gate electrode 24 is raised above the gate threshold, a channel is formed in the main body layer 42b near the gate insulating film 22, and the channel connects the source layer 40 to the bottom layer 46. FIG. Electrons then flow from the source electrode 30 to the drain electrode 32 via the source layer 40 , the channel, the bottom layer 46 , the high concentration layer 48 , the drift layer 50 and the drain layer 52 . That is, the switching element 10 is turned on. The high-concentration layer 48 having a high n-type impurity concentration is provided under the bottom layer 46, thereby reducing the resistance of the path through which electrons flow. Therefore, this switching element 10 has a low on-resistance.

When the potential of the gate electrode 24 is lowered below the gate threshold, the channel disappears and the switching element 10 is turned off. When the switching element 10 is turned off, a depletion layer spreads from the body layer 42 to the bottom layer 46 , the high concentration layer 48 and the drift layer 50 . A potential difference between the body layer 42 and the drain layer 52 is maintained by the bottom layer 46 , the heavily doped layer 48 , and the depletion layer extending through the drift layer 50 . Further, in the switching element 10, the electric field relaxation layers 42c are arranged beside the bottom layer 46, and the bottom layer 46 is sandwiched between the electric field relaxation layers 42c. Therefore, the bottom layer 46 is depleted by depletion layers extending from the electric field relaxation layers 42c on both sides. Therefore, when the switching element 10 is turned off, the depletion layer instantly spreads to the bottom layer 46 , and concentration of the electric field on the gate insulating film 22 near the bottom of the trench 20 is suppressed. That is, the electric field generated in the vicinity of the bottom surface of the trench 20 is alleviated by the electric field relaxation layer 42c. Therefore, this switching element 10 has a high breakdown voltage.

Next, a method for manufacturing the switching element 10 will be described. The switching element 10 is manufactured from a semiconductor wafer having a drain layer 52 made of GaN. First, as shown in FIG. 2, the n-type drift layer 50 made of GaN is epitaxially grown on the drain layer 52 . Here, the drift layer 50 having a thickness of about 4.9 μm and an n-type impurity concentration of about 2×10 ¹⁶ /cm ³ is formed. Next, a p-type body layer 42 made of GaN is epitaxially grown on the drift layer 50 . Here, a body layer 42 having a thickness of about 2.3 μm and a p-type impurity concentration of about 5×10 ¹⁷ /cm ³ is formed.

Next, as shown in FIG. 3, a trench 20 having a bottom surface within the body layer 42 is formed in the surface of the body layer 42 .

Next, as shown in FIG. 4, a mask 60 is formed on the surface of the body layer 42 so as not to cover the trench 20 . Then, an n-type impurity (for example, Si (silicon)) is ion-implanted into the bottom surface of the trench 20 through the mask 60 . Here, by adjusting the injection energy of the n-type impurities, the n-type impurities are distributed in a depth range extending from the bottom surface of the trench 20 to the drift layer 50 as shown in the range 62 in FIG. to inject. Next, the implanted n-type impurity is activated. This renders body layer 42 in area 62 n-type, forming n-type bottom layer 46 in body layer 42 immediately below trench 20, as shown in FIG. Here, the bottom layer 46 is formed with an n-type impurity concentration of about 5.5×10 ¹⁷ /cm ³ . A high-concentration layer 48 having a high n-type impurity concentration is formed immediately below the bottom layer 46 by implanting n-type impurities into the n-type drift layer 50 . Heavy layer 48 has a higher n-type impurity concentration than drift layer 50 and bottom layer 46 . In addition, the portion of the body layer 42 that has not been n-typed below the bottom surface of the trench 20 serves as an electric field relaxation layer 42c. Of the body layer 42 that has not been converted to the n-type, the portion above the bottom surface of the trench 20 becomes the main body layer 42b.

Next, as shown in FIG. 1, a gate insulating film 22 and a gate electrode 24 are formed inside the trench 20 . Next, the source layer 40 and the body contact layer 42a are formed by selectively implanting n-type impurities and p-type impurities into a part of the main body layer 42b. Next, an interlayer insulating film 26 is formed on the surface of the gate electrode 24 . Furthermore, the source electrode 30 is formed so as to cover the surfaces of the interlayer insulating film 26, the source layer 40, and the body layer 42. Next, as shown in FIG. Next, the drain electrode 32 is formed on the back surface of the drain layer 52 . By performing the above steps, the switching element 10 shown in FIG. 1 is completed.

As described above, according to this manufacturing method, part of the body layer 42 formed by epitaxial growth serves as the electric field relaxation layer 42c. That is, by epitaxial growth, the p-type electric field relaxation layer 42c made of GaN and projecting downward from the bottom surface of the trench 20 can be formed. That is, according to the manufacturing method of the embodiment, each semiconductor layer can be formed by epitaxial growth and n-type impurity ion implantation without performing p-type impurity ion implantation. Epitaxial growth and n-type impurity ion implantation can be suitably performed on GaN-based semiconductors. Therefore, according to the manufacturing method of the embodiment, the switching element 10 can be suitably manufactured.

Further, according to this manufacturing method, the high-concentration layer 48 having a high n-type impurity concentration can be formed under the bottom layer 46, so that the on-resistance of the switching element 10 can be reduced. Further, since the high-concentration layer 48 is formed at a position not in contact with the trench 20, the depletion layer extending from the electric field relaxation layer 42c easily spreads to the vicinity of the bottom of the trench 20, effectively alleviating the electric field concentration at the bottom of the trench 20. be able to.

The technical elements disclosed in this specification are listed below. Each of the following technical elements is independently useful.

In one example of the manufacturing method disclosed in the present specification, in the step of forming the bottom layer, n-type impurities are implanted into a range extending from the body layer to the drift layer, so that the bottom layer and the drift layer are located below the bottom layer. Alternatively, a high-concentration layer having a high n-type impurity concentration may be formed.

With this configuration, the ON resistance of the switching element can be reduced.

Although the embodiments have been described in detail above, they are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or in the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in this specification or drawings simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

10: switching element 12: semiconductor substrate 20: trench 22: gate insulating film 24: gate electrode 26: interlayer insulating film 30: source electrode 32: drain electrode 40: source layer 42: body layer 42a: body contact layer 42b: main body Layer 42c: electric field relaxation layer 46: bottom layer 48: high concentration layer 50: drift layer 52: drain layer

Claims (1)

A method for manufacturing a switching element,
epitaxially growing a p-type body layer made of a GaN-based semiconductor on an n-type drift layer made of a GaN-based semiconductor;
forming a trench in the surface of the body layer, the bottom of which is located within the body layer;
forming an n-type bottom layer in the body layer distributed from the bottom surface of the trench to the drift layer by implanting an n-type impurity into the bottom surface of the trench;
forming a gate insulating film and a gate electrode in the trench;
forming an n-type source layer in the body layer before or after forming the trench, the bottom layer, the gate insulating film and the gate electrode ;
has
after forming the trench, the bottom layer, the gate insulating film, the gate electrode and the source layer, the source layer is separated from the bottom layer by the body layer and is in contact with the gate insulating film;
In the step of forming the bottom layer, by implanting n-type impurities into a range spanning from the body layer to the drift layer, a lower portion of the bottom layer has a higher n-type impurity concentration than the bottom layer and the drift layer. A manufacturing method for forming a highly concentrated layer .

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