JP7121816B2 - Manufacturing method of resistor array, output buffer and semiconductor device - Google Patents

Description

The present invention relates to a resistor array including a plurality of resistors, an output buffer having this resistor array, and a method of manufacturing a semiconductor device.

2. Description of the Related Art An electronic device made of a semiconductor device is provided with an output buffer that compensates for signal attenuation on a transmission line connecting the electronic devices in order to externally output a signal generated by the electronic device. A resistor (hereinafter referred to as an output resistor) is connected to the output terminal of the output buffer to prevent electrostatic damage and to achieve impedance matching with respect to the transmission line.

In addition, an output buffer circuit that employs a variable resistor as such an output resistor has been proposed (see, for example, Japanese Unexamined Patent Application Publication No. 2002-100001). The variable resistor is composed of a transfer gate of a MOS (Metal Oxide Semiconductor) transistor, and the resistance value of the pass gate is made variable by controlling the gate voltage.

JP 2009-164718 A

However, in order to set the transfer gate to a desired resistance value, a circuit (for example, a reference resistor, a comparator, and an output driver) is required to generate a gate voltage corresponding to the resistance value and supply it to the gate end of the transfer gate. As a result, there arises a problem that the scale of the apparatus increases.

In addition, when the above-described output resistor is a fixed resistor using polysilicon or the like, the resistance value required for preventing electrostatic breakdown and impedance matching with the transmission line is a low resistance of, for example, 700 ohms or less. A problem arises in that the resistance error rate due to manufacturing variations becomes large.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a resistor array that can be adjusted to a desired resistance value with high accuracy, an output buffer having this resistor array, and a method of manufacturing a semiconductor device in which the resistor array is formed. and

A resistor array according to the present invention is a resistor array formed of a semiconductor, and each includes first to Mth (M is an integer equal to or greater than 2) resistors connected in series. an integer of 2 or more), a common line that commonly connects one ends of the M-th resistors of the first to n-th series resistors, and the first to n-th series resistors a short-circuit line for short-circuiting both ends of each resistor except at least one of the first to M-th resistors or both ends of the resistor string in each of .

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device, comprising: first to n-th series resistor units each including first to M-th resistors (M is an integer equal to or greater than 2); a common line connecting one ends of the Mth resistor of each of the first to n-th series resistance sections; a first manufacturing step of manufacturing, as a semiconductor device for measurement, a semiconductor device in which a resistor array having short-circuit lines for short-circuiting both ends of each resistor or both ends of a resistor string except for one predetermined resistor of a resistance value measuring step of measuring the resistance value of the resistor array formed in the semiconductor device for measurement as an actual measured resistance value; a resistance selection information generation step of generating resistance selection information designating one of the first to Mth resistances as a valid resistance; a common line connecting one end of each of the M-th resistors of the first to n-th series resistors; and the resistor selection information in each of the first to n-th series resistors. a second manufacturing step of manufacturing a semiconductor device in which a resistor array having a short-circuit line for short-circuiting both ends of each resistor except the one resistor or both ends of a resistor string is formed as a semiconductor device for shipment; have

An output buffer according to the present invention is an output buffer that takes in an input signal and outputs it to the outside through an external terminal, and includes first to Mth resistors (M is an integer of 2 or more) connected in series, respectively. 1st to n-th (n is an integer equal to or greater than 2) series resistance units; a common line connecting one end of the M-th resistor of each of the 1st to n-th series resistance units and the external terminal; and a short-circuit line that short-circuits both ends of each resistor except at least one of the first to M-th resistors or both ends of a resistor string in each of the first to n-th series resistor units. and the first to n-th series resistors, respectively, and the first to n-th series resistors corresponding to the first to n-th amplified signals obtained by individually amplifying the input signals. and first to n-th drivers that supply one end of the first resistor of each series resistor section.

Further, an output buffer according to the present invention is an output buffer that takes in an input signal and outputs it to the outside through an external terminal, comprising first to n-th (n is an integer equal to or greater than 2) resistors, a common line connecting one end of each of the n-th resistors to the external terminal; first to n-th three-state drivers that supply amplified first to n-th amplified signals to the other ends of the corresponding first to n-th resistors; and the first to n-th three-state drivers and an output impedance adjuster that supplies first to n-th enable signals individually set to one of an enabled state and a disabled state to the first to n-th three-state drivers.

In the present invention, in each of the series resistor units of a resistor array having a plurality of series resistor units each including a plurality of resistors connected in series, both ends of each resistor excluding at least one resistor of the plurality of resistors or the resistor By shorting the ends of the columns with conductive lines, the resistance of the resistor array itself is adjusted to the desired resistance. Further, in the present invention, the output resistor section includes first to n-th resistors, and the first resistor unit supplies the first to n-th amplified signals obtained by separately amplifying the input signals to the first to n-th resistors, respectively. to n-th three-state drivers, in which the first to n-th three-state drivers are individually and fixedly set to one of an enabled state and a disabled state to obtain a resistance value of the output resistor unit is adjusted.

Therefore, even if the actual resistance value of the resistor array (output resistor section) immediately after manufacturing does not match the desired resistance value, by changing the combination of effective resistors among a plurality of resistors, the resistor It becomes possible to adjust the resistance value of the array (output resistor section) to a desired resistance value. Furthermore, by increasing the number of resistors included in the resistor array (output resistor section) or by reducing the difference in resistance value between resistors, it is possible to increase the resolution when adjusting the resistance value. Even a low resistance value for impedance matching of a transmission line can be adjusted to a desired resistance value with high accuracy.

1 is a circuit diagram showing an example of an output buffer 100 including an output resistor section 10 as a resistor array according to the present invention; FIG. FIG. 10 is a cross-sectional view showing a cross-section of a series resistance part in each of RA selection pattern, RB selection pattern and RC selection pattern; 3 is a flow diagram schematically showing a method of manufacturing a semiconductor IC chip including the output buffer 100; FIG. 4 is a diagram showing an example of resistance selection patterns PT1 to PT46 by series resistance sections R1 to R22 and resistance ratios in each resistance selection pattern; FIG. 3 is a circuit diagram showing an output buffer 300 according to the present invention; FIG.

FIG. 1 is a circuit diagram showing an example of an output buffer 100 including a resistor array according to the invention. The output buffer 100 is formed on, for example, a semiconductor IC (Integrated Circuit) chip. The output buffer 100 amplifies the signal SIG generated by the internal circuit formed in the semiconductor IC chip and outputs the amplified signal to the outside through the output pad 200 of the semiconductor IC chip.

The output buffer 100, as shown in FIG. 1, has an output resistor section 10 consisting of a resistor array, a pre-driver section 20 and an output driver section 30. FIG.

The pre-driver section 20 includes drivers PD1 to PD(n) (n is an integer equal to or greater than 2) whose input terminals are connected to each other and individually receive a single signal SIG via the input terminals. The drivers PD1 to PD(n) supply the amplified signals a1 to a(n) obtained by individually amplifying the signal SIG to the output driver section 30 .

The output driver section 30 includes drivers OD1-OD(n) that individually receive the amplified signals a1-a(n), respectively. The drivers OD1 to OD(n) supply the amplified signals b1 to b(n) obtained by amplifying the amplified signals a1 to a(n) respectively received to the output resistor section 10. FIG.

The output resistor section 10 has series resistor sections R1 to R(n) each including a resistor group in which resistors RA, RB and RC having different resistance values are connected in series. All of the resistors RA, RB, and RC have resistance values sufficient to protect against electrostatic breakdown. Also, the resistance values of the resistors RA, RB, and RC have, for example, the following magnitude relationship.

RA>RB>RC
Amplified signals b1 to b(n) are individually supplied to one end Q1 of the resistor RA of each of the series resistors R1 to R(n), and one end Q3 of the resistor RB is connected to the other end Q2 of each resistor RA. ing. One end Q5 of the resistor RC is connected to the other end Q4 of the resistor RB of each of the series resistors R1 to R(n). The other end Q6 of the resistor RC of each of the series resistors R1 to R(n) is commonly connected to the output pad 200 via a common line LO.

Each of the series resistor units R1 to R(n) has an RA selection pattern in which only the resistor RA among the resistors RA, RB, and RC is effective, an RB selection pattern in which only the resistor RB is effective, and a resistor It is formed in one form of RC selection pattern in which only RC is the effective resistance.

In the embodiment shown in FIG. 1, the series resistance portion R1 is formed in the RB selection pattern, the series resistance portion R2 is formed in the RA selection pattern, and the series resistance portion R3 is formed in the RC selection pattern. ing.

In the RA selection pattern, one end Q3 of the resistor RB and the other end Q6 of the resistor RC are short-circuited by a short-circuit line LMR, as indicated by the series resistor portion R2 in FIG. 1, for example. In other words, in the RA selection pattern, both ends of the resistor string (RB, RC) excluding the resistor RA among the resistors RA, RB, and RC are short-circuited by the short-circuit line LMR. As a result, the actual resistance value of the series resistor R2 in the RA selection pattern becomes the resistance value of the resistor RA.

In the RB selection pattern, one end Q1 and the other end Q2 of the resistor RA are short-circuited by a short-circuit line LL, and one end Q5 and the other end Q6 of the resistor RC are short-circuited by a short-circuit line LL, as shown by the series resistor portion R1 in FIG. Shorted by LR. That is, in the RB selection pattern, both ends of each resistor (RA, RC) other than the resistor RB among the resistors RA, RB, and RC are short-circuited by the short-circuit line LL or LR. As a result, the actual resistance value of the series resistor R1 in the RB selection pattern becomes the resistance value of the resistor RB.

In the RC selection pattern, one end Q1 of the resistor RA and the other end Q4 of the resistor RB are short-circuited by a short-circuit line LML, as indicated by the series resistor portion R3 in FIG. 1, for example. That is, in the RC selection pattern, among the resistors RA, RB and RC, both ends of the resistor string (RA, RB) excluding the resistor RC are short-circuited by the short-circuit line LML. As a result, the actual resistance value of the series resistor R3 in the RC selection pattern becomes the resistance value of the resistor RC.

FIG. 2 is a cross-sectional view showing one of the series resistors R1 to R(n) and showing the cross section of the series resistors in each of the RA selection pattern, the RB selection pattern and the RC selection pattern. As shown in FIG. 2, in any of the RA selection pattern, the RB selection pattern and the RC selection pattern, each of the series resistors R1 to R(n) is polysilicon formed dispersedly on the surface of the semiconductor substrate SUB. It has resistance regions PLa, PLb and PLc, an insulating layer OF, contact holes C1 to C6, and metal layers MT1 and MT2.

The insulating layer OF is made of SiO2, for example, and is formed so as to cover the surface of the semiconductor substrate SUB and the surfaces of the polysilicon resistance regions PLa, PLb, and PLc. The contact holes C1 to C6 of each series resistance section are formed through the insulating layer OF from one surface to the other surface. The inside of each of the contact holes C1 to C6 is filled with the same material as the metal layer MT1 (MT2) made of a conductive material such as aluminum. At this time, the contact hole C1 is formed on one end of the polysilicon resistance region PLa, and the contact hole C2 is formed on the other end of the polysilicon resistance region PLa. A contact hole C3 is formed on one end of the polysilicon resistance region PLb, and a contact hole C4 is formed on the other end of the polysilicon resistance region PLb. A contact hole C5 is formed on one end of the polysilicon resistance region PLc, and a contact hole C6 is formed on the other end of the polysilicon resistance region PLc.

As shown in FIG. 2, in each series resistance portion, a region p1 surrounded by a broken line including a polysilicon resistance region PLa and contact holes C1 and C2 becomes the resistance RA shown in FIG. A region p2 surrounded by a dashed line including C4 and C4 becomes a resistor RB. Further, in FIG. 2, a region p3 surrounded by a broken line including the polysilicon resistance region PLc and the contact holes C5 and C6 becomes the resistor RC shown in FIG.

As shown in FIG. 2, each of the resistors RA, RB, and RC includes a high resistance portion HA having a high resistance value and a high resistance portion HA in each polysilicon resistance region (PLa, PLb, PLc). A low resistance portion LA having a resistance value lower than that is formed. That is, as shown in FIG. 2, in each polysilicon resistor region, a first contact hole (for example, C1, C3, C5) formed at one end and a second contact hole formed at the other end. A high resistance area HA is formed in the center of the holes (for example, C2, C4, C6), and a low resistance area LA is formed in the vicinity of each of the first and second contact holes. Therefore, the resistance value of each resistor (RA, RB, RC) is a combined resistance value of the resistance value at each high resistance portion HA and the resistance value at each pair of low resistance portions LA.

Here, in the RA selection pattern, as shown in FIG. 2, a metal layer MT1 is formed so as to cover the opening of the contact hole C1 and the surface of the insulating layer OF. Furthermore, in the RA selection pattern, a metal layer MT2 is formed to cover the openings of the contact holes C2 to C6 and the surface of the insulating layer OF over the region r1 including the contact holes C2 to C6. In the RA selection pattern, the metal layer MT2 carries the shorting lines LMR shown in FIG.

Further, in the RB selection pattern, as shown in FIG. 2, the metal layer MT1 extends over the region r2 including the contact holes C1 to C3 so as to cover the openings of the contact holes C1 to C3 and the surface of the insulating layer OF. formed. Furthermore, in the RB selection pattern, a metal layer MT2 is formed to cover the openings of the contact holes C4 to C6 and the surface of the insulating layer OF over the region r3 including the contact holes C4 to C6. In the RB selection pattern, the metal layer MT1 serves as the shorting line LL shown in FIG. 1, and the metal layer MT2 serves as the shorting line LR shown in FIG.

Further, in the RC selection pattern, a metal layer MT1 is formed so as to cover the openings of the contact holes C1 to C5 and the surface of the insulating layer OF over the region r4 including the contact holes C1 to C5. Furthermore, in the RC selection pattern, a metal layer MT2 is formed so as to cover the opening of the contact hole C6 and the surface of the insulating layer OF. That is, in the RC selection pattern, the metal layer MT1 bears the short-circuit line LML shown in FIG.

In the above embodiment, the number of resistors connected in series in each of the series resistor units R1 to R(n) is three, ie, the resistors RA, RB, and RC. can be

In short, the output resistor section 10 as a resistor array includes first to n-th (n is an integer of 2 or more) each including first to M-th (M is an integer of 2 or more) resistors (RA, RB, RC). ) and the following common line and short-circuit line. That is, one ends of the M-th resistor (RC) of each of the first to n-th series resistance sections are connected to each other by a common line (LO), and in each of the first to n-th series resistance sections, Both ends of each resistor except at least one resistor among the first to Mth resistors or both ends of the resistor array are short-circuited by short-circuit lines (LL, LR, LMR, LML).

A method of manufacturing a semiconductor IC chip including the output buffer 100 shown in FIGS. 1 and 2 will be described below along the schematic manufacturing flow shown in FIG.

First, a semiconductor manufacturing device (not shown) measures a semiconductor IC chip in which all the series resistors R1 to R(n) of the output resistor 10 in the output buffer 100 are formed in the RA selection pattern shown in FIG. A chip A is manufactured (step S1). Next, the semiconductor manufacturing apparatus manufactures a semiconductor IC chip in which all of the series resistance sections R1 to R(n) of the output resistance section 10 are formed in the RB selection pattern shown in FIG. 2 as the measurement chip B (step S2 ). Next, the semiconductor manufacturing apparatus manufactures a semiconductor IC chip in which the series resistors R1 to R(n) of the output resistor 10 are all formed in the RC selection pattern shown in FIG. 2 as a measurement chip C (step S3 ).

After manufacturing the measuring chips A to C in steps S1 to S3, first, the measuring chip A is connected to a tester (not shown).

The tester measures the resistance value of the output resistance section 10 of the measurement chip A as the measured resistance value XRA (step S4). For example, in step S4, the tester supplies amplified signals b1 to b(n) each having a voltage value corresponding to logic level 1 (or 0) to the output resistor section 10 via the output driver 30, Take in 200 voltage values. Here, in the measuring chip A, all the series resistors R1 to R(n) are formed in the RA selection pattern. Of RB and RC, only n resistors RA are connected in parallel. Therefore, in step S4, the tester determines the combined resistance of the circuit in which n resistors RA are connected in parallel based on the voltage value of the pad 200 and the voltage value corresponding to the logic level 1 (or 0) that has been taken in as described above. is calculated as the measured resistance value XRA of the output resistance section 10.

Next, the measuring chip B is connected to the tester. The tester measures the resistance value of the output resistance section 10 of the measurement chip B as the measured resistance value XRB (step S5). For example, in step S5, the tester supplies the amplified signals b1 to b(n) each having a voltage value corresponding to logic level 1 (or 0) to the output resistor section 10 via the output driver 30, and the output pad Take in 200 voltage values. Here, in the measuring chip B, all the series resistors R1 to R(n) are formed in the RB selection pattern, so the output resistor part 10 of the measuring chip B is equivalently equivalent to the resistors RA, Only n resistors RB out of RB and RC are connected in parallel. Therefore, in step S5, the tester determines the combined resistance of the circuit in which n resistors RB are connected in parallel, based on the voltage value of the pad 200 and the voltage value corresponding to the logic level 1 (or 0), which is read as described above. The value is calculated as the measured resistance value XRB of the output resistance section 10 .

Next, the measuring chip C is connected to the tester. The tester measures the resistance value of the output resistance section 10 of the measurement chip C as the measured resistance value XRC (step S6). For example, in step S6, the tester supplies the amplified signals b1 to b(n) each having a voltage value corresponding to logic level 1 (or 0) to the output resistor section 10 via the output driver 30, and the output pad Take in 200 voltage values. Here, in the measuring chip C, all the series resistors R1 to R(n) are formed with RC selection patterns, so the output resistor 10 of the measuring chip C is equivalently equivalent to the resistors RA, Of RB and RC, only n resistors RC are connected in parallel. Therefore, in step S6, the tester determines the combined resistance of the circuit in which n resistors RC are connected in parallel based on the voltage value of the pad 200 and the voltage value corresponding to the logic level 1 (or 0), which has been taken in as described above. The value is calculated as the measured resistance value XRC of the output resistor section 10 .

Next, based on the measured resistance values XRA, XRB, and XRC, the tester generates manufacturing resistance selection information indicating a resistance selection pattern that matches the combined resistance value of the series resistance units R1 to R(n) with the desired resistance value. (step S7). The desired resistance value is the resistance value required as the resistance value of the output resistance section 10, and the resistance selection pattern is for each of the series resistance sections R1 to R(n). This pattern indicates which of the RA selection pattern, the RB selection pattern, and the RC selection pattern is adopted in the . That is, the manufacturing resistor selection information designates which of the series-connected resistors RA, RB, and RC is to be the effective resistor for each of the series resistor units R1 to R(n). It is information to do.

For example, in step S7, the tester first determines the ratio of the measured resistance value XRA (hereinafter referred to as resistance ratio) is calculated as the maximum resistance ratio, and the resistance ratio of the actually measured resistance value XRC is calculated as the minimum resistance ratio. Here, the tester has 3 to the power of n resistance selection patterns assumed from the fact that each of the series resistance units R1 to R(n) can take one of the RA selection pattern, the RB selection pattern, and the RC selection pattern. Among them, those having different combined resistance values due to their resistance selection patterns are extracted. For example, when the number “n” of the series resistance units R1 to R(n) is 22, there are 3 to the 22nd power of resistance selection patterns by the series resistance units R1 to R22. As representative resistance selection patterns, 46 resistance selection patterns PT1 to PT46 as shown in FIG. 4 are extracted. Then, based on the calculated maximum resistance ratio and minimum resistance ratio, the tester obtains the resistance ratio corresponding to the combined resistance value in each of the resistance selection patterns extracted as described above, and selects each resistance. Assign to pattern. For example, if the resistance ratio (maximum resistance ratio) of the measured resistance value XRA is "1.25", the tester selects a resistance selection pattern that maximizes the combined resistance value, that is, the series resistance part R1 as shown in FIG. A resistance ratio of "1.25" is assigned to the resistance selection pattern PT1 in which all of R22 are RA selection patterns. Further, when the resistance ratio (minimum resistivity) of the measured resistance value XRC is, for example, "0.75", the tester selects a resistance selection pattern that minimizes the combined resistance value, that is, the series resistance part R1 as shown in FIG. A resistance ratio of "0.75" is assigned to the resistance selection pattern PT46 in which all of R22 are RC selection patterns. At this time, among the series resistance units R1 to R22, the more the number of series resistance units formed with the RA selection pattern, the greater the combined resistance value, while the more the number of series resistance units formed with the RC selection pattern. The combined resistance value decreases as the value increases. Therefore, based on the maximum resistance ratio "1.25" and the minimum resistance ratio "0.75", the tester adopts the resistance selection pattern for each of the resistance selection patterns PT2 to PT45 as shown in FIG. Allocate the resistance ratio corresponding to the combined resistance value in the case of Next, the tester divides the desired resistance value required as the resistance value of the output resistor section 10 by the measured resistance value XRB and sets the result of division as the measured resistance ratio, and the same resistance ratio as this measured resistance ratio or the nearest value A resistance selection pattern corresponding to the resistance ratio of is selected from the resistance selection pattern group described above, for example, the resistance selection patterns PT1 to PT46. Then, the tester designates one effective resistor among the resistors RA, RB, and RC for each of the information represented by the selected resistor selection pattern, that is, each of the series resistor units R1 to R(n). Generate manufacturing resistor selection information. For example, when the measured resistance ratio is "1.21", the tester selects PT4 from the resistance selection patterns PT1 to PT46 shown in FIG. As shown in FIG. 4, the resistor selection pattern PT4 represents that each of the series resistors R1 to R19 is formed in the RA selection pattern and each of the series resistors R20 to R22 is formed in the RB selection pattern. there is Therefore, at this time, the tester designates the resistor RA among the resistors RA, RB, and RC as a valid resistor in each of the series resistors R1 to R19, and specifies the resistor RB as a valid resistor in each of the series resistors R20 to R22. Generate manufacturing resistor selection information to specify as a resistor.

Then, when the manufacturing resistor selection information is generated in step S7 described above, the semiconductor manufacturing equipment connects the short-circuit lines (LL, LR, LMR , LML) is manufactured as a semiconductor device for shipment (step S8).

Incidentally, in the manufacturing flow shown in FIG. 3, three measuring chips A, B and C are manufactured and the resistance values of the respective output resistor portions 10 are actually measured to correspond to the resistors RA, RB and RC respectively. Measured resistance values XRA, XRB and XRC are obtained. However, by manufacturing only two of the measuring chips A to C (for example, measuring chips A and B) and actually measuring the resistance value of each output resistor section 10, two resistors (for example, resistors RA and RB ) is obtained, and the measured resistance value of the remaining one resistor (eg, resistor RC) is calculated based on the measured resistance value (for example, XRA and XRB). Further, in the above embodiment, all the series resistors R1 to R(n) in each of the measuring chips A, B, and C are manufactured with a single resistor selection pattern, but two or three resistor selections are possible. You may make it manufacture by mixing a pattern.

In short, in the present invention, the output resistor section 10 (resistor array) whose resistance value is adjusted by the following first manufacturing process, resistance measurement process, resistance selection information generating process, and second manufacturing process. What is necessary is just to manufacture the semiconductor IC chip containing it as a semiconductor device for shipment. First, in the first manufacturing process (S1 to S3), first to n-th series resistor units (R1 to R(n)) each including first to M-th resistors (RA, RB, RC) and , a common line (LO) connecting one ends of the M-th resistors (RC) of the first to n-th series resistance sections, and A semiconductor for measurement in which a resistor array (10) having short-circuit lines (LL, LR, LMR, LML) for short-circuiting both ends of each resistor except a predetermined one resistor or both ends of a resistor string is formed. Manufacture equipment. Next, in resistance value measurement steps (S4 to S6), resistance values of the resistance array (10) formed in the semiconductor device for measurement are measured as actual resistance values (XRA, XRB, XRC). Next, in the resistance selection information generation step (S7), based on the measured resistance value, one resistance among the first to Mth resistors is set as an effective resistance for each of the first to nth series resistor units. Generates specified manufacturing resistor selection information. Then, in the second manufacturing step (S8), the first to n-th series resistor sections each including the first to M-th resistors and the M-th resistor of each of the first to n-th series resistor sections In each of the common line connecting one end to each other and the first to n-th series resistor parts, short-circuit both ends of each resistor or both ends of the resistor string except for the one resistor indicated by the above-described manufacturing resistor selection information A semiconductor IC chip formed with a resistor array having short-circuit lines (LL, LR, LMR, LML) is manufactured as a semiconductor device for shipment.

Therefore, according to the manufacturing method shown in FIG. 3 and the output resistor section 10 as a resistor array, the output buffer 100 including the output resistor section 10 whose resistance value is adjusted to a desired resistance value is formed. It becomes possible to manufacture the device. At this time, according to the output resistor section 10 and the manufacturing method shown in FIG. ) or by reducing the difference in the resistance values between the resistors, the resolution in adjusting the resistance values can be increased. Therefore, for example, even a low resistance value for impedance matching of a transmission line can be adjusted to a desired resistance value with high accuracy. Also, only the metal wiring MT1 or MT2 of the output resistor section 10 is changed in the semiconductor device for shipment from the semiconductor device for measurement. Therefore, among the mask patterns for manufacturing the semiconductor device for shipment, mask patterns other than the mask pattern for forming the metal wiring MT1 or MT2 of the output resistor section 10 are created for manufacturing the semiconductor device for measurement. is the same as the mask pattern Therefore, after manufacturing the semiconductor device for measurement, it is possible to suppress an increase in the manufacturing cost due to the change of the mask pattern when manufacturing a new semiconductor device for shipment whose resistance value has been adjusted.

FIG. 5 is a circuit diagram showing the configuration of output buffer 300 according to the present invention. The output buffer 300 is formed on a semiconductor IC chip similarly to the output buffer 100 shown in FIG. Externally output via pad 200 .

The output buffer 300 has an output resistor section 10A consisting of a resistor array, a pre-driver section 20A, an output driver section 30, and an output impedance adjustment section 50. FIG.

The pre-driver section 20A has three-state drivers PQ1 to PQ(n) (where n is 2 or more) that individually take in a single signal SIG via the input terminals. integer). Enable signals Y1 to Y(n) corresponding to the drivers PQ1 to PQ(n) are individually supplied to the drivers PQ1 to PQ(n). Each driver PQ is set to a disabled state when the enable signal Y supplied to it represents, for example, logic level 0, and fixes its own output terminal to a high impedance state. Further, the drivers PQ1 to PQ(n) are set to an enable state when the enable signal Y supplied to them represents, for example, logic level 1, and output a signal obtained by amplifying the signal SIG to their own output terminals. output through The drivers PQ1-PQ(n) supply the output driver section 30 with amplified signals a1-a(n) representing the voltage values of the respective output terminals.

The output driver section 30 includes drivers OD1-OD(n) that individually receive the amplified signals a1-a(n), respectively. The drivers OD1-OD(n) supply the amplified signals b1-b(n) obtained by amplifying the amplified signals a1-a(n) respectively received to the output resistor section 10A.

The output resistor section 10A has resistors RR1 to RR(n) that individually receive the amplified signals b1 to b(n) at one end thereof, respectively. The other ends of the resistors RR1-RR(n) are commonly connected to the output pad 200 via a common line LO. The resistance values of the resistors RR1 to RR(n) may be the same or different from each other, as long as they have a resistance value sufficient to protect against electrostatic breakdown.

The output impedance adjuster 50 outputs binary (logical level 0 or 1) enable signals Y1 to Y(n) to the driver PQ1 to individually set the drivers PQ1 to PQ(n) to an enabled state or a disabled state. ~PQ(n).

In short, the output buffer 300 shown in FIG. 5 has the following output resistance section, first to n-th three-state drivers, and output impedance adjustment section. That is, the output resistor section (10A) includes first to n-th resistors (RR1 to RR(n)) and a common line (LO ) and including. The 1st to n-th three-state drivers (PQ1 to PQ(n)) are provided corresponding to the 1st to n-th resistors, respectively, and individually amplify the input signal (SIG). The n-th amplified signal (a1 to a(n)) is supplied to the other end of each of the corresponding first to n-th resistors. The output impedance adjuster (50) provides first to n-th enable signals (Y1 to Y(n )) to the first to n-th three-state drivers.

A method of adjusting the output impedance in the output buffer 300 shown in FIG. 5 will be described below.

In the initial state before product shipment, the output impedance adjustment unit 50 sets each of the drivers PQ designated in advance among the drivers PQ1 to PQ(n) to an enabled state, and sets each of the other drivers PQ to a disabled state. enable signals Y1-Y(n) to be supplied to drivers PQ1-PQ(n). Therefore, in the initial state, the resistor RR connected in series with the disabled driver PQ among the drivers PQ1 to PQ(n) is disabled and connected in series with the enabled driver PQ. The resistor RR that is connected is effective. As a result, the resistance value of the output resistance section 10A becomes the combined resistance value of each of the resistors RR connected in series with the driver PQ set in the enabled state. Therefore, for example, when the drivers PQ1 to PQ5 among the drivers PQ1 to PQ(n) are set to the enabled state and the other drivers PQ6 to PQ(n) are set to the disabled state, the resistance value of the output resistor section 10A is , the combined resistance value of the resistors RR1 to RR5.

Next, for the semiconductor IC chip including the output impedance adjustment section 50 in such an initial state, the tester sets the resistance value of the output resistance section 10A to the measured resistance value in the same manner as in step S5 shown in FIG. Measure.

Here, when the measured resistance value is lower than the desired resistance value required as the resistance value of the output resistor section 10A, the tester selects the desired resistance value from among the resistors RR1 to RR(n). A group of resistors RR having a combined resistance value higher than the measured resistance value by the amount of the error from the measured resistance value is selected. If the measured resistance value is higher than the desired resistance value, the tester selects the desired resistance value from among the resistors RR1 to RR(n) by the difference between the desired resistance value and the measured resistance value. Select a group of resistors RR whose combined resistance value is lower than the resistance value.

The tester is designed to generate the enable signals Y1 to Y(n) for setting each of the resistors RR belonging to the selected group to the enabled state and the other resistors RR to the disabled state even after the power is turned off. , the setting of the output impedance adjustment section 50 is fixed. That is, by setting the number of effective resistors RR among the resistors RR1 to RR(n) of the output resistor section 10A and the combination of the effective resistors RR, the output impedance adjustment section 50 sets the output resistor section 10A. is adjusted to a desired resistance value.

A semiconductor IC chip including the output buffer 300 adjusted in this way is shipped as a product.

Therefore, according to the output buffer 300 shown in FIG. 5, even if the actual resistance value of the output resistance section 10A immediately after manufacturing does not match the desired resistance value, the effective resistance combination among the plurality of resistances By changing the direction, the resistance value can be adjusted to a desired resistance value. Further, by increasing the number of resistors included in the output resistor section 10A and decreasing the resistance value of each resistor, it is possible to increase the resolution when adjusting the resistance value. Even a low resistance value can be adjusted to a desired resistance value with high accuracy.

10, 10A output resistor units 20, 20A predriver units 100, 300 output buffers LL, LR, LML, LMR short-circuit line LO common lines R1 to R(n) series resistor units RR1 to RR(n) resistors

Claims (9)

A resistor array formed of a semiconductor,
1st to n-th series resistor units each including 1st to M- th resistors connected in series;
a common line that commonly connects one end of each of the first to n-th series resistance units;
a short-circuit line that short-circuits both ends of each resistor excluding at least one of the first to M-th resistors or both ends of a resistor string in each of the first to n-th series resistor units,
A single input signal that is individually amplified is input to each of the first to n-th series resistance units ,
The resistor array , wherein M and n are integers of 2 or more . 2. The method according to claim 1, wherein said first to Mth resistors have different resistance values, and said at least one resistor is any one of said first to Mth resistors. Resistor array as described. 2. The resistor array according to claim 1, wherein said single input signal is individually amplified via a driver section and input to each of said first to n-th series resistor sections. The driver section has respective input terminals connected to each other, receives the single input signals individually through the input terminals, and amplifies the signals obtained by individually amplifying the single input signals. 4. The resistor array of claim 3, further comprising a pre-driver section including a plurality of output drivers. The driver section further includes an output driver section that individually receives the signals output from the pre-driver section, amplifies the received signals, and outputs the amplified signals to the first to n-th series resistor sections. 5. The resistor array of claim 4, comprising: A method for manufacturing a semiconductor device,
1st to n-th series resistance units each including 1st to M- th resistors;
a common line connecting one ends of each of the first to n-th series resistance sections in common ; and a short-circuit line for short-circuiting both ends of each resistor except one resistor or both ends of a resistor array, and manufacturing a semiconductor device having a resistor array formed thereon as first to Mth semiconductor devices for measurement. process and
a resistance value measuring step of measuring a combined resistance value of each of the resistor arrays formed in the first to Mth semiconductor devices for measurement as first to Mth measured resistance values;
Based on the first to M-th measured resistance values, the first to M-th series resistance units are connected to each of the first to n-th series resistor units so that the combined resistance value of the resistor array becomes a desired resistance value . a resistance selection information generating step of generating resistance selection information designating one of the resistances as a valid resistance;
first to n-th series resistance sections each including first to M-th resistors; a common line connecting one end of each of the first to n-th series resistance sections in common; a semiconductor device in which a resistor array is formed having a short-circuit line that short-circuits both ends of each resistor except the one resistor indicated by the resistor selection information or both ends of a resistor string in each of the n-th series resistor units; a second manufacturing step of manufacturing as a semiconductor device for shipment ,
A method of manufacturing a semiconductor device, wherein M and n are integers of 2 or more . 7. The method of manufacturing a semiconductor device according to claim 6, wherein the first to Mth resistors have different resistance values. An output buffer that takes in an input signal and outputs it to the outside via an external terminal,
1st to n-th series resistance units each including 1st to M- th resistors connected in series; and a common line connecting one end of each of the first to n-th series resistance units in common; and a short-circuit line that short-circuits both ends of each resistor except at least one of the first to M-th resistors or both ends of a resistor string in each of the first to n-th series resistor units. Department and
are provided corresponding to the first to n-th series resistors, respectively, are connected to each other at their input terminals, and individually amplify the input signals inputted through the input terminals. and first to n-th drivers for supplying first to n-th amplified signals to the corresponding first to n-th series resistor units , respectively ;
The output buffer , wherein the M and the n are integers of 2 or more . 9. The method according to claim 8, wherein the first to Mth resistors have different resistance values, and the at least one resistor is any one of the first to Mth resistors. The stated output buffer.

Images