JP7129161B2 - Time interleave operation check circuit - Google Patents

Description

In particular, the present invention is particularly applicable to modulation/demodulation circuits and time interleaving/deinterleaving sections of OFDM-FPU (for example, ARIB-STD B33). The present invention relates to a time interleave operation check circuit that detects a data mismatch that rarely occurs due to malfunction of a time interleave circuit when performing an interleave operation, using logic/memory in an FPGA.

Conventionally, a technique of comparing an output signal output by a device under test and an expected value signal has been used. For example, Patent Document 1 discloses a test apparatus for testing a device under test, which includes an address signal and a test signal supplied to the device under test, and an expected value to be output by the device under test to which the test signal is supplied. a pattern generator for generating a signal; and an output signal output by the device under test according to the test signal and the expected value signal are compared, and if the output signal and the expected value signal do not match, a fail signal. and a failure analysis memory for storing the fail signal generated by the logic comparator in an address area indicated by the address signal generated by the pattern generator, wherein the failure analysis memory comprises: A fail address value, which is the value of the address signal generated by the pattern generator, and a fail data value, which is the value of the fail signal generated by the logic comparator, are sequentially stored in different address areas as a set of data. 1 storage unit, and a second storage unit that reads out a combination of the fail address value and the fail data value from the first storage unit and stores the fail data value in an address area indicated by the fail address value. is disclosed.

Also, it is known that a malfunction of a time interleaving circuit causes a data mismatch, and various techniques have been developed as countermeasures against this phenomenon. For example, Patent Document 2 discloses a plurality of data latch circuits to which time-series data are commonly supplied to input terminals, and a first counter for sequentially supplying latch commands to the data latch circuits in synchronization with the supply of write clocks. , a multiplexer for sequentially retrieving and outputting data latched in the plurality of data latch circuits, and a second counter for supplying a switching signal to the multiplexer in synchronization with a readout clock. Disclosed is an interleave circuit equipped with a malfunction detection function, which is provided with a mismatch detection circuit that detects a mismatch between the states of a first counter and a second counter at the time of termination and outputs a signal indicating that the interleave circuit has malfunctioned. According to this technique, it is known that the read clock is missing by detecting a mismatch between the states of the first counter and the second counter.

For example, Patent Document 3 discloses a latch circuit group composed of a plurality of latch circuits to which time-series data is commonly applied to input terminals, and a write circuit that distributes a write clock to each latch circuit of the latch circuit group. clock distribution means, a multiplexer for sequentially reading and outputting the data latched in each latch circuit of the latch circuit group, switching signal generating means for supplying a switching signal to the multiplexer in synchronization with the read clock, and each of the latch circuit groups. a memory circuit group for storing that a write clock has been applied to a latch circuit; read clock distribution means for distributing a switching signal applied to the multiplexer to reset terminals of recording circuits constituting the memory circuit group; An interleave circuit having a malfunction detection function is disclosed which includes malfunction detection means for reading the storage state of each memory circuit of a circuit group and detecting lack of a read clock with respect to a write clock. According to this technique, even if even one read clock is missing from the write clock, this state can be detected and a malfunction can be displayed.

JP-A-2004-317317 Japanese Utility Model Laid-Open No. 63-50080 JP-A-63-109380

However, since the technique disclosed in the above patent document requires a complicated circuit configuration, it is difficult to realize it with the condition that the amount of resources is reduced as much as possible, for example, logic and memory in FPGA. It is also difficult to convert

The present invention is intended to solve the above-mentioned problems, and it is possible to compare data with a simple circuit configuration and operation timing, and to accurately check the malfunction of the time interleave circuit even under conditions where resources are limited. An object of the present invention is to provide a time interleave circuit operation check circuit.

In order to deal with the above problems, the present invention takes the following technical means.
That is, the invention according to claim 1 is a time interleave operation check circuit for checking malfunction of a time interleave circuit that performs time interleave processing on data to be processed in an OFDM modulation/demodulation circuit,
The time interleaving operation check circuit has an internal memory, and stores only one OFDM symbol of data extracted from data before being subjected to time interleaving processing by the time interleaving circuit in the internal memory, and A time interleave operation check characterized by checking malfunction of the time interleave circuit by comparing data for one OFDM symbol stored in a memory and predetermined processed data after the time interleave processing. circuit.

The invention according to claim 2 is the time interleave operation check circuit according to claim 1, wherein the comparison processing is performed when the time interleave processing for the data to be processed is completed by the time interleave circuit, and the superframe is completed. It is characterized in that it is performed in synchronization with the timing at which the data of the leading OFDM symbol is output.

The invention according to claim 3 is the time interleave operation check circuit according to claim 1 or 2, wherein the predetermined unit data is obtained by the following equation (1 ), and the predetermined processing data is 1 following the superframe head position of the data output from the time interleaving circuit after performing the time interleaving processing. It is characterized by data for symbols.

Further, the invention according to claim 4 is a time interleave operation check circuit for checking malfunction of a time deinterleave circuit that performs time deinterleave processing on data to be processed in an OFDM modulation/demodulation circuit,
The time interleaving operation check circuit has a built-in memory, and stores only one OFDM symbol worth of data extracted from the data before time deinterleaving processing is performed by the time deinterleaving circuit in the built-in memory, and A malfunction of the time deinterleaving circuit is checked by comparing data for one OFDM symbol stored in the internal memory and predetermined processed data after the time deinterleaving. It is a time interleave operation check circuit.

Further, the invention according to claim 5 is the time interleave operation check circuit according to claim 4, wherein the comparison processing is performed when the time deinterleaving circuit completes the time deinterleaving processing for the data to be processed, It is characterized in that it is performed in synchronization with the timing at which the data of the first OFDM symbol of the superframe is output.

The invention according to claim 6 is the time interleave operation check circuit according to claim 4 or 5, wherein the predetermined unit data is obtained by time deinterleaving so that the number of delay symbols of the data carrier is reduced from the beginning of the superframe. and the predetermined processing data is one symbol following the head position of the superframe of the data output from the time deinterleaving circuit after performing the time deinterleaving processing. The data are characterized by

The invention according to claim 7 is the time interleave operation check circuit according to claims 1 to 6, wherein the time interleave operation check circuit comprises a write enable signal generation circuit and a write address generation circuit. and storing the predetermined unit data in the built-in memory according to the write address for the built-in memory generated by the write address generation circuit when the write enable signal generation circuit generates the write enable signal. and

According to the present invention, when performing a sampling inspection of data for which time interleaving/deinterleaving processing is to be performed, the sampling position is devised. It becomes possible to implement even under such conditions.

1 is a block diagram showing an embodiment of a time interleave operation check circuit and a time interleave circuit (time deinterleave circuit) according to the present invention; FIG. FIG. 4 is a diagram showing an example of a timing chart in an embodiment of the time interleave operation check circuit according to the present invention; FIG. 4 is an example diagram showing the structure of main line data that is time-interleaved in the time-interleaving circuit including the embodiment of the time-interleaving operation check circuit according to the present invention; FIG. 4 is an example diagram showing the structure of main line data and the operation of the check circuit in the time interleave circuit including the embodiment of the time interleave operation check circuit according to the present invention; 1 is a detailed block diagram showing an embodiment of a time interleave operation check circuit and a time interleave circuit according to the present invention; FIG.

An embodiment of a time interleaved operation check circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a time interleave operation check circuit and a time interleave circuit (time deinterleave circuit) according to the present invention, and FIG. FIG. 3 is a detailed block diagram showing a time interleaving circuit;

As for symbols, 10 is a time interleave operation check circuit, 12 is an OFDM modulation/demodulation circuit, 14 is a time interleave circuit, 16 is a built-in memory, 18 is a write enable signal generation circuit, 20 is a write address generation circuit, and 22 is a data comparison circuit. Section 24 indicates an external memory.

First, as shown in FIG. 1, the time interleave operation check circuit 10 in this embodiment checks malfunction of the time interleave circuit 14 that performs time interleave processing on data to be processed in the OFDM modulation/demodulation circuit 12. A built-in memory 16 is provided, in which predetermined unit data extracted from data before being subjected to time interleaving processing by a time interleaving circuit 14 are stored, and the predetermined unit data stored in the built-in memory 16 are stored. , and predetermined processed data after the time interleave processing is performed by the data comparator 22, thereby checking malfunction of the time interleave circuit 14. FIG.

When the time interleaving circuit 14 is replaced with a time deinterleaving circuit, the time interleaving operation check circuit 10 is provided with a built-in memory 16, in which the time deinterleaving circuit performs time deinterleaving. Predetermined unit data extracted from the data before deinterleaving is stored, and the predetermined unit data stored in the built-in memory 16 is compared with the processed data after the time deinterleave processing by the data comparison unit 22. As a result, the time interleave operation check circuit 10 for checking malfunction of the time deinterleave circuit is obtained.

In this embodiment, an external memory 24 (a large-capacity memory such as a DRAM) mounted outside the FPGA is particularly used in the time interleave/deinterleave circuit part in the modulation/demodulation circuit of the OFDM-FPU (for example, ARIB-STD B33). It is used for detecting "data mismatch" that rarely occurs due to malfunction of the time interleaving circuit when time interleaving/deinterleaving processing is performed by using the logic/memory in the FPGA. Note that the present invention is also applicable to similar OFDM modulation/demodulation standards (eg, ARIB-STD B31, B43, B57, etc.).

"Data mismatch" due to malfunction of the time interleaving circuit or time deinterleaving circuit rarely occurs, but once it occurs, it occurs continuously. , it would be a very useful technique if it could be detected with very few resources. Therefore, in this embodiment, comparison with data before and after time interleaving/deinterleaving is performed by a method called "sampling inspection".

That is, only a predetermined unit (specifically, data for one OFDM symbol) that can be covered by the built-in memory 16 in the FPGA is extracted from the data before time interleaving/de-interleaving and stored in the built-in memory 16 in the FPGA. , and time-interleaved/de-interleaved data to detect data inconsistencies.

Here, in the present embodiment, when performing a sampling inspection, it is possible to devise a sampling position and compare data with a simple circuit structure and operation timing. Specifically, as shown in FIG. 2, the object of the sampling inspection is the head of the interleaved superframe output from the time interleaving circuit 14 after the time interleaving processing is completed by the time interleaving circuit 14 of the main line. This is assumed to be OFDM symbol data (data of one symbol number).

As a result, the main line time interleaving/deinterleaving processing is completed, and the data can be compared in synchronization with the timing (sync_out) at which the leading OFDM symbol data is output (see FIG. 2). When the time interleaving operation check circuit 10 checks for a malfunction of the time deinterleaving circuit, the target of the sampling inspection is then subjected to time deinterleaving processing by the time deinterleaving circuit 14 of the main line. This is assumed to be first OFDM symbol data (one symbol number data) of a superframe after deinterleave processing output from the circuit.

In addition, in this embodiment, the time interleave operation check circuit 10 includes a write enable signal generation circuit 18 and a write address generation circuit 20, as shown in FIG. When the write enable signal generating circuit 18 generates a write enable signal, the built-in memory 16 stores predetermined unit data of main line data before interleave processing (before deinterleaving processing). The storage in the built-in memory 16 is performed according to the write address of the built-in memory 16 generated by the write address generation circuit 20 .

The sampling inspection of data includes a time interleave operation check circuit 10, a write address generation circuit 20 that generates a write address (wr_addr) to the built-in memory 16, and a write address generation circuit 20 that generates a write enable signal (not shown in FIG. 1). It is realized by the enable signal generation circuit 18 . The output of a delay generation circuit (not shown) used in the time interleaving circuit 14 (time deinterleaving circuit) can be used to specify the data position for sampling inspection, thereby reducing the number of resources used. It is possible to suppress it.

Specifically, in the case of time interleave processing, as shown in FIG. 2, when the number of delay symbols due to interleaving of a certain data carrier is (maximum number of delay symbols)-(number of symbols after sync_in), wr_en is It becomes H (a write enable signal is generated to write), and predetermined unit data is stored in the built-in memory 16 according to the write address (wr_addr). After that, when all subcarriers have been stored in the built-in memory 16, the state (STATE) becomes write_finish and sync_out becomes H. The write address to the built-in memory 16 matches the carrier number of the data input to data_in in FIG.

Next, in this embodiment, the procedure of time interleave processing and sampling inspection according to the OFDM-FPU standard will be described with reference to FIGS. The time interleaving circuit 14 delays the contents of the data carrier in units of OFDM symbols. In the standard, the number of delay OFDM symbols of data carriers is represented by the following equation (Equation 2).

Here, D is the number of delay OFDM symbols, I is the cell length (parameter for determining the time interleaving depth), and i is the subcarrier number of the data carrier. Also, in the standard, the superframe position after time interleaving is the symbol containing the most delayed data.

When the time interleaving circuit 14 is operated according to this procedure, the input main line data (data_in), as an example in the case of I=1, is given by the following equation (Equation 3) without changing the carrier number and for each carrier number: Data delayed by the prescribed number of symbols (main line data after time interleave processing) is output (see FIGS. 3 and 4).

In the case of the time deinterleaving circuit, in order to equalize the total number of delay symbols in the time interleaving circuit and the deinterleaving circuit, the delay amount of the data carrier can be expressed by the following equation (equation 4). Here, Ddeint indicates the number of OFDM symbols delayed in the time deinterleaving circuit, and Dmax indicates the maximum number of OFDM symbols delayed in the time interleaving circuit 14 .

Next, the data sampling inspection position will be described. The data to be stored in the FPGA built-in memory 16 for sampling inspection in order to detect data discrepancies in the time interleaving circuit 14 or the time deinterleaving circuit is represented by the following equation (Equation 5) where the number of delay OFDM symbols is Data carrier. Here, N is the number of symbols from the beginning of the superframe.

When the data corresponding to the number of delay symbols is input to the time interleave operation check circuit 10, the write enable signal generation circuit 18 sets the write enable of the built-in memory 16 of the FPGA to "H" to transmit the data to the built-in memory 16. Store (see FIG. 5). In case of time interleave processing, #N symbol #403 data carrier, #N+1 symbol #134 data carrier, .

As shown in FIG. 4, for example, the number of delay symbols of the #N symbol #403 data carrier is 671, so that it is output from the time interleaving circuit 14 after 671 symbols from the top position of the superframe (see FIG. 4). middle, main line data after interleaving).

As a result, the data stored in the built-in memory 16 of the FPGA are all data output from the time interleaving circuit 12 "after the maximum number of delay symbols from the head position of the superframe". The data output from the interleave circuit 14 is equal to the data for one symbol following the superframe head position (the data match).

Simple timing of referring only to the sync_out signal by comparing the data for one symbol following the sync_out signal representing the superframe head position of the data output from the time interleave circuit 14 with the data stored in the built-in memory 16. It is possible to detect the data discrepancy of the time interleave circuit 14 by control (see FIGS. 2, 5, etc.).

Note that the capacity of the built-in memory 16 of the FPGA required for sampling inspection is (the number of information bits per data carrier)×(the maximum number of data carriers per symbol). The necessary memory capacity is estimated to be approximately 16 bits/carrier×1344 carriers<32 kbits, and can be realized with a capacity that can be sufficiently covered by the built-in memory 16 in the FPGA.

Also, the same circuit as that used in the time interleaving circuit 14 of the main line can be used as the circuit for obtaining the amount of delay of the data carrier (delayed OFDM symbol number D and Ddeint). Therefore, modularization of circuits and reduction in the amount of resources can be expected.

It should be noted that if the circuit is configured so as to have the delay amount specified in the standard, reading from the built-in memory 16 and comparison with the main line data must be performed before writing data for one symbol in the built-in memory 16 is completed. , When applied to the actual circuit, as shown in the figure, in the "reading" state (STATE), the main line data (data_out) and synchronization signal (sync_out) are implemented to be delayed by one symbol. However, since this delay can also be realized by adjusting the read address of the time interleave circuit 14, there is practically no increase in resources.

The time interleave operation check circuit according to the present invention devises the sampling position and timing when performing a sampling inspection on data for which time interleaving processing/time deinterleaving processing is to be performed. , this technique is useful for comparing data discrepancies before and after time interleaving/deinterleaving.

10 time interleave operation check circuit 12 OFDM modulation/demodulation circuit 14 time interleave circuit 16 built-in memory 18 write enable signal generation circuit 20 write address generation circuit 22 data comparator 24 external memory

Claims (7)

A time interleave operation check circuit for checking malfunction of a time interleave circuit that performs time interleave processing on data to be processed in an OFDM modulation/demodulation circuit,
The time interleaving operation check circuit has an internal memory, and stores only one OFDM symbol of data extracted from data before being subjected to time interleaving processing by the time interleaving circuit in the internal memory, and A time interleave operation check characterized by checking malfunction of the time interleave circuit by comparing data for one OFDM symbol stored in a memory and predetermined processed data after the time interleave processing. circuit. The comparison process is performed in synchronization with timing at which the time interleaving circuit completes the time interleaving process for the data to be processed and the data of the first OFDM symbol of the superframe is output. 2. The time interleave operation check circuit according to claim 1. The predetermined unit data is composed of data carriers whose number of delay symbols of the data carrier is a value calculated from the following equation (Equation 6) by time interleaving processing, and the predetermined processing data is: 3. The time interleave operation check circuit according to claim 1, wherein the data output from said time interleave circuit after time interleave processing is data for one symbol following a superframe head position.

A time interleave operation check circuit for checking malfunction of a time deinterleave circuit that performs time deinterleave processing on data to be processed in an OFDM modulation/demodulation circuit,
The time interleaving operation check circuit has a built-in memory, and stores only one OFDM symbol worth of data extracted from the data before time deinterleaving processing is performed by the time deinterleaving circuit in the built-in memory, and A malfunction of the time deinterleaving circuit is checked by comparing data for one OFDM symbol stored in the internal memory and predetermined processed data after the time deinterleaving. Time interleave operation check circuit. The comparison processing is performed synchronously with the timing at which the time deinterleaving circuit completes the time deinterleaving processing of the data to be processed and the data of the first OFDM symbol of the superframe is output. 5. The time interleave operation check circuit according to claim 4. The predetermined unit data is composed of data whose delay symbol number of the data carrier is the number of symbols from the beginning of the superframe by time deinterleaving processing, and the predetermined processing data is time deinterleaving processing. 6. The time interleave operation check circuit according to claim 4, wherein the data output from the time deinterleave circuit after performing the above is data for one symbol following a superframe head position. The time interleave operation check circuit includes a write enable signal generation circuit and a write address generation circuit. When the write enable signal generation circuit generates the write enable signal, the write address generation circuit generates the write address generation circuit. 7. The time interleave operation check circuit according to claim 1, wherein said predetermined unit data is stored in said built-in memory according to a write address to said built-in memory.

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