JP7130384B2 - Solid-state imaging device, imaging device, and imaging method - Google Patents

Description

The present invention relates to a solid-state imaging device, an imaging device, and an imaging method.

2. Description of the Related Art In recent years, imaging apparatuses have been proposed that perform focus detection and the like using signals obtained by an imaging device such as a CMOS sensor. Japanese Patent Application Laid-Open No. 2002-200001 proposes a technique of performing pupil-division focus detection using a signal obtained from an image pickup device. In Patent Document 1, one microlens and two photodiodes are provided for each pixel of the imaging device, and each photodiode receives light that has passed through different pupil regions of the imaging lens. In Document 1, focus detection is performed by comparing output signals from two photodiodes, and a captured image is generated by adding output signals from the two photodiodes.

Also, as a new type of image sensor, an image sensor as shown in Patent Document 2 has been proposed. In the image sensor disclosed in Patent Document 2, each pixel is provided with the following signal processing circuit. In Patent Document 2, a storage capacitor that stores charges generated by a photoelectric conversion element, a comparator that compares the voltage of the storage capacitor with a reference voltage, and outputs a pulse when the two match a reference voltage, and the output of the comparator Each pixel is provided with reset means for returning the voltage of the storage capacitor to the reset voltage.

JP 2001-124984 A JP 2015-173432 A

However, there is a concern that conventional techniques cannot necessarily perform good imaging.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a solid-state image pickup device, an image pickup apparatus, and an image pickup method capable of performing excellent photographing.

According to one aspect of the embodiment, a plurality of sensor units that emit pulses at a frequency corresponding to the frequency of photon reception, and a plurality of counters that count the number of pulses of signals emitted from the plurality of sensor units, When a count value of a first counter for counting the number of pulses of a signal emitted from the first sensor unit among the plurality of sensor units reaches a predetermined value, the signal emitted from the first sensor unit is reduced. The number of pulses is counted by a second counter that counts the number of pulses of a signal emitted from a second sensor unit different from the first sensor unit among the plurality of sensor units . A solid-state imaging device is provided.

According to the present invention, it is possible to provide a solid-state image pickup device, an image pickup apparatus, and an image pickup method capable of performing excellent image pickup.

It is a figure which shows the unit pixel with which the solid-state image sensor by 1st Embodiment was equipped. 4 is a timing chart showing the operation of the solid-state imaging device according to the first embodiment; 4 is a conceptual diagram showing the relationship between the exit pupil of the imaging lens and the unit pixel; FIG. FIG. 5 is a diagram showing an example of output characteristics of a unit pixel provided in the solid-state imaging device according to the first embodiment; It is a figure which shows the solid-state image sensor by 1st Embodiment. 1 is a block diagram showing an imaging device according to a first embodiment; FIG. It is a figure which shows the solid-state image sensor by 1st Embodiment. It is a figure which shows the unit pixel with which the solid-state image sensor by 2nd Embodiment was equipped. It is a figure which shows the layout of the sensor part of the unit pixel with which the solid-state image sensor by 2nd Embodiment was equipped. It is a figure which shows the relationship between a count upper limit reach|attainment signal and a control signal. It is a figure which shows the unit pixel with which the solid-state image sensor by 3rd Embodiment is equipped. It is a figure which shows the operation|movement of the solid-state image sensor by 3rd Embodiment. It is a figure which shows the solid-state image sensor by 4th Embodiment.

An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited to the following embodiments, and can be modified as appropriate. Also, the embodiments shown below may be combined as appropriate.

[First embodiment]
A solid-state imaging device, an imaging apparatus, and an imaging method according to the first embodiment will be described with reference to FIGS. 1 to 7. FIG.

First, the unit pixel 100 provided in the solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 1 is a diagram showing a unit pixel 100 provided in a solid-state imaging device according to this embodiment. The unit pixel 100 has avalanche photodiodes (hereinafter also referred to as "APD") 101A, 101B, quench resistors 102A, 102B, waveform shaping sections 103A, 103B, and AND gates 104A, 104B. The unit pixel 100 further has OR gates 105A, 105B and counters 106A, 106B.

The unit pixel 100 is provided with two APDs 101A and 101B, which are light receiving elements. The anode of APD 101A is connected to ground potential. The cathode of the APD 101A is connected to one end of the quench resistor 102A and the input terminal of the waveform shaping section 103A. The other end of the quench resistor 102A is connected to a predetermined potential _VAPD which is a reverse bias potential. Thus, APD 101A is connected to a predetermined potential V _APD through quench resistor 102A. The anode of APD 101B is connected to ground potential. A cathode of the APD 101B is connected to one end of the quench resistor 102B and an input terminal of the waveform shaping section 103B. The other end of the quench resistor 102B is connected to a predetermined potential _VAPD which is a reverse bias potential. Thus, _APD 101B is connected to a predetermined potential VAPD through quench resistor 102B.

A sensor section 107A, which emits pulses at a frequency corresponding to the photon reception frequency, is composed of an APD 101A, a quench resistor 102A, and a waveform shaping section 103A. Further, the sensor section 107B, which emits pulses at a frequency corresponding to the photon reception frequency, is composed of the APD 101B, the quench resistor 102B, and the waveform shaping section 103B. Reference numerals 107A and 107B are used when describing individual sensor units, and reference numeral 107 is used when describing the sensor units in general.

Light transmitted through the same microlens 301 (see FIG. 3) is received by APD 101A and APD 101B, respectively. Thus, the APD 101A and the APD 101B can acquire signals corresponding to light beams passing through different regions of the exit pupil. Signals obtained by the two APDs 101A and 101B are added by components provided after the APDs 101A and 101B. An image signal is generated from the signal acquired by the unit pixel 100 in this way.

When photons are incident on the APDs 101A and 101B, charges are generated by the avalanche multiplication phenomenon. The charge generated by the avalanche image multiplication phenomenon is discharged through quench resistors 102A and 102B.

The potentials of the signals APD_A and APD_B input to the waveform shaping units 103A and 103B change according to the generation and discharge of charges in response to the incidence of photons on the APDs 101A and 101B. The waveform shaping sections 103A and 103B generate pulse-shaped signals by performing edge detection and amplification on the input signals.

Reference numerals 101A and 101B are used when describing individual APDs, and reference numeral 101 is used when describing APDs in general. Reference numerals 102A and 102B are used when describing individual quench resistors, and reference numeral 102 is used when describing quench resistors in general. Reference numerals 103A and 103B are used when describing individual waveform shaping units, and reference numeral 103 is used when describing the waveform shaping units in general. Reference numerals 105A and 105B are used when describing individual counters, and reference numeral 105 is used when describing counters in general.

The APD 101, the quench resistor 102, and the waveform shaping section 103 function as a 1-bit AD conversion section (sensor section) that converts the presence or absence of incident photons to the APD 101 into a pulse signal.

A signal output from the waveform shaping section 103A is supplied to the AND gate 104A. The AND gate 104A is supplied with a count upper limit value arrival signal _LA from the counter 106A. The count upper limit value reaching signal _LA is a signal indicating that the count value of the counter 106A has reached the count upper limit value. Therefore, the pulse signal output from the waveform shaping section 103A is supplied to the OR gate 105B after the count value of the counter 106A reaches the count upper limit value. The count upper limit value is the upper limit value that can be counted by the counter.

A signal output from the waveform shaping section 103B is supplied to the AND gate 104B. The AND gate 104B is also supplied with a count upper limit reach signal LB from the counter _106B . The count upper limit value reaching signal LB is a signal indicating that the count value of the counter _106B has reached the count upper limit value. Therefore, the pulse signal output from the waveform shaping section 103B is supplied to the OR gate 105A after the count value of the counter 106B reaches the count upper limit value.

OR gate 105A supplies pulse signal PLS_A to the input terminal of counter 106A. The signal output from the waveform shaping section 103A and the signal output from the AND gate 104B are supplied to the OR gate 105A. OR gate 105B supplies pulse signal PLS_B to the input terminal of counter 106B. The signal output from the waveform shaping section 103B and the signal output from the AND gate 104A are supplied to the OR gate 105B.

The OR gate 105A supplies the pulse signal output from the waveform shaping section 103A to the counter 106A before the count value of the counter 106A reaches the count upper limit. The OR gate 105B supplies the pulse signal output from the waveform shaping section 103B to the counter 106B before the count value of the counter 106B reaches the count upper limit.

When the count value of the counter 106A reaches the count upper limit, the signal output from the waveform shaping section 103A is input to the OR gate 105B via the AND gate 104A. Therefore, after the count value of the counter 106A reaches the count upper limit, the signal obtained by synthesizing the pulse signal output from the waveform shaping section 103A and the pulse signal output from the waveform shaping section 103B is , are output from the OR gate 105B. More specifically, when a pulse signal is output from either waveform shaping section 103A or waveform shaping section 103B, a pulse signal is output from OR gate 105B.

When the count value of the counter 106B reaches the count upper limit, the signal output from the waveform shaping section 103B is input to the OR gate 105A via the AND gate 104B. Therefore, after the count value of the counter 106B reaches the count upper limit, the signal obtained by synthesizing the pulse signal output from the waveform shaping section 103A and the pulse signal output from the waveform shaping section 103B is , are output from the OR gate 105A. More specifically, when a pulse signal is output from either waveform shaping section 103A or waveform shaping section 103B, a pulse signal is output from OR gate 105A.

The counter 106A counts the number of pulse signals supplied from the OR gate 105A and outputs a signal A indicating the counting result to the outside of the unit pixel 100. FIG. The counter 106B counts the number of pulse signals supplied from the OR gate 105B and outputs a signal B indicating the count result to the outside of the unit pixel 100. FIG.

Various drive signals such as reset signals and enable signals are supplied to the counters 106A and 106B provided in each unit pixel 100 . After the count value of the counter 106 reaches the count upper limit value, even if a pulse signal is newly input to the counter 106, the count value of the counter 106 does not change.

Thus, in this embodiment, when the count value of the counter 106A reaches the count upper limit, the pulse signal that should have been counted by the counter 106A is counted by the counter 106B. On the other hand, when the count value of the counter 106B reaches the count upper limit, the pulse signal that should have been counted by the counter 106B is counted by the counter 106A. Therefore, according to the present embodiment, even if one of the counter 106A and the counter 106B reaches the count upper limit value, unless both the counter 106A and the counter 106B reach the count upper limit value, Pulse signals can be successfully counted.

Next, the operation of the unit pixel 100 provided in the solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing the operation of the unit pixel 100 provided in the solid-state imaging device according to this embodiment. FIG. 2 shows the operation of one unit pixel 100 among the plurality of unit pixels 100 provided in the pixel section (pixel array) 501 (see FIG. 5). A digital image signal corresponding to the optical image formed on the pixel portion 501 is acquired by performing the operation shown in FIG. 2 in parallel in the plurality of unit pixels 100 .

Driving signals such as a reset signal CNT_RST and an enable signal CNT_EN are appropriately supplied to the counters 106A and 106B. When the pulse-like reset signal CNT_RST is supplied, the count values of the counters 106A and 106B are reset to zero. Further, when the H level enable signal CNT_EN is supplied, the counters 106A and 106B count pulse signals. In FIG. 2, symbol CNT_A indicates the count value of counter 106A, and symbol CNT_B indicates the count value of counter 106B. In FIG. 2, for the sake of simplification of explanation, the counter 106 counts in eight steps from 0 to 7, and the case where the count upper limit value of the counter 106 is 7 will be explained as an example. The count upper limit value is actually set to be sufficiently large.

At timing t200, when the reset signal CNT_RST supplied to the counters 106A and 106B goes high, the count values of the counters 106A and 106B are reset to zero.

At timing t201, when the reset signal CNT_RST supplied to the counters 106A and 106B becomes L level, the resetting of the counters 106A and 106B ends. At timing t201, the enable signal CNT_EN becomes H level. This enables the counting of pulse signals by the counters 106A and 106B. Thus, an imaging period is started, which is a period for counting pulse signals corresponding to photons incident on the APDs 101A and 101B.

At timing t202, a photon enters the APD 101A. When a photon is incident on the APD 101A, charges are generated by the avalanche multiplication phenomenon, the charges are discharged through the quench resistor 102A, and the potential of the cathode of the APD 101A changes. Therefore, it takes a certain amount of time for the signal APD_A to return to a constant potential again. Waveform shaping section 103A detects a falling edge of signal APD_A and outputs a short-time pulse signal. The pulse signal output from the waveform shaping section 103A is input to the counter 106A via the OR gate 105A, and the count value of the counter 106A changes from 0 to 1.

Between timings t202 and t203, neither counter 106A nor counter 106B reaches the count upper limit value. Therefore, the pulse signal output from the waveform shaping section 103A is counted by the counter 106A, and the pulse signal output from the waveform shaping section 103B is counted by the counter 106B.

At the timing t203, the count value of the counter 106A becomes 7. That is, the count value of the counter 106A reaches the count upper limit. Therefore, the count upper limit value arrival signal _LA output from the counter 106A becomes H level.

During timings t203 to _t204 , the count upper limit value arrival signal LA is at H level, so the pulse signal output from the waveform shaping section 103A is supplied to the OR gate 105B via the AND gate 104A. Therefore, when a pulse signal is output from either waveform shaping section 103A or waveform shaping section 103B, pulse signal PLS_B is output from OR gate 105B. That is, the counter 106B can count pulse signals output from either the waveform shaping section 103A or the waveform shaping section 103B.

At timing t204, the enable signal CNT_EN becomes L level, and the imaging period ends. The count values of the counters 106A and 106B when the imaging period ends are output to the outside of the unit pixel 100 as signals A and B, respectively.

In the example shown in FIG. 2, the number of photons equal to or greater than the count upper limit of the APD 101A is incident on the APD 101A, so the count value of the counter 106A reaches the count upper limit. Therefore, in the example shown in FIG. 2, the number of photons incident on the APD 101A and the signal A do not match. After the count value of the counter 106A reaches the count upper limit, the number of photons incident on the APD 101A is counted by the counter 106B. However, the signal obtained by adding signal A and signal B matches the total number of photons incident on APD 101A and APD 101B.

Next, pupil division type focus detection performed by the imaging apparatus according to the present embodiment will be described with reference to FIG. FIG. 3 is a conceptual diagram showing the relationship between the exit pupil of the photographing lens and the unit pixel. FIG. 3A shows how a light beam is incident on a unit pixel 100 arranged near the optical axis OA. On the other hand, FIG. 3(b) shows how the luminous flux is incident on the unit pixel 100 arranged at a position away from the optical axis OA.

APD 101A and APD 101B are arranged in the unit pixel 100 .
As shown in FIG. 3A, the luminous flux that has passed through the exit pupil 300 is centered on the optical axis OA, passes through the microlens 301 and the color filter 302, and enters the unit pixel 100. As shown in FIG. The distance from the exit pupil 300 to the unit pixel 100 is called pupil distance.

A light flux passing through pupil region 303A, which is the first region of exit pupil 300, enters APD 101A. A light flux passing through a pupil region 303B, which is a second region different from the first region in exit pupil 300, enters APD 101B. Therefore, the APD 101A and the APD 101B receive light passing through different areas of the exit pupil of the imaging lens. Therefore, the phase difference can be detected by comparing the signal acquired by the APD 101A and the signal acquired by the APD 101B. If the count value of at least one of the counters 106A and 106B reaches the count upper limit, the signals obtained by these counters 106 cannot be used to correctly detect the phase difference. Therefore, when the count value of at least one of the counter 106A and the counter 106B reaches the count upper limit value, the signal A and the signal B acquired by the unit pixel 100 provided with the counter 106 are It is not used for phase difference detection.

As shown in FIG. 3B, in the unit pixel 100 arranged away from the optical axis OA, the microlens 301 is not arranged directly above the unit pixel 100, and the microlens 301 is shifted from directly above the unit pixel 100. It is preferable to dispose the microlens 301 at a position where At the reference pupil distance, the position of the microlens 301 is shifted so that the luminous flux that has passed through the pupil region 303A is incident on the APD 101A, and the luminous flux that has passed through the pupil region 303B is incident on the APD 101B. By setting the position of the microlens 301 in this way, imaging plane phase difference AF can be performed satisfactorily even when an object is imaged at a position away from the optical axis OA. However, the pupil distance differs depending on the type of lens and zoom magnification. When the pupil distance changes, in the unit pixel 100 located away from the optical axis OA, a light flux passing through a region shifted from the pupil region 303A is incident on the APD 101A, and the region shifted from the pupil region 303B. is incident on the APD 101B. Then, the amount of light incident on the APD 101A and the APD 101B is biased.

Next, the output characteristics of the solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 4 is a diagram showing an example of output characteristics of a unit pixel provided in the solid-state imaging device according to this embodiment. In FIG. 4, signals A and B are indicated using dashed lines. Further, in FIG. 4, the synthesized signal generated by synthesizing the signal A and the signal B is indicated using a solid line. In addition, FIG. 4 shows the signal B and the combined signal using the dashed-dotted line when the method of the present embodiment is not applied. The horizontal axis of FIG. 4 indicates the amount of incident light, and the vertical axis of FIG. 4 indicates the signal value. FIG. 4 shows an example in which the amount of light incident on the APD 101A is greater than the amount of light incident on the APD 101B. As described above, in the unit pixel 100 located away from the optical axis OA, such deviation of the amount of light is likely to occur.

The amount of light X1 in FIG. 4 is the amount of light at which the count value of the counter 106A reaches the count upper limit. The value of the synthesized signal when the light amount is X1 is Y1. The amount of light X2 in FIG. 4 is the amount of light at which the count value of the counter 106B reaches the count upper limit. The value of the synthesized signal when the amount of light is X2 is Y2. At this time, the value Y2 of the synthesized signal is a value obtained by adding the count upper limit value of the counter 106A and the count upper limit value of the counter 106B.

When the amount of light is less than X1, neither the count value of the counter 106A nor the count value of the counter 106B reaches the count upper limit value. At a light quantity less than X1, all of the signal A, the signal B, and the combined signal maintain their linearity.

Since the count value of the counter 106A reaches the count upper limit at the light intensities X1 to X2, the photons incident on the APDs 101A and 101B are counted by the counter 106B. The linearity of the combined signal is maintained even at the light intensities of X1 to X2.

At a light intensity of X2 or more, both the count value of the counter 106A and the count value of the counter 106B have reached the count upper limit value, so neither the signal A nor the signal B changes, and therefore the composite signal does not change either.

If the method according to this embodiment is not applied, the linearity of the composite signal is maintained only when the light amount is less than X1. In contrast, in this embodiment, the linearity of the combined signal is maintained up to X2, which is larger than X1. That is, in this embodiment, a good combined signal can be obtained as long as both the count value of the counter 106A and the count value of the counter 106B do not reach the count upper limit value. Therefore, according to this embodiment, it is possible to obtain a good image even for a brighter subject.

Next, the configuration of the solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 5 is a diagram showing a solid-state imaging device 500 according to this embodiment.

The solid-state imaging device 500 has a pixel section 501 in which a large number of unit pixels 100 are arranged in a matrix, an output control section 502 , a signal processing section 503 and a timing control section 504 . Signals A and B are input to the output control unit 502 from each of the plurality of unit pixels 100 arranged in the pixel unit 501 . The output control unit 502 appropriately selects the signal A and the signal B supplied from each of the plurality of unit pixels 100 and outputs them to the signal processing unit 503 .

The signal processing unit 503 performs addition processing on the signal A and the signal B acquired by the unit pixel 100 as necessary. When imaging plane phase difference AF is not performed, it is not necessary to output signal A and signal B separately. Output to the outside.

A timing control unit 504 supplies a drive signal to the pixel unit 501 . The timing control unit 504 also supplies a signal for driving the output control unit 502, a signal for driving the signal processing unit 503, and the like.

Next, an imaging device having the solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 6 is a block diagram showing the imaging device according to this embodiment. As shown in FIG. 6, an imaging device 610 according to this embodiment includes a solid-state imaging device 500, a lens control unit 601, a control unit (overall control calculation unit) 603, a memory unit 604, a display unit 605, an operation It has a unit 606 and a recording unit 607 . An imaging device 610 is provided with an imaging lens 600 . The imaging lens 600 may or may not be detachable from the body of the imaging device 610 . The control unit 603 , the memory unit 604 , the display unit 605 , the operation unit 606 , and the recording unit 607 can appropriately input and output signals and the like via the bus line 608 .

An optical image generated by the imaging lens 600 is formed on the imaging surface of the solid-state imaging device 500 . The solid-state imaging device 500 generates an image signal by photoelectrically converting the optical image formed on the imaging surface by the imaging lens 600 .

Based on instructions from the control unit 603, the lens control unit 601 drives a focus lens (not shown) provided in the photographing lens 600, drives an aperture stop (not shown) provided in the photographing lens 600, and the like.

A control unit 603 controls the entire imaging device 610 . A control unit 603 controls the solid-state imaging device 500 . The control unit 603 also performs correction processing, development processing, and the like on the image signal output from the solid-state imaging device 500 . In addition, the control unit 603 performs phase difference detection using signals output from the solid-state imaging device 500, specifically, the signals A and B as described above. The control unit 603 supplies information indicating a control amount for driving the focus lens to the lens control unit 601 according to the phase difference detection result.

The memory unit 604 temporarily holds image data. A display unit 605 displays various information and captured images. The operation unit 606 is various interfaces for the user to operate the imaging device 610 . The control unit 603 controls each functional block based on an operation instruction by the user through the operation unit 606 . The recording unit 607 includes a recording medium (not shown). The recording medium may or may not be detachable from the recording unit 607 . Image data and the like are recorded on the recording medium. For example, a semiconductor memory or the like can be used as the recording medium.

Next, the solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 7A is a perspective view showing the structure of the solid-state imaging device according to this embodiment. FIG. 7B is a diagram showing a unit pixel included in the solid-state imaging device according to this embodiment. FIG. 7C is a cross-sectional view showing the solid-state imaging device 500 according to this embodiment.

As shown in FIG. 7A, a solid-state imaging device 500 according to this embodiment has an upper substrate (first semiconductor chip) 700 and a lower substrate (second semiconductor chip) 701 . An optical image formed by the photographing lens 600 is imaged on the partial pixel portion 501A provided on the upper substrate 700 .

As shown in FIG. 7B, the unit pixel 100 has a sensor region 702 and a counting section 703. As shown in FIG. The sensor region 702 is formed in a partial pixel portion 501A provided on the upper substrate 700. As shown in FIG. The counting section 703 is formed on the lower substrate 701 .

As shown in FIG. 7A, a plurality of sensor regions 702 are arranged in a matrix in a partial pixel section 501A provided on the upper substrate 700. As shown in FIG. A plurality of counting units 703 are arranged in a matrix in the partial pixel unit 501B provided on the lower substrate 701 .

As shown in FIG. 7B, the sensor area 702 has a sensor section 107A and a sensor section 107B. On the other hand, counting section 703 includes AND gates 104A and 104B, OR gates 105A and 105B, and counters 106A and 106B. A counting unit 703 counts the number of pulses of signals emitted from the sensor units 107A and 107B.

As shown in FIG. 7A, the output control section 502, the signal processing section 503, and the timing control section 504 are arranged on the lower substrate 701. As shown in FIG.

As shown in FIG. 7C, a wiring layer 704 is formed on the upper substrate 700 . A microlens 301 and a color filter 302 are arranged on the side of the upper substrate 700 opposite to the side on which the wiring layer 704 is formed, that is, on the back side of the upper substrate 700 . Photons are incident from the back side of the upper substrate 700 and reach the PDs 101A and 101B.

A wiring layer 705 is formed on the lower substrate 701 . A connection electrode 706a provided on the wiring layer 704 of the upper substrate 700 and a connection electrode 706b provided on the wiring layer 705 of the lower substrate 701 are electrically connected. That is, the upper substrate 700 and the lower substrate 701 are electrically connected through the connection electrodes 706a and 706b.

Counters 106A and 106B are multi-bit counters. Therefore, the counting unit 703 has a large circuit scale. However, since the counting part 703 is arranged on the lower substrate 701 separate from the upper substrate 700 on which the sensor region 702 is arranged, the sensor region 702 can secure a sufficient opening area.

Note that the structure of the solid-state imaging device 500 is not limited to the above, and can be set as appropriate. For example, a solid-state imaging device may be configured by stacking three or more semiconductor chips. Also, a single semiconductor chip may constitute a solid-state imaging device. Further, in the above embodiment, the case where photons are incident from the back surface side of the upper substrate 700 is described as an example. can be Also, a plurality of semiconductor chips used in the solid-state imaging device 500 may be manufactured according to different process rules.

Further, in the present embodiment, the case where when the count value of the counter 106 reaches the count upper limit value, counting is performed using only the counter 106 whose count value has not reached the count upper limit value has been described as an example. is not limited to For example, when the count value of the counter 106 reaches a predetermined value, only the counters 106 whose count value has not reached the predetermined value may be used for counting. In this case, the counter 106 whose count value reaches the predetermined value does not count pulse signals after the count value reaches the predetermined value.

As described above, according to the present embodiment, imaging plane phase difference AF can be performed satisfactorily using the signal output from the sensor unit 107A and the signal output from the sensor unit 107B. Moreover, according to the present embodiment, when the count value of the first counter that counts the number of pulses of the signal emitted from the first sensor unit of the plurality of sensor units 107 reaches a predetermined value, the counting unit 703 may operate in the following modes of operation. That is, in the operation mode in which the number of pulses of the signal emitted from the first sensor section is counted by the second counter that counts the number of pulses of the signal emitted from the second sensor section different from the first sensor section. A counting unit 703 may operate. As described above, in this embodiment, the pulse signals output from the respective sensor units 107A and 107B can be counted satisfactorily as long as both the count value of the counter 106A and the count value of the counter 106B do not reach the count upper limit value. . Therefore, according to the present embodiment, it is possible to perform better imaging.

[Second embodiment]
A solid-state imaging device, an imaging apparatus, and an imaging method according to the second embodiment will be described with reference to FIGS. 8 to 10. FIG. The same components as those of the solid-state imaging device according to the first embodiment shown in FIGS. 1 to 7 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

In the solid-state imaging device according to this embodiment, a unit pixel 800 is divided vertically and horizontally.

Next, a unit pixel 800 provided in the solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 8 is a diagram showing a unit pixel 800 provided in the solid-state imaging device according to this embodiment.

A unit pixel 800 has four sensor portions 808A to 808D. Reference numerals 808A to 808D are used when describing individual sensor units, and reference numeral 808 is used when describing the sensor units in general. The sensor section 808A has an APD 801A, a quench resistor 802A, and a waveform shaping section 803A. The sensor section 808B has an APD 801B, a quench resistor 802B, and a waveform shaping section 803B. The sensor section 808C has an APD 801C, a quench resistor 802C, and a waveform shaping section 803C. The sensor section 808D has an APD 801D, a quench resistor 802D, and a waveform shaping section 803D. Reference numerals 801A to 801D are used when describing individual APDs, and reference numeral 801 is used when describing APDs in general. Reference numerals 802A-802D are used when describing individual quench resistors, and reference numeral 802 is used when describing quench resistors in general. Reference numerals 803A to 803D are used when describing individual waveform shaping units, and reference numeral 803 is used when describing the waveform shaping units in general.

The unit pixel 800 further has OR gates 805A-805D and counters 806A-806D. Reference numerals 805A to 805D are used when describing individual OR gates, and reference numeral 805 is used when describing OR gates in general. Reference numerals 806A to 806D are used when describing individual counters, and reference numeral 806 is used when describing counters in general.

The unit pixel 800 includes AND gates 804A-B, 804A-C, 804A-D, 804B-A, 804B-C, 804B-D, 804C-A, 804C-B, 804C-D, 804D-A, 804D-B. , 804D-C. When discussing individual AND gates, these symbols 804A-B, 804A-C, 804A-D, 804B-A, 804B-C, 804B-D, 804C-A, 804C-B, 804C-D, 804D-A, 804D-B, 804D-C are used. Reference numeral 804 is used when describing AND gates in general.

AND gates 804A-B are used to supply pulse signals output from sensor section 808A to OR gate 805B. AND gates 804A-C are used to supply the pulse signal output from sensor section 808A to OR gate 805C. AND gates 804A-D are used to supply the pulse signal output from sensor section 808A to OR gate 805D.

AND gate 804B-A is used to supply the pulse signal output from sensor section 808B to OR gate 805A. AND gates 804B-C are used to supply pulse signals output from sensor section 808B to OR gate 805C. AND gates 804B-D are used to supply pulse signals output from sensor section 808B to OR gate 805D.

AND gate 804C-A is used to supply the pulse signal output from sensor section 808C to OR gate 805A. AND gate 804C-B is used to supply the pulse signal output from sensor section 808C to OR gate 805B. AND gates 804C-D are used to supply pulse signals output from sensor section 808C to OR gate 805D.

AND gate 804D-A is used to supply the pulse signal output from sensor section 808D to OR gate 805A. AND gate 804D-B is used to supply the pulse signal output from sensor section 808D to OR gate 805B. AND gate 804D-C is used to supply the pulse signal output from sensor section 808D to OR gate 805C.

Counters 806A to 806D output count upper limit value reaching signals L _A to L _D , respectively, when the count value reaches the count upper limit value. The symbols L _A to L _D are used when describing individual count upper limit reaching signals, and the symbol L is used when describing the count upper limit reaching signals in general.

Control unit 807 controls control signals S AB , S AC , S _AD , S _{B -A ,} and S _B according to count upper limit reach signals L _A to L _D supplied from counters 806A to 806D. - outputs _C , S _BD , S _C-A , S _CB , S _C-D , S _D-A , S _D-B and S _D-C . When discussing the individual control signals, the symbols S AB , S _AC , S AD , S _BA , S _BC , S _BD , S _{C - A} , S _{C- B} 1 , S _CD , S _D-A , S _D-B , and S _D-C are used, and symbol S is used when general control signals are described.

The AND gate 804 becomes effective when the control signal S supplied to the AND gate 804 becomes H level, and supplies the pulse signal supplied from the sensor section 808 to the OR gate 805 corresponding to the AND gate 804 . The OR gates 805A-805D supply the counter 806 with pulse signals corresponding to the input pulse signals. The counters 806A to 806D count the number of pulse signals supplied from the OR gates 805A to 805D, respectively, and output signals A to D indicating the counting results to the outside of the unit pixel 800, respectively.

When the count values of the counters 806A to 806D reach the count upper limit, the control unit 807 enables the AND gate 804 according to the priority according to the operation mode signal supplied from the outside of the solid-state imaging device 500. FIG. The operation mode signal indicates whether the solid-state imaging device is to be controlled in the first operation mode or the second operation mode. The control performed by the control unit 807 will be described later using FIG.

Next, a unit pixel 800 provided in the solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 9 is a diagram showing the layout of the sensor section 808 of the unit pixel 800 provided in the solid-state imaging device according to this embodiment.

As shown in FIG. 9, a sensor section 808A is arranged in the upper left region of the unit pixel 800. As shown in FIG. A sensor section 808B is arranged in the upper right region of the unit pixel 800 . A sensor section 808C is arranged in the lower left region of the unit pixel 800 . A sensor section 808D is arranged in the lower right region of the unit pixel 800 . One microlens 900 is provided for one unit pixel 800 . Light passing through microlens 900 is received by these sensor portions 808A-808D.

In this embodiment, since the sensor units 808 are arranged vertically and horizontally, signals corresponding to light fluxes passing through each of a plurality of pupil regions divided in the vertical direction and a plurality of pupil regions divided in the horizontal direction It is possible to obtain a signal corresponding to the luminous flux passing through each of the . Therefore, according to this embodiment, it is possible to detect the phase difference in the vertical direction and the phase difference in the horizontal direction. For example, when a signal corresponding to a light flux passing through each of a plurality of pupil regions divided only in the horizontal direction is used, an object such as a vertical line that varies greatly in the horizontal direction can be imaged satisfactorily. Surface phase difference AF can be performed. However, in such a case, it is difficult to satisfactorily perform imaging plane phase difference AF for an object such as a horizontal line that changes little in the horizontal direction.

On the other hand, in the present embodiment, a signal corresponding to a light flux passing through each of a plurality of pupil regions divided in the vertical direction and the horizontal direction can be obtained. It can be selected depending on the direction of magnitude. Therefore, according to the present embodiment, imaging plane phase difference AF can be performed satisfactorily for various subjects. For example, the first signal is acquired by adding the pulse signal output from the sensor section 808A and the pulse signal output from the sensor section 808B. A second signal is obtained by adding the pulse signal output from the sensor unit 808C and the pulse signal output from the sensor unit 808D. By comparing the first signal and the second signal, imaging plane phase difference AF can be favorably performed on a subject such as a horizontal line. A third signal is obtained by adding the pulse signal output from the sensor section 808A and the pulse signal output from the sensor section 808C. A fourth signal is obtained by adding the signal output from the sensor unit 808B and the signal output from the sensor unit 808D. Then, by comparing the third signal and the fourth signal, imaging plane phase difference AF can be favorably performed on a subject such as a vertical line.

Next, the operation of the control unit 807 provided in the solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 10 is a diagram showing the relationship between the count upper limit reaching signal and the control signal. FIG. 10 shows the case where the first operation mode is set and the case where the second operation mode is set. FIG. 10 shows which control signal S is output when which count upper limit value reaching signal L is at the H level. _LA indicates the case where count upper limit value reaching signal _LA is at H level. _LA ·LB indicates the case where the count upper limit value reaching signal _LA and the count upper limit value reaching signal _LB are at the _H level. L _A , L _B , and L _C indicate the case where count upper limit reach signal _{LA, count upper limit reach signal L B ,} and count upper limit reach signal L _C are at H level. LB indicates that the count upper limit value reaching signal _LB is at _H level. _LA , _LB , and LD indicate the case where the count upper limit reach signal _LA , the count upper limit reach signal _LB , and the count upper limit reach signal _LD are at the _H level. LC· _LD indicates the case where the count upper limit value reaching signal _LC and the count upper limit value reaching signal _LD are at the _H level. L _A , L _C , and L _D indicate the case where count upper limit reach signal _{LA, count upper limit reach signal L C ,} and count upper limit reach signal L _D are at H level. LC indicates the case where count upper limit value reaching signal _LC is at _H level. _LB , _LC , and LD indicate the case where count upper limit value reaching signal _LB , count upper limit value reaching signal _LC , and count upper limit value reaching signal _LD are at _H level. LD indicates that count upper limit value reaching signal _LD is at _H level. L _A ·L _C indicates the case where count upper limit value reaching signal L _A and count upper limit value reaching signal L _C are at H level. LB and _LD indicate the case where the count upper limit value reaching signal _LB and the count upper limit value reaching signal _LD are at the _H level.

The first operation mode is a mode in which horizontal lines are preferentially detected, and the second operation mode is a mode in which vertical lines are preferentially detected. Switching between the first operating mode and the second operating mode can be set by the user via the operation unit 606 . Further, the first operation mode and the second operation mode may be switched by providing a tilt sensor in the imaging device and detecting the vertical position and the horizontal position of the imaging device. Further, based on an image taken in advance, a direction in which the brightness of the subject changes significantly is detected, and based on the result of the detection, the first operation mode and the second operation mode are switched. good too.

In the first operation mode, when the count upper limit value arrival signal LA becomes H level, the control section 807 supplies the H level control signal S _AB to the AND gates 804A- _B . As a result, the pulse signal output from the sensor section 808A is supplied to the OR gate 805B via the AND gates 804A-B, and the pulse signal output from the sensor section 808A is counted by the counter 806B.

In the first operation mode, when not only the count upper limit reach signal _LA but also the count upper limit reach signal LB become _H level, the control section 807 supplies the following signals. That is, the control section 807 supplies the H-level control signal S AC to the AND gates 804A- _C and the H-level control signal SBD to the AND gates 804B- _D . As a result, the pulse signal output from the sensor section 808A is supplied to the OR gate 805C via the AND gates 804A-C, and the pulse signal output from the sensor section 808A is counted by the counter 806C. Also, the pulse signal output from the sensor section 808B is supplied to the OR gate 805D via the AND gates 804B-D, and the pulse signal output from the sensor section 808B is counted by the counter 806D.

In the first operation mode, when not only count upper limit reach signal _LA and count upper limit reach signal LB but also count upper limit reach signal _LC become _H level, control section 807 outputs the following signals. supply. That is, the control section 807 supplies the H-level control signals S _AD to the AND gates 804A-D. Since the count upper limit value reaching signal LA and the count upper limit value reaching signal LB are at H level, the AND gate _{804B -D is} supplied with the H level control signal SBD. Further, since the count upper limit value arrival signal L _C is at H level, the control signal S CD of H level is supplied to the AND gates 804C- _D . As a result, the pulse signal output from the sensor section 808A is supplied to the OR gate 805D via the AND gates 804A-D, and the pulse signal output from the sensor section 808A is counted by the counter 806D. Also, the pulse signal output from the sensor section 808B is supplied to the OR gate 805D via the AND gates 804B-D, and the pulse signal output from the sensor section 808B is counted by the counter 806D. Also, the pulse signal output from the sensor section 808C is supplied to the OR gate 805D via the AND gates 804C-D, and the pulse signal output from the sensor section 808C is counted by the counter 806D.

In the first operation mode, when the count upper limit value arrival signal LB becomes H level, the control section 807 supplies the H level control signal S BA to the AND gate _804B - _A . As a result, the pulse signal output from the sensor section 808B is supplied to the OR gate 805A via the AND gate 804B-A, and the pulse signal output from the sensor section 808B is counted by the counter 806A.

In the first operation mode, when not only the count upper limit reach signal _LB but also the count upper limit reach signal _LA go high, the controller 807 supplies the following signals. That is, the control section 807 supplies the H-level control signal SBD to the AND gates 804B _- D and supplies the H-level control signal SAC to the AND gates 804A _- C. As a result, the pulse signal output from the sensor section 808B is supplied to the OR gate 805D via the AND gates 804B-D, and the pulse signal output from the sensor section 808B is counted by the counter 806D. Also, the pulse signal output from the sensor section 808A is supplied to the OR gate 805C via the AND gates 804A-C, and the pulse signal output from the sensor section 808A is counted by the counter 806C.

In the first operation mode, when not only count upper limit reach signal LB and count upper limit reach signal _LA but also count upper limit reach signal _LD become _H level, control section 807 outputs the following signals. supply. That is, the control section 807 supplies the H-level control signal SBC to the AND gates 804B- _C . Since the count upper limit value reaching signal LA and the count upper limit value reaching signal LB are at H level, the control signals S _AC of H level are supplied to the AND gates _804A to _804A to 804C. Since the count upper limit value arrival signal LD is at H level, the AND gate 804D- _C is supplied with the H level control signal _SD-C . As a result, the pulse signal output from the sensor section 808B is supplied to the OR gate 805C via the AND gates 804B-C, and the pulse signal output from the sensor section 808B is counted by the counter 806C. Also, the pulse signal output from the sensor section 808A is supplied to the OR gate 805C via the AND gates 804A-C, and the pulse signal output from the sensor section 808A is counted by the counter 806C. Also, the pulse signal output from the sensor section 808D is supplied to the OR gate 805C via the AND gate 804D-C, and the pulse signal output from the sensor section 808D is counted by the counter 806C.

In the first operation mode, when the count upper limit value arrival signal LC becomes H level, the control section 807 supplies the H level control signal S CD to the AND gates 804C _{- D} . As a result, the pulse signal output from the sensor section 808C is supplied to the OR gate 805D via the AND gates 804C-D, and the pulse signal output from the sensor section 808C is counted by the counter 806D.

In the first operation mode, when not only the count upper limit reach signal LC but also the count upper limit reach signal _LD become _H level, the control section 807 supplies the following signals. That is, the control section 807 supplies an H level control signal SCA to the AND gate 804C _- A and an H level control signal _SD-B to the AND gate 804D-B. As a result, the pulse signal output from the sensor section 808C is supplied to the OR gate 805A via the AND gate 804C-A, and the pulse signal output from the sensor section 808C is counted by the counter 806A. Also, the pulse signal output from the sensor section 808D is supplied to the OR gate 805B via the AND gate 804D-B, and the pulse signal output from the sensor section 808D is counted by the counter 806B.

In the first operation mode, when not only the count upper limit reach signal _LC and the count upper limit reach signal _LD but also the count upper limit reach signal _LA go high, the controller 807 outputs the following signals. supply. That is, the control section 807 supplies the H level control signal SCB to the AND gate 804C _- B. Since the count upper limit value reaching signal LC and the count upper limit value reaching signal LD are at the H level, the AND gate _804D - _B is supplied with the H level control signal _SD-B . Also, since the count upper limit value arrival signal LA is at H level, the control signal S _AB at H level is supplied to the AND gates 804A- _B . As a result, the pulse signal output from the sensor section 808C is supplied to the OR gate 805B via the AND gate 804C-B, and the pulse signal output from the sensor section 808C is counted by the counter 806B. Also, the pulse signal output from the sensor section 808D is supplied to the OR gate 805B via the AND gate 804D-B, and the pulse signal output from the sensor section 808D is counted by the counter 806B. Also, the pulse signal output from the sensor section 808A is supplied to the OR gate 805B via the AND gates 804A-B, and the pulse signal output from the sensor section 808A is counted by the counter 806B.

In the first operation mode, when the count upper limit reaching signal LD becomes H level, the control section 807 supplies the H level control signal S DC to the AND gate _804D - _C . As a result, the pulse signal output from the sensor section 808D is supplied to the OR gate 805C via the AND gate 804D-C, and the pulse signal output from the sensor section 808D is counted by the counter 806C.
In the first operation mode, when not only the count upper limit reach signal LD but also the count upper limit reach signal _LC become _H level, the control section 807 supplies the following signals. That is, the control section 807 supplies the H-level control signal _SD-B to the AND gate 804D-B, and supplies the H-level control signal SCA to the AND gate 804C _- A. As a result, the pulse signal output from the sensor section 808D is supplied to the OR gate 805B via the AND gate 804D-B, and the pulse signal output from the sensor section 808D is counted by the counter 806B. Also, the pulse signal output from the sensor section 808C is supplied to the OR gate 805A via the AND gate 804C-A, and the pulse signal output from the sensor section 808C is counted by the counter 806A.
In the first operation mode, when not only count upper limit reach signal LD and count upper limit reach signal _LC but also count upper limit reach signal _LB become _H level, control section 807 outputs the following signals. supply. That is, the control section 807 supplies the H level control signal _SD-A to the AND gate 804D-A. Since the count upper limit value reaching signal LD and the count upper limit value reaching signal LC are at the H level, the AND gate _{804C - A} is supplied with the H level control signal SC-A. Also, since the count upper limit value arrival signal L _B is at H level, the control signal S _B-A at H level is supplied to the AND gate 804B-A. As a result, the pulse signal output from the sensor section 808D is supplied to the OR gate 805A via the AND gate 804D-A, and the pulse signal output from the sensor section 808D is counted by the counter 806A. Also, the pulse signal output from the sensor section 808B is supplied to the OR gate 805A via the AND gate 804B-A, and the pulse signal output from the sensor section 808B is counted by the counter 806A. Also, the pulse signal output from the sensor section 808C is supplied to the OR gate 805A via the AND gate 804C-A, and the pulse signal output from the sensor section 808C is counted by the counter 806A.

In the second operation mode, when the count upper limit value arrival signal LA becomes H level, the control section 807 supplies the H level control signals S AC to the AND gates _804A - _C . As a result, the pulse signal output from the sensor section 808A is supplied to the OR gate 805C via the AND gates 804A-C, and the pulse signal output from the sensor section 808A is counted by the counter 806C.

In the second operation mode, when not only the count upper limit reach signal _LA but also the count upper limit reach signal LC become _H level, the control section 807 supplies the following signals. That is, the control section 807 supplies an H level control signal S AB to the AND gates 804A- _B and an H level control signal S CD to the AND gates 804C- _D . As a result, the pulse signal output from the sensor section 808A is supplied to the OR gate 805B via the AND gates 804A-B, and the pulse signal output from the sensor section 808A is counted by the counter 806B. Also, the pulse signal output from the sensor section 808C is supplied to the OR gate 805D via the AND gates 804C-D, and the pulse signal output from the sensor section 808C is counted by the counter 806D.

In the second operation mode, when not only count upper limit reach signal _LA and count upper limit reach signal LB but also count upper limit reach signal _LC become _H level, control section 807 outputs the following signals. supply. That is, the control section 807 supplies the H-level control signals S _AD to the AND gates 804A-D. Since the count upper limit reach signal LA and the count upper limit reach signal _{L C are} at H level, the AND gates 804C- _D are supplied with the control signal SC-D at H level. Also, since the count upper limit value arrival signal L _B is at H level, the AND gates 804B- _{D are supplied with the control signal S B-D} at H level. As a result, the pulse signal output from the sensor section 808A is supplied to the OR gate 805D via the AND gates 804A-D, and the pulse signal output from the sensor section 808A is counted by the counter 806D. Also, the pulse signal output from the sensor section 808B is supplied to the OR gate 805D via the AND gates 804B-D, and the pulse signal output from the sensor section 808B is counted by the counter 806D. Also, the pulse signal output from the sensor section 808C is supplied to the OR gate 805D via the AND gates 804C-D, and the pulse signal output from the sensor section 808C is counted by the counter 806D.

In the second operation mode, when count upper limit value reaching signal LB is at H level, control signal S _BD at H level is supplied to AND gates 804B- _D . As a result, the pulse signal output from the sensor section 808B is supplied to the OR gate 805D via the AND gates 804B-D, and the pulse signal output from the sensor section 808B is counted by the counter 806D.

In the second operation mode, when not only the count upper limit reach signal LB but also the count upper limit reach signal _LD become _H level, the control section 807 supplies the following signals. That is, the control section 807 supplies an H level control signal SBA to the AND gates 804B- _A and an H level control signal SDC to the AND gates 804D- _C . As a result, the pulse signal output from the sensor section 808B is supplied to the OR gate 805A via the AND gate 804B-A, and the pulse signal output from the sensor section 808B is counted by the counter 806A. Also, the pulse signal output from the sensor section 808D is supplied to the OR gate 805C via the AND gate 804D-C, and the pulse signal output from the sensor section 808D is counted by the counter 806C.

In the second operation mode, when not only count upper limit reach signal _LB and count upper limit reach signal _LD but also count upper limit reach signal _LA go high, control section 807 outputs the following signals: supply. That is, the control section 807 supplies the H-level control signal SBC to the AND gates 804B- _C . Since the count upper limit value reaching signal LB and the count upper limit value reaching signal LD are at the H level, the AND gate _804D - _C is supplied with the H level control signal _SD-C . Since even the count upper limit value arrival signal LA is at H level, AND gates 804A _{-C are} supplied with H level control signals S AC. As a result, the pulse signal output from the sensor section 808A is supplied to the OR gate 805C via the AND gates 804A-C, and the pulse signal output from the sensor section 808A is counted by the counter 806C. Also, the pulse signal output from the sensor section 808B is supplied to the OR gate 805C via the AND gates 804B-C, and the pulse signal output from the sensor section 808B is counted by the counter 806C. Also, the pulse signal output from the sensor section 808D is supplied to the OR gate 805C via the AND gate 804D-C, and the pulse signal output from the sensor section 808D is counted by the counter 806C.

In the second operation mode, when the count upper limit value arrival signal LC becomes H level, the control section 807 supplies the H level control signal S _{C -A} to the AND gate 804C-A. As a result, the pulse signal output from the sensor section 808C is supplied to the OR gate 805A via the AND gate 804C-A, and the pulse signal output from the sensor section 808C is counted by the counter 806A.

In the second operation mode, when not only the count upper limit reach signal _LC but also the count upper limit reach signal _LA go high, the control section 807 supplies the following signals. That is, the control section 807 supplies an H level control signal S AB to the AND gates 804A- _B and an H level control signal S CD to the AND gates 804C- _D . As a result, the pulse signal output from the sensor section 808A is supplied to the OR gate 805B via the AND gates 804A-B, and the pulse signal output from the sensor section 808A is counted by the counter 806B. Also, the pulse signal output from the sensor section 808C is supplied to the OR gate 805D via the AND gates 804C-D, and the pulse signal output from the sensor section 808C is counted by the counter 806D.

In the second operation mode, when not only count upper limit reach signal LC and count upper limit reach signal _LA but also count upper limit reach signal _LD become _H level, control section 807 outputs the following signals. supply. That is, the control section 807 supplies the H level control signal SCB to the AND gate 804C _- B. Since the count upper limit value reaching signal L _C and the count upper limit value reaching signal LA are at the H level, the control signals S _AB at the H level are supplied to the AND gates 804A- _B . Further, since the count upper limit value arrival signal LD is at H level, the control signal _SD -B at H level is supplied to the AND gate _804D -B. As a result, the pulse signal output from the sensor section 808A is supplied to the OR gate 805B via the AND gates 804A-B, and the pulse signal output from the sensor section 808A is counted by the counter 806B. Also, the pulse signal output from the sensor section 808C is supplied to the OR gate 805B via the AND gate 804C-B, and the pulse signal output from the sensor section 808C is counted by the counter 806B. Also, the pulse signal output from the sensor section 808D is supplied to the OR gate 805B via the AND gate 804D-B, and the pulse signal output from the sensor section 808D is counted by the counter 806B.

In the second operation mode, when the count upper limit reaching signal LD becomes H level, the control section 807 supplies the H level control signal _SD-B to the AND gate _804D -B. As a result, the pulse signal output from the sensor section 808D is supplied to the OR gate 805B via the AND gate 804D-B, and the pulse signal output from the sensor section 808D is counted by the counter 806B.
In the second operation mode, when not only the count upper limit reach signal LD but also the count upper limit reach signal _LB become _H level, the control section 807 supplies the following signals. That is, the control section 807 supplies an H level control signal SBA to the AND gates 804B- _A and an H level control signal SDC to the AND gates 804D- _C . As a result, the pulse signal output from the sensor section 808B is supplied to the OR gate 805A via the AND gate 804B-A, and the pulse signal output from the sensor section 808B is counted by the counter 806A. Also, the pulse signal output from the sensor section 808D is supplied to the OR gate 805C via the AND gate 804D-C, and the pulse signal output from the sensor section 808D is counted by the counter 806C.
In the second operation mode, when not only count upper limit reach signal LB and count upper limit reach signal _LD but also count upper limit reach signal _LC become _H level, control section 807 outputs the following signals. supply. That is, the control section 807 supplies the H level control signal _SD-A to the AND gate 804D-A. Since the count upper limit value reaching signal LB and the count upper limit value reaching signal LD are at the H level, the AND gate _{804B -A is} supplied with the H level control signal SBA. Since the count upper limit value arrival signal L _C is at H level, the control signal S _C-A at H level is supplied to the AND gate 804C-A. As a result, the pulse signal output from the sensor section 808B is supplied to the OR gate 805A via the AND gate 804B-A, and the pulse signal output from the sensor section 808B is counted by the counter 806A. Also, the pulse signal output from the sensor section 808C is supplied to the OR gate 805A via the AND gate 804C-A, and the pulse signal output from the sensor section 808C is counted by the counter 806A. Also, the pulse signal output from the sensor section 808D is supplied to the OR gate 805A via the AND gate 804D-A, and the pulse signal output from the sensor section 808D is counted by the counter 806A.

Which counter 806 counts the pulse signal output from the sensor unit 808A when the count value of the counter 806A reaches the count upper limit value will be described. In the first operation mode, when the count value of only counter 806A out of the plurality of counters 806 reaches the count upper limit value, control signal SAB attains _H level. As a result, the pulse signal output from the sensor section 808A is counted by the counter 806B. Thereafter, when the count value of not only the counter _806A but also the counter _806B reaches the count upper limit value, not only the control signal SAB but also the control signal SAC become H level. As a result, the pulse signal output from the sensor section 808A is counted by the counter 806C. Note that the pulse signal output from the sensor section 808A is counted by a counter 806B. Thereafter, when the count value reaches the count upper limit value not only in the counters 806A and 806B but also in the counter 806C, not only the control signals _{S AB} and S AC but also the control signals S _AD becomes H level. As a result, the pulse signals output from the sensor units 808A to 808D are counted by the counter 806D. Thus, in the first operation mode, when the counter 806A reaches the count upper limit value, the priority of the counter 806 that counts the pulse signals from the sensor section 808A is the order of the counter 806B, the counter 806C, and the counter 806D. It has become.

Similarly, the priority of the counter 806 that counts the pulse signal output from the sensor section 808B when the counter 806B reaches the count upper limit value is the counter 806A, the counter 806D, and the counter 806C in the first operation mode. are in order.
Similarly, the priority of the counter 806 that counts the pulse signal output from the sensor unit 808C when the counter 806C reaches the count upper limit value is the counter 806D, the counter 806A, and the counter 806B in the first operation mode. are in order.
Similarly, the priority of the counter 806 that counts the pulse signal output from the sensor unit 808D when the counter 806D reaches the count upper limit value is the counter 806C, the counter 806B, and the counter 806A in the first operation mode. are in order.

As described above, in the first operation mode, when the counter 806 reaches the count upper limit value, the following control is performed. That is, control is performed so that the counter 806 preferentially counts the count value output from the sensor unit 808 laterally adjacent to the sensor unit 808 corresponding to the counter 806 that has reached the count upper limit value. will be

The operation of the solid-state imaging device according to this embodiment will be described more specifically. Immediately after the imaging period starts, the count value of each counter 806 has not reached the count upper limit. Therefore, the pulse signals output from the sensor units 808A-808D are counted by the counters 806A-806D, respectively.

When the amount of light incident on the sensor section 808A is large and the count value of the counter 806A first reaches the count upper limit, the control signal S _AB becomes H level. As a result, the counter 806B counts not only the pulse signal output from the sensor section 808B but also the pulse signal output from the sensor section 808A.

When not only the count value of the counter 806A but also the count value of the counter _806B reach the count upper limit value, the control signals SAC and SBD become _H level. The control signal S _AB is maintained at H level. The counter 806C counts not only pulse signals output from the sensor section 808C but also pulse signals output from the sensor section 808A. Further, the counter 806D counts not only the pulse signal output from the sensor section 808D but also the pulse signal output from the sensor section 808B.

When not only the count values of the counters 806A and 806B but also the count value of the counter _806C reach the count upper limit value, the control signal SAD and the control signal SCD become _H level. Control signal SBD is maintained at _H level. The counter 806D counts the pulse signals output from all the sensor units 808A-808D.

In the first operation mode, for example, even if the count value of the counter 806A reaches the count upper limit value, unless both the count value of the counter 806A and the count value of the counter 806B reach the count upper limit value, the following operations are performed. Become. That is, the value obtained by adding the count value of the counter 806A and the count value of the counter 806B is obtained by adding the number of pulse signals output from the sensor section 808A and the number of pulse signals output from the sensor section 808B. is the same as the value obtained by Therefore, in the first operation mode, even if either one of the count value of the counter 806A and the count value of the counter 806B reaches the count upper limit value, the horizontal line can be detected satisfactorily. . Similarly, in the first operation mode, even if either one of the count value of the counter 806C and the count value of the counter 806D reaches the count upper limit value, the horizontal line can be detected satisfactorily. .

In the second operation mode, for example, even if the count value of the counter 806A reaches the count upper limit value, unless both the count value of the counter 806A and the count value of the counter 806C reach the count upper limit value, the following operations are performed. Become. That is, the value obtained by adding the count value of the counter 806A and the count value of the counter 806C is obtained by adding the number of pulse signals output from the sensor section 808A and the number of pulse signals output from the sensor section 808C. is the same as the value obtained by Therefore, in the second operation mode, even when either one of the count value of the counter 806A and the count value of the counter 806C reaches the count upper limit value, the vertical line can be detected satisfactorily. obtain. Similarly, in the second operation mode, even if either one of the count value of the counter 806B and the count value of the counter 806D reaches the count upper limit value, the vertical line can be detected satisfactorily. obtain.

As described above, in this embodiment, the pulse signals output from the sensor units 808A to 808D can be counted well as long as the count values of the counters 806A to 806D do not all reach the count upper limit. Therefore, according to the present embodiment, it is possible to perform better imaging.

Further, according to the present embodiment, in the first operation mode, even if one of the count value of the counter 806A and the count value of the counter 806B reaches the count upper limit value, the horizontal line Detection can be done well. Further, according to the present embodiment, in the first operation mode, even if one of the count value of the counter 806C and the count value of the counter 806D reaches the count upper limit value, the horizontal line Detection can be done well. Further, according to the present embodiment, in the second operation mode, even if one of the count value of the counter 806A and the count value of the counter 806C reaches the count upper limit value, the vertical line can be successfully detected. Further, according to the present embodiment, in the second operation mode, even if one of the count value of the counter 806B and the count value of the counter 806D reaches the count upper limit value, the horizontal line Detection can be done well. Therefore, according to the present embodiment, imaging plane phase difference AF can be performed satisfactorily even for a subject with a higher brightness.

[Third Embodiment]
A solid-state imaging device, an imaging apparatus, and an imaging method according to the third embodiment will be described with reference to FIGS. 11 and 12. FIG. The same components as those of the solid-state imaging devices and the like according to the first and second embodiments shown in FIGS.

In the solid-state imaging device according to this embodiment, in the first imaging mode, the unit pixels are driven in the same manner as in the first embodiment, and in the second imaging mode, the counter 106A functions as a low-order bit counter, A counter 106B functions as a counter for upper bits.

A unit pixel 1100 provided in the solid-state imaging device according to this embodiment will be described with reference to FIG. 11 . FIG. 11 is a diagram showing a unit pixel 1100 provided in the solid-state imaging device according to this embodiment.

A shooting mode signal is supplied to the unit pixel 1100 . The shooting mode signal indicates whether the solid-state imaging device should be operated in the first shooting mode or the second shooting mode (third operation mode). A unit pixel 1100 has a first selection section 1107 and a second selection section 1108 added to the unit pixel 100 (see FIG. 1) described above in the first embodiment.

_A first input terminal of the first selection unit 1107 is supplied with the count upper limit value reach signal LB output from the counter 106B. A signal at H level is input to the second input terminal of the first selection unit 1107 . "1" shown in FIG. 11 indicates an H level signal. In the first photographing mode, the first selection unit 1107 supplies the AND gate _1104B with a signal corresponding to the count upper limit value reaching signal LB supplied from the counter 106B. In the second imaging mode, the first selector 1107 supplies an H level signal to the AND gate 104B.

A first input terminal of the second selection unit 1108 is supplied with a signal output from the OR gate 105B. A second input terminal of the second selection unit 1108 is supplied with the carry signal CA output from the counter 106A. In the first shooting mode, the second selection unit 1108 supplies the signal supplied from the OR gate 105B to the counter 106B. In the second imaging mode, the second selection unit 1108 supplies the carry signal CA supplied from the counter 106A to the counter 106B.

In the first photographing mode, the count upper limit reaching signal LB output from the counter _106B is input to the AND gate 104B, and the signal output from the OR gate 105B is input to the counter 106B. Therefore, in the first imaging mode, the unit pixel 1100 operates similarly to the unit pixel 100 described above in the first embodiment. In the first shooting mode, when the count value of the counter 106A reaches the count upper limit value, the count value of the counter 106A is held at the count upper limit value.

In the second shooting mode, an H level signal is input from the first selector 1107 to the AND gate 104B. Therefore, in the second imaging mode, both the pulse signal output from the waveform shaping section 103A and the pulse signal output from the waveform shaping section 103B are supplied to the counter 106A via the OR gate 105A. Therefore, in the second imaging mode, the counter 106A counts the pulse signal supplied from the waveform shaping section 103A and the pulse signal supplied from the waveform shaping section 103B. In the second photographing mode, when a pulse signal is input to the counter 106A whose count value has reached the count upper limit value, the count value of the counter 106A is reset to 0, and the carry signal CA is output from the counter 106A. . A carry signal CA output from the counter 106A is supplied to the counter 106B. The counter 106B counts the number of resets of the counter 106A based on the carry signal CA supplied from the counter 106A. Therefore, in the second imaging mode, the counter 106A functions as a low-order bit counter among the counters that count the number of photons incident on the unit pixel 1100 . In addition, the counter 106B functions as a high-order bit counter for counting the number of photons incident on the unit pixel 1100 . Thus, in the second imaging mode, the value obtained by adding the number of photons incident on the APD 101A and the number of photons incident on the APD 101B is counted by the serially connected counters 106A and 106B. be.

In the first shooting mode, the value obtained by adding the count upper limit value of the counter 106A and the count upper limit value of the counter 106B is the maximum value of the image signal. On the other hand, in the second shooting mode, the number of bits of the counter is doubled, so the maximum value of the image signal increases dramatically. Thus, in the second shooting mode, the maximum value of the image signal can be dramatically increased compared to the first shooting mode.

Next, operation of the solid-state imaging device according to the third embodiment will be described with reference to FIG. FIG. 12 is a diagram showing the operation of the solid-state imaging device according to the third embodiment. FIG. 12 shows regions of the pixel portion 1200 that are driven in the first imaging mode.

In the AF information acquisition region 1201 of the pixel portion 1200, the unit pixels 1100 are driven in the first shooting mode. On the other hand, in areas other than the AF information acquisition area 1201 in the pixel portion 1200, the unit pixels 1100 are driven in the second imaging mode.

The AF information acquisition area 1201 can be set by the user via the operation unit 606 . Alternatively, the subject may be detected by the control unit 603 based on an image acquired in advance, and the AF information acquisition area 1201 may be set by the control unit 603 based on the result of subject detection.

In this manner, signals used for imaging plane phase difference AF may be acquired in the first imaging mode, and signals used for images may be acquired in the second imaging mode. This embodiment is suitable, for example, when the brightness of subjects other than the main subject is high. As described above, this embodiment can also provide a solid-state imaging device, an imaging apparatus, and an imaging method capable of excellent imaging.

[Fourth embodiment]
A solid-state imaging device, an imaging apparatus, and an imaging method according to the fourth embodiment will be described with reference to FIG. The same components as those of the solid-state imaging devices and the like according to the first to third embodiments shown in FIGS.

Differences of this embodiment from the first to third embodiments will be described below. The imaging apparatus according to the present embodiment applies the present embodiment in a configuration in which outputs of unit pixels are added.

The solid-state imaging device according to the present embodiment can output an image with a low number of pixels by adding and outputting signals obtained by a plurality of unit pixels 1300 . Such an image with a low number of pixels is used, for example, when an image is temporarily displayed on a display unit of an imaging device. In this embodiment, a case where signals acquired by two unit pixels 1300 arranged in the same column are added is described as an example, but the present invention is not limited to this.

A unit pixel 1300 provided in the solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 13 is a diagram showing a solid-state imaging device according to this embodiment. FIG. 13 shows a unit pixel 1300 located in the first column among the plurality of unit pixels 1300 provided in the pixel array 1310. FIG. A unit pixel 1300_R1 is a unit pixel located in the first row. A unit pixel 1300_G2 is a unit pixel located in the second row. A unit pixel 1300_R3 is a unit pixel located in the third row. A unit pixel 1300_G4 is a unit pixel located in the fourth row. A unit pixel 1300_R5 is a unit pixel located in the fifth row. A unit pixel 1300_G6 is a unit pixel located in the sixth row. A unit pixel 1300_Gn-2 is a unit pixel located in the (n-2)th (n is a multiple of 6) row. A unit pixel 1300_Rn-1 is a unit pixel located in the (n-1)th row. A unit pixel 1300_Gn is a unit pixel located in the n-th row, which is the last row of the pixel array 1310 .

In the pixel array 1310 of the solid-state imaging device according to this embodiment, color filters are arranged according to the Bayer arrangement. The columns shown in FIG. 13 are columns in which R pixels provided with filters that transmit red and G pixels provided with filters that transmit green are alternately arranged. Unit pixels 1300_R1, 1300_R3, 1300_R5, and 1300_Rn-1 are R pixels. Unit pixels 1300_G2, 1300_G4, 1300_G6, 1300_Gn-2, and 1300_Gn are G pixels.

Reference numerals 1300_R1 to 1300_Gn are used when describing individual unit pixels, and reference numeral 1300 is used when describing unit pixels in general.

Addition processing is performed on the signal output from the unit pixel 1300_R1 located in the first row of the pixel array 1310 and the signal output from the unit pixel 1300_R3 located in the third row of the pixel array 1310. will be Addition processing is performed on the signal output from the unit pixel 1300_G4 located in the fourth row of the pixel array 1310 and the signal output from the unit pixel 1300_G6 located in the sixth row of the pixel array 1310. will be Similarly, the signal output from the unit pixel 1300 located in the seventh row of the pixel array 1310 and the signal output from the unit pixel 1300 located in the ninth row of the pixel array 1310 are added. processing takes place. In this way, the signal output from the unit pixel 1300 located on the n-2th row of the pixel array 1310 and the signal output from the unit pixel 1300 located on the n-th row of the pixel array 1310 are different. Addition processing is performed on the Addition processing is performed on signals acquired by pixels provided with color filters that transmit light of the same color, that is, color filters with the same transmission wavelength range. A signal obtained by addition processing is used when generating an image as a signal corresponding to one pixel. Note that the addition processing is performed by the signal processing unit 503 (see FIG. 5) that is provided after the pixel array 1310 .

A unit pixel 1300 has one APD 1301 , one quench resistor 1302 , one waveform shaping section 1303 , one AND gate 1304 , one OR gate 1305 and one counter 1306 . In addition, the unit pixel 1300 further has a control section 1307 .

The anode of APD 1301 is connected to ground potential. A cathode of the APD 1301 is connected to one end of the quench resistor 1302 and an input terminal of the waveform shaping section 1303 . The other end of quench resistor 1302 is connected to a predetermined potential _VAPD which is a reverse bias potential. Thus, APD 1301 is connected to a predetermined potential V _APD through quench resistor 1302 .

A pulse signal output from the waveform shaping section 1303 is supplied to the OR gate 1305 . A pulse signal output from the waveform shaping unit 1303 is supplied to another unit pixel 1300 via a wiring 1308 which will be described later.

A pulse signal output from the waveform shaping unit 1303 of another unit pixel 1300 is supplied to the AND gate 1304 via a wiring 1308 which will be described later. Also, a control signal output from the control unit 1307 is supplied to the AND gate 1304 . The signal output from AND gate 1304 is provided to OR gate 1305 .

The signal output from OR gate 1305 is supplied to counter 1306 . A count upper limit reaching signal output from the counter 1306 is supplied to the control unit 1307 . Also, a count upper limit value reaching signal output from the counter 1306 is supplied to a control unit 1307 provided in another unit pixel 1300 via a wiring 1309 to be described later.

An upper limit reaching signal output from a counter 1306 provided in another unit pixel 1300 is supplied to the control unit 1307 via a wiring 1309 to be described later.

The unit pixel 1300_R1 and the unit pixel 1300_R3 are connected by wirings 1308_R1, 1308_R3, 1309_R1 and 1309_R3. The unit pixel 1300_G4 and the unit pixel 1300_G6 are connected by wirings 1308_G4, 1308_G6, 1309_G4, and 1309_G6. The unit pixel 1300_Gn-2 and the unit pixel 1300_Gn are connected by wirings 1308_Gn-2, 1308_Gn, 1309_Gn-2 and 1309_Gn. Reference numerals 1308 and 1309 are used when wiring in general is described, and reference numerals 1308_R1 to 1308_Gn and 1309_R1 to 1309_Gn are used when describing individual wirings.

A wiring 1308_R1 is for supplying a pulse signal output from the waveform shaping unit 1303 provided in the unit pixel 1300_R1 to the AND gate 1304 provided in the unit pixel 1300_R3. A wiring 1308_R3 is for supplying a pulse signal output from the waveform shaping unit 1303 provided in the unit pixel 1300_R3 to the AND gate 1304 provided in the unit pixel 1300_R1. The wiring 1309_R1 is for supplying the count upper limit value reaching signal output from the counter 1306 provided in the unit pixel 1300_R1 to the control unit 1307 provided in the unit pixel 1300_R3. The wiring 1309_R1 is for supplying the count upper limit value reaching signal output from the counter 1306 provided in the unit pixel 1300_R1 to the control unit 1307 provided in the unit pixel 1300_R3.

A wiring 1308_G4 is for supplying a pulse signal output from the waveform shaping unit 1303 provided in the unit pixel 1300_G4 to the AND gate 1304 provided in the unit pixel 1300_G6. A wiring 1308_G6 is for supplying a pulse signal output from the waveform shaping unit 1303 provided in the unit pixel 1300_G6 to the AND gate 1304 provided in the unit pixel 1300_G4. The wiring 1309_G4 is for supplying the count upper limit value reaching signal output from the counter 1306 provided in the unit pixel 1300_G4 to the control unit 1307 provided in the unit pixel 1300_G6. The wiring 1309_G6 is for supplying the count upper limit value reaching signal output from the counter 1306 provided in the unit pixel 1300_G6 to the control unit 1307 provided in the unit pixel 1300_G4.

A wiring 1308_Gn-2 is for supplying a pulse signal output from the waveform shaping unit 1303 provided in the unit pixel 1300_Gn-2 to the AND gate 1304 provided in the unit pixel 1300_Gn. A wiring 1308_Gn is for supplying a pulse signal output from the waveform shaping unit 1303 provided in the unit pixel 1300_Gn to the AND gate 1304 provided in the unit pixel 1300_Gn−2. The wiring 1309_Gn-2 is for supplying the count upper limit reaching signal output from the counter 1306 provided in the unit pixel 1300_Gn-2 to the control unit 1307 provided in the unit pixel 1300_Gn. The wiring 1309_Gn is for supplying the count upper limit value reaching signal output from the counter 1306 provided in the unit pixel 1300_Gn to the control unit 1307 provided in the unit pixel 1300_Gn−2.

The control unit 1307 performs the following control when the count value of the counter 1306 of the unit pixel 1300 provided with the control unit 1307 reaches the count upper limit value. That is, control is performed so that the pulse signal output from the waveform shaping section 1303 of the unit pixel 1300 is counted by the counter 1306 provided in the unit pixel 1300 different from the unit pixel 1300 concerned. For example, when the count value of the counter 1306 provided in the unit pixel 1300_R1 reaches the count upper limit value, the count upper limit value reaching signal output from the counter 1306 provided in the unit pixel 1300_R1 becomes H level. Then, an H-level count upper limit value reaching signal is supplied to the control unit 1307 provided in the unit pixel 1300_R3 via the wiring 1309_R1. When an H-level count upper limit value reaching signal is supplied via the wiring 1309_R1, the control unit 1307 provided in the unit pixel 1300_R3 supplies an H-level control signal to the AND gate 1304 provided in the unit pixel 1300_R3. . The counter 1306 of the unit pixel 1300_R3 counts not only pulse signals output from the waveform shaping section 1303 provided in the unit pixel 1300_R3 but also pulse signals output from the waveform shaping section 1303 provided in the unit pixel 1300_R1. become.

As described above, in this embodiment, when the count value of the counter 1306 reaches the count upper limit value, the following occurs. That is, the pulse signal output from the waveform shaping unit 1303 of the unit pixel 1300 provided with the counter 1306 is processed by the counter 1306 provided in the unit pixel 1300 different from the unit pixel 1300 provided with the counter 1306. counted. Therefore, this embodiment can also provide a solid-state imaging device, an imaging apparatus, and an imaging method that can perform better imaging.

Note that, in the above description, an example in which addition processing is performed on signals output from a plurality of unit pixels 1300 arranged in the same column has been described, but the present invention is not limited to this. For example, addition processing may be performed on signals output from a plurality of unit pixels 1300 arranged in separate columns.

Also, in the above description, an example in which one APD 1301 is provided in one unit pixel 1300 has been described, but the present invention is not limited to this. For example, as in the first to third embodiments, one unit pixel 1300 may be provided with a plurality of APDs 1301 .

[Modified embodiment]
Although preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of the gist.

The present invention supplies a program that implements one or more functions of the above-described embodiments to a system or apparatus via a network or a recording medium, and one or more processors in the computer of the system or apparatus reads and executes the program. It can also be realized by processing to It can also be implemented by a circuit (for example, ASIC) that implements one or more functions.

101A, 101B...APD
102A, 102B... quench resistor 100... unit pixel

Claims (6)

a plurality of sensor units that emit pulses at a frequency corresponding to the frequency of photon reception; and a plurality of counters that count the number of pulses of signals emitted from the plurality of sensor units;
When a count value of a first counter for counting the number of pulses of a signal emitted from the first sensor unit among the plurality of sensor units reaches a predetermined value, the signal emitted from the first sensor unit is reduced. The number of pulses is counted by a second counter that counts the number of pulses of a signal emitted from a second sensor unit different from the first sensor unit among the plurality of sensor units . Solid-state image sensor. 2. The solid-state imaging device according to claim 1, wherein said predetermined value is a count upper limit value that is an upper limit value that can be counted by said first counter. 3. The solid-state imaging device according to claim 1, wherein light passing through the same microlens reaches said first sensor section and said second sensor section. The second sensor unit is positioned in a first direction with respect to the first sensor unit,
further comprising a third sensor unit positioned in a second direction different from the first direction with respect to the first sensor unit;
When the count value of the second counter reaches the predetermined value, the number of pulses of the signal emitted from the first sensor section and the number of pulses of the signal emitted from the third sensor section are counted. 4. The solid-state imaging device according to claim 1, further comprising a third counter for counting. a solid-state imaging device having a plurality of sensor units that emit pulses at a frequency corresponding to the frequency of photon reception; and a plurality of counters that count the number of pulses of signals emitted from the plurality of sensor units;
a processing unit that performs predetermined processing on a signal output from the solid-state imaging device ;
When a count value of a first counter for counting the number of pulses of a signal emitted from the first sensor unit among the plurality of sensor units reaches a predetermined value, the signal emitted from the first sensor unit is reduced. The imaging device , wherein the number of pulses is counted by a second counter that counts the number of pulses of a signal emitted from a second sensor unit different from the first sensor unit among the plurality of sensor units. . a step of counting the number of pulses of a signal emitted from the sensor unit at a frequency corresponding to the frequency of photon reception;
When a count value of a first counter for counting the number of pulses of a signal emitted from the first sensor unit among the plurality of sensor units reaches a predetermined value, the signal emitted from the first sensor unit is reduced. and counting the number of pulses by a second counter that counts the number of pulses of a signal emitted from a second sensor unit different from the first sensor unit.

Images