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JP7152543B2 - Semiconductor package structure - Google Patents
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JP7152543B2 - Semiconductor package structure - Google Patents

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JP7152543B2
JP7152543B2 JP2021026628A JP2021026628A JP7152543B2 JP 7152543 B2 JP7152543 B2 JP 7152543B2 JP 2021026628 A JP2021026628 A JP 2021026628A JP 2021026628 A JP2021026628 A JP 2021026628A JP 7152543 B2 JP7152543 B2 JP 7152543B2
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exposed surface
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heat dissipation
area
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JP2022100191A (en
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東昇 李
規浩 ▲ほう▼
兆▲けい▼ 魏
晉村 郭
佩螢 李
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▲き▼邦科技股▲分▼有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)

Description

本発明は、巻き取り可能であり、放熱シートを貼り付けている可撓性の半導体パッケージ構造に関するものである。 The present invention relates to a flexible semiconductor package structure that can be rolled up and attached with a heat dissipation sheet.

薄膜フリップチップパッケージ（ＣＯＦ）は薄膜トランジスタ液晶ディスプレイ（Ｔｈｉｎ ｆｉｌｍ ｔｒａｎｓｉｓｔｏｒ ｌｉｑｕｉｄ ｃｒｙｓｔａｌ ｄｉｓｐｌａｙ、ＴＦＴ ＬＣＤ）のドライバＩＣのパッケージ方式の１つであり、高解像度及び高性能が求められる。この種の薄膜フリップチップパッケージは、高熱が発生することによりドライバＩＣが損壊することがあった。 A thin film flip-chip package (COF) is one of package methods for a driver IC of a thin film transistor liquid crystal display (TFT LCD), and requires high resolution and high performance. This type of thin film flip chip package may damage the driver IC due to high heat generation.

薄膜フリップチップパッケージ構造として、例えば、特許文献１に記載されたものが知られている。第一放熱部材の接着層によりチップ及び薄膜基板に貼り付け、チップに対する放熱を行っている。特許文献１には接着層の端部が基材、熱伝導層、第一金属層、及び第二金属層の端部に平たく揃えていると記載されているため、薄膜フリップチップパッケージ構造が押圧された場合、外力（例えば、巻き取る際の圧力等）により基材、熱伝導層、第一金属層、及び第二金属層の端部に接着層が溢れ出すか突出し、薄膜フリップチップパッケージ構造が汚染された。また、薄膜フリップチップパッケージ構造が巻き取られた場合、基材、熱伝導層、第一金属層、及び第二金属層の端部に溢れ出すか突出する接着層により薄膜フリップチップパッケージ構造が相互に接着してしまい、薄膜フリップチップパッケージ構造の品質及び歩留まりに影響を与えた。 As a thin film flip chip package structure, for example, the one described in Patent Document 1 is known. The adhesive layer of the first heat dissipation member is attached to the chip and the thin film substrate to dissipate heat to the chip. Patent Document 1 describes that the edges of the adhesive layer are flush with the edges of the base material, the thermally conductive layer, the first metal layer, and the second metal layer, so that the thin film flip chip package structure is pressed. When the adhesive layer overflows or protrudes at the edges of the base material, the thermally conductive layer, the first metal layer, and the second metal layer due to external force (such as pressure during winding), the thin film flip chip package structure is formed. was contaminated. In addition, when the thin film flip chip package structure is rolled up, the adhesive layer that overflows or protrudes at the edges of the substrate, the thermally conductive layer, the first metal layer, and the second metal layer keeps the thin film flip chip package structure together. , thus affecting the quality and yield of the thin film flip chip package structure.

台湾登録実用新案第Ｍ６０２７２５号公報Taiwan Registered Utility Model No. M602725

本発明は、上述に鑑みてなされたものであり、その目的は、チップに貼り付けた放熱シートの接着層が放熱シートに溢れ出すか突出し汚染される事象を回避する半導体パッケージ構造を提供することにある。 SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor package structure that avoids the phenomenon that the adhesive layer of a heat dissipation sheet attached to a chip overflows or protrudes into the heat dissipation sheet and is contaminated. It is in.

本発明の半導体パッケージ構造は、回路層を有している可撓性基板と、前記可撓性基板に設置し、前記回路層に電気的に接続し、露出面を露出しているチップと、前記チップの前記露出面に設置し、キャリアと、放熱層と、接着層とを含み、前記放熱層は前記キャリアと前記接着層との間に位置し、前記接着層は第一接着面により前記チップの前記露出面に貼り付け、前記放熱層と前記チップとの間に前記接着層を包囲している空間を形成している放熱シートと、を備え、前記接着層は前記チップの前記露出面に投影し、前記露出面に第一投影領域を形成し、前記チップの前記露出面は第一端部を有し、前記放熱層の表面は第二端部を有し、前記第一投影領域は第三端部を有し、前記第一端部、前記第二端部、及び前記第三端部により前記空間を定義し、前記キャリアは前記チップの前記露出面に投影し、前記露出面に第三投影領域を形成し、前記第三投影領域は第五端部を有し、前記第五端部は前記露出面の前記第一端部と前記第一投影領域の前記第三端部との間に位置している。
A semiconductor package structure of the present invention comprises: a flexible substrate having a circuit layer; a chip mounted on the flexible substrate, electrically connected to the circuit layer, and having an exposed surface exposed; A carrier, a heat dissipation layer and an adhesive layer are disposed on the exposed surface of the chip, wherein the heat dissipation layer is positioned between the carrier and the adhesive layer, and the adhesive layer is disposed on the exposed surface of the chip by a first adhesive surface. a heat dissipation sheet attached to the exposed surface of the chip and forming a space surrounding the adhesive layer between the heat dissipation layer and the chip, wherein the adhesive layer is attached to the exposed surface of the chip. to form a first projection area on the exposed surface, the exposed surface of the chip having a first edge, the surface of the heat dissipation layer having a second edge, the first projection area has a third end and defines the space with the first end, the second end and the third end, the carrier projecting onto the exposed surface of the chip and the exposed surface forming a third projection area in the third projection area, the third projection area having a fifth end, the fifth end being the first end of the exposed surface and the third end of the first projection area is located between

本発明は、接着層が押圧された場合、絞り出された接着層を空間に収容することで接着層が放熱シートに溢れ出す或いは突出する事象を回避する。また、複数の可撓性の半導体パッケージ構造を巻き取る際に、これら可撓性の半導体パッケージ構造が相互に接着する事象も回避する。 According to the present invention, when the adhesive layer is pressed, the squeezed-out adhesive layer is accommodated in the space, thereby avoiding the phenomenon that the adhesive layer overflows or protrudes into the heat dissipation sheet. It also avoids the phenomenon of the flexible semiconductor packaging structures sticking together when winding the flexible semiconductor packaging structures.

本発明の第一実施形態に係る半導体パッケージ構造の回路基板の平面図である。1 is a plan view of a circuit board of a semiconductor package structure according to a first embodiment of the present invention; FIG. 本発明の第一実施形態に係る半導体パッケージ構造の回路基板の断面図である。1 is a cross-sectional view of a circuit board of a semiconductor package structure according to a first embodiment of the present invention; FIG.

以下、本発明による実施形態を図面に基づいて説明する。 BEST MODE FOR CARRYING OUT THE INVENTION An embodiment according to the present invention will be described below with reference to the drawings.

（第一実施形態）
本発明の第一実施形態について図１から図２に基づいて説明する。 (First embodiment)
A first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG.

本発明に係る半導体パッケージ構造１００（例えば、薄膜フリップチップパッケージ、ＣＯＦ等）は、可撓性基板１１０と、チップ１２０と、放熱シート１３０と、を備えている。可撓性基板１１０は回路層１１１及び保護層１１２を有している。
図１及び図２に示すように、本実施形態では、回路層１１１は可撓性基板１１０の表面に設置し、保護層１１２は回路層１１１を被覆し、保護層１１２は回路層１１１の複数のインナーリード１１１ａを露出している。 A semiconductor package structure 100 (eg, thin film flip chip package, COF, etc.) according to the present invention comprises a flexible substrate 110 , a chip 120 and a heat dissipation sheet 130 . A flexible substrate 110 has a circuit layer 111 and a protective layer 112 .
As shown in FIGS. 1 and 2 , in this embodiment, the circuit layer 111 is placed on the surface of the flexible substrate 110 , the protective layer 112 covers the circuit layer 111 , and the protective layer 112 covers the circuit layers 111 . The inner lead 111a of is exposed.

図１及び図２に示すように、チップ１２０は可撓性基板１１０に設置し、チップ１２０は複数のバンプ１２１により回路層１１１のこれらインナーリード１１１ａに電気的に接続し、チップ１２０は露出面１２０ａを露出している。
本実施形態では、可撓性基板１１０とチップ１２０との間にアンダーフィル１４０を充填し、アンダーフィル１４０はこれらバンプ１２１を被覆している。 As shown in FIGS. 1 and 2, the chip 120 is mounted on the flexible substrate 110, the chip 120 is electrically connected to these inner leads 111a of the circuit layer 111 by a plurality of bumps 121, and the chip 120 is exposed on the exposed surface. 120a is exposed.
In this embodiment, an underfill 140 is filled between the flexible substrate 110 and the chip 120 , and the underfill 140 covers these bumps 121 .

放熱シート１３０はチップ１２０の露出面１２０ａに設置し、放熱シート１３０はキャリア１３１と、放熱層１３２と、接着層１３３と、を備えている。放熱層１３２はキャリア１３１と接着層１３３との間に位置し、接着層１３３は第一接着面１３３ａ及び第二接着面１３３ｂを有している。接着層１３３は第一接着面１３３ａによりチップ１２０の露出面１２０ａに貼り付け、接着層１３３は第二接着面１３３ｂにより放熱層１３２の表面１３２ａに貼り付け、放熱層１３２とチップ１２０との間に接着層１３３を包囲する空間Ｒを形成している。 A heat dissipation sheet 130 is installed on the exposed surface 120 a of the chip 120 , and the heat dissipation sheet 130 includes a carrier 131 , a heat dissipation layer 132 and an adhesive layer 133 . The heat dissipation layer 132 is located between the carrier 131 and the adhesive layer 133, and the adhesive layer 133 has a first adhesive surface 133a and a second adhesive surface 133b. The adhesive layer 133 is attached to the exposed surface 120a of the chip 120 by the first adhesive surface 133a, and the adhesive layer 133 is attached to the surface 132a of the heat dissipation layer 132 by the second adhesive surface 133b. A space R surrounding the adhesive layer 133 is formed.

接着層１３３はチップ１２０の露出面１２０ａに投影し、露出面１２０ａに第一投影領域Ａ１を形成している。接着層１３３は放熱層１３２の表面１３２ａに投影し、表面１３２ａに第二投影領域Ａ２を形成している。キャリア１３１はチップ１２０の露出面１２０ａに投影し、露出面１２０ａに第三投影領域Ａ３を形成している。 The adhesive layer 133 is projected onto the exposed surface 120a of the chip 120 to form a first projected area A1 on the exposed surface 120a. The adhesive layer 133 is projected onto the surface 132a of the heat dissipation layer 132 to form a second projection area A2 on the surface 132a. The carrier 131 projects onto the exposed surface 120a of the chip 120 to form a third projected area A3 on the exposed surface 120a.

また、第一投影領域Ａ１は露出面１２０ａ中に位置し、第一投影領域Ａ１の領域面積は露出面１２０ａの表面積未満である。第二投影領域Ａ２は表面１３２ａ中に位置し、第二投影領域Ａ２の領域面積は表面１３２ａの表面積未満である。
本実施形態では、チップ１２０の露出面１２０ａは第一端部１２０ｂを有し、放熱層１３２の表面１３２ａは第二端部１３２ｂを有し、第一投影領域Ａ１は第三端部Ａ１１を有し、第二投影領域Ａ２は第四端部Ａ２１を有し、第三投影領域Ａ３は第五端部Ａ３１を有している。第五端部Ａ３１は露出面１２０ａの第一端部１２０ｂと第一投影領域Ａ１の第三端部Ａ１１との間に位置し、第五端部Ａ３１と露出面１２０ａの第一端部１２０ｂとが重畳している。 Also, the first projection area A1 is located in the exposed surface 120a, and the area area of the first projection area A1 is less than the surface area of the exposed surface 120a. The second projection area A2 is located in the surface 132a, and the area area of the second projection area A2 is less than the surface area of the surface 132a.
In this embodiment, the exposed surface 120a of the chip 120 has a first end 120b, the surface 132a of the heat dissipation layer 132 has a second end 132b, and the first projection area A1 has a third end A11. The second projection area A2 has a fourth edge A21, and the third projection area A3 has a fifth edge A31. The fifth end A31 is positioned between the first end 120b of the exposed surface 120a and the third end A11 of the first projection area A1, and the fifth end A31 and the first end 120b of the exposed surface 120a are superimposed.

図１及び図２に示すように、本実施形態では、第一端部１２０ｂと第三端部Ａ１１との間に２０μｍ以上である間隔を有し、第二端部１３２ｂと第四端部Ａ２１との間に２０μｍ以上である間隔を有し、第一端部１２０ｂ、第二端部１３２ｂ、及び第三端部Ａ１１により空間Ｒを定義している。
本実施形態では、第一端部１２０ｂ、第二端部１３２ｂ、第三端部Ａ１１、及び第四端部Ａ２１により空間Ｒを定義している。空間Ｒは保留空間であり、接着層１３３が押圧された場合、保留された空間Ｒに押圧された接着層１３３を収容することにより、接着層１３３が放熱シート１３０に溢れ出す或いは突出する事象を回避し、半導体パッケージ構造１００が汚染されないようにしている。また、複数の半導体パッケージ構造１００を巻き取る際に、これら半導体パッケージ構造１００が相互に接着する事象も回避している。 As shown in FIGS. 1 and 2, in this embodiment, there is a gap of 20 μm or more between the first end 120b and the third end A11, and the second end 132b and the fourth end A21 A space R is defined by the first end 120b, the second end 132b, and the third end A11.
In this embodiment, the space R is defined by the first end portion 120b, the second end portion 132b, the third end portion A11, and the fourth end portion A21. The space R is a reserved space, and when the adhesive layer 133 is pressed, the pressed adhesive layer 133 is accommodated in the reserved space R, thereby preventing the adhesive layer 133 from overflowing or projecting onto the heat dissipation sheet 130 . to avoid contamination of the semiconductor package structure 100 . In addition, when winding a plurality of semiconductor package structures 100, the phenomenon that these semiconductor package structures 100 adhere to each other is also avoided.

（その他の実施形態）
その他の実施形態では、第一端部、第二端部、及び第三端部ではなく、第二端部、第三端部、及び第四端部により空間Ｒを定義している。 (Other embodiments)
In other embodiments, the space R is defined by the second, third and fourth ends rather than the first, second and third ends.

その実施形態の他の基本的構成は、第一実施形態と同様である。 Other basic configurations of this embodiment are the same as those of the first embodiment.

以上、本発明は、上記実施形態に限定されるものではなく、その要旨を逸脱しない範囲において種々の形態で実施可能である。 As described above, the present invention is not limited to the above-described embodiments, and can be implemented in various forms without departing from the gist of the present invention.

１００ 半導体パッケージ構造、
１１０ 可撓性基板、
１１１ 回路層、
１１１ａ インナーリード、
１１２ 保護層、
１２０ チップ、
１２０ａ 露出面、
１２０ｂ 第一端部、
１２１ バンプ、
１３０ 放熱シート、
１３１ キャリア、
１３２ 放熱層、
１３２ａ 表面、
１３２ｂ 第二端部、
１３３ 接着層、
１３３ａ 第一接着面、
１３３ｂ 第二接着面、
１４０ アンダーフィル、
Ａ１ 第一投影領域、
Ａ１１ 第三端部、
Ａ２ 第二投影領域、
Ａ２１ 第四端部、
Ａ３ 第三投影領域、
Ａ３１ 第五端部、
Ｒ 空間。 100 semiconductor package structure,
110 flexible substrate;
111 circuit layer,
111a inner lead,
112 protective layer,
120 chips,
120a exposed surface,
120b first end,
121 Bump,
130 heat dissipation sheet,
131 Carrier,
132 heat dissipation layer,
132a surface,
132b second end,
133 adhesive layer,
133a first adhesive surface,
133b second adhesive surface,
140 underfill,
A1 first projection area,
A11 third end,
A2 second projection area,
A21 fourth end,
A3 third projection area,
A31 fifth end,
R space.

Claims (6)

回路層を有している可撓性基板と、
前記可撓性基板に設置し、前記回路層に電気的に接続し、露出面を露出しているチップと、
前記チップの前記露出面に設置し、キャリアと、放熱層と、接着層とを含み、前記放熱層は前記キャリアと前記接着層との間に位置し、前記接着層は第一接着面により前記チップの前記露出面に貼り付け、前記放熱層と前記チップとの間に前記接着層を包囲している空間を形成している放熱シートと、を備え、
前記接着層は前記チップの前記露出面に投影し、前記露出面に第一投影領域を形成し、
前記チップの前記露出面は第一端部を有し、前記放熱層の表面は第二端部を有し、前記第一投影領域は第三端部を有し、前記第一端部、前記第二端部、及び前記第三端部により前記空間を定義し、
前記キャリアは前記チップの前記露出面に投影し、前記露出面に第三投影領域を形成し、前記第三投影領域は第五端部を有し、前記第五端部は前記露出面の前記第一端部と前記第一投影領域の前記第三端部との間に位置していることを特徴とする半導体パッケージ構造。 a flexible substrate having a circuit layer;
a chip mounted on the flexible substrate and electrically connected to the circuit layer with an exposed surface exposed;
A carrier, a heat dissipation layer and an adhesive layer are disposed on the exposed surface of the chip, wherein the heat dissipation layer is positioned between the carrier and the adhesive layer, and the adhesive layer is disposed on the exposed surface of the chip by a first adhesive surface. a heat dissipation sheet attached to the exposed surface of the chip and forming a space surrounding the adhesive layer between the heat dissipation layer and the chip ;
the adhesive layer projects onto the exposed surface of the chip to form a first projected area on the exposed surface;
The exposed surface of the chip has a first end, the surface of the heat dissipation layer has a second end, the first projected area has a third end, the first end, the defining the space by a second end and the third end;
The carrier projects onto the exposed surface of the chip and forms a third projected area on the exposed surface, the third projected area having a fifth end, the fifth end being the exposed surface of the exposed surface. A semiconductor package structure located between a first end and the third end of the first projection area . 前記第一投影領域の領域面積は前記露出面の表面積未満であり、前記第一投影領域は前記露出面中に位置し、前記接着層は第二接着面により前記放熱層の前記表面に貼り付け、前記接着層は前記放熱層の前記表面に投影し、前記表面には第二投影領域を形成し、前記第二投影領域の領域面積は前記表面の表面積未満であり、前記第二投影領域は前記表面中に位置していることを特徴とする請求項１に記載の半導体パッケージ構造。 The area of the first projected area is less than the surface area of the exposed surface, the first projected area is located in the exposed surface, and the adhesive layer is attached to the surface of the heat dissipation layer by a second adhesive surface. the adhesive layer is projected onto the surface of the heat dissipation layer to form a second projection area on the surface, the area of the second projection area is less than the surface area of the surface, and the second projection area is is located in said surface. 前記第二投影領域は第四端部を有し、前記第一端部、前記第二端部、前記第三端部、及び前記第四端部により前記空間を定義していることを特徴とする請求項２に記載の半導体パッケージ構造。 The second projection area has a fourth edge, and the space is defined by the first edge, the second edge, the third edge, and the fourth edge. 3. The semiconductor package structure according to claim 2. 前記第二端部と前記第四端部との間には２０μｍ以上である間隔を有していることを特徴とする請求項３に記載の半導体パッケージ構造。 4. The semiconductor package structure of claim 3, wherein the second end and the fourth end have a gap of 20 [mu]m or more. 前記第一端部と前記第三端部との間には２０μｍ以上である間隔を有していることを特徴とする請求項１に記載の半導体パッケージ構造。 2. The semiconductor package structure as claimed in claim 1 , wherein the first end and the third end have a distance of 20 [mu]m or more. 前記第五端部と前記露出面の前記第一端部とは重畳していることを特徴とする請求項１に記載の半導体パッケージ構造。 2. The semiconductor package structure of claim 1 , wherein the fifth end and the first end of the exposed surface overlap.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001007262A (en) 1999-06-17 2001-01-12 Nec Corp Semiconductor device and method of manufacturing semiconductor device
JP2001244362A (en) 2000-02-28 2001-09-07 Nec Corp Semiconductor device
US20050168952A1 (en) 2004-02-04 2005-08-04 Siliconware Precision Industries Co., Ltd. Semiconductor package
US20070262444A1 (en) 2006-05-10 2007-11-15 Siliconware Precision Industries Co., Ltd. Semiconductor device and chip structure thereof
US20100019379A1 (en) 2008-07-24 2010-01-28 Broadcom Corporation External heat sink for bare-die flip chip packages
CN114520197A (en) 2020-11-19 2022-05-20 颀邦科技股份有限公司 Flexible semiconductor package structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW258829B (en) * 1994-01-28 1995-10-01 Ibm
KR100760770B1 (en) * 2006-03-29 2007-09-21 삼성에스디아이 주식회사 Plasma display
US20090091021A1 (en) * 2007-10-03 2009-04-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
JP2012164846A (en) * 2011-02-08 2012-08-30 Renesas Electronics Corp Semiconductor device, semiconductor device manufacturing method and display device
US10770368B2 (en) * 2015-12-02 2020-09-08 Novatek Microelectronics Corp. Chip on film package and heat-dissipation structure for a chip package
TWM610924U (en) * 2020-12-23 2021-04-21 頎邦科技股份有限公司 Flexible semiconductor package

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001007262A (en) 1999-06-17 2001-01-12 Nec Corp Semiconductor device and method of manufacturing semiconductor device
JP2001244362A (en) 2000-02-28 2001-09-07 Nec Corp Semiconductor device
US20050168952A1 (en) 2004-02-04 2005-08-04 Siliconware Precision Industries Co., Ltd. Semiconductor package
US20070262444A1 (en) 2006-05-10 2007-11-15 Siliconware Precision Industries Co., Ltd. Semiconductor device and chip structure thereof
US20100019379A1 (en) 2008-07-24 2010-01-28 Broadcom Corporation External heat sink for bare-die flip chip packages
CN114520197A (en) 2020-11-19 2022-05-20 颀邦科技股份有限公司 Flexible semiconductor package structure

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