JP7160771B2 - Connection test system, computer, connection test device and connection test method - Google Patents

Description

The present disclosure relates to a connection test system, a computer, a connection test device, and a connection test method.

SoM (System on Module) or CoM (Computer on Module) is a small module that has the basic configuration of a computer, such as a CPU (Central Processing Unit), memory, and high-speed serial interface, and is equipped with sufficient functions as a computer. A computer called

The SoM or CoM is equipped with a Peripheral Component Interconnect Express (hereinafter sometimes referred to as "PCIe") interface capable of high-speed serial communication, and the CPU possessed by the SoM or CoM communicates using multiple lanes. It is possible. When the CPU can communicate using a maximum of 16 lanes, the port setting pattern for these 16 lanes is, for example, one port accommodating an x16 link (hereinafter sometimes referred to as "x16 port"). a pattern in which only one port is set (hereinafter sometimes referred to as "setting pattern SP1"), and a pattern in which two ports accommodating x8 links (hereinafter sometimes referred to as "x8 ports") are set (hereinafter sometimes referred to as (sometimes referred to as "configuration pattern SP2"), or a pattern in which one x8 port and two ports accommodating x4 links (hereinafter sometimes referred to as "x4 ports") are set (hereinafter It is possible to adopt any one of the three setting patterns (sometimes referred to as "setting pattern SP3").

An endpoint device having an x16 port (hereinafter referred to as an "x16 endpoint device") is an endpoint device that is a communication partner of a CPU that can adopt any of the above three setting patterns as a port setting pattern. ), endpoint devices with x8 ports (hereinafter sometimes referred to as “x8 endpoint devices”), and endpoint devices with x4 ports (hereinafter referred to as “x4 endpoint devices”) There is).

In addition, the endpoint device is usually mounted on a PCIe card, and by mounting the PCIe card in the card slot of the carrier board on which the SoM or CoM is mounted, communication between the CPU and the endpoint device becomes possible. Become.

JP 2014-137614 A JP 2008-171291 A JP 2007-280237 A

Here, in order to perform a port connection test for a CPU that adopts the setting pattern SP1, it is necessary to attach a PCIe card on which one x16 endpoint device is mounted to the carrier board. Also, in order to perform a port connection test for a CPU that adopts the setting pattern SP2, it is necessary to attach a PCIe card on which two x8 endpoint devices are mounted to the carrier board. Also, in order to perform a port connection test for a CPU that adopts the setting pattern SP3, it is necessary to mount a PCIe card on which one x8 endpoint device and two x4 endpoint devices are mounted on the carrier board. Therefore, in order to perform a connection test for all setting patterns of a CPU that can take any of the setting patterns SP1, SP2, and SP3 as a port setting pattern, the PCIe card mounted on the carrier board is set to each setting pattern of the CPU port. I had to replace it accordingly. In other words, in order to perform the port connection test for all setting patterns of the CPU ports, it was necessary to change the hardware configuration of the connection test system having the SoM or CoM and the PCIe card.

An object of the technology disclosed herein is to perform port connection tests for all setting patterns of CPU ports without changing the hardware configuration of a connection test system.

In an aspect of the disclosure, the connection testing system has a computer and a testing device. The computer has a CPU and a memory. The CPU is connected to the testing apparatus via a plurality of lanes. The memory stores a plurality of port setting patterns for the plurality of lanes. The test apparatus has a plurality of endpoint devices and a switch. The plurality of endpoint devices communicate with the CPU via a bus and the plurality of lanes. The switch has the bus, and a connection pattern of the bus in the switch is switchable. The CPU sequentially sets different numbers of ports for the plurality of lanes according to each of the plurality of setting patterns, controls the connection pattern, and controls the plurality of lanes and the By communicating with the plurality of endpoint devices via a bus, a connection test of the sequentially set ports is performed.

According to the aspect of the disclosure, the port connection test can be performed for all setting patterns of the ports of the CPU without changing the hardware configuration of the connection test system.

FIG. 1 is a diagram illustrating a configuration example of a connection test system according to Example 1 of the present disclosure. FIG. 2 is a diagram illustrating an example of a setting pattern table according to the first embodiment of the present disclosure; FIG. 3 is a flowchart illustrating an example of a processing procedure of the connection testing system according to the first embodiment of the present disclosure; FIG. 4 is a diagram illustrating a port setting example according to the first embodiment of the present disclosure; FIG. 5 is a diagram illustrating an example of port settings according to the first embodiment of the present disclosure; FIG. 6 is a diagram illustrating an example of port settings according to the first embodiment of the present disclosure; FIG. 7 is a diagram illustrating an example of a connection test success/failure table according to the first embodiment of the present disclosure;

Hereinafter, embodiments of the present disclosure will be described based on the drawings.

[Example 1]
<Configuration of connection test system>
FIG. 1 is a diagram illustrating a configuration example of a connection test system according to Example 1 of the present disclosure. In FIG. 1 , the connection test system 1 has a carrier board 4 , a computer 2 , a PCIe slot 7 and a PCIe card 3 . An example of computer 2 is SoM or CoM.

The computer 2 has a CPU 5 and a memory 6 . The CPU 5 has a port setting register 505 and a port 51 . Further, the CPU 5 includes, as the functions of the CPU 5, a pattern acquisition unit 501, a pattern determination unit 502, a switch mode setting unit 503, a port setting unit 504, a connection pattern setting unit 506, a connection test execution unit 507, a connection It has a state measurement unit 508 and a success/failure determination unit 509 .

The PCIe card 3 has a PCIe switch 8 and endpoint devices 11D, 12D and 13D. Endpoint device 11D is a x8 endpoint device, and endpoint devices 12D and 13D are x4 endpoint devices.

The PCIe switch 8 includes ports 52, 53, 54 and 55, a switch mode setting register 801, a US (Up Stream) port setting register 802, a DS (Down Stream) port setting register 803, and a connection pattern setting register 804. have

Endpoint device 11D has port 11P, endpoint device 12D has port 12P, and endpoint device 13D has port 13P.

Computer 2 is coupled to carrier board 4 using stacking connectors. In addition, the carrier board 4 is provided with a PCIe slot 7, and by mounting the PCIe card 3 in the PCIe slot 7, communication between the CPU 5 and each of the endpoint devices 11D, 12D, and 13D becomes possible. Become. Communication between the CPU 5 and each endpoint device 11D, 12D, 13D is performed via the PCIe switch 8. FIG.

The CPU 5 and the PCIe switch 8 are connected via ports 51 and 52, and communication between the CPU 5 and the PCIe switch 8 is performed using the link LA. The CPU 5 can communicate with the PCIe switch 8 using 16 lanes 0 to 15 at maximum. Access from the CPU 5 to the switch mode setting register 801, the US port setting register 802, the DS port setting register 803, and the connection pattern setting register 804 is performed using the register access bus RB.

The PCIe switch 8 and the endpoint device 11D are connected via the port 53 and the port 11P, and communication between the PCIe switch 8 and the endpoint device 11D is performed using the link LB. PCIe switch 8 and endpoint device 12D are connected via port 54 and port 12P, and communication between PCIe switch 8 and endpoint device 12D is performed using link LC. The PCIe switch 8 and the endpoint device 13D are connected via the port 55 and the port 13P, and communication between the PCIe switch 8 and the endpoint device 13D is performed using the link LD. Link LB is a x8 link, link LC is a x4 link, and link LD is a x4 link. Port 11P is an x8 port, port 12P is an x4 port, and port 13P is an x4 port.

Hereinafter, the port of the CPU 5 may be called "CPU port", and the port of the PCIe switch 8 may be called "PCIe port". Also, among the plurality of PCIe ports, the port connected to the CPU port is sometimes called the "US port", and the port connected to each of the ports 11P, 12P, and 13P is sometimes called the "DS port".

FIG. 2 is a diagram illustrating an example of a setting pattern table according to the first embodiment of the present disclosure; A setting pattern table TA shown in FIG. 2 is stored in the memory 6 in advance. Setting patterns SP1, SP2, and SP3 are registered in the setting pattern table TA as an example.

In the first row of the setting pattern table TA, the setting pattern SP1 sets a single port accommodating an x16 link composed of lanes 0 to 15 for each of the CPU port and the US port, and sets the DS port , a port 53 accommodating an x8 link consisting of lanes 0-7, a port 54 accommodating an x4 link consisting of lanes 8-11, and an x4 link consisting of lanes 12-15. port 55 is set. In the first row of the setting pattern table TA, "connection pattern CP1" is registered as the connection pattern corresponding to setting pattern SP1, and "base mode" is registered as the connection mode corresponding to setting pattern SP1.

Also, in the second row of the setting pattern table TA, the setting pattern SP2 is for each of the CPU port and the US port, a first port accommodating an x8 link composed of lanes 0 to 7, and lanes 8 to 15. Two ports are set, the second port accommodating the configured x8 link, and the DS port is configured with the port 53 accommodating the x8 link configured with lanes 0 to 7 and lanes 8 to 11. 10 shows that a port 54 that accommodates an x4 link configured with lanes 12 to 15 and a port 55 that accommodates an x4 link configured with lanes 12 to 15 are set. In the second row of the setting pattern table TA, "connection pattern CP2" is registered as the connection pattern corresponding to setting pattern SP2, and "virtual switch mode" is registered as the connection mode corresponding to setting pattern SP2.

Also, in the third row of the setting pattern table TA, the setting pattern SP3 is for each of the CPU port and the US port, the first port accommodating the x8 link composed of lanes 0 to 7, and the lanes 8 to 11. Three ports are configured, the second port accommodating the configured x4 link and the third port accommodating the x4 link configured with lanes 12-15, and lanes 0-7 for the DS port. A port 53 accommodating an x8 link configured, a port 54 accommodating an x4 link configured with lanes 8-11, and a port 55 accommodating an x4 link configured with lanes 12-15 are set. indicates In the third row of the setting pattern table TA, "connection pattern CP3" is registered as the connection pattern corresponding to setting pattern SP3, and "virtual switch mode" is registered as the connection mode corresponding to setting pattern SP3.

The connection modes “base mode” and “virtual switch mode” are modes that can be set in the PCIe switch 8 . "Base mode" is a mode when a single port is set for a US port, and "virtual switch mode" is a mode when multiple ports are set for a US port.

<Processing procedure in the connection test system>
FIG. 3 is a flowchart illustrating an example of a processing procedure of the connection testing system according to the first embodiment of the present disclosure; 4, 5, and 6 are diagrams showing port setting examples according to the first embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example of a connection test success/failure table according to the first embodiment of the present disclosure;

In the flowchart shown in FIG. 3, in step S101, the pattern acquisition unit 501 refers to the setting pattern table TA stored in the memory 6, and sets the number of registered rows of the setting pattern table TA to "N". For example, since the setting pattern table TA shown in FIG. 2 has three registered rows, the pattern acquisition unit 501 sets the number of registered rows N to "3" in step S101.

Next, in step S103, the pattern acquisition unit 501 sets the value of the counter "n" to "1".

Next, in step S105, the pattern acquisition unit 501 refers to the setting pattern table TA stored in the memory 6, and determines the setting registered in the n-th row (that is, the first row here) in the setting pattern table TA. A pattern (that is, setting pattern SP1 here) is obtained, and CPU ports/US ports: 0 to 15, DS ports: 0 to 7, 8 to 11, 12 to 15 are registered in association with the setting pattern SP1. , connection pattern CP1, and connection mode: base mode.

Next, in step S107, the pattern determination unit 502 determines which of the setting patterns SP1, SP2, and SP3 the setting pattern acquired in step S105 is. Since the setting pattern acquired in step S105 for the first time is "SP1", the process proceeds from step S107 to step S109.

Next, in step S109, since the connection mode corresponding to the setting pattern SP1 acquired in the first step S105 is "base mode," the switch mode setting unit 503 sets the register value of the switch mode setting register 801 to "base mode." mode". For example, in the switch mode setting register 801, when the register value "0b" corresponds to the base mode and the register value "1b" corresponds to the virtual switch mode, in step S109 the switch mode setting unit 503 sets the switch mode setting register Set the register value of 801 to '0b'. By setting the register value of the switch mode setting register 801 to "0b", the PCIe switch 8 operates in the base mode.

Next, in step S111, since the CPU port setting value corresponding to the setting pattern SP1 acquired in the first step S105 is "0 to 15", the port setting unit 504 sets the register value of the port setting register 505 to " x16 port”. For example, in the port setting register 505, the register value "00b" corresponds to "x8 port x 1, x4 port x 2 (one x8 port and two x4 ports)", and the register value "10b" corresponds to "x8 port x2 (two x8 ports)” and the register value “11b” corresponds to “x16 port x1 (one x16 port)”, in step S111, the port setting unit 504 performs port setting The register value of register 505 is set to "11b". By setting the register value of the port setting register 505 to "11b", as shown in FIG. 4, a single port 61 accommodating an x16 link composed of lanes 0 to 15 is set as a CPU port. be. That is, port 51 (FIG. 1) is not split, and single port 61, which is an x16 port, is set as the CPU port.

Next, in step S113, since the US port setting value corresponding to the setting pattern SP1 obtained in the first step S105 is "0 to 15", the port setting unit 504 sets the register value of the US port setting register 802 to Set to a value that corresponds to "x16 port". For example, in the US port setting register 802, the register value "001b" corresponds to "x16 port x 1", the register value "010b" corresponds to "x8 port x 2", and the register value "011b" corresponds to "x8 port x1, x4 port x2” and the register value “100b” corresponds to “x4 port x4 (four x4 ports)”, in step S113, the port setting unit 504 sets the US port setting register Set the register value of 802 to "001b". By setting the register value of the US port setting register 802 to "001b", as shown in FIG. 4, a single port 62 accommodating an x16 link composed of lanes 0 to 15 is set as a US port. be done. That is, port 52 (FIG. 1) is not split and a single port 62, which is an x16 port, is configured as a US port. Therefore, port 61 and port 62 are connected using link L11, which is an x16 link.

Next, in step S115, since the DS port setting values corresponding to the setting pattern SP1 acquired in the first step S105 are "0 to 7, 8 to 11, 12 to 15", the port setting unit 504 sets the DS The register value of the port setting register 803 is set to a value corresponding to "x8 port x1, x4 port x2". For example, in the DS port setting register 803, the register value "001b" corresponds to "x16 port x 1", the register value "010b" corresponds to "x8 port x 2", and the register value "011b" corresponds to "x8 port x1, x4 port x2” and the register value “100b” corresponds to “x4 port x4”, the port setting unit 504 sets the register value of the DS port setting register 803 to “011b” in step S115. ”. By setting the register value of the DS port setting register 803 to "011b", as shown in FIG. 11, and a port 65 that accommodates an x4 link consisting of lanes 12-15. Therefore, port 63 and port 11P are connected using link L12 which is an x8 link, port 64 and port 12P are connected using link L13 which is an x4 link, and port 65 and port 13P are connected using It is connected using link L14, which is a x4 link.

Next, in step S117, since the connection pattern corresponding to the setting pattern SP1 acquired in the first step S105 is "CP1", the connection pattern setting unit 506 sets the register value of the connection pattern setting register 804 to "connection pattern CP1” is set to a value corresponding to For example, in the connection pattern setting register 804, the register value "01b" corresponds to "connection pattern CP1", the register value "10b" corresponds to "connection pattern CP2", and the register value "11b" corresponds to "connection pattern CP3". , in step S117, the connection pattern setting unit 506 sets the register value of the connection pattern setting register 804 to "01b". By setting the register value of the connection pattern setting register 804 to "01b", the connection pattern of the PCI bus PB of the PCIe switch 8 becomes the connection pattern CP1 as shown in FIG. By adopting the connection pattern CP1 for the PCI bus PB, three ports 63, 64 and 65 are connected in parallel to a single port 62 using the PCI bus PB as shown in FIG. .

When the connection state between the CPU 5 and the PCIe switch 8 and the connection state between the PCIe switch 8 and the endpoint devices 11D, 12D, and 13D are as shown in FIG. 507 performs a port 61 connectivity test. For example, the connection test executing unit 507 performs a connection test of the port 61 by transmitting and receiving predetermined signals to and from each of the endpoint devices 11D, 12D, and 13D.

Next, in step S<b>121 , the connection state measurement unit 508 actually measures the connection state of the port 61 . For example, the connection state measurement unit 508 actually measures the link width and link speed of the link L11 as the connection state of the port 61 .

Next, in step S123, the success/failure determination unit 509 determines whether or not the measured values of the link width and the link speed of the link L11 match the expected values.

Then, when the measured values of both the link width and the link speed of the link L11 match the expected values (step S123: Yes), in step S125, the success/failure determination unit 509 performs a connection test of the port 61 (that is, setting pattern connection test for SP1) is determined to be successful.

On the other hand, if the measured value of either the link width or the link speed in the link L11 does not match the expected value (step S123: No), in step S127, the success/failure determination unit 509 determines that the connection test of the port 61 has failed. I judge.

As described above, the PCIe card 3 attached to the PCIe slot 7 functions as a connection test device for the computer 2 to test the connection of the CPU port.

Next, in step S129, the pattern acquisition unit 501 determines whether the value of the counter n has reached the value of the number of registered rows N, that is, whether or not the connection test has been completed for all the setting patterns registered in the setting pattern table TA. determine whether or not Here, "N=3" is still "n=1", and among the setting patterns SP1, SP2, and SP3 registered in the setting pattern table TA, the setting patterns SP2 and SP3 are still set. Since the connection test has not been executed (step S129: No), the process proceeds to step S131.

In step S131, the pattern acquisition unit 501 increments the value of the counter n from "1" to "2". After the process of step S131, the process returns to step S105.

Next, in step S105, the pattern acquisition unit 501 refers to the setting pattern table TA stored in the memory 6, and determines the setting registered in the n-th row (that is, the second row here) in the setting pattern table TA. A pattern (that is, setting pattern SP2 here) is acquired, and CPU ports/US ports: 0 to 7, 8 to 15, DS ports: 0 to 7, 8 to 11 are registered in association with setting pattern SP2. , 12-15, connection pattern CP2, and connection mode: virtual switch mode.

Next, in step S107, the pattern determination unit 502 determines which of the setting patterns SP1, SP2, and SP3 the setting pattern acquired in step S105 is. Since the setting pattern acquired in step S105 for the second time is "SP2", the process proceeds from step S107 to step S133.

Next, in step S133, since the connection mode corresponding to the setting pattern SP2 acquired in the second step S105 is "virtual switch mode", the switch mode setting unit 503 sets the register value of the switch mode setting register 801 to " 1b”. By setting the register value of the switch mode setting register 801 to "1b", the PCIe switch 8 operates in the virtual switch mode.

Next, in step S135, the CPU port setting values corresponding to the setting pattern SP2 acquired in the second step S105 are "0 to 7, 8 to 15". Set the register value to "10b". By setting the register value of the port setting register 505 to "10b", as shown in FIG. A port 72 is set up to accommodate an x8 link consisting of . That is, port 51 (FIG. 1) is divided into two ports, port 71, which is an x8 port, and port 72, which is an x8 port.

Next, in step S137, since the US port setting values corresponding to the setting pattern SP2 acquired in the second step S105 are "0 to 7, 8 to 15", the port setting unit 504 sets the US port setting register 802 to register value to "010b". By setting the register value of the US port setting register 802 to "010b", as shown in FIG. A port 74 is configured to accommodate an x8 link configured with 15. That is, port 52 (FIG. 1) is split into two ports, port 73, which is an x8 port, and port 74, which is an x8 port. Therefore, ports 71 and 73 are connected using link L21, which is an x8 link, and ports 72 and 74 are connected using link L22, which is an x8 link.

Next, in step S139, since the DS port setting values corresponding to the setting pattern SP2 obtained in the second step S105 are "0 to 7, 8 to 11, 12 to 15", the port setting unit 504 sets the DS The register value of the port setting register 803 is set to "011b". By setting the register value of the DS port setting register 803 to "011b", as shown in FIG. 11, and a port 77 for accommodating an x4 link consisting of lanes 12 to 15 are set. Therefore, port 75 and port 11P are connected using link L23 which is an x8 link, port 76 and port 12P are connected using link L24 which is an x4 link, and port 77 and port 13P are connected using It is connected using link L25, which is a x4 link.

Next, in step S141, since the connection pattern corresponding to the setting pattern SP2 acquired in the second step S105 is "CP2", the connection pattern setting unit 506 sets the register value of the connection pattern setting register 804 to "10b". set to By setting the register value of the connection pattern setting register 804 to "10b", the connection pattern of the PCI bus PB of the PCIe switch 8 becomes the connection pattern CP2 as shown in FIG. By adopting the connection pattern CP2 for the PCI bus PB, as shown in FIG. ports are connected in parallel.

When the connection state between the CPU 5 and the PCIe switch 8 and the connection state between the PCIe switch 8 and the endpoint devices 11D, 12D, and 13D are as shown in FIG. 507 performs a connection test of ports 71 and 72 by transmitting and receiving predetermined signals to and from endpoint devices 11D, 12D and 13D.

Next, in step S121, the connection state measurement unit 508 actually measures the link width and link speed of link L21 as the connection state of port 71, and the link width and link speed of link L22 as the connection state of port 72. .

Next, in step S123, the success/failure determination unit 509 determines whether the measured values of the link width and the link speed of the link L71 and the measured values of the link width and the link speed of the link L72 match the expected values. do.

Then, when all the measured values of the link width and the link speed of the link L71 and the link width and the link speed of the link L72 match the expected values (step S123: Yes), in step S125, the success/failure determination unit 509 , ports 71 and 72 (that is, the connection test for the setting pattern SP2) is determined to be successful.

On the other hand, if the measured value of either the link width or the link speed of the link L71 or the link width or the link speed of the link L72 does not match the expected value (step S123: No), in step S127, the success/failure determination unit 509 determines that the connection test for ports 71 and 72 has failed.

Next, in step S129, the pattern acquisition unit 501 determines whether the value of the counter n has reached the value of the number of registered rows N, that is, whether or not the connection test has been completed for all the setting patterns registered in the setting pattern table TA. determine whether or not Here, "N=3" is still "n=2", and among the setting patterns SP1, SP2, and SP3 registered in the setting pattern table TA, the connection test for the setting pattern SP3 is still performed. has not been executed (step S129: No), the process proceeds to step S131.

In step S131, the pattern acquisition unit 501 increments the value of the counter n from "2" to "3". After the process of step S131, the process returns to step S105.

Next, in step S105, the pattern acquisition unit 501 refers to the setting pattern table TA stored in the memory 6, and sets the setting registered in the n-th row (that is, the third row here) in the setting pattern table TA. A pattern (that is, setting pattern SP3 here) is obtained, and CPU ports/US ports: 0 to 7, 8 to 11, 12 to 15, DS ports: 0 to 7 are registered in association with setting pattern SP3. , 8-11, 12-15, connection pattern CP3, and connection mode: virtual switch mode.

Next, in step S107, the pattern determination unit 502 determines which of the setting patterns SP1, SP2, and SP3 the setting pattern acquired in step S105 is. Since the setting pattern acquired in step S105 for the third time is "SP3", the process proceeds from step S107 to step S143.

Next, in step S143, since the connection mode corresponding to the setting pattern SP3 acquired in the third step S105 is "virtual switch mode", the switch mode setting unit 503 sets the register value of the switch mode setting register 801 to " 1b”. By setting the register value of the switch mode setting register 801 to "1b", the PCIe switch 8 operates in the virtual switch mode.

Next, in step S145, since the CPU port setting values corresponding to the setting pattern SP3 acquired in the third step S105 are "0 to 7, 8 to 11, 12 to 15", the port setting unit 504 sets the port The register value of the setting register 505 is set to "00b". By setting the register value of the port setting register 505 to "00b", as shown in FIG. and a port 83 accommodating an x4 link composed of lanes 12 to 15 are set. That is, the port 51 (FIG. 1) is divided into three ports, a port 81 that is an x8 port, a port 82 that is an x4 port, and a port 83 that is an x4 port.

Next, in step S147, since the US port setting values corresponding to the setting pattern SP3 acquired in the third step S105 are "0 to 7, 8 to 11, 12 to 15", the port setting unit 504 sets the US The register value of the port setting register 802 is set to "011b". By setting the register value of the US port setting register 802 to "011b", as shown in FIG. 11, and a port 86 that accommodates an x4 link consisting of lanes 12-15. That is, port 52 (FIG. 1) is divided into three ports: port 84, which is an x8 port; port 85, which is an x4 port; and port 86, which is an x4 port. Therefore, ports 81 and 84 are connected using a link L31 which is an x8 link, ports 82 and 85 are connected using a link L32 which is an x4 link, and ports 83 and 86 are connected using a link L32 which is an x4 link. They are connected using link L33, which is a x4 link.

Next, in step S149, since the DS port setting values corresponding to the setting pattern SP3 acquired in the third step S105 are "0 to 7, 8 to 11, 12 to 15", the port setting unit 504 sets the DS The register value of the port setting register 803 is set to "011b". By setting the register value of the DS port setting register 803 to "011b", as shown in FIG. 11, and a port 89 that accommodates an x4 link consisting of lanes 12-15. Therefore, port 87 and port 11P are connected using link L34, which is an x8 link, port 88 and port 12P are connected using link L35, which is an x4 link, and port 89 and port 13P are connected using It is connected using link L36, which is a x4 link.

Next, in step S151, since the connection pattern corresponding to the setting pattern SP3 acquired in the third step S105 is "CP3", the connection pattern setting unit 506 sets the register value of the connection pattern setting register 804 to "11b". set to By setting the register value of the connection pattern setting register 804 to "11b", the connection pattern of the PCI bus PB of the PCIe switch 8 becomes the connection pattern CP3 as shown in FIG. By adopting the connection pattern CP3 for the PCI bus PB, as shown in FIG. port 89 is connected to.

When the connection state between the CPU 5 and the PCIe switch 8 and the connection state between the PCIe switch 8 and the endpoint devices 11D, 12D, and 13D are as shown in FIG. 507 performs a connection test of ports 81, 82, 83 by transmitting and receiving predetermined signals to and from endpoint devices 11D, 12D, 13D.

Next, in step S121, the connection state measurement unit 508 actually measures the link width and link speed of link L31 as the connection state of port 81, and the link width and link speed of link L32 as the connection state of port 82. , as the connection state of the port 83, the link width and link speed of the link L33 are actually measured.

Next, in step S123, the success/failure determination unit 509 determines the measured values of the link width and the link speed of the link L81, the measured values of the link width and the link speed of the link L82, and the measured values of the link width and the link speed of the link L83. Determine whether the measured value matches the expected value.

Then, when all the measured values of the link width and link speed of link L81, the link width and link speed of link L82, and the link width and link speed of link L83 match the expected values (step S123: Yes), In step S125, the success/failure determination unit 509 determines that the connection test for ports 81, 82, and 83 (that is, the connection test for setting pattern SP3) has succeeded.

On the other hand, if any of the measured values of the link width or link speed of link L81, the link width or link speed of link L82, or the link width or link speed of link L83 does not match the expected value (step S123: No ), and in step S127, the success/failure determination unit 509 determines that the connection test of the ports 81, 82, and 83 has failed.

Next, in step S129, the pattern acquisition unit 501 determines whether the value of the counter n has reached the value of the number of registered rows N, that is, whether or not the connection test has been completed for all the setting patterns registered in the setting pattern table TA. determine whether or not Here, "N=3" is "n=3", and the connection test for all the setting patterns SP1, SP2, SP3 registered in the setting pattern table TA is completed (step S129). : Yes), the process ends.

Here, for example, the success/failure determination unit 509 records the success/failure of the connection test in the connection test success/failure table TB (FIG. 7) stored in the memory 6 . For example, if the connection tests for the setting patterns SP1 and SP2 succeed, but the connection test for the setting pattern SP3 fails, the success/failure determination unit 509 determines whether the connection test succeeds or fails as shown in FIG. "1 (success)" is set for SP1 and SP2, and "0 (failure)" is set for the setting pattern SP3.

The first embodiment has been described above.

[Example 2]
In the first embodiment, the case where the PCIe card 3 having the PCIe switch 8 and the endpoint devices 11D, 12D, and 13D functions as a connection test device for the computer 2 to perform a CPU port connection test has been described.

However, the PCIe switch 8 and the endpoint devices 11D, 12D, and 13D do not necessarily have to be mounted on the PCIe card 3 in order for the computer 2 to function as a connection test device for performing a CPU port connection test.

For example, by directly mounting the PCIe switch 8 and the endpoint devices 11D, 12D, and 13D on the carrier board 4 without providing the PCIe slot 7 on the carrier board 4, the PCIe switch 8 and the end point devices can be connected in the same manner as in the first embodiment. The point devices 11D, 12D, and 13D can be made to function as a connection test device for the computer 2 to test the connection of the CPU port.

The second embodiment has been described above.

[Example 3]
All or part of each process in the above description on the computer 2 may be realized by causing the CPU 5 to execute a program corresponding to each process. For example, a program corresponding to each process in the above description may be stored in the memory 6, and the program may be read out from the memory 6 by the CPU 5 and executed. In addition, the program is stored in a program server connected to the computer 2 via an arbitrary network, downloaded from the program server to the computer 2 and executed, or stored in a recording medium readable by the computer 2 and executed. It may be read from a recording medium and executed. Examples of recording media readable by the computer 2 include portable media such as memory cards, USB memories, SD cards, flexible disks, magneto-optical disks, CD-ROMs, DVDs, and Blu-ray (registered trademark) disks. A storage medium is included. A program is a data processing method written in any language and any writing method, and may be in any format such as source code or binary code. In addition, the program is not necessarily limited to a single configuration, but may be configured distributed as multiple modules or multiple libraries, or cooperating with a separate program represented by an OS (Operating System). Also includes those that achieve a function.

Further, the specific form of distributing and integrating the configurations of the CPU 5 and the PCIe switch 8 is not limited to the illustrated one, and all or part of each component can be , can be functionally or physically distributed and integrated in any unit.

The third embodiment has been described above.

As described above, the connection test system of the present disclosure (connection test system 1 of Example 1) has a computer (computer 2 of Example 1) and a test device (PCIe card 3 of Example 1). The computer has a CPU (CPU 5 of Example 1) and a memory (Memory 6 of Example 1). The CPU is connected to the test equipment via multiple lanes. The memory stores a plurality of port setting patterns for a plurality of lanes (setting patterns SP1, SP2, and SP3 of the first embodiment). The test apparatus has a plurality of endpoint devices (endpoint devices 11D, 12D, and 13D of Example 1) and switches (PCIe switch 8 of Example 1). Multiple endpoint devices communicate with the CPU via a bus (PCI bus PB in Example 1) and multiple lanes. The switch has a bus, and the connection pattern of the bus in the switch (connection patterns CP1, CP2, CP3 in the first embodiment) can be switched. The CPU sequentially sets a different number of ports for a plurality of lanes according to each of a plurality of setting patterns, controls the connection pattern, and controls a plurality of end ports via a plurality of lanes and buses in each of the plurality of setting patterns. By communicating with the point device, the connection test of the set port is performed sequentially.

By doing so, the port connection test can be performed for all setting patterns of the ports of the CPU without changing the hardware configuration of the connection test system. Therefore, when performing port connection tests for all setting patterns of ports, there is no need to prepare a separate testing apparatus for each setting pattern, so that the manufacturing cost of the computer to be tested can be reduced.

In addition, the switch has a first connection mode (base mode of the first embodiment) in which a single port set by the CPU and a plurality of endpoint devices are connected by a bus, and a plurality of ports set by the CPU. and a second connection mode (virtual switch mode of the first embodiment) in which a plurality of endpoint devices are connected via a bus. In contrast, the CPU sets a single port for multiple lanes in the first connection mode, while setting multiple ports for multiple lanes in the second connection mode.

By doing so, the CPU and a plurality of endpoint devices can be connected via the bus of the switch for each of all setting patterns of the ports of the CPU.

1 connection test system 2 computer 3 PCIe card 4 carrier board 5 CPU
6 memory 7 PCIe slot 8 PCIe switch

Claims (6)

a computer having a CPU connected to a test apparatus via a plurality of lanes, and a memory storing a plurality of port setting patterns for the plurality of lanes;
the test apparatus comprising: a plurality of endpoint devices communicating with the CPU via a bus and the plurality of lanes; and a switch having the bus and capable of switching a connection pattern of the bus;
and
The CPU sequentially sets different numbers of ports for the plurality of lanes according to each of the plurality of setting patterns, controls the connection pattern, and controls the plurality of lanes and the performing a connection test of the sequentially set ports by communicating with the plurality of endpoint devices via a bus;
Connection test system. The switch has a first connection mode in which a single port set by the CPU and the plurality of endpoint devices are connected by the bus, and a plurality of ports set by the CPU and the plurality of endpoint devices. a second connection mode in which devices are connected by the bus;
The connection test system according to claim 1. The CPU configures the single port for the plurality of lanes in the first connection mode, and configures the plurality of ports for the plurality of lanes in the second connection mode. ,
The connection test system according to claim 2. a CPU connected to a test device via a plurality of lanes;
a memory that stores a plurality of port setting patterns for the plurality of lanes;
and
When connected to the test apparatus having a plurality of endpoint devices communicating with the CPU via a bus and the plurality of lanes, and a switch having the bus and capable of switching the connection pattern of the bus and said CPU sequentially sets different numbers of ports for said plurality of lanes according to each of said plurality of setting patterns, controls said connection pattern, and controls said plurality of lanes in each of said plurality of setting patterns. and performing a connection test of the sequentially set ports by communicating with the plurality of endpoint devices via the bus;
Computer. connectable to a computer having a CPU connected to the device via a plurality of lanes and a memory storing a plurality of port setting patterns for the plurality of lanes;
a plurality of endpoint devices communicating with the CPU via a bus and the plurality of lanes;
a switch having the bus and capable of switching a connection pattern of the bus;
and
When the CPU sequentially sets different numbers of ports for the plurality of lanes according to each of the plurality of setting patterns, the connection pattern is controlled by the CPU, and the plurality of endpoint devices are connected to the plurality of communicating with the CPU via the bus and the plurality of lanes in each of the set patterns of
Connection test equipment. a computer having a CPU connected to a test apparatus via a plurality of lanes, and a memory storing a plurality of port setting patterns for the plurality of lanes;
the test apparatus comprising: a plurality of endpoint devices communicating with the CPU via a bus and the plurality of lanes; and a switch having the bus and capable of switching a connection pattern of the bus;
is connected and
The CPU sequentially sets different numbers of ports for the plurality of lanes according to each of the plurality of setting patterns, controls the connection pattern, and controls the plurality of lanes and the performing a connection test of the sequentially set ports by communicating with the plurality of endpoint devices via a bus;
Connection test method.

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