JP7174247B2 - Semiconductor device manufacturing method - Google Patents

Description

The present application relates to a method of manufacturing a semiconductor device.

Semiconductor devices are manufactured in various forms. is exposed to form a p-pad electrode as a conductive portion between the p-side wiring connected to the light emitting element and the outside (for example, Patent Document 1, etc.).

JP 2012-195321 A

In such a process, not only the semiconductor laminate and the protective film but also part of the p-side wiring are etched, so that the etching surface becomes rough. If the p-pad electrode is formed on such an etched surface, the etched surface of the p-side wiring may become rough, causing the p-pad electrode to become rough, resulting in wire bonding failure of the p-pad electrode.
On the other hand, attempts have been made to prevent the p-side wiring from becoming rough by forming an etching stop layer in a portion between the protective film and the p-side wiring.
However, there is a problem that the process of forming the etching stop layer becomes complicated and the manufacturing process increases.
An object of one embodiment of the present invention is to provide a method of manufacturing a semiconductor device in which the process is simplified while preventing roughening of the p-side wiring due to etching by forming a layer that is difficult to etch.

The present application includes the following inventions.
preparing a semiconductor laminate in which an n-side semiconductor layer, an active layer and a p-side semiconductor layer are laminated in this order;
forming a protective film and a first p-wiring layer in this order from the p-side semiconductor layer side on a part of the upper surface of the p-side semiconductor layer;
forming a second p-wiring layer provided over the upper surface of the p-side semiconductor layer and the upper surface of the first p-wiring layer and electrically connected to the p-side semiconductor layer;
In a part of the upper surface of the p-side semiconductor layer where the protective film, the first p-wiring layer and the second p-wiring layer are not formed, the p-side semiconductor layer and the active layer are removed and the exposing an n-side semiconductor layer from the p-side semiconductor layer and the active layer;
forming an n-wiring layer provided on the upper surface of the n-side semiconductor layer exposed from the p-side semiconductor layer and the active layer and electrically connected to the n-side semiconductor layer;
The semiconductor laminate and the protective film are removed from the n-side semiconductor layer side by etching using an etchant with a lower etching rate for the first p-wiring layer than for the second p-wiring layer. exposing the lower surface of the 1p wiring layer from the protective film;
and forming a p-electrode provided on the lower surface of the first p-wiring layer exposed from the protective film and electrically connected to the first p-wiring layer.

According to the method for manufacturing a semiconductor device according to one embodiment of the present invention, the steps can be simplified, and semiconductor devices can be manufactured with a high yield.

It is a flow chart which shows a manufacturing method of a semiconductor device of a 1st embodiment. 1B is a flow chart showing further optional steps in the method of manufacturing the semiconductor device shown in FIG. 1A; It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor element shown to FIG. 1A. It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor element shown to FIG. 1A. It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor element shown to FIG. 1A. It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor element shown to FIG. 1A. It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor element shown to FIG. 1A. It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor element shown to FIG. 1A. It is a schematic sectional drawing for demonstrating the manufacturing method of the semiconductor element shown to FIG. 1A. 1C is a schematic cross-sectional view for explaining an arbitrary step in the method of manufacturing the semiconductor device shown in FIG. 1B; FIG. 1C is a schematic cross-sectional view for explaining an arbitrary step in the method of manufacturing the semiconductor device shown in FIG. 1B; FIG. 1C is a schematic cross-sectional view for explaining an arbitrary step in the method of manufacturing the semiconductor device shown in FIG. 1B; FIG. 1C is a schematic cross-sectional view for explaining an arbitrary step in the method of manufacturing the semiconductor device shown in FIG. 1B; FIG. 1C is a schematic cross-sectional view for explaining an arbitrary step in the method of manufacturing the semiconductor device shown in FIG. 1B; FIG. 1C is a schematic cross-sectional view for explaining an arbitrary step in the method of manufacturing the semiconductor device shown in FIG. 1B; FIG. 2F is a schematic cross-sectional view showing a modification of the step of exposing the lower surface of the first p-wiring layer 14p shown in FIG. 2F; FIG. 1C is a schematic cross-sectional view for explaining an arbitrary step in the method of manufacturing the semiconductor device shown in FIG. 1B; FIG. FIG. 4 is a schematic plan view of a semiconductor device obtained by the semiconductor device manufacturing method of FIGS. 2 and 3; 4 is a schematic cross-sectional view of a semiconductor device obtained by the method of manufacturing a semiconductor device of FIGS. 2 and 3; FIG.

Since the drawings referred to in the following description schematically show the embodiments, the scales, intervals, positional relationships, etc. of each member may be exaggerated, or some members may be omitted. be. Also, the scale and spacing of each member may not match between the plan view and the cross-sectional view. In addition, in the following description, the same names and symbols basically indicate the same or homogeneous members, and detailed description thereof will be omitted as appropriate. Also, in this specification, terms such as "upper" and "lower" indicate relative positions between components, and are not intended to indicate absolute positions.

As shown in FIG. 1A, a method for manufacturing a semiconductor device according to one embodiment of the present invention includes:
a step of preparing a semiconductor laminate in which an n-side semiconductor layer, an active layer and a p-side semiconductor layer are laminated in this order (S1);
forming a protective film and a first p-wiring layer in this order from the p-side semiconductor layer side on a part of the upper surface of the p-side semiconductor layer (S2);
forming a second p-wiring layer provided over the upper surface of the p-side semiconductor layer and the upper surface of the first p-wiring layer and electrically connected to the p-side semiconductor layer (S3);
removing the p-side semiconductor layer and the active layer in a part of the upper surface of the p-side semiconductor layer where the protective film, the first p-wiring layer and the second p-wiring layer are not formed; exposing the n-side semiconductor layer from the p-side semiconductor layer and the active layer (S4);
forming an n-wiring layer provided on the upper surface of the n-side semiconductor layer exposed from the p-side semiconductor layer and the active layer and electrically connected to the n-side semiconductor layer (S5);
removing the semiconductor laminate and the protective film from the n-side semiconductor layer side by etching using a gas in which the etching rate of the first p-wiring layer is lower than the etching rate of the second p-wiring layer; a step of exposing the lower surface of the 1p wiring layer from the protective film (S6);
forming a p-electrode provided on the lower surface of the first p-wiring layer exposed from the protective film and electrically connected to the first p-wiring layer (S7).
These steps are preferably performed in this order.
By such a manufacturing method, a complicated process is avoided, and a simple method of forming a hard-to-etch layer as the first p-wiring layer in a part between the protective film and the p-side wiring allows the p-side wiring to be formed. It is possible to effectively prevent the wiring from being roughened or the like. As a result, good electrical connection can be achieved between the p-side wiring and the p-electrode connected to the p-side wiring, thereby reducing power consumption and effectively preventing peeling or deterioration of the electrode material. It is possible to simply and easily manufacture a high-quality semiconductor device capable of achieving high reproducibility.

(Preparation of semiconductor laminate 12: S1)
As shown in FIGS. 1A and 2A, the n-side semiconductor layer 12n, the active layer 12a and the p-side semiconductor layer 12p are stacked in this order to form the semiconductor stack 12. As shown in FIGS.
Examples of materials for the semiconductor laminate 12 include various semiconductors such as III-V group compound semiconductors and II-VI group compound semiconductors. Specific examples include nitride-based semiconductor materials such as InXAlYGa1 _- XYN ( _0≤X , 0≤Y, _X +Y≤1), particularly InN, AlN, GaN, InGaN, AlGaN, InGaAlN or the like is preferably used.
Each of the n-side semiconductor layer, the active layer and the p-side semiconductor layer may have a single layer structure or a laminated structure. The active layer preferably has, for example, a multiple quantum well structure or a single quantum well structure. The thickness of each of these layers can be adjusted as appropriate.
Preferably, the semiconductor laminate 12 is formed on the first substrate 11 . The first substrate 11 is a growth substrate for epitaxially growing a semiconductor layer by a method known in the art, such as MOCVD (metal organic chemical vapor deposition). Examples of the first substrate 11 include a sapphire substrate, a Si substrate, a GaN substrate, and the like. The first substrate 11 may have an uneven surface as shown in FIG. 2A. Also, the first substrate 11 may have an off-angle on its surface.

(Formation of protective film 13 and first p-wiring layer 14p: S2)
As shown in FIGS. 1A and 2B, a protective film 13 and a first p-wiring layer 14p are formed in this order on part of the upper surface of the p-side semiconductor layer 12p, that is, in a predetermined pattern.
The protective film 13 can be formed using materials known in the art, such as sputtering and vacuum deposition. For example, oxide films such as Si, Ti, V, Zr, Nb, Hf, Ta, Al, nitride films, oxynitride films, etc., specifically SiO ₂ , ZrO ₂ , SiN, SiON, BN, SiC, SiOC , Al ₂ O ₃ , AlN, AlGaN and the like. The protective film 13 may be composed of a single layer film or laminated film of a single material, or may be composed of laminated films of different materials. Among them, a laminated film of an oxide film and a nitride film is preferable, a laminated film of SiO ₂ and SiN is more preferable, and a laminated film of SiN—SiO ₂ is mentioned from the semiconductor laminated body side. The thickness of the protective film can be set arbitrarily.

The first p-wiring layer 14p can be formed using a material known in the art by sputtering, vacuum deposition, or the like. For example, platinum group metals and alloys containing platinum group elements can be used. The first p-wiring may be a single layer or may have a multi-layer structure. Above all, the first p-wiring layer 14p preferably has a multilayer structure, more preferably a multilayer structure including an Rh layer. For example, multilayer structures such as Ti--Rh, Ti--Rh--Ti, and Rh--Ti from the semiconductor laminate 12 side can be mentioned. The first p-wiring layer 14p constitutes a p-side wiring layer together with a second p-wiring layer, which will be described later. In other words, it functions as a layer that suppresses the occurrence of roughness in the p-wiring layer. The thickness of the first p-wiring layer 14p can be arbitrarily set so as to fulfill the functions described above. For example, the thickness of the first p-wiring layer 14p is 0.1 μm to 0.5 μm.

In the method of patterning the protective film 13 and the first p-wiring layer 14p on the upper surface of the p-side semiconductor layer 12p, a resist mask having a desired opening is formed in advance on the semiconductor laminate, and the protective film 13 is formed on the resist mask. and the first p-wiring layer 14p are formed, and the resist mask is lifted off to form the protective film 13 and the first p-wiring layer 14p in a predetermined pattern on a part of the upper surface of the semiconductor stack 12. By adopting such a method, since the patterning of the protective film 13 and the first p-wiring layer can be performed with the same resist mask, the occurrence of roughening of the p-wiring layer having a different pattern from that of the protective film after the formation of the protective film is suppressed. The manufacturing process can be simplified as compared with the case of forming a layer to hold the film. Moreover, by using this method, it is not necessary to etch the first p-wiring layer 14p, which is a layer that is difficult to etch, so that the protective film 13 and the first p-wiring layer 14p can be easily patterned.

More preferably, the protective film 13 and the first p-wiring layer 14p have the same or substantially the same shape in plan view. By forming the same shape in this way, etching of the second p-wiring layer 15p can be reduced or prevented when the semiconductor stacked body 12 and the protective film 13 are etched in a later step, and the p-side wiring can be roughened. etc. can be effectively prevented from occurring.

(Formation of second p-wiring layer 15: S3)
As shown in FIGS. 1A and 2C, a second p-wiring layer 15p is formed on the obtained p-side semiconductor layer 12p. It is preferable that the second p-wiring layer 15p be a member having relatively high light reflectivity. By using a member having relatively high light reflectivity for the second p-wiring layer 15p, light from the active layer 12a can be efficiently extracted in the direction of the n-side semiconductor layer 12n.
Here, it is difficult to select a member that has both the function of suppressing the occurrence of roughness of the p-wiring layer and the relatively high light reflectivity. Therefore, it is preferable that the first p-wiring layer 14 is a layer that suppresses the above-described roughness of the wiring layer, and the second p-wiring layer 15p is a layer that has relatively high light reflectivity.

The second p-wiring layer 15p can be formed using a material known in the art by sputtering, vacuum deposition, or the like. For example, Ni, Pt, Pd, Rh, Ru, Os, Ir, Ti, Zr, Hf, V, Nb, Ta, Co, Fe, Mn, Mo, Cr, W, La, Cu, Ag, Y, Al, It can be made of a metal such as Si or Au or an alloy thereof. The second p-wiring layer 15p may be formed of either a single layer film or a laminated film of these metals or alloys, and among these, a material containing Ag is preferable. The thickness of the second p-wiring layer 15p can be set arbitrarily, for example, 0.1 μm to 2.0 μm.

The second p-wiring layer 15p is arranged over the upper surface of the p-side semiconductor layer 12p and the upper surface of the first p-wiring layer 14p, and is electrically connected to the p-side semiconductor layer 12p. For this purpose, for example, a resist mask having desired openings is formed above the semiconductor laminate 12, the protective film 13 and the first p-wiring layer 14p, and the second p-wiring layer is formed on the resist mask. It is preferable to form the second p-wiring layer 15p by a mask lift-off method. In addition, the second p-wiring layer 15p is formed on the entire surface of the obtained semiconductor laminate, and the upper surface of the p-side semiconductor layer and the upper surface of the first p-wiring layer are formed by a method such as patterning by photolithography and etching. The second p-wiring layer 15p can be formed in a predetermined pattern covering the entire surface.

(Exposure of n-side semiconductor layer 12n: S4)
As shown in FIGS. 1A and 2D, in the semiconductor laminate 12 having the second p-wiring layer 15p and the like formed thereon, the protective film 13, the first p-wiring layer 14p and the second p-wiring layer are formed on the top surface of the p-side semiconductor layer 12p. In a part of the region where 15p is not formed, the p-side semiconductor layer 12p and the active layer 12a are removed to expose the n-side semiconductor layer 12n from the p-side semiconductor layer 12p and the active layer 12a. As a result, for example, an exposed portion 12x of the n-side semiconductor layer 12n as shown in FIG. 5A, which will be described later, can be formed. Such exposure is achieved by, for example, forming a resist mask having an opening in a part of the upper surface of the p-side semiconductor layer 12p where the protective film 13, the first p-wiring layer 14p and the second p-wiring layer 15p are not formed. Then, using the resist mask, the p-side semiconductor layer 12p and the active layer 12a are etched.

It is preferable to previously form a protective film 16 covering the upper surfaces of the protective film 13, the first p-wiring layer 14p and the second p-wiring layer 15p. The protective film 16 can be made of the same material as the protective film 13 described above. In addition, the protective film 16 can be made of SiN, which can prevent moisture from entering the conductive member from the outside and suitably prevent migration of the first p-wiring layer 14p and the second p-wiring layer 15p. The exposed portion 12x formed by partially removing the semiconductor laminate 12 may have its surface exposed from the p-side semiconductor layer 12p and the active layer 12a, or may be partially exposed in the thickness direction of the n-side semiconductor layer 12n. may be removed by etching together with the p-side semiconductor layer 12p and the active layer 12a and exposed from the p-side semiconductor layer 12p and the active layer 12a.

Although the planar shape of the exposed portion 12x is not particularly limited, in the case of forming the semiconductor element shown in FIG. 5A, a plurality of exposed portions 12x are arranged in one semiconductor element. Shapes such as polygonal, circular or elliptical may be mentioned. The total area of the exposed portions 12x in plan view can be appropriately adjusted depending on the size of the semiconductor element. mentioned. Also, the diameter or one side of each exposed portion 12x is about 5.0 μm to 30.0 μm. It is preferable that the plurality of exposed n-side semiconductor layers 12n have substantially the same size and substantially the same shape. As a result, variations in the current density distribution of the semiconductor device can be suppressed.

(Formation of n wiring layer 18n: S5)
As shown in FIGS. 1A and 2E, an n wiring layer 18n electrically connected to the n-side semiconductor layer 12n is formed on the n-side semiconductor layer 12n exposed from the p-side semiconductor layer 12p and the active layer 12a.
For the n-wiring layer 18n, materials similar to those exemplified for the second p-wiring layer 15p can be used. For example, it can be made of a material containing a metal such as Ti, Al, Si, Cu, or an alloy thereof. The n-wiring layer 18n may be formed of either a single layer film or a laminated film of these metals or alloys. The thickness of the n-wiring layer 18n can be set arbitrarily, for example, 0.3 μm to 1.0 μm.

A plurality of n-side semiconductor layers 12n exposed from the p-side semiconductor layer 12p and the active layer 12a are formed in a predetermined region of the semiconductor laminate in plan view. In addition, the p-side semiconductor layer 12p and the active layer 12a are exposed from the upper surface of the semiconductor stacked body 12n on the side surface of the recess formed by removing the p-side semiconductor layer 12p and the active layer 12a. Therefore, in order to prevent the n wiring layer 18n from contacting the p-side semiconductor layer 12p and the active layer 12a exposed from the upper surface of the semiconductor multilayer body 12n, an insulating film is formed above the semiconductor multilayer body 12 before the n wiring layer 18n is formed. 17 is preferred. The insulating film 17 has an opening only on the n-side semiconductor layer 12n exposed from the p-side semiconductor layer 12p and the active layer 12a, and an n-wiring layer 18n electrically conducting the exposed n-side semiconductor layer 12n through this opening. is preferably formed. The insulating film 17 can be formed using materials similar to those exemplified for the protective films 13 and 16 described above.

The planar shape of the n-wiring layer 18n is not particularly limited as long as it contacts the p-side semiconductor layer 12p and the n-side semiconductor layer 12n exposed from the active layer 12a. , there are a plurality of n-side semiconductor layers 12n exposed from the p-side semiconductor layer 12p and the active layer 12a. Specifically, it may be a quadrangle surrounding and overlapping a region in which a plurality of exposed portions 12x are formed, or a shape similar thereto. The planar shape of the n-wiring layer 18 may be, for example, one with rounded corners.

(Exposed lower surface of first p-wiring layer 14p: S6)
When the semiconductor laminate 12 is formed on the first substrate 11, after removing the first substrate 11 from the semiconductor laminate 12, the first p wiring layer 14p is formed as shown in FIGS. 1A and 2F. In a part of the region where the first p-wiring layer 14p is formed, the semiconductor stacked body 12 and the protective film 13 are removed from the side opposite to the first p-wiring layer 14p to expose the lower surface of the first p-wiring layer 14p from the semiconductor stacked body 12 and the protective film 13. Let

The semiconductor stack 12 and protective film 13 can be removed using methods known in the art. Examples include photolithography and etching processes. Etching may be either dry etching or wet etching. Among them, dry etching is preferable.

The n-side semiconductor layer 12n, the active layer 12a, the p-side semiconductor layer 12p, and the protective film 13 may be etched using one kind of mask prepared in one photolithography process, or may be etched using different masks for each or part of them. may be formed and etched using the mask. Also, the n-side semiconductor layer 12n, the active layer 12a, the p-side semiconductor layer 12p, and the protective film 13 may be etched using the same etchant. Etching using a different etchant is preferred. For example, the etching rate for the first p-wiring layer 14p is relatively low so as to reliably stop the etching at the lower surface of the first p-wiring layer 14p. Etching using a highly effective etchant is preferred. In order to prevent the etchant from acting on layers other than the layer to be etched during etching, the etching rate of the first p-wiring layer 14p is set to be lower than the etching rate of the second p-wiring layer 15p. is more preferable. By using such an etchant, the first p-wiring layer 14p functions as a layer that suppresses the occurrence of roughening of the p-wiring layer as described above. Then, the semiconductor laminate 12 is sequentially removed, and the protective film 13 can be further removed to expose the lower surface of the first p-wiring layer 14p. By suppressing the occurrence of surface roughness of the p-wiring layer, it is possible to improve the contact between the p-electrode 20p described later and the p-wiring layer. Furthermore, since the surface of the p-wiring layer is prevented from being roughened, the p-electrode 20p is less likely to be roughened. can be good.

For example, when the n-side semiconductor layer 12n, the active layer 12a, and the p-side semiconductor layer 12p are formed of GaN-based semiconductor layers, examples of the etchant include gas containing chlorine gas. Further, when the protective film 13 is formed of a laminated film of SiN--SiO ₂ , the etchant may be gas containing fluorine gas. Each of these etchants has a higher etching rate for the semiconductor laminate 12 or the protective film 13 than, for example, the etching rate for the first p-wiring layer 14p formed of a Ti/Rh/Ti laminated film. The difference between these etching rates is 1500 Å/min to 2000 Å/min.

(Formation of p-electrode 20p: S7)
As shown in FIGS. 1A and 2G, a p-electrode 20p is formed that is electrically connected to the exposed first p-wiring layer 14p on the bottom surface.
The p-electrode 20p can be formed of, for example, the conductive material exemplified for the first p-wiring layer 14p, the second p-wiring layer 15p, and the like. The p-electrode 20p can be formed using a method known in the art, such as a lift-off method, photolithography and etching process. Among them, the p-electrode 20p preferably includes, for example, an Au layer, more preferably formed of a conductive material with the Au layer disposed on the outermost surface, and more preferably a Ti/Pt/Au layer. The thickness of the p-electrode 20p is, for example, 0.1 μm to 1.0 μm.

Before forming the p-electrode 20p, the lower surface of the semiconductor layer 12n exposed by removing the substrate 11 and the side surface of the semiconductor laminate 12 exposed by exposing the first p-wiring layer 14p are insulated. It is preferred to form membrane 19 . In addition, it is preferable that unevenness is formed on the lower surface of the semiconductor layer 12n described above, as shown in FIG. 2G. The insulating film 19 has an opening only on part of the first p-wiring layer 14p. A p-electrode 20p is formed in the opening of the insulating film 19 for electrically conducting the exposed first p-wiring layer 14p. For the insulating film 19, materials similar to those exemplified for the protective film and the insulating film can be used. Details of the fine unevenness formed on the surface of the n-side semiconductor layer 12n shown in FIG. 2G will be described later.

The planar shape of the p-electrode 20p is not particularly limited as long as it is in contact with the first p-wiring layer 14p. Normally, when forming the semiconductor element shown in FIG. It is preferable to place the Specifically, the p-electrode 20p is adjacent to the semiconductor laminate 12 and has a rectangular shape or a shape similar thereto.

(Manufacturing process of other semiconductor elements)
In the above-described method for manufacturing a semiconductor device, in addition to S1 to S7, when the above-described semiconductor laminate is formed on a first substrate, a step of bonding it to a second substrate, a step of removing the first substrate, and various insulating films are performed. And/or a step of forming a conductive film may be included. Specifically, in the above-described method for manufacturing a semiconductor element, it is preferable to further include a step of bonding the semiconductor element to the second substrate in order to form the bonded substrate structure. It is more preferable to include a step of bonding with the second substrate, a step of removing the first substrate, and the like.

(Bonding to the second substrate 23, etc.)
As shown in FIGS. 1B and 3A to 3E, the step of bonding to the second substrate includes a step of forming the conductive material layer 21 (S5-1) and a step of flattening the upper surface of the conductive material layer 21 ( S5-2), a step of preparing a second substrate 23 (S5-3), and a step of bonding the semiconductor laminate 12 and the second substrate 23 together (S5-4). When formed on one substrate 11, the step of removing the first substrate 11 (S5-5) may be included, and at any stage, the step of forming a metal layer on the back surface of the second substrate side ( S7-1), a step of singulating the obtained semiconductor laminate 12 into semiconductor elements (S7-2), and the like may be further included.

(Formation of conductive material layer 21: S5-1)
As shown in FIGS. 1B and 3A, a conductive material layer 21 is formed on the semiconductor laminate 12 on which the n-wiring layer 18n is formed so as to be connected to the n-wiring layer 18n.
In this case, since the semiconductor element is usually formed by being separated into a predetermined planar shape, for example, the conductive material layer 21 is formed into individual pieces that separate the semiconductor stacked body 12 for each semiconductor element in plan view. It is preferable to form it so as not to be provided on the planned line. As a result, it is possible to easily separate the semiconductor elements into individual pieces, which will be described later. For this purpose, the conductive material layer 21 is formed on the n-wiring layer 18n using a mask having a predetermined shape or using a resist mask having openings at predetermined portions, and patterned by patterning or lift-off. is preferred.

Examples of the material of the conductive material layer 21 include single-layer films or laminated films such as Al, Cu, W, Ti, Mo, Ta, and metals or alloys thereof.
When the conductive material layer 21 is bonded to a second substrate, which will be described later, the stress caused by the difference in thermal expansion coefficient between the semiconductor laminate 12 and the bonding member laminated on the second substrate causes the bonding member, etc. It also plays a role in reducing warpage. A material used as a bonding member usually has a larger thermal expansion coefficient than a semiconductor material generally used as the semiconductor laminate 12 . Therefore, it is preferable to use a material having a smaller thermal expansion coefficient than the conductive material layer 21 and the bonding member in order to reduce the internal stress generated in the semiconductor element when the bonding member is cooled and shrinks after being heated. For example, the conductive material layer 21 can be made of an AlCu alloy. The conductive material layer 21 can be formed by known methods such as sputtering and vapor deposition. The thickness of the conductive material layer 21 is, for example, about 10.0 μm to 20.0 μm.

(Planarization of conductive material layer 21: S5-2)
After forming the conductive material layer 21, it is preferable to planarize its surface as shown in FIGS. 1B and 3B. As a result, it is possible to bond with good adhesion to the second substrate, which will be described later.
The planarization of the conductive material layer 21 can be performed using a method known in the art, such as CMP. In order to planarize the conductive material layer 21, for example, about 10% to 90% of the thickness of the conductive material layer 21 is removed. For example, it is preferable to remove the conductive material layer 21 so as to leave a thickness of about 1.0 μm.

After planarizing the surface of the conductive material layer 21, as shown in FIG. 3C, it is preferable to form a bonding layer 22 on the surface for bonding with a second substrate, which will be described later. The bonding layer 22 can be formed using, for example, a metal material with a relatively low melting point such as TiNiSn, NiSn, AuSn, PbSn, Au, AuGe, AuZn. Alternatively, as the bonding layer 22, an anisotropic conductive adhesive in which conductive particles are contained in a thermosetting resin may be used. The thickness of the bonding layer 22 is, for example, 1.0 μm to 5.0 μm.

(Preparation of second substrate 23: S5-3)
As shown in FIGS. 1B and 3D, a second substrate 23 is prepared for bonding to the obtained semiconductor laminate 12 .
Examples of the second substrate 23 include conductive substrates made of Si, Mo, CuW, or the like. Among them, a Si substrate is preferable from the viewpoint of low resistivity, low cost, and easy chip formation. The thickness of the second substrate 23 is 50 μm to 500 μm, preferably 100 μm to 300 μm, from the viewpoints of heat dissipation, mechanical strength, miniaturization of the semiconductor element, and the like.

It is preferable to form the metal layer 24 and the bonding layer 25 in this order on the second substrate 23 . A layer containing Pt is preferable as the metal layer 24 . The thickness of the metal layer 24 is, for example, 0.05 μm to 0.25 μm. Also, the bonding layer 25 can be formed using the aforementioned metal material having a relatively low melting point or the anisotropic conductive adhesive containing conductive particles in the thermosetting resin. The thickness of the bonding layer 25 is, for example, 1.0 μm to 5.0 μm. By forming the metal layer 24 between the second substrate 23 and the bonding layer 25 in this manner, the adhesion between the second substrate 23 and the bonding layer 25 can be further improved. These metal layer 24 and bonding layer 25 can be formed by sputtering, vapor deposition, or a combination thereof.

(Lamination: S5-4)
As shown in FIGS. 1B and 3E, the second substrate 23 and the semiconductor laminate 12 are bonded together with bonding layers 22 and 25 interposed therebetween. As a method for bonding the bonding layers 22 and 25, for example, a method of pressing the bonding layers 22 and 25 against each other while the semiconductor laminate 12 and the second substrate 23 are heated, an atomic diffusion bonding method, a hydroxyl group A room temperature bonding method such as a bonding method and a surface activation bonding method can be used. When the second substrate 23 and the semiconductor laminate 12 are bonded together by heating, the heating temperature, time, and the like can be appropriately set depending on the bonding member, the conductive material, and the like used. Thereby, the bonding layers 22 and 25 are integrally or substantially integrally bonded, and the second substrate 23 can be integrally bonded onto the semiconductor laminate 12 .

(Removal of first substrate 11: S5-5)
As shown in FIGS. 1B and 3F, the first substrate 11 is removed. The removal of the first substrate may be performed either before or after bonding the second substrate 23 and the semiconductor laminate 12 together. After that, it is preferable to remove the first substrate 11 from the semiconductor stack 12 as shown in FIGS. 1B and 3F. The first substrate 11 can be removed by separating it from the semiconductor laminate 12 by a laser lift-off method, grinding, etching, or the like. Further, as shown in FIG. 3F, after removing the first substrate 11, the exposed surface of the n-side semiconductor layer 12n may be polished by CMP processing or the like to planarize the surface of the n-side semiconductor layer 12n. preferable.
Note that the step of exposing the lower surface of the first p wiring layer 14p in S6 shown in FIG. This is preferably performed after performing a series of formation and bonding steps of the second substrate represented by 1 to S5-5 (see FIG. 4A).

(Formation of metal layer 26: S7-1)
As shown in FIGS. 1B and 4B, after removing the first substrate 11 and polishing the exposed surface of the n-side semiconductor layer 12n, the second substrate 23 on the side opposite to the semiconductor laminate 12 side is subjected to a polishing process. A metal layer 26 is preferably formed on the surface. Such a metal layer 26 can be formed using materials similar to those exemplified for the first p-wiring layer, second p-wiring layer, n-electrode, and the like. Among others, the pad electrode preferably contains Au, Al, or a platinum group element metal suitable for wire bonding or the like, and is more preferably formed of a layer containing Pt or a Pt layer. In this case, the thickness of the metal layer 26 is, for example, 500 Å to 5000 Å.
Moreover, it is preferable to grind the surface of the second substrate 23 before forming the metal layer 26 . By grinding the surface of the second substrate 23, it is possible to easily divide into individual semiconductor elements, which will be described later.

Before or after forming the metal layer 26, it is preferable to form fine unevenness on the surface of the n-side semiconductor layer 12n. By forming such fine unevenness, the surface area of the n-side semiconductor layer 12n on the side of the light extraction surface is increased, and the light extraction efficiency can be increased. Such fine unevenness may be formed by wet etching using, for example, a tetramethylammonium hydroxide (TMAH) solution.

(Separation into semiconductor devices: S7-2)
Thereafter, as shown in FIG. 1B, the obtained semiconductor laminate 12 is singulated into individual semiconductor elements. Singulation can be performed by a dicing method such as blade dicing or laser dicing. A groove or the like may be formed in the semiconductor laminate 12, the second substrate 23, or the like before singulation, and the groove or the like may be used for singulation. The groove can be formed by etching the semiconductor laminate 12 or the like using a resist mask or by laser scribing.
In particular, as described above, when the conductive material layer 21 is not formed on the intended singulation line of the semiconductor element, the conductive material layer 21 does not need to be cut, and the semiconductor element 1 can be singulated. can be easily done. The singulation can be performed into a shape of the semiconductor element in a plan view, for example, a square, a rectangle, a polygon such as a hexagon, a circle, or the like.
By performing the above steps, the semiconductor device shown in FIGS. 5A and 5B can be manufactured.
For example, the length of the semiconductor element in the longitudinal direction is 500 μm to 2500 μm, and the length in the lateral direction is 400 μm to 2000 μm.

Such a manufacturing method is a simple method of forming a layer that is difficult to etch as the first p-wiring layer in a part between the protective film and the p-side wiring. can be effectively prevented. As a result, good electrical connection can be achieved between the p-side wiring and the p-electrode connected to the p-side wiring, thereby reducing power consumption and effectively preventing peeling or deterioration of the electrode material. It is possible to simply and easily manufacture a high-quality semiconductor device capable of achieving high reproducibility.

1 semiconductor element 11 first substrate 12 semiconductor laminate 12a active layer 12n n-side semiconductor layer 12p p-side semiconductor layer 12x exposed portions 13, 16 protective film 14p first p-wiring layer 15p second p-wiring layer 17, 19 insulating film 18n n-wiring Layer 20p p-electrode 21 conductive material layers 22, 25 bonding layer 23 second substrate 24, 26 metal layer

Claims (6)

preparing a semiconductor laminate in which an n-side semiconductor layer, an active layer and a p-side semiconductor layer are laminated in this order;
forming a protective film and a first p-wiring layer in this order from the p-side semiconductor layer side on a part of the upper surface of the p-side semiconductor layer;
forming a second p-wiring layer provided over the upper surface of the p-side semiconductor layer and the upper surface of the first p-wiring layer and electrically connected to the p-side semiconductor layer;
In a part of the upper surface of the p-side semiconductor layer where the protective film, the first p-wiring layer and the second p-wiring layer are not formed, the p-side semiconductor layer and the active layer are removed and the exposing an n-side semiconductor layer from the p-side semiconductor layer and the active layer;
forming an n-wiring layer provided on the upper surface of the n-side semiconductor layer exposed from the p-side semiconductor layer and the active layer and electrically connected to the n-side semiconductor layer;
The semiconductor laminate and the protective film are removed from the n-side semiconductor layer side by etching using an etchant with a lower etching rate for the first p-wiring layer than for the second p-wiring layer. exposing the lower surface of the 1p wiring layer from the protective film;
and forming a p-electrode provided on the lower surface of the first p-wiring layer exposed from the protective film and electrically connected to the first p-wiring layer. forming the semiconductor stack on a first substrate;
forming a conductive material layer above the n-wiring layer;
planarizing a top surface of the conductive material layer;
preparing a second substrate on which a metal layer is formed;
a step of making the conductive material layer and the metal layer face each other and bonding the first substrate and the second substrate together;
2. The method of manufacturing a semiconductor device according to claim 1, further comprising removing the first substrate from the semiconductor stack. 3. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of exposing the n-side semiconductor layer, the n-side semiconductor layer is exposed at a plurality of locations. 4. The method of manufacturing a semiconductor device according to claim 1, wherein said first p-wiring layer contains Rh. 2. In the step of forming the protective film and the first p-wiring layer in this order, the protective film on the upper surface of the p-side semiconductor layer and the first p-wiring layer are formed by lifting off a resist mask. 5. A method for manufacturing a semiconductor device according to any one of 1 to 4. 6. The method of manufacturing a semiconductor device according to claim 1, wherein said etching is performed by dry etching.

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