JP7176676B2 - detector - Google Patents

Description

The present invention relates to a detection device such as a humidity detection device.

2. Description of the Related Art As a detection device, for example, a humidity detection device is of a capacitance type that uses, as a dielectric, a moisture-sensitive film formed of a polymer material whose dielectric constant changes according to the amount of absorbed moisture. In this capacitance-type humidity detector, a humidity-sensitive film is arranged between electrodes, and humidity (relative humidity) is obtained by measuring the capacitance between the electrodes (see, for example, Patent Document 1).

In the humidity detection device described in Patent Document 1, a sensor unit whose capacitance changes according to humidity and a circuit unit that performs processing such as converting electric charges output from the sensor unit into voltage are arranged side by side on a substrate. ing.

As a circuit unit used in such a capacitance-type humidity detection device, a configuration is known in which a charge output from a sensor unit is converted into a voltage by a charge amplifier (see, for example, Patent Document 2). In addition to the charge amplifier, this circuit section is provided with a drive circuit and the like for driving the sensor section with a square-wave AC drive signal.

Patent No. 5547296 Patent No. 6228865

In the humidity detection device described in Patent Document 1, the sensor section and the circuit section are arranged side by side. A stack structure in which the sensor unit is mounted is assumed.

When the sensor section and the circuit section are arranged side by side, the influence of noise transmitted between them is small because they are separated from each other. are close to each other, there is concern about the influence of noise.

In particular, as described above, when the sensor section is driven by the AC drive signal from the circuit section, large noise can occur in both the sensor section and the circuit section, so it is desirable to improve noise immunity. .

An object of the present invention is to improve noise immunity.

The disclosed technology includes a semiconductor substrate, a detection unit provided above the semiconductor substrate for outputting a signal corresponding to a physical quantity, and a sensor that alternately inverts the polarities in the semiconductor substrate below the detection unit. a noise suppressing section composed of a plurality of laminated semiconductor layers , wherein the detecting section includes a lower electrode formed above the semiconductor substrate; a moisture sensitive film formed above the lower electrode; an upper electrode formed on the humidity-sensitive film; a lower electrode; a reference electrode disposed between the noise suppressor and the lower electrode; and a reference capacitor having an insulating film interposed between a lower electrode and a detecting device for outputting a signal corresponding to humidity .

According to the present invention, noise immunity can be improved.

It is a figure which illustrates schematic structure of the humidity detection apparatus which concerns on 1st Embodiment. FIG. 2 is a cross-sectional view schematically showing a cross section taken along line AA in FIG. 1; FIG. 3 is a plan view of the humidity detection device with the mold resin removed; It is a schematic plan view showing the configuration of a sensor chip. 1 is a circuit diagram illustrating the configuration of an ESD protection circuit; FIG. FIG. 3 is a diagram illustrating a layer structure of an NMOS transistor that constitutes an ESD protection circuit; 4 is a circuit diagram illustrating the configuration of a humidity detection unit; FIG. 4 is a circuit diagram illustrating the configuration of a temperature detection unit; FIG. It is a schematic sectional view for explaining the element structure of the sensor chip. 4 is a plan view illustrating shapes of a lower electrode and an upper electrode; FIG. FIG. 3 is a plan view illustrating the shape of an n-type diffusion layer and a guard ring that constitute the heating section; It is a figure which illustrates the equivalent circuit of a noise suppression part. 1 is a diagram illustrating the configuration of an ASIC chip; FIG. It is a figure which illustrates the structure of a humidity measurement process part. 4 is a timing chart for explaining a measurement sequence;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In each drawing, the same components are denoted by the same reference numerals, and redundant description may be omitted. In addition, in the present disclosure, humidity when simply described as humidity means relative humidity.

<First embodiment>
[Outline configuration]
A configuration of the humidity detection device 10 according to the first embodiment of the present invention will be described.

FIG. 1 is a diagram illustrating a schematic configuration of a humidity detection device 10 according to the first embodiment. FIG. 1A is a top plan view of the humidity detection device 10. FIG. FIG. 1B is a bottom view of the humidity detection device 10 viewed from below. FIG. 1(C) is a side view of the humidity detection device 10 viewed from the lateral direction. FIG. 2 is a cross-sectional view schematically showing a cross section taken along line AA in FIG. 1(A).

The humidity detection device 10 has a substantially rectangular planar shape, and one of two pairs of opposing sides is parallel to the X direction and the other is parallel to the Y direction. The X direction and the Y direction are orthogonal to each other. Also, the humidity detection device 10 has a thickness in the Z direction perpendicular to the X and Y directions. The planar shape of the humidity detection device 10 is not limited to a rectangular shape, and may be circular, elliptical, polygonal, or the like.

The humidity detection device 10 includes a sensor chip 20 as a first semiconductor chip, an ASIC (Application Specific Integrated Circuit) chip 30 as a second semiconductor chip, a mold resin 40 as a sealing member, and a plurality of lead terminals 41. have

The sensor chip 20 is laminated on the ASIC chip 30 via a first DAF (Die Attach Film) 42 . That is, the sensor chip 20 and the ASIC chip 30 have a stack structure.

The sensor chip 20 and the ASIC chip 30 are electrically connected by a plurality of first bonding wires 43 . The ASIC chip 30 and the plurality of lead terminals 41 are electrically connected by a plurality of second bonding wires 44 .

The sensor chip 20, the ASIC chip 30, the plurality of first bonding wires 43, the plurality of second bonding wires 44, and the plurality of lead terminals 41 laminated in this manner are sealed with the mold resin 40 and packaged. ing. This package method is called a PLP (Plating Lead Package) method.

On the bottom surface of the ASIC chip 30, the second DAF 45 used for packaging by the PLP method remains, although the details will be described later. The second DAF 45 has a role of insulating the bottom surface of the ASIC chip 30 . A second DAF 45 and a plurality of lead terminals 41 are exposed on the lower surface of the humidity detection device 10 .

Each lead terminal 41 is made of nickel or copper. The first DAF 42 and the second DAF 45 are each made of an insulating material such as a mixture of resin and silica. The molding resin 40 is a black resin having a light shielding property such as an epoxy resin containing a mixture of carbon black, silica, or the like.

An opening 50 is formed on the upper surface side of the humidity detection device 10 to expose a part of the sensor chip 20 from the mold resin 40 . The opening 50 has, for example, a tapered wall, and the opening area becomes smaller downward. The lowermost portion of the opening 50 that actually exposes the sensor chip 20 is called an effective opening 51 .

When forming the opening 50 , the mold is pressed against the sensor chip 20 and sealed with the molding resin 40 . The pressing force exerted by the mold on the sensor chip 20 and the ASIC chip 30 at this time may cause damage such as chip cracking. In order to prevent this breakage, the thickness T1 of the sensor chip 20 and the thickness T2 of the ASIC chip 30 are each preferably 200 μm or more, for example.

FIG. 3 is a plan view of the humidity detection device 10 with the mold resin 40 removed. As shown in FIG. 3, the sensor chip 20 and the ASIC chip 30 each have a substantially rectangular planar shape and have two sides parallel to the X direction and two sides parallel to the Y direction. The sensor chip 20 is smaller than the ASIC chip 30 and is stacked on the surface of the ASIC chip 30 with the first DAF 42 interposed therebetween.

The sensor chip 20 is provided with a humidity detection section 21 , a temperature detection section 22 and a heating section 23 in a region exposed by the effective opening 51 . The heating portion 23 is formed on the lower surface side of the humidity detection portion 21 so as to cover the formation area of the humidity detection portion 21 . That is, the area of the heating section 23 is larger than that of the humidity detection section 21 . In this manner, the mold resin 40 as a sealing member seals the sensor chip 20 and the like while exposing the humidity detection section 21 and the temperature detection section 22 .

A plurality of bonding pads (hereinafter simply referred to as pads) 24 are formed at the end of the sensor chip 20 . Six pads 24 are formed in this embodiment. The pads 24 are made of, for example, aluminum or an aluminum silicon alloy (AlSi).

The ASIC chip 30 is a semiconductor chip for signal processing and control, and includes a humidity measurement processing unit 31, a temperature measurement processing unit 32, a heating control unit 33, and a failure determination unit 34 (all of which are shown in FIG. 13). It is

A plurality of first pads 35 and a plurality of second pads 36 are provided in a region of the surface of the ASIC chip 30 that is not covered with the sensor chip 20 . The first pads 35 and the second pads 36 are made of, for example, aluminum or an aluminum silicon alloy (AlSi).

The first pads 35 are connected to corresponding pads 24 of the sensor chip 20 via first bonding wires 43 . The second pads 36 are connected to corresponding lead terminals 41 via second bonding wires 44 . The lead terminals 41 are arranged around the ASIC chip 30 .

During manufacturing, the mounting position of the ASIC chip 30 is determined with the lead terminal 41 as a reference. The mounting position of the sensor chip 20 on the ASIC chip 30 is determined based on either the position of the ASIC chip 30 or the lead terminals 41 . The opening 50 is formed by a transfer molding method or the like using a mold, and the position of this mold is determined with the lead terminal 41 as a reference.

Reference numeral 25 shown in FIG. 3 represents a formation allowable region for the humidity detection section 21 and the temperature detection section 22 on the sensor chip 20 . The formation allowable region 25 is formed in the opening 50 so as to be reliably exposed from the opening 50 even when the largest misalignment occurs between the ASIC chip 30, the sensor chip 20, and the mold during mounting. It is set within the formation area of 50. If the humidity detector 21 and the temperature detector 22 are formed within the formation permissible region 25, they are reliably exposed from the opening 50 regardless of the positional deviation.

[Configuration of sensor chip]
Next, the configuration of the sensor chip 20 will be described.

FIG. 4 is a schematic plan view showing the configuration of the sensor chip 20. As shown in FIG. The aforementioned pad 24 is a terminal used for external voltage application and potential detection. In FIG. 4, the plurality of pads 24 shown in FIG. 3 are shown separately from the pads 24a-24f. The pads 24a to 24f are simply referred to as pads 24 when there is no need to distinguish between them.

The pad 24a functions as a ground electrode terminal (GND) grounded to ground potential. The pad 24a is electrically connected to each part such as the temperature detection part 22 and the heating part 23 through wiring and a substrate. Pad 24a is electrically connected to p-type semiconductor substrate 70 (see FIG. 9) that constitutes sensor chip 20. As shown in FIG.

Pad 24 b is a signal terminal (TS) electrically connected to lower electrode 83 of humidity detector 21 . Pad 24c is a first drive terminal (T1) electrically connected to upper electrode 84 of humidity detector 21 . The pad 24d is a second drive terminal (T2) electrically connected to the reference electrode 82 (see FIG. 9) of the humidity detector 21. As shown in FIG.

The pad 24 e is a temperature detection terminal (TMP) electrically connected to the temperature detection section 22 . The pad 24e is used to acquire a temperature detection signal. The pad 24 f is a heating terminal (HT) electrically connected to the heating section 23 . Pad 24f is used to supply a drive voltage for driving heating unit 23 .

An electrostatic discharge (ESD) protection circuit 60 is connected to each of the pads 24b to 24f other than the pad 24a. Each ESD protection circuit 60 is connected between each of the pads 24b to 24f as input terminals or output terminals and the pad 24a as a ground electrode terminal. In this embodiment, the ESD protection circuit 60 is composed of one diode 61 . The diode 61 has an anode connected to the pad 24a and a cathode connected to one of the pads 24b to 24f.

The ESD protection circuit 60 is preferably arranged near the pads 24b-24f so as to be as far away from the effective opening 51 as possible. Since the ESD protection circuit 60 is covered with the mold resin 40, unnecessary charge generation due to the photoelectric effect does not occur.

[Configuration of ESD protection circuit]
Next, the configuration of the ESD protection circuit 60 will be described.

FIG. 5 is a circuit diagram illustrating the configuration of the ESD protection circuit 60. As shown in FIG. As shown in FIG. 5, the diode 61 forming the ESD protection circuit 60 is formed of, for example, an N-channel MOS (Metal-Oxide-Semiconductor) transistor (hereinafter referred to as an NMOS transistor). Specifically, the diode 61 is formed by short-circuiting the source, gate, and back gate of an NMOS transistor (so-called diode connection). This short circuit functions as an anode. The drain of this NMOS transistor functions as the cathode.

FIG. 6 is a diagram illustrating the layer structure of the NMOS transistor that constitutes the ESD protection circuit 60. As shown in FIG. This NMOS transistor has two n-type diffusion layers 71 and 72 formed on the surface layer of a p-type semiconductor substrate 70 for constituting the sensor chip 20 , a contact layer 73 and a gate electrode 74 . A gate electrode 74 is formed on the surface of the p-type semiconductor substrate 70 with a gate insulating film 75 interposed therebetween. A gate electrode 74 is arranged between the two n-type diffusion layers 71 and 72 .

For example, the n-type diffusion layer 71 functions as a source and the n-type diffusion layer 72 functions as a drain. Contact layer 73 is a low-resistance layer (p-type diffusion layer) for electrical connection with p-type semiconductor substrate 70 as a back gate. The n-type diffusion layer 71, the gate electrode 74 and the contact layer 73 are commonly connected and short-circuited. This short-circuit portion functions as an anode, and the n-type diffusion layer 72 functions as a cathode.

The p-type semiconductor substrate 70 is, for example, a p-type silicon substrate. The gate electrode 74 is made of metal or polycrystalline silicon (polysilicon). The gate insulating film 75 is made of, for example, an oxide film such as silicon dioxide.

[Configuration of Humidity Detector]
Next, the configuration of the humidity detector 21 will be described.

FIG. 7 is a circuit diagram illustrating the configuration of the humidity detection section 21. As shown in FIG. As shown in FIG. 7 , the humidity detection section 21 has a humidity detection capacitor 80 and a reference capacitor 81 .

One electrode (lower electrode 83) of the humidity detector 21 is connected to a pad 24b as a signal terminal TS. The other electrode (upper electrode 84) of the humidity detector 21 is connected to the pad 24c as the first drive terminal T1. One electrode of the reference capacitor 81 is shared with one electrode (lower electrode 83 ) of the humidity detection section 21 . The other electrode (reference electrode 82) of the reference capacitor 81 is connected to the pad 24d as the second drive terminal T2.

The humidity detection capacitor 80 is provided with a humidity sensitive film 86, which will be described later, between electrodes. The humidity sensitive film 86 is made of a polymeric material such as polyimide that absorbs moisture in the air and changes its dielectric constant according to the amount of moisture absorbed. Therefore, the capacitance of the humidity detection capacitor 80 changes according to the amount of moisture absorbed by the humidity sensitive film 86 .

The reference capacitor 81 is provided with a second insulating film 111 (see FIG. 9), which will be described later, between electrodes. The second insulating film 111 is made of an insulating material such as silicon dioxide (SiO ₂ ) that does not absorb moisture. Therefore, the capacitance of the reference capacitor 81 does not change, or changes very little.

Since the amount of moisture contained in the humidity sensitive film 86 corresponds to the humidity around the humidity detection device 10, by detecting the difference between the capacitance of the humidity detection capacitor 80 and the capacitance of the reference capacitor 81, , relative humidity can be measured. This relative humidity measurement is performed by the humidity measurement processor 31 (see FIG. 13) in the ASIC chip 30 .

[Configuration of Temperature Detector]
Next, the configuration of the temperature detection section 22 will be described.

FIG. 8 is a circuit diagram illustrating the configuration of the temperature detection section 22. As shown in FIG. The temperature detection unit 22 is a bandgap type temperature sensor that detects temperature by utilizing the characteristic that the electrical characteristics of the semiconductor bandgap change proportionally with changes in temperature. For example, the temperature detection unit 22 includes one or a plurality of bipolar transistors having two terminals by connecting any two of a base, an emitter, and a collector. The temperature can be measured by detecting the resistance value between the two terminals.

As shown in FIG. 8, in this embodiment, the temperature detection unit 22 is configured by connecting in parallel a plurality (e.g., eight) of npn-type bipolar transistors 90 whose bases and collectors are connected. By connecting a plurality of bipolar transistors 90 in parallel in this way, the junction area of the pn junction is increased and the ESD resistance is improved.

The emitter of bipolar transistor 90 is connected to pad 24a as a ground electrode terminal. The base and collector of the bipolar transistor 90 are connected to the pad 24e as a terminal for temperature detection.

The temperature is measured by the temperature measurement processor 32 (see FIG. 13) in the ASIC chip 30 based on the potential of the pad 24e.

[Sensor chip element structure]
Next, the element structure of the sensor chip 20 will be described.

FIG. 9 is a schematic cross-sectional view for explaining the element structure of the sensor chip 20. As shown in FIG. In FIG. 9, the pads 24a, 24b, 24c, and 24e are shown in the same cross section as the humidity detection section 21, the temperature detection section 22, and the heating section 23, which facilitates understanding of the structure. It does not mean that they actually exist within the same cross section. The cross sections of the humidity detection unit 21, the temperature detection unit 22, and the heating unit 23 are also simplified in order to facilitate understanding of the structure, and the positional relationship and the like of each unit are different from the actual ones.

As shown in FIG. 9, the sensor chip 20 is formed using the p-type semiconductor substrate 70 described above. This p-type semiconductor substrate 70 is formed with a first deep n-well 100a and a second deep n-well 100b. A temperature detector 22 is formed in the first deep n-well 100a. A heating portion 23 is formed in the second deep n-well 100b.

P-type diffusion layers 103a and 103b are formed on the surface layer of the p-type semiconductor substrate 70 where neither the first deep n-well 100a nor the second deep n-well 100b are formed. P-type contact layers 104a and 104b are formed on the surface layers of the p-type diffusion layers 103a and 103b, respectively. The contact layers 104a and 104b are low-resistance layers (p-type diffusion layers) for electrical connection between a predetermined wiring layer formed on the p-type semiconductor substrate 70 and the p-type semiconductor substrate 70. FIG.

A p-well 101 and an n-well 102 are formed on the surface of the first deep n-well 100a. An n-type diffusion layer 91 and a p-type diffusion layer 92 are formed in the surface layer of the p-well 101 . An n-type diffusion layer 93 is formed in the surface layer of the n-well 102 . The n-type diffusion layer 91, the p-type diffusion layer 92, and the n-type diffusion layer 93 constitute the aforementioned npn-type bipolar transistor 90, functioning as an emitter, a base, and a collector, respectively.

A p-well 105 is formed on the surface of the second deep n-well 100b. One or more n-type diffusion layers 106 are formed in the surface layer of the p-well 105 . In this embodiment, a plurality of n-type diffusion layers 106 are formed. For example, each n-type diffusion layer 106 extends in a direction orthogonal to the plane of the drawing, and forms a one-dimensional lattice as a whole (see FIG. 11). The n-type diffusion layer 106 has a predetermined resistance value (for example, a sheet resistance value of about 3Ω) and functions as a resistor that generates heat when current flows. That is, the n-type diffusion layer 106 constitutes the heating portion 23 described above.

In addition, in the surface layer of the second deep n-well 100b, an n-type diffusion layer 109a is formed around the p-well 105 in which the n-type diffusion layer 106 forming the heating section 23 is formed. An n-type contact layer 109b is formed on the surface layer of the n-type diffusion layer 109a.

N-type diffusion layer 109 a is formed to surround p-well 105 . The p-type diffusion layer 103b described above is formed to surround the n-type diffusion layer 109a. The n-type diffusion layer 109a and the p-type diffusion layer 103b constitute a guard ring 200 (see FIG. 11) which will be described later.

Each layer in the p-type semiconductor substrate 70 is formed using a normal semiconductor manufacturing process (CMOS process). Therefore, n-type diffusion layer 106 as a resistor is formed in the same manufacturing process as n-type diffusion layers 91 and 93 included in part of temperature detection section 22 . The n-type diffusion layers 106, 91, 93 and the contact layer 109b are formed at the same time by an ion-implantation process of doping impurities into the substrate by ion-implanting n-type impurities (for example, phosphorus). That is, the n-type diffusion layer 106 as a resistor has the same depth from the surface of the p-type semiconductor substrate 70 as the n-type diffusion layers 91 and 93 included in a part of the temperature detection section 22 . Further, the n-type diffusion layer 106 may have the same depth from the surface of the p-type semiconductor substrate 70 as the p-type diffusion layer 92 included in a part of the temperature detection section 22 .

The n-type diffusion layers 106, 91, 93 and the contact layer 109b can be formed by a thermal diffusion process in which impurities are added by heat treatment instead of the ion implantation process.

Further, the n-type diffusion layers 71 and 72 of the ESD protection circuit 60 described above are also formed by the same manufacturing process (ion implantation process or thermal diffusion process) as the n-type diffusion layers 106, 91 and 93 and the contact layer 109b. . The contact layer 73 is formed in the same manufacturing process (ion implantation process or thermal diffusion process) as the p-type diffusion layer 92, the contact layers 104a and 104b, and the like.

A first insulating film 110 , a second insulating film 111 and a third insulating film 112 are laminated in this order on the surface of the p-type semiconductor substrate 70 . These are made of an insulating material such as silicon dioxide (SiO ₂ ) or silicon nitride (SiN).

A first wiring layer 120 is formed on the first insulating film 110 . A second wiring layer 121 is formed on the second insulating film 111 . The second insulating film 111 covers the first wiring layer 120 . The third insulating film 112 covers the second wiring layer 121 . The first wiring layer 120 and the second wiring layer 121 are made of a conductive material such as aluminum.

A first plug layer 122 having a plurality of first plugs for connecting the first wiring layer 120 to the p-type semiconductor substrate 70 is formed in the first insulating film 110 . A second plug layer 123 having a plurality of second plugs for connecting the first wiring layer 120 and the second wiring layer 121 is formed in the second insulating film 111 . The first plug layer 122 and the second plug layer 123 are made of a conductive material such as tungsten.

For example, the wiring 94 for connecting the base and collector of the bipolar transistor 90 described above is formed by the first wiring layer 120 and is connected to the p-type diffusion layer 92 and the n-type diffusion layer 93 via the first plug layer 122. Connected. Also, the wiring 94 is connected to the pad 24e as a terminal for temperature detection through the second plug layer 123 and the second wiring layer 121. As shown in FIG. Also, the n-type diffusion layer 91 as the emitter of the bipolar transistor 90 is connected through the first plug layer 122, the first wiring layer 120 and the second wiring layer 121 to the pad 24a as the ground electrode terminal.

A wiring 107 for grounding one end of the heating portion 23 to the ground potential is formed of the first wiring layer 120 and connected via the first plug layer 122 to the n-type diffusion layer 106 and the contact layer 104b. A wiring 108 for connecting the other end of the heating portion 23 to a pad 24f as a heating terminal is connected to the n-type diffusion layer 106 and the contact layer 109b via the first plug layer 122, and is connected to the second It is connected to the pad 24 f through the plug layer 123 and the second wiring layer 121 .

The reference electrode 82 of the reference capacitor 81 is formed of the first wiring layer 120, and is connected to the pad 24d (not shown in FIG. 9) as the second drive terminal T2 via the second plug layer 123 and the second wiring layer 121. ).

The lower electrode 83 of the humidity detection capacitor 80 is formed of the second wiring layer 121 and connected to the pad 24b as the signal terminal TS. Furthermore, the wiring 85 for connecting the upper electrode 84 of the humidity detection capacitor 80 to the pad 24c as the first drive terminal T1 is formed of the second wiring layer 121. As shown in FIG. Note that the lower electrode 83 is arranged at a position facing the reference electrode 82 with the second insulating film 111 interposed therebetween.

The pads 24a to 24f are formed on the third insulating film 112 with a conductive material such as aluminum, and are connected to the second wiring layer 121 through the third insulating film 112. FIG.

A humidity sensitive film 86 is formed on the third insulating film 112 . The humidity sensitive film 86 has a thickness of 0.5 μm to 1.5 μm and is made of a polymeric material that easily adsorbs and desorbs water molecules according to humidity. The moisture sensitive film 86 is, for example, a polyimide film with a thickness of 1 μm. The polymeric material forming the moisture-sensitive film 86 is not limited to polyimide, and may be cellulose, polymethylmethacrylate (PMMA), polyvinyl alcohol (PVA), or the like.

The upper surface of the humidity sensitive film 86 is flat, and a planar upper electrode 84 is formed on this upper surface. The upper electrode 84 is formed at a position facing the lower electrode 83 with the humidity sensitive film 86 interposed therebetween. A portion of the upper electrode 84 is connected to the wiring 85 . The upper electrode 84 is, for example, a conductive film made of aluminum or the like with a thickness of 200 nm. In addition, the upper electrode 84 is formed with a plurality of openings 84a so that water molecules in the air are efficiently taken into the humidity sensitive film 86. As shown in FIG.

An overcoat film 87 is provided on the humidity sensitive film 86 so as to cover the upper electrode 84 . The overcoat film 87 is made of a polymeric material, for example, the same material as the moisture sensitive film 86 . The thickness of the overcoat film 87 is, for example, 0.5 μm to 10 μm.

The humidity sensitive film 86 and the overcoat film 87 are formed with openings for exposing the pads 24a to 24f.

Thus, the lower electrode 83 and the upper electrode 84 constitute the parallel-plate humidity detection capacitor 80 . The lower electrode 83 and the reference electrode 82 constitute a parallel-plate reference capacitor 81 . The humidity detection capacitor 80 and the reference capacitor 81 are arranged above the heating section 23 .

Therefore, the heat generated by the heating portion 23 heats the humidity sensitive film 86 between the lower electrode 83 and the upper electrode 84 . As a result, the moisture-sensitive film 86 absorbs an amount of water molecules corresponding to the humidity when the temperature rises due to heating, so that the dielectric constant changes and the capacitance of the humidity detection capacitor 80 decreases. Also, the temperature detection unit 22 detects a temperature rise caused by the heating unit 23 .

FIG. 10 is a plan view illustrating shapes of the lower electrode 83 and the upper electrode 84. FIG. As shown in FIG. 10, both the lower electrode 83 and the upper electrode 84 are rectangular. The upper electrode 84 is formed so as to cover the lower electrode 83 .

The opening 84a is preferably as small as possible, and the smaller the opening, the more the electric field is prevented from leaking into the air. Actually, a large number of openings 84a are formed. In addition, the opening 84a is not limited to a square shape, and may be an elongated strip shape or a circular shape. Also, the openings 84a may be arranged in a zigzag pattern. The openings 84a are preferably circular and staggered.

Although not shown in FIG. 10, a rectangular reference electrode 82 is formed below the lower electrode 83 .

FIG. 11 is a plan view illustrating the shape of the n-type diffusion layer 106 forming the heating section 23. FIG. As shown in FIG. 11, the n-type diffusion layer 106 has a one-dimensional lattice shape in which a plurality of elongated strip-shaped regions are arranged in parallel. One end of the one-dimensional grid-like n-type diffusion layer 106 is connected to the wiring 107 described above, and the other end is connected to the wiring 108 described above. The heating unit 23 is positioned below the temperature detection unit 22 so as to cover the entire temperature detection unit 22 .

FIG. 11 also shows a guard ring 200 composed of the n-type diffusion layer 109a and the p-type diffusion layer 103b. The n-type diffusion layer 109a is connected to the second deep n-well 100b and is given the potential of the pad 24f as the heating terminal HT. The n-type diffusion layer 109a is electrically connected to the p-well 105 through the wiring 107 and applies the ground potential to the p-well 105. As shown in FIG.

Guard ring 200 stabilizes the potential of noise suppressor 210 (see FIG. 12) formed in p-type semiconductor substrate 70 below humidity detector 21 .

Note that the reference electrode 82 is arranged between the noise suppressor 210 and the lower electrode 83 .

[Noise suppressor]
Next, the functions and actions of the noise suppressor will be described.

FIG. 12 is a diagram illustrating an equivalent circuit of the noise suppressor 210 configured on the p-type semiconductor substrate 70. As shown in FIG. In FIG. 12, CJ1 represents the junction capacitance of the pn junction formed between the n-type diffusion layer 106 and the p-well 105. In FIG. CJ2 represents the junction capacitance of the pn junction formed between the p-well 105 and the second deep n-well 100b. CJ3 represents the junction capacitance of the pn junction formed between the layers of the second deep n-well 100b and the p-type semiconductor substrate .

R1 represents the diffusion resistance of the n-type diffusion layer 106; R2 represents the p-well 105 diffusion resistance. R3 represents the diffusion resistance of the second deep n-well 100b. The substrate resistance of the p-type semiconductor substrate 70 is shown.

The noise suppressor 210 is composed of the n-type diffusion layer 106, the p-well 105, the second deep n-well 100b, and the p-type semiconductor substrate . That is, the noise suppressing section 210 is configured by forming a laminated structure of four semiconductor layers whose polarities are alternately reversed. In this embodiment, the noise suppressor 210 has an npnp structure.

A power supply voltage VDD, for example, is supplied to the pad 24f as the heating terminal HT through a pull-down resistor RP and a switch circuit SW. When driving the heating unit 23, the switch circuit SW is turned on, and the power supply voltage VDD is applied to the pad 24a as a driving voltage. At this time, the n-type diffusion layer 106 as a resistor generates heat, and each pn junction included in the noise suppressing section 210 is in a reverse bias state.

When the heating unit 23 is not driven, the switch circuit SW is turned off to be in a pull-down state, and the pad 24a is connected to the ground via the pull-down resistor RP.

An arrow Np in FIG. 12 represents the magnitude of the peak voltage of noise generated in the ASIC chip 30 and directed to the humidity detection section 21 . In this manner, the noise suppression unit 210 attenuates the peak voltage of noise by dividing it with the capacitor formed at each pn junction. The noise N whose peak voltage is attenuated by the noise suppression section 210 is transmitted to the humidity detection section 21 . In the humidity detection unit 21, the influence of noise on the humidity detection operation is suppressed.

The noise suppression unit 210 has a similar suppression effect on noise generated in the sensor chip 20 and directed to the ASIC chip 30 .

[Configuration of ASIC chip]
Next, the configuration of the ASIC chip 30 will be described.

FIG. 13 is a block diagram illustrating the configuration of the ASIC chip 30. As shown in FIG. As shown in FIG. 13, the ASIC chip 30 includes a humidity measurement processing section 31, a temperature measurement processing section 32, a heating control section 33, and a failure determination section .

First, the configuration of the humidity measurement processing unit 31 will be described.

FIG. 14 is a diagram illustrating the configuration of the humidity measurement processing section 31. As shown in FIG. As shown in FIG. 14 , the humidity measurement processing section 31 has a drive section 300 , a charge amplifier 301 , a control section 302 and an AD converter (ADC) 303 .

The driving section 300 includes a first driving circuit DRV1 and a second driving circuit DRV2. The charge amplifier 301 is a charge-voltage conversion (CV conversion) section including a capacitor C1, an operational amplifier OP1, and a switch circuit SW1.

The first drive circuit DRV<b>1 applies a first drive signal, which is a square-wave AC drive signal, to the first drive terminal T<b>1 of the sensor chip 20 under the control of the control unit 302 . Under the control of the control unit 302, the second drive circuit DRV2 supplies the second drive terminal T2 of the sensor chip 20 with a square-wave AC drive signal, which is the second drive signal reverse to the first drive signal. Apply a signal. The high level of the first drive signal and the second drive signal is equal to, for example, power supply voltage VDD, and the low level thereof is equal to, for example, ground potential GND.

The first drive signal and the second drive signal have opposite phases to each other. That is, when the first drive signal is at high level, the second drive signal is at low level, and when the first drive signal is at low level, the second drive signal is at high level.

The capacitor C1 has one end connected to the signal terminal TS of the sensor chip 20 and the other end connected to the output of the operational amplifier OP1.

The operational amplifier OP1 has an inverting input terminal connected to the signal terminal TS, and a non-inverting input terminal to which the reference voltage Vref is input. The reference voltage Vref is, for example, an intermediate value between the high level and the low level of the first drive signal and the second drive signal.

Since the operational amplifier OP1 has a very large voltage gain, the voltage at the signal terminal TS is substantially equal to the reference voltage Vref. Further, since the input impedance of the inverting input terminal of the operational amplifier OP1 is very high, almost no current flows into the inverting input terminal. The operational amplifier OP1 outputs a voltage Vo obtained by amplifying the difference between the voltage of the signal terminal TS and the reference voltage Vref.

The switch circuit SW1 is a circuit for discharging charges accumulated in the capacitor C1, and is connected in parallel with the capacitor C1. The switch circuit SW1 is turned on or off under the control of the control section 302 .

The ADC 303 converts the output voltage Vo of the operational amplifier OP1 into a digital signal Ds under the control of the control section 302 .

A control unit 302 controls each unit in the ASIC chip 30 . The control unit 302 executes the generation of the drive signal by the drive unit 300, the discharge of the capacitor C1 by the switch circuit SW1, and the analog-to-digital conversion operation by the ADC 303 based on a predetermined measurement sequence.

FIG. 15 is a timing chart explaining the measurement sequence. In the measurement sequence, the control section 302 controls each section so as to alternately repeat the reset period Trst and the charge transfer period Tchg. In the reset period Trst, the control unit 302 turns on the switch circuit SW1 to discharge the capacitor C1, sets the first drive signal to high level, and sets the second drive signal to low level. In the charge transfer period Tchg, the control unit 302 turns off the switch circuit SW1 to make the capacitor C1 chargeable, sets the first drive signal to low level, and sets the second drive signal to high level.

By this control, the voltage Vo represented by the following formula (1) is output from the charge amplifier 301 in the charge transfer period Tchg.

Vo=VDD×(Cs−Cr)/C1+Vref (1)
Here, Cs is the capacitance of the humidity detection capacitor 80 and Cr is the capacitance of the reference capacitor 81 .

The control unit 302 performs humidity calculation processing using the digital signal Ds output from the ADC 303 to calculate the relative humidity (% RH).

The temperature measurement processing unit 32 detects the potential of the pad 24e as a terminal for temperature detection, and calculates the temperature corresponding to the detected potential.

The heating control unit 33 applies a predetermined driving voltage (for example, the power supply voltage VDD described above) to the pad 24f as a heating terminal, thereby causing a current (for example, about 10 mA) to flow through the heating unit 23 to generate heat. The heating controller 33 controls the amount of heat generated by controlling the voltage applied to the pad 24f.

The failure determination section 34 performs failure determination based on the relative humidity measured by the humidity measurement processing section 31 and the temperature measured by the temperature measurement processing section 32 . The failure determination unit 34 provides the heating control unit 33 with instructions regarding the start and end of heating by the heating unit 23 at the time of failure determination.

For example, the failure determination unit 34 acquires the humidity H1 from the humidity measurement processing unit 31 and acquires the temperature T1 from the temperature measurement processing unit 32 in an initial state in which the heating unit 23 does not generate heat. Then, the failure determination unit 34 causes the heating unit 23 to start heating, and acquires the humidity H2 from the humidity measurement processing unit 31 and the temperature T2 from the temperature measurement processing unit 32 again after a certain period of time has elapsed.

When the temperature rises due to heating (T2>T1) and the humidity decreases due to heating (H2<H1), the failure determination unit 34 determines that the humidity detection device 10 is normal. , it is determined that the humidity detection device 10 is in a failed state.

[effect]
As in the above measurement sequence, the ASIC chip 30 generates an AC drive signal and applies it to the humidity detection section 21 of the sensor chip 20, so the ASIC chip 30 may generate large noise. According to the present embodiment, the noise suppressor 210 arranged below the humidity detector 21 (on the side of the ASIC chip 30) attenuates the peak voltage of noise traveling from the ASIC chip 30 to the humidity detector 21. The influence of noise on the section 21 is suppressed, and the noise resistance is improved.

In order to suppress such noise, interposing an insulating layer between the sensor chip 20 and the ASIC chip 30 can be considered. It is not preferable because it is necessary to make each chip thin due to the demand.

[Modification]
In the above embodiment, the noise suppression unit 210 is configured by four semiconductor layers stacked so that the polarities are alternately reversed, but the number of semiconductor layers that make up the noise suppression unit is not limited. 2 or more is sufficient.

Moreover, in the above embodiment, the sensor chip 20 is constructed of the p-type semiconductor substrate 70, but instead of this, it is also possible to construct it using an n-type semiconductor substrate.

In the above-described embodiment, the humidity detection unit 21 is a capacitance change type humidity sensor. good too.

The present invention can also be applied to a detection device that detects physical quantities other than humidity. That is, instead of the humidity detector 21, it is possible to provide a detector that outputs a signal corresponding to a physical quantity other than humidity.

In addition, in the present disclosure, the positional relationship between two elements represented by the words “cover” and “on” means that the first element is indirectly provided on the surface of the second element via another element. It includes both cases where it is provided and cases where it is provided directly.

Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications can be made to the above-described embodiments without departing from the scope of the present invention. and substitutions can be added.

10 humidity detection device (detection device), 20 sensor chip (first semiconductor chip), 21 humidity detection unit (detection unit), 22 temperature detection unit, 23 heating unit, 24 bonding pad, 25 formation allowable area, 30 ASIC chip ( second semiconductor chip), 40 mold resin, 50 opening, 60 ESD protection circuit, 80 humidity detection capacitor, 81 reference capacitor, 82 reference electrode, 83 lower electrode, 84 upper electrode, 84a opening, 86 humidity sensitive film, 106 n-type diffusion layer, 200 guard ring, 210 noise suppression unit, 300 drive unit, 301 charge amplifier (charge-voltage conversion unit)

Claims (6)

a semiconductor substrate;
a detection unit provided above the semiconductor substrate and configured to output a signal corresponding to a physical quantity;
a noise suppressing section composed of a plurality of semiconductor layers laminated so that polarities are alternately reversed in the semiconductor substrate below the detecting section;
has
The detection unit is
a humidity detecting capacitor having a lower electrode formed above the semiconductor substrate, a humidity sensitive film formed above the lower electrode, and an upper electrode formed on the humidity sensitive film;
a reference capacitor including the lower electrode, a reference electrode arranged between the noise suppression portion and the lower electrode, and an insulating film arranged between the reference electrode and the lower electrode;
has
Outputs a signal according to humidity
detection device. 2. The detection device according to claim 1, wherein a voltage is applied to said noise suppressing section so that each pn junction formed between said plurality of semiconductor layers is reverse-biased. the noise suppression unit includes a diffusion layer formed on a surface layer of the semiconductor substrate;
3. The detection device according to claim 1, wherein the diffusion layer functions as a resistor that generates heat when current flows. 2. The detection device according to claim 1 , wherein the humidity sensitive film is made of polyimide. a first semiconductor chip including the semiconductor substrate and the detection unit;
a second semiconductor chip including a drive section for driving the detection section and a charge-voltage conversion section for converting the charge output from the detection section into a voltage;
has
5. The detection device according to claim 1 , wherein said first semiconductor chip is stacked on said second semiconductor chip. 6. The detection device according to claim 5 , wherein the drive section applies an AC drive signal to the detection section.

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