JP7179526B2 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Description

The present disclosure relates to a semiconductor device mounted with a semiconductor element and a manufacturing method thereof.

In recent years, so-called micromachines (MEMS: Micro Electro Mechanical Systems), in which a Si (silicon) substrate is microfabricated and various semiconductor elements are mounted on the Si substrate, are becoming widespread. For example, Patent Document 1 discloses a conventional semiconductor device in which a semiconductor element is mounted on a Si substrate. The semiconductor device described in the document includes a Si substrate (substrate), a semiconductor element (light-emitting element), and a wiring layer (wiring pattern). A semiconductor element is mounted on the Si substrate. The wiring layer is formed on the Si substrate and electrically connected to the semiconductor element. The wiring layer serves as terminals when the semiconductor device is mounted on a circuit board of an electronic device or the like. The wiring layer is formed on the upper surface of the Si substrate.

A conventional semiconductor device configured as described above is manufactured as follows. That is, in the conventional method of manufacturing a semiconductor device, after forming a wiring layer on a Si wafer, a plurality of semiconductor elements are mounted on the Si wafer. Then, the Si wafer is diced to divide the Si wafer into individual pieces for each semiconductor element. A conventional semiconductor device is manufactured as described above.

JP 2009-94409 A

In the conventional method of manufacturing a semiconductor device, after the wiring layer is formed, the semiconductor element is diced into individual pieces, so the wiring layer is not formed on the side surface of the Si substrate formed by dicing. Therefore, when a semiconductor device is mounted on a circuit board of an electronic device or the like using solder, it is necessary to use an X-ray inspection device or the like in order to check the bonding state of the solder.

The present disclosure has been conceived under such circumstances, and an object of the present disclosure is to provide a semiconductor device capable of easily confirming the joint state of solder when mounted on a circuit board such as an electronic device. and to provide a method for manufacturing the semiconductor device.

A semiconductor device provided by a first aspect of the present disclosure includes a semiconductor element having an element main surface and an element back surface facing opposite to each other in a first direction, and a wiring layer main surface facing opposite to each other in the first direction. and a wiring layer rear surface, the wiring layer principal surface facing the element rear surface and conducting to the semiconductor element, and a wiring layer conducting to the wiring layer and extending from the wiring layer rear surface to the first wiring layer. a sealing resin including a columnar conductor projecting in a direction, a first resin layer covering the semiconductor element and the main surface of the wiring layer, and a second resin layer covering the back surface of the wiring layer; an external electrode that is exposed and electrically connected to the columnar conductor, wherein the sealing resin has a resin side surface facing in a second direction orthogonal to the first direction and the same direction as the element back surface. and the columnar conductor has a side exposed surface exposed from the resin side surface and a back exposed surface connected to the side exposed surface and exposed from the resin back surface. wherein the external electrode includes a side covering portion covering the exposed side surface and a back covering portion covering the exposed back surface.

In a preferred embodiment of the semiconductor device, the columnar conductor overlaps the second resin layer when viewed in the second direction.

In a preferred embodiment of the semiconductor device, the sealing resin has a resin main surface facing the opposite side of the resin back surface in the first direction, and the resin side surface is connected to the resin back surface. 1 side surface and a second side surface connected to the resin main surface, and the first side surface is arranged more inward of the sealing resin than the second side surface when viewed in the first direction. The first side surface and the exposed side surface are flush with each other.

In a preferred embodiment of the semiconductor device, the first side surface extends over the first resin layer and the second resin layer.

In a preferred embodiment of the semiconductor device, the semiconductor element is provided with a columnar electrode interposed between the back surface of the element and the main surface of the wiring layer and electrically connecting the semiconductor element and the wiring layer. there is

In a preferred embodiment of the semiconductor device, the interface between the first resin layer and the second resin layer is flush with the main surface of the wiring layer.

In a preferred embodiment of the semiconductor device, the dimension of the first resin layer in the first direction is larger than the dimension of the second resin layer in the first direction.

In a preferred embodiment of the semiconductor device, the first resin layer and the second resin layer are made of the same material.

In a preferred embodiment of the semiconductor device, the columnar conductor faces a third direction orthogonal to both the first direction and the second direction, and has a resin contact side surface in contact with the sealing resin, and and a projecting portion projecting in the third direction from the resin contacting side surface when viewed in the first direction, the projecting portion being connected to the resin contacting side surface and being in contact with the sealing resin. have a face.

In a preferred embodiment of the semiconductor device, the locking surface faces the same direction as the side exposed surface.

In a preferred embodiment of the semiconductor device, the semiconductor device further includes a supporting substrate facing the main surface of the element and supporting the semiconductor element.

A preferred embodiment of the semiconductor device further comprises a bonding layer interposed between the support substrate and the semiconductor element.

A method for manufacturing a semiconductor device provided by a second aspect of the present disclosure includes the steps of preparing a support substrate having a substrate main surface and a substrate back surface facing opposite to each other in a first direction; a step of mounting a semiconductor element having an element main surface and an element back surface facing sideways on the support substrate with the element main surface and the substrate back surface facing each other; a first resin layer forming step of forming a first resin layer covering the semiconductor element while exposing the top surface; and a wiring layer main surface and a wiring layer back surface facing opposite sides in the first direction. forming a wiring layer in which the main surface of the wiring layer is in contact with the columnar electrode and the first resin layer; forming a columnar conductor protruding from the back surface of the wiring layer in the first direction; a second resin layer forming step of forming a second resin layer that is in contact with a resin layer and covers a part of the columnar conductor and the wiring layer; and an external electrode forming step of forming an external electrode to cover the columnar conductor, wherein the columnar conductor has a rear surface side exposed surface facing the same direction as the substrate rear surface and a side surface side facing a second direction orthogonal to the first direction. an exposed surface, the exposed back surface and the exposed side surface are each exposed from the second resin layer and connected to each other; and the external electrode extends from the exposed side surface. It is characterized by including a covering side surface covering portion and a rear surface covering portion covering the rear surface side exposed surface.

In a preferred embodiment of the method for manufacturing a semiconductor device, in the step of forming a first resin layer, after forming a first resin member covering all of the semiconductor element and the columnar electrode, the top surface of the columnar electrode is formed. The first resin layer is formed by grinding the first resin member from the side in which the back surface of the substrate faces until is exposed.

In a preferred embodiment of the method for manufacturing a semiconductor device, in the step of forming the second resin layer, after forming the second resin member covering all of the wiring layer and the columnar conductors, the second resin member is formed. By grinding from the side in which the back surface of the substrate faces, the second resin layer is formed and the exposed back surface is formed.

In a preferred embodiment of the method for manufacturing a semiconductor device, in the step of forming the second resin layer, grooves connecting the second resin layer to the first resin layer are formed by half-cut dicing using a dicing blade. Thus, the side exposed surface exposed from the second resin layer is formed in the groove.

In a preferred embodiment of the method for manufacturing the semiconductor device, the step of forming the external electrodes is by electroless plating.

A preferred embodiment of the semiconductor device manufacturing method further includes a supporting substrate grinding step of grinding the supporting substrate from the substrate main surface toward the substrate rear surface after the second resin layer forming step.

In a preferred embodiment of the manufacturing method of the semiconductor device, in the supporting substrate grinding step, the entire supporting substrate is ground.

According to the semiconductor device of the present disclosure, when the semiconductor device is mounted on a circuit board of an electronic device or the like, it is possible to easily check the solder joint state. Further, according to the method of manufacturing a semiconductor device of the present disclosure, it is possible to manufacture a semiconductor device that allows easy confirmation of the solder joint state when mounted on a circuit board of an electronic device or the like.

1 is a perspective view (perspective view seen from the bottom side) showing a semiconductor device according to a first embodiment; FIG. 1 is a plan view showing a semiconductor device according to a first embodiment; FIG. It is a bottom view showing the semiconductor device according to the first embodiment. 1 is a side view (front view) showing a semiconductor device according to a first embodiment; FIG. FIG. 3 is a cross-sectional view taken along line VV of FIG. 2; 3 is a cross-sectional view taken along line VI-VI of FIG. 2; FIG. FIG. 6 is an enlarged cross-sectional view of a part of FIG. 5 ; FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment; It is a sectional view showing a semiconductor device concerning a 2nd embodiment. It is a top view which shows the semiconductor device concerning 3rd Embodiment. FIG. 22 is a cross-sectional view along line XXII-XXII of FIG. 21; It is a sectional view showing a semiconductor device concerning a 4th embodiment.

Preferred embodiments of the semiconductor device of the present disclosure and the method of manufacturing the semiconductor device of the present disclosure will be described below with reference to the drawings.

[First embodiment]
1 to 7 show a semiconductor device according to a first embodiment of the present disclosure. A semiconductor device A1 of this embodiment includes a semiconductor element 10, a support substrate 20, a plurality of internal electrodes 30, a plurality of external electrodes 40, a bonding layer 50, and a sealing resin 60. FIG.

FIG. 1 is a perspective view showing a semiconductor device A1, showing a state when viewed from the bottom side. FIG. 2 is a plan view showing the semiconductor device A1. In FIG. 2, the support substrate 20 and the bonding layer 50 are omitted, and the sealing resin 60 is indicated by an imaginary line (chain double-dashed line). FIG. 3 is a bottom view showing the semiconductor device A1, and shows the sealing resin 60 with imaginary lines (double-dot chain lines). FIG. 4 is a side view (front view) showing the semiconductor device A1. FIG. 5 is a cross-sectional view along line VV in FIG. FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. FIG. 7 is an enlarged cross-sectional view of a part of the cross section shown in FIG. 5 . For convenience of explanation, three mutually orthogonal directions are defined as the x-direction, the y-direction, and the z-direction in these figures, respectively. The x direction is the horizontal direction in the plan view (see FIG. 2) of the semiconductor device A1. The y direction is the vertical direction in the plan view (see FIG. 2) of the semiconductor device A1. The z direction is the thickness direction of the semiconductor device A1. The x-direction, y-direction and z-direction respectively correspond to the "second direction", "third direction" and "first direction" described in the claims.

The semiconductor device A1 is a device surface-mounted on a circuit board of various electronic devices. The semiconductor device A1 is of a leadless package type in which terminals for mounting on a circuit board do not protrude from the sealing resin 60. In particular, on each side surface of the sealing resin 60 (four resin side surfaces 63 to be described later), It is a QFN package type in which terminals are arranged. The semiconductor device A1 has a rectangular shape when viewed in the z direction (hereinafter also referred to as “plan view”). The size of the semiconductor device A1 is not particularly limited, but is, for example, 1 to 5 mm square in plan view.

The semiconductor element 10 is an element serving as a functional core of the semiconductor device A1. Semiconductor element 10 is an integrated circuit (IC) such as an LSI (Large Scale Integration), for example. The semiconductor element 10 may be a voltage control element such as an LDO (Low Drop Out), an amplification element such as an operational amplifier, or a discrete semiconductor element such as a diode. The semiconductor element 10 has a rectangular shape when viewed in the z direction (hereinafter also referred to as “plan view”). Semiconductor element 10 is supported by support substrate 20 . The semiconductor element 10 overlaps the support substrate 20 in plan view. The semiconductor element 10 has an element main surface 11 and an element rear surface 12, as shown in FIGS.

The element main surface 11 and the element back surface 12 are spaced apart in the z-direction and face opposite sides. The element main surface 11 faces the support substrate 20 . A plurality of electrode pads (not shown) are formed on the element back surface 12 . The electrode pad is made of Al (aluminum), for example. A plurality of columnar electrodes 13 are formed in the semiconductor element 10 so as to be in contact with each electrode pad. Each columnar electrode 13 has conductivity. The material of each columnar electrode 13 is not particularly limited, but in this embodiment, the main component is Cu (copper). Each columnar electrode 13 has a rectangular shape in plan view. The planar shape of each columnar electrode 13 is not limited, and may be circular or polygonal.

The support substrate 20 supports the semiconductor element 10 . Support substrate 20 is made of, for example, a single crystal intrinsic semiconductor material. In this embodiment, the intrinsic semiconductor material is Si. The support substrate 20 has a rectangular shape in plan view, as shown in FIGS. The thickness (z-direction dimension) of the support substrate 20 is not particularly limited, but is, for example, about 40 to 500 μm. The support substrate 20 has a substrate main surface 21 , a substrate back surface 22 and a plurality of substrate side surfaces 23 .

The substrate main surface 21 and the substrate back surface 22 are spaced apart in the z-direction and face opposite to each other, as shown in FIGS. The substrate main surface 21 is the upper surface of the support substrate 20 shown in FIGS. 4 to 6, and the substrate rear surface 22 is the lower surface of the support substrate 20 shown in FIGS. The substrate rear surface 22 faces the circuit board when the semiconductor device A1 is mounted on the circuit board. In this embodiment, the substrate main surface 21 is exposed to the outside of the semiconductor device A1, and the substrate back surface 22 is covered with the sealing resin 60. As shown in FIG.

The plurality of substrate side surfaces 23 are sandwiched between the substrate main surface 21 and the substrate back surface 22, as shown in FIGS. Each substrate side surface 23 is connected to the substrate main surface 21 at its upper end in the z direction shown in FIGS. 4 to 6, and is connected to the substrate rear surface 22 at its lower end in the z direction shown in FIGS. Each substrate side surface 23 is flat and perpendicular to each of the substrate main surface 21 and the substrate back surface 22 . Each substrate side surface 23 may be inclined with respect to the substrate main surface 21 and the substrate back surface 22 . In this embodiment, the support substrate 20 has four substrate side surfaces 23 facing in different x-directions and y-directions, respectively, as shown in FIGS.

The plurality of internal electrodes 30 are conductors arranged inside the semiconductor device A1. Each internal electrode 30 is electrically connected to the semiconductor element 10 . In this embodiment, each internal electrode 30 includes a wiring layer 31 and columnar conductors 32 .

In each internal electrode 30, the wiring layer 31 is in contact with the columnar electrode 13 of the semiconductor element 10 and electrically connected to the semiconductor element 10, as shown in FIGS. Each wiring layer 31 has a rectangular shape in plan view. The shape and arrangement of the wiring layer 31 are not limited to those shown in FIGS. 2, 3, 5 and 6. FIG. The thickness (z-direction dimension) of the wiring layer 31 is not particularly limited, but is, for example, about 5 to 15 μm. In the present embodiment, each wiring layer 31 is composed of an underlying layer 31a and a plated layer 31b which are laminated to each other, as shown in FIG. The underlying layer 31a is composed of a Ti layer and a Cu layer laminated to each other, and has a thickness of about 200 to 800 nm. The plated layer 31b is mainly composed of Cu, and its thickness is set to be thicker than that of the base layer 31a. Since the base layer 31a and the plated layer 31b are integrated, they are shown as the wiring layer 31 without distinguishing between them in FIGS. The material and thickness of the wiring layer 31 are not limited. The wiring layer 31 has a wiring layer main surface 311 and a wiring layer rear surface 312 .

In each wiring layer 31, the wiring layer main surface 311 and the wiring layer back surface 312 are separated from each other in the z direction and face opposite sides. The wiring layer main surface 311 faces the same direction as the element main surface 11 of the semiconductor element 10 , and the wiring layer back surface 312 faces the same direction as the element back surface 12 of the semiconductor element 10 . In this embodiment, the wiring layer main surface 311 faces the element back surface 12 , and the columnar electrodes 13 are sandwiched between the wiring layer main surface 311 and the element back surface 12 .

In each internal electrode 30, the columnar conductor 32 is in contact with the wiring layer 31 and is electrically connected to the wiring layer 31, as shown in FIG. Each columnar conductor 32 protrudes in the z-direction from the rear surface 312 of each wiring layer. Further, each columnar conductor 32 is located outside the semiconductor device A1 among the internal electrodes 30 in plan view. In this embodiment, each columnar conductor 32 has a rectangular shape in plan view. The planar shape of the columnar conductor 32 is not limited to this, and may be circular or polygonal. The thickness (z-direction dimension) of each columnar conductor 32 is not particularly limited, but is, for example, about 100 to 200 μm. In this embodiment, the main component of the columnar conductors 32 is Cu. The material and thickness of the columnar conductors 32 are not limited. For example, like the wiring layer 31, the columnar conductor 32 may be composed of a base layer and a plated layer that are laminated to each other. In this embodiment, each columnar conductor 32 has a side exposed surface 321 , a back surface exposed surface 322 and a resin contact side surface 323 .

Each side exposed surface 321 faces either the x direction or the y direction. Each side exposed surface 321 is exposed from one of the side surfaces of the sealing resin 60 (resin side surface 63 to be described later). Each back surface side exposed surface 322 faces the same direction as the element back surface 12 and the substrate back surface 22 . Each rear surface side exposed surface 322 is exposed from the rear surface of the sealing resin 60 (resin rear surface 62 described later). The side exposed surface 321 and the back exposed surface 322 are connected. The resin contact side surface 323 is a surface that is connected to the side exposed surface 321 and the rear surface side exposed surface 322 and is in contact with the sealing resin 60 (second resin layer 60B described later).

Each of the plurality of external electrodes 40 is a conductor that is electrically connected to each internal electrode 30 and exposed to the outside of the semiconductor device A1. Each external electrode 40 serves as a terminal when the semiconductor device A1 is mounted on a circuit board. The plurality of external electrodes 40 are formed by electroless plating. In this embodiment, each external electrode 40 is composed of a Ni layer, a Pd layer, and an Au layer laminated together. The thickness of each external electrode 40 is not particularly limited, but is, for example, about 3 to 10 μm. The thickness, material, and forming method of the external electrode 40 are not limited. For example, an Ni layer and an Au layer may be stacked, or Sn (tin) may be used. In this embodiment, each external electrode 40 includes a side surface covering portion 41 and a rear surface covering portion 42, as shown in FIGS. 1 and 4-7.

In each external electrode 40, the side surface covering portion 41 and the back surface covering portion 42 are connected. The side covering portion 41 is a portion of each external electrode 40 formed on the side surface of the semiconductor device A1. The side covering portion 41 covers the side exposed surface 321 of each columnar conductor 32 . In this embodiment, as shown in FIG. 7, the side surface covering portion 41 further covers the side surface 313 of each wiring layer 31 exposed from the resin side surface 63 . The back surface covering portion 42 is a portion of each external electrode 40 formed on the back surface of the semiconductor device A1 and covers the back surface side exposed surface 322 .

As shown in FIGS. 5 and 6, the bonding layer 50 is interposed between the semiconductor element 10 and the support substrate 20 to bond them. The bonding layer 50 is Ag paste, solder, or the like, for example. Note that the bonding layer 50 is not limited to these. For example, it may be a film adhesive such as a die bonding film (DAF: Die Attach Film).

The encapsulating resin 60 is a synthetic resin containing, for example, a black epoxy resin as a main component. The sealing resin 60 partially covers the semiconductor element 10 and the plurality of internal electrodes 30, as shown in FIGS. As shown in FIGS. 2 and 3, the sealing resin 60 has a rectangular shape in plan view. Although the thickness of the sealing resin 60 is not particularly limited, it is, for example, approximately 200 to 500 μm.

The sealing resin 60 includes a first resin layer 60A and a second resin layer 60B. In this embodiment, the sealing resin 60 has an interface between the first resin layer 60A and the second resin layer 60B, as shown in FIGS. The first resin layer 60A and the second resin layer 60B may be integrated without an interface between the first resin layer 60A and the second resin layer 60B. The interface between the first resin layer 60A and the second resin layer 60B is flush with the wiring layer main surface 311 . 5 and 6, the sealing resin 60 has a portion where the wiring layer 31 is sandwiched between the first resin layer 60A and the second resin layer 60B.

The first resin layer 60</b>A covers the semiconductor element 10 , the substrate rear surface 22 of the support substrate 20 , the wiring layer main surface 311 of each wiring layer 31 and the bonding layer 50 . The second resin layer 60B covers the wiring layer rear surface 312 of each wiring layer 31 and part of each columnar conductor 32 . As shown in FIGS. 1 and 4 to 6, the first resin layer 60A is arranged closer to the main surface of the semiconductor device A1 (upper in FIGS. 4 to 6) than the second resin layer 60B in the z direction. It is In this embodiment, as shown in FIGS. 5 and 6, the plurality of internal electrodes 30 overlap the second resin layer 60B when viewed in the x direction or the y direction.

The sealing resin 60 has a resin main surface 61 , a resin back surface 62 and a plurality of resin side surfaces 63 . As shown in FIGS. 4 to 6, the resin main surface 61 and the resin back surface 62 are separated from each other and face opposite sides in the z direction. The resin main surface 61 faces the same direction as the element main surface 11 and the substrate main surface 21 , and the resin back surface 62 faces the same direction as the element back surface 12 and the substrate back surface 22 . The back-side exposed surface 322 of the columnar conductor 32 is exposed from the resin back surface 62 . The resin rear surface 62 and the rear surface side exposed surface 322 are flush with each other. Each of the plurality of resin side surfaces 63 faces the same direction as each substrate side surface 23, as shown in FIGS. Each resin side surface 63 has a step.

Each resin side 63 has a first side 631 and a second side 632 . In each resin side surface 63, the first side surface 631 and the second side surface 632 face the same direction. In each resin side surface 63 , the first side surface 631 is arranged inside the sealing resin 60 relative to the second side surface 632 in plan view. In other words, the second side surface 632 is arranged outside the sealing resin 60 relative to the first side surface 631 in plan view. In plan view, the distance between the first side surface 631 and the second side surface 632 is about 5 to 100 μm.

In each resin side surface 63 , the first side surface 631 is connected to the resin back surface 62 . Also, the side exposed surface 321 of the columnar conductor 32 is exposed from the first side surface 631 . The first side surface 631 and the exposed side surface 321 are flush with each other. The first side surface 631 straddles a portion of the first resin layer 60A and the second resin layer 60B. In each resin side surface 63 , the second side surface 632 is connected to the resin main surface 61 . The second side surface 632 is flush with the substrate side surface 23 . The second side surface 632 is part of the first resin layer 60A.

Next, an example of a method for manufacturing the semiconductor device A1 will be described with reference to FIGS. 8 to 19. FIG. 8 to 18 are cross-sectional views showing one step in the method of manufacturing the semiconductor device A1. These cross-sectional views correspond to the cross-section shown in FIG. For convenience of understanding, the cross-sectional views shown in FIGS. 8 to 18 have the z direction opposite to the cross-sectional view in FIG. FIG. 19 is a bottom view showing a step in the method of manufacturing the semiconductor device A1.

First, as shown in FIG. 8, a support substrate 820 is prepared, and a semiconductor element 810 is mounted on the support substrate 820 . The support substrate 820 is an assembly of portions corresponding to the support substrate 20 of the semiconductor device A1. A semiconductor element 810 corresponds to the semiconductor element 10 of the semiconductor device A1. In this embodiment, the material of the support substrate 820 is an intrinsic semiconductor material of Si. In the step of preparing the support substrate 820 (support substrate preparation step), for example, a silicon wafer is prepared as the support substrate 820 . The support substrate 820 has a substrate main surface 821 and a substrate back surface 822 facing opposite sides in the z-direction. A semiconductor element 810 has an element main surface 811 and an element back surface 812 . An electrode pad (not shown) is formed on the element back surface 812 , and a columnar electrode 813 in contact with the electrode pad is formed so as to protrude from the element back surface 812 . In the process of mounting the semiconductor elements 810 on the support substrate 820 (element mounting process), the plurality of semiconductor elements 810 are mounted on the support substrate 820 via the bonding material 850 with the element main surface 811 facing the substrate back surface 822 . Deploy. The columnar electrodes 813 may be already formed on the prepared semiconductor element 810, or may be formed after the element mounting process. The bonding material 850 corresponds to the bonding layer 50 of the semiconductor device A1. In this embodiment, Ag paste or solder, for example, is used as the bonding material 850 . As the bonding material 850, for example, DAF may be used to attach the semiconductor element 810 to the back surface 822 of the support substrate 820. FIG.

Next, as shown in FIG. 9, a first resin member 891 is formed on the back surface 822 side of the support substrate 820 . The step of forming the first resin member 891 (first resin member forming step) is, for example, resin molding. In this embodiment, the first resin member 891 has electrical insulation, and is made of a synthetic resin containing, for example, a black epoxy resin as a main component. Through the first resin member forming step, the semiconductor element 810 and the columnar electrodes 813 are completely covered with the first resin member 891, as shown in FIG.

Next, as shown in FIG. 10, the first resin member 891 is ground. In the step of grinding the first resin member 891 (first resin member grinding step), in FIG. 9, the first resin member 891 is ground from the side in which the substrate rear surface 822 faces (upper side in FIG. 9). At this time, as shown in FIG. 10, the top surface 813a of the columnar electrode 813 is ground until it is exposed from the first resin member 891. Then, as shown in FIG. Thereby, as shown in FIG. 10, a first resin layer 860A covering the semiconductor element 810 while exposing the top surface 813a of the columnar electrode 813 is formed. The first resin layer 860A will later become the first resin layer 60A of the sealing resin 60 of the semiconductor device A1. As shown in FIG. 10, the top surface 813a of the columnar electrode 813 is flush with the top surface of the first resin layer 860A (the surface facing away from the surface in contact with the support substrate 820). In the present embodiment, the process including the first resin member forming process and the first resin member grinding process corresponds to the "first resin layer forming process" recited in the claims.

Next, as shown in FIGS. 11 to 13, internal electrodes 830 are formed. The internal electrode 830 will later become the internal electrode 30 of the semiconductor device A1. The process of forming the internal electrodes 830 (internal electrode forming process) includes a process of forming an underlying layer 830a, a process of forming a first plating layer 830b, a process of forming a second plating layer 830c, and removing unnecessary underlying layers 830a. includes the step of In this embodiment, these steps are performed in the order described above. The base layer 830a will later become part of the wiring layer 31 (base layer 31a) of the semiconductor device A1. Also, the first plating layer 830b will later become part of the wiring layer 31 (plating layer 31b) of the semiconductor device A1. The second plated layer 830c will later become the columnar conductor 32 of the semiconductor device A1.

In the step of forming the underlying layer 830a (underlying layer forming step), as shown in FIG. 11, the underlying layer 830a is formed. The base layer forming step is performed, for example, by a sputtering method. The underlying layer 830a in this embodiment is composed of a Ti layer and a Cu layer that are laminated to each other. In the base layer forming step, after forming a Ti layer covering the entire surface of the first resin layer 860A and all of the columnar electrodes 813 exposed from the surface of the first resin layer 860A, a Cu layer is formed in contact with the Ti layer. . Thus, the base layer 830a shown in FIG. 11 is formed.

In the step of forming the first plating layer 830b (first plating layer forming step), as shown in FIG. 11, the first plating layer 830b is formed. The first plating layer forming step is, for example, pattern formation by photolithography and electroplating. In the first plating layer forming step, a resist layer (not shown) for forming the first plating layer 830b is formed by photolithography. In forming the resist layer, a photosensitive resist is applied so as to cover the entire surface of the underlying layer 830a, and patterning is performed by exposing and developing the photosensitive resist. This patterning exposes a portion of the underlying layer 830a (the portion forming the first plating layer 830b). Then, a first plated layer 830b is formed on the underlying layer 830a exposed from the resist layer by electrolytic plating using the underlying layer 830a as a conductive path. The first plating layer 830b is formed integrally with the underlying layer 830a. Then, the resist layer is removed. Thereby, the first plated layer 830b shown in FIG. 11 is formed.

In the step of forming the second plating layer 830c (second plating layer forming step), as shown in FIG. 12, the second plating layer 830c is formed. The second plating layer forming step, like the first plating layer forming step, is, for example, pattern formation by photolithography and electroplating. In the second plating layer forming step, a resist layer (not shown) for forming the second plating layer 830c is formed by photolithography. In forming the resist layer, a photosensitive resist is applied so as to cover the entire surfaces of the base layer 830a and the first plating layer 830b, and patterning is performed by exposing and developing the photosensitive resist. This patterning exposes a portion of the first plating layer 830b (the portion forming the second plating layer 830c). Then, a second plating layer 830c is formed on the first plating layer 830b exposed from the resist layer by electroplating using the base layer 830a and the first plating layer 830b as conductive paths. Then, the resist layer is removed. Thereby, the second plating layer 830c shown in FIG. 12 is formed.

In the step of forming the unnecessary underlying layer 830a (underlying layer removing step), as shown in FIG. 13, the underlying layer 830a that is not covered with the first plating layer 830b is removed. The underlayer removing step is, for example, wet etching. This wet etching uses, for example, a mixed solution of H ₂ SO ₄ (sulfuric acid) and H ₂ O ₂ (hydrogen peroxide). By the base layer removing step, as shown in FIG. 13, the first resin layer 860A is exposed from the portion where the base layer 830a is removed. Further, by removing the underlying layer 830a, the underlying layer 830a is divided, and a plurality of internal electrodes 830 are formed. Each of the plurality of internal electrodes 830 includes a wiring layer 831 composed of an underlying layer 830a and a first plated layer 830b, and a columnar conductor 832 composed of a second plated layer 830c. In each internal electrode 830 , the wiring layer 831 has a wiring layer main surface 831 a facing in the same direction as the substrate main surface 821 and a wiring layer rear surface 831 b facing in the same direction as the substrate rear surface 822 . The wiring layer main surface 831 a is in contact with the first resin layer 860 A and the columnar electrodes 813 . The wiring layer back surface 831b is in contact with the columnar conductor 832, and the columnar conductor 832 protrudes from the wiring layer back surface 831b in the z direction. 13 and subsequent drawings (FIGS. 14 to 19) showing the manufacturing process, the underlying layer 830a and the first plated layer 830b are shown as the wiring layer 831, and the second plated layer 830c is shown as the columnar conductor 832. As shown in FIG.

Next, as shown in FIG. 14, a second resin member 892 is formed on the first resin layer 860A. The step of forming the second resin member 892 (second resin member forming step) is, for example, resin molding. In this embodiment, the second resin member 892 is made of the same material as the first resin member 891 . That is, the second resin member 892 has electrical insulation, and is made of a synthetic resin containing, for example, a black epoxy resin as a main component. Through the second resin member forming process, the internal electrodes 830 (the wiring layers 831 and the columnar conductors 832) are completely covered with the second resin member 892, as shown in FIG. Also, the second resin member 892 is in contact with the first resin layer 860A. In this embodiment, as shown in FIG. 14, the interface between the second resin member 892 and the first resin layer 860A is visible. The member 892 and the first resin layer 860A may be integrated. That is, the interface between the second resin member 892 and the first resin layer 860A may be formed so as not to be visually recognized.

Next, as shown in FIG. 15, the second resin member 892 is ground. In the step of grinding the second resin member 892 (second resin member grinding step), in FIG. 14, the second resin member 892 is ground from the side in which the substrate rear surface 822 faces (upward in FIG. 14). At this time, the grinding is performed until the columnar conductor 832 is exposed from the second resin member 892 . As a result, as shown in FIG. 15, the columnar conductor 832 is formed with a rear surface side exposed surface 832b exposed from the second resin member 892. Next, as shown in FIG. The back surface side exposed surface 832b faces the same direction as the substrate back surface 822, as shown in FIG. In addition, as shown in FIG. 15, the back-side exposed surface 832b is flush with the upper surface of the second resin member 892 (the surface facing away from the surface in contact with the first resin layer 860A).

Then, as shown in FIG. 16, grooves 861 are formed. The step of forming the grooves 861 (groove forming step) is by half-cut dicing using a dicing blade. Although the width of the dicing blade is not particularly limited, it is, for example, about 30 to 100 μm. In the present embodiment, in the groove forming step, grooves 861 are formed that are recessed in the direction in which the substrate main surface 821 faces from the surface in the direction in which the substrate rear surface 822 faces in FIG. 16 . The grooves 861 are formed in a grid pattern in which streaks extending along the x-direction and streaks extending along the y-direction intersect in plan view. Also, the groove 861 extends from the second resin member 892 to the first resin layer 860A. Therefore, in the groove 861, the surface of the columnar conductor 832 facing the x direction or the y direction is exposed from the second resin member 892, and the columnar conductor 832 is formed with the side exposed surface 832a. The side exposed surface 832a is connected to the back exposed surface 832b. Through the groove forming process, a second resin layer 860B covering part of the columnar conductor 832 and the wiring layer 831 is formed. The second resin layer 860B will later become the second resin layer 60B of the sealing resin 60 of the semiconductor device A1. Therefore, as shown in FIG. 16, the groove 861 is connected from the second resin layer 860B to the first resin layer 860A, and the side exposed surface 832a is exposed from the second resin layer 860B in the groove 861. . Also, through the groove forming process, the sealing resin 860 including the first resin layer 860A and the second resin layer 860B is formed. The sealing resin 860 will later become the sealing resin 60 of the semiconductor device A1. In this embodiment, the process including the second resin member forming process, the second resin member grinding process and the groove forming process corresponds to the "second resin layer forming process" described in the claims.

Next, as shown in FIG. 17, external electrodes 840 are formed to cover the surfaces of the columnar conductors 832 exposed from the sealing resin 860 . Specifically, the external electrodes 840 are formed to cover the exposed side surfaces 832a and the exposed back surfaces 832b of the columnar conductors 832 . The external electrode 840 will later become the external electrode 40 of the semiconductor device A1. The step of forming the external electrodes 840 (external electrode forming step) is by electroless plating. In this embodiment, a Ni layer, a Pd layer and an Au layer are deposited in this order by the electroless plating. At this time, the Ni layer is formed so as to be in contact with and cover the exposed side surfaces 832a and the exposed back surfaces 832b of the columnar conductors 832 . In the present embodiment, the Ni layer is also formed on the surface of the wiring layer 831 exposed from the second resin layer 860B in the trench 861 . A Pd layer is formed on the Ni layer, and an Au layer is formed on the Pd layer. Thereby, the external electrodes 840 shown in FIG. 17 are formed. Note that no Ni layer is deposited on the support substrate 820 made of Si, which is an intrinsic semiconductor material, and the external electrode 840 is not formed on the surface of the support substrate 820 exposed from the sealing resin 860 . As shown in FIG. 17, the external electrode 840 formed by the external electrode forming process includes a side covering portion 841 covering the exposed side surface 832a and a rear covering portion 842 covering the exposed rear surface 832b.

Next, as shown in FIG. 18, the substrate rear surface 822 side of the support substrate 820 is ground to thin the support substrate 820 . Although the method of grinding is not particularly limited, for example, it is performed using a mechanical grinder. By the step of grinding the support substrate 820 (support substrate grinding step), the support substrate 820 is ground with a whetstone, and the support substrate 820 is thinned.

Next, by cutting the sealing resin 860 and the support substrate 820, the semiconductor elements 810 are divided into individual pieces. The step of cutting the sealing resin 860 and the support substrate 820 (cutting step) is by blade dicing. In the blade dicing, a dicing blade thinner than the dicing blade used in the groove forming step is used. The width of the dicing blade in the cutting process is, for example, about 20-90 μm. In this embodiment, by cutting along a plurality of cutting lines CL shown in FIGS. 18 and 19, the semiconductor elements 810 are divided into individual pieces. A cutting line CL extending in the x direction shown in FIG. 19 is set so as to pass through the width direction center of the groove 861 extending in the x direction in plan view. A cutting line CL extending in the y direction shown in FIG. 19 is set so as to pass through the width direction center of the groove 861 extending in the y direction in plan view. Pieces divided by the cutting process become the semiconductor devices A1 shown in FIGS.

Through the above steps, the semiconductor device A1 shown in FIGS. 1 to 7 is manufactured. The method for manufacturing the semiconductor device A1 described above is merely an example, and the present invention is not limited to this.

Next, the effects of the semiconductor device A1 and the manufacturing method thereof according to the first embodiment will be described.

According to the semiconductor device A<b>1 , the columnar conductor 32 has the side exposed surface 321 and the back surface exposed surface 322 exposed from the sealing resin 60 . In addition, the external electrode 40 includes a side surface covering portion 41 covering the side surface side exposed surface 321 and a back surface covering portion 42 covering the rear surface side exposed surface 322. exposed to the outside of According to such a configuration, when the semiconductor device A1 is mounted on a circuit board such as an electronic device using solder, a solder fillet is formed across the side surface covering portion 41 and the back surface covering portion 42 . Therefore, the solder joint state can be visually confirmed from above and from the side of the semiconductor device A1. That is, the joint state of the solder can be easily confirmed visually without using an X-ray inspection device or the like. Furthermore, since a solder fillet is formed, the mounting strength of the semiconductor device A1 to the circuit board can be increased.

The semiconductor device A1 includes internal electrodes 30 formed by electrolytic plating and external electrodes 40 formed by electroless plating. Conventionally, lead frames have been used to form side electrodes on semiconductor devices. On the other hand, the semiconductor device A1 is wired by plating and does not use a lead frame formed of a metal plate. Wiring by plating can be made thinner than when a leadframe structure is used. Therefore, the thickness of the semiconductor device A1 can be reduced. Furthermore, as ICs and LSIs become more highly integrated, the number of terminals increases, making it necessary to miniaturize internal electrodes and the like. had limits. On the other hand, since the semiconductor device A1 forms the internal electrodes 30 by plating, it is also possible to cope with miniaturization. Therefore, it becomes possible to manufacture a semiconductor device having more terminals.

According to the semiconductor device A1, the external electrode 40 covering a part of the internal electrode 30 (columnar conductor 32) is provided. The external electrodes 40 are made of a material having higher solder wettability than the internal electrodes 30 . Therefore, when the semiconductor device A1 is mounted on the circuit board, the solder spreads over the surfaces of the external electrodes 40. FIG. Therefore, unevenness of the solder is suppressed, and the joint strength of the solder can be increased. Therefore, the mounting strength of the semiconductor device A1 to the circuit board can be increased. Further, the main material of the internal electrodes 30 (columnar conductors 32) is Cu, and an oxide film is formed on the surface of Cu by oxidation in the atmosphere. The oxide film has lower solder wettability and lower conductivity than Cu. Therefore, by covering the exposed portions of the internal electrodes 30 (the columnar conductors 32) with the external electrodes 40, it is possible to suppress a decrease in solder wettability and conductivity.

According to the method for manufacturing the semiconductor device A1, the rear surface side exposed surface 832b of the columnar conductor 832 is formed by grinding in the second resin member grinding step. Therefore, the rear exposed surface 832b has grinding traces. Therefore, the rear surface side exposed surface 832b becomes a relatively rough surface due to the grinding marks. As a result, the adhesiveness between the back surface side exposed surface 832b and the back cover portion 842 of the external electrode 840 is enhanced by the anchor effect. That is, in the semiconductor device A1, the adhesiveness between the rear surface side exposed surface 322 of the columnar conductor 32 and the rear surface covering portion 42 of the external electrode 40 is enhanced.

According to the manufacturing method of the semiconductor device A1, the exposed side surfaces 832a of the columnar conductors 832 are formed by blade dicing. Therefore, the side exposed surface 832a has cutting traces. The side exposed surface 832a becomes a relatively rough surface due to the cutting marks. As a result, the adhesiveness between the side exposed surface 832a and the side covering portion 841 of the external electrode 840 is enhanced due to the anchor effect. That is, in the semiconductor device A1, the adhesion between the side exposed surface 321 of the columnar conductor 32 and the side covering portion 41 of the external electrode 40 is enhanced.

According to the manufacturing method of the semiconductor device A1, the wiring layer 831 of the internal electrode 830 is formed on the first resin layer 860A. Since the first resin layer 860A (the first resin member 891) has been ground in the first resin member grinding step, the surface exposed in FIG. 10 has grinding marks. Therefore, the surface of the first resin layer 860A becomes a relatively rough surface due to the grinding marks. As a result, the adhesiveness between the wiring layer 831 and the first resin layer 860A increases due to the anchor effect. That is, in the semiconductor device A1, the adhesiveness between the wiring layer 31 and the first resin layer 60A is increased. Also, in the second resin member forming step, the second resin member 892 is formed on the first resin layer 860A. Therefore, due to the anchor effect, the adhesiveness between the second resin member 892 (the second resin layer 860B) and the first resin layer 860A increases. That is, in the semiconductor device A1, the adhesiveness between the first resin layer 60A and the second resin layer 60B is increased.

According to the manufacturing method of the semiconductor device A1, the supporting substrate grinding step is performed after the groove 861 is formed (after the groove forming step). As a result, warping of the semiconductor device during manufacturing due to the formation of the groove 861 can be suppressed.

20 to 23 show another embodiment of the disclosed semiconductor device and its manufacturing method. In these figures, the same or similar elements as in the above embodiment are denoted by the same reference numerals as in the above embodiment.

[Second embodiment]
FIG. 20 shows a semiconductor device according to the second embodiment. The semiconductor device A2 of the second embodiment is mainly different from the semiconductor device A1 in that the support substrate 20 is not provided.

FIG. 20 is a cross-sectional view showing the semiconductor device A2, which corresponds to FIG. 5 of the first embodiment.

Compared to the semiconductor device A1 (see FIG. 5), the semiconductor device A2 does not include the support substrate 20 and the bonding layer 50, and the element main surface 11 of the semiconductor element 10 is covered with the sealing resin 60 (first resin layer 60A). ).

The semiconductor device A2 having such a configuration is manufactured, for example, by grinding the entire supporting substrate 820 in the supporting substrate grinding step (see FIG. 18) in the manufacturing method of the semiconductor device A1. In addition, in the support substrate grinding step in this embodiment, the bonding material 850 is also removed by grinding until the element main surface 811 of the semiconductor element 810 is exposed. Therefore, the semiconductor device A2 shown in FIG. 20 does not include the bonding layer 50. As shown in FIG.

According to the semiconductor device A2, similarly to the semiconductor device A1, the columnar conductors 32 each have a side exposed surface 321 and a back exposed surface 322 exposed from the sealing resin 60. As shown in FIG. In addition, the external electrode 40 includes a side surface covering portion 41 covering the side surface side exposed surface 321 and a back surface covering portion 42 covering the rear surface side exposed surface 322. exposed to the outside of Therefore, when the semiconductor device A2 is mounted on a circuit board of an electronic device or the like using solder, a solder fillet extending over the side surface covering portion 41 and the back surface covering portion 42 is formed. It can be visually confirmed from above and from the side of A2. That is, the joint state of the solder can be easily confirmed visually without using an X-ray inspection device or the like.

According to the semiconductor device A2, the support substrate 20 and the bonding layer 50 are not provided. Therefore, the thickness of the semiconductor device A2 can be reduced by the thickness of the support substrate 20 and the bonding layer 50. FIG. Therefore, the thickness of the semiconductor device A2 can be reduced.

According to the semiconductor device A2, the element main surface 11 of the semiconductor element 10 is exposed to the outside. By adopting this configuration, the semiconductor device A2 can efficiently radiate heat generated from the semiconductor element 10 to the outside in comparison with the semiconductor device A1.

[Third embodiment]
21 and 22 show the semiconductor device according to the third embodiment. The semiconductor device A3 of the third embodiment differs from the semiconductor device A1 in that the columnar conductors 32 include projecting portions 324 .

FIG. 21 is a plan view showing the semiconductor device A3. In FIG. 21, the support substrate 20 and the bonding layer 50 are omitted, and the sealing resin 60 is indicated by an imaginary line (chain double-dashed line). 22 is a cross-sectional view taken along line XXII-XXII of FIG. 21. FIG.

In this embodiment, each columnar conductor 32 includes a plurality of protrusions 324, as shown in FIGS. The projecting portion 324 is a portion projecting from the resin contact side surface 323 . In this embodiment, the plurality of projecting portions 324 protrude one by one from the pair of resin contact side surfaces 323 of each columnar conductor 32 . Each columnar conductor 32 has a T shape in plan view, as shown in FIG. In this embodiment, the protruding portion 324 also protrudes from the portion of the wiring layer 31 that overlaps the columnar conductor 32 in plan view. Each protrusion 324 has a locking surface 325 .

The locking surface 325 is a surface protruding from the resin contact side surface 323 . In this embodiment, the angle formed by the locking surface 325 and the resin contact side surface 323 is a right angle. That is, the locking surface 325 is perpendicular to the resin contact side surface 323 . Note that the locking surface 325 may be inclined with respect to the resin contact side surface 323 . In each columnar conductor 32 , the locking surface 325 faces the same direction as the side exposed surface 321 . The locking surface 325 is in contact with the sealing resin 60 . The sealing resin 60 is interposed between the resin side surface 63 where the side surface side exposed surface 321 is exposed and the locking surface 325 .

In the semiconductor device A3 having such a configuration, for example, in the internal electrode forming step (see FIGS. 11 to 13) in the manufacturing method of the semiconductor device A1, the regions where the first plating layer 830b and the second plating layer 830c are formed are changed. Thus, the protruding portion 324 is formed.

According to the semiconductor device A3, similarly to the semiconductor device A1, the columnar conductor 32 has the exposed side surface 321 and the exposed back surface 322 exposed from the sealing resin 60, respectively. Further, the external electrode 40 includes a side surface covering portion 41 covering the side surface side exposed surface 321 and a rear surface covering portion 42 covering the rear surface side exposed surface 322. Both the side surface covering portion 41 and the rear surface covering portion 42 are the semiconductor device A3 exposed to the outside of Accordingly, when the semiconductor device A3 is mounted on a circuit board of an electronic device or the like using solder, a solder fillet is formed across the side surface covering portion 41 and the back surface covering portion 42, so that the state of solder bonding can be controlled by the semiconductor device. It can be visually confirmed from above and from the side of A3. That is, the joint state of the solder can be easily confirmed visually without using an X-ray inspection device or the like.

According to the semiconductor device A3, the columnar conductor 32 includes a projecting portion 324. The projecting portion 324 projects from the resin contact side surface 323 and has the locking surface 325 in contact with the sealing resin 60. there is According to such a configuration, even if a stress outward in the x direction (y direction) is applied to the internal electrode 30 having the side exposed surface 321 facing the x direction (y direction), the locking surface 325 is sealed. Caught on resin 60 . Therefore, the semiconductor device A3 can prevent the internal electrode 30 from coming off in the x direction (y direction).

[Fourth embodiment]
FIG. 23 shows a semiconductor device according to the fourth embodiment. The semiconductor device A4 of the fourth embodiment differs from the semiconductor device A1 in that each resin side surface 63 has no step.

FIG. 23 is a cross-sectional view showing the semiconductor device A4, which corresponds to FIG. 5 of the first embodiment.

In this embodiment, as shown in FIG. 23, on each side surface of the semiconductor device A1, the substrate side surface 23, the resin side surface 63, and the side exposed surface 321 are flush with each other.

The semiconductor device A4 having such a configuration can be produced by, for example, performing the second resin member grinding step (see FIG. 15), the groove forming step (see FIG. 16) and the external electrode forming step (FIG. 17) in the manufacturing method of the semiconductor device A1. ) is not performed, and the supporting substrate grinding step (see FIG. 18) is performed. After the support substrate grinding process, a dicing tape is attached so as to cover the entire substrate main surface 821 of the support substrate 820 . Then, without cutting the dicing tape completely, it is divided into individual pieces for each semiconductor element 810 in the same manner as in the above-described cutting step. At this time, the individual pieces of each semiconductor element 810 are not separated by the attached dicing tape. In this embodiment, when the semiconductor element 810 is divided into individual pieces, the columnar conductor 832 is formed with the side exposed surface 832a and the second resin layer 860B. Therefore, in the present embodiment, the steps including the step of forming the second resin member, the step of grinding the second resin member, and the step of dividing into individual pieces for each semiconductor element 810 are the "second resin layer It corresponds to "formation process". After that, the same process as the external electrode forming step (see FIG. 17) is performed to form external electrodes 840 . By doing so, the semiconductor device A4 having the cross-sectional shape shown in FIG. 23 can be manufactured. That is, it is possible to form a semiconductor device A4 in which each resin side surface 63 has no step.

According to the semiconductor device A4, similarly to the semiconductor device A1, the columnar conductor 32 has the exposed side surface 321 and the exposed back surface 322 exposed from the sealing resin 60, respectively. In addition, the external electrode 40 includes a side surface covering portion 41 covering the side surface side exposed surface 321 and a back surface covering portion 42 covering the rear surface side exposed surface 322. exposed to the outside of Therefore, when the semiconductor device A4 is mounted on a circuit board of an electronic device or the like using solder, a solder fillet extending over the side surface covering portion 41 and the back surface covering portion 42 is formed. It can be visually confirmed from above and from the side of A4. That is, the joint state of the solder can be easily confirmed visually without using an X-ray inspection device or the like.

In the first to fourth embodiments, by exposing the internal electrodes 30 (side exposed surfaces 321) from the four resin side surfaces 63, the external electrodes 40 that serve as terminals are formed on the respective resin side surfaces 63. However, the present invention is not limited to this. For example, the internal electrodes 30 (side exposed surfaces 321) may be exposed on each of the pair of resin side surfaces 63 facing the x direction or each of the pair of resin side surfaces 63 facing the y direction. That is, although the semiconductor devices A1 to A4 are of the so-called QFN package type, they may be of the so-called SON package type.

In the first to fourth embodiments, two external electrodes 40 are exposed from one resin side surface 63, but the number of external electrodes 40 exposed from one resin side surface 63 is is not limited to That is, the number of external electrodes 40 exposed from one resin side surface 63 may be one, three, or more. Furthermore, the number of external electrodes 40 exposed from the resin side surface 63 may be different for each resin side surface 63 .

The semiconductor device and manufacturing method thereof according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device of the present disclosure can be changed in various ways. Further, the specific processing of each step of the manufacturing method of the semiconductor device of the present disclosure can be changed in design in various ways.

A1 to A4: semiconductor device 10: semiconductor element 11: element main surface 12: element back surface 13: columnar electrode 20: support substrate 21: substrate main surface 22: substrate back surface 23: substrate side surface 30: internal electrode 31: wiring layer 31a: Base layer 31b: Plating layer 311: Wiring layer main surface 312: Wiring layer back surface 313: Side surface 32: Columnar conductor 321: Side exposed surface 322: Back surface exposed surface 323: Resin contact side surface 324: Protruding portion 325: Engagement Stop surface 40 : External electrode 41 : Side surface covering portion 42 : Back surface covering portion 50 : Bonding layer 60 : Sealing resin 60A : First resin layer 60B : Second resin layer 61 : Resin main surface 62 : Resin back surface 63 : Resin side surface 631: first side surface 632: second side surface 810: semiconductor element 811: element main surface 812: element back surface 813: columnar electrode 813a: top surface 820: support substrate 821: substrate main surface 822: substrate back surface 830: internal electrode 830a: Base layer 830b: First plating layer 830c: Second plating layer 831: Wiring layer 831a: Wiring layer main surface 831b: Wiring layer back surface 832: Columnar conductor 832a: Side exposed surface 832b: Back side exposed surface 840: External electrode 841 : Side covering portion 842 : Back covering portion 850 : Bonding material 860 : Sealing resin 860A : First resin layer 891 : First resin member 860B : Second resin layer 892 : Second resin member 861 : Groove CL : Cutting line

Claims (16)

a semiconductor element having an element main surface and an element back surface facing opposite to each other in a first direction;
a wiring layer having a wiring layer main surface and a wiring layer back surface facing opposite to each other in the first direction, the wiring layer main surface facing the element back surface and conducting to the semiconductor element;
a columnar conductor electrically connected to the wiring layer and protruding in the first direction from the rear surface of the wiring layer;
a sealing resin including a first resin layer covering the semiconductor element and the main surface of the wiring layer, and a second resin layer covering the rear surface of the wiring layer;
an external electrode exposed from the sealing resin and conducting to the columnar conductor;
a support substrate facing the main surface of the element and supporting the semiconductor element;
and
The sealing resin has a resin side surface facing in a second direction orthogonal to the first direction, a resin back surface facing in the same direction as the element back surface , and a resin main surface facing in the first direction opposite to the resin back surface. and
The columnar conductor has a side exposed surface exposed from the side surface of the resin and a back exposed surface connected to the side exposed surface and exposed from the resin back surface,
the external electrode includes a side surface covering portion covering the side exposed surface and a back surface covering portion covering the back surface side exposed surface ;
The resin side surface has a first side surface connected to the resin back surface and a second side surface connected to the resin main surface,
The first side surface is arranged inside the sealing resin relative to the second side surface when viewed in the first direction,
The first side surface and the exposed side surface are flush with each other,
the support substrate has a substrate side surface facing the second direction and contains an intrinsic semiconductor material in composition;
The substrate side surface and the second side surface are flush with each other,
A semiconductor device characterized by: The columnar conductor overlaps the second resin layer when viewed in the second direction,
2. The semiconductor device according to claim 1. The first side surface straddles the first resin layer and the second resin layer,
3. The semiconductor device according to claim 1 or 2 . The semiconductor element is provided with a columnar electrode interposed between the back surface of the element and the main surface of the wiring layer and conducting between the semiconductor element and the wiring layer.
4. The semiconductor device according to claim 1 . an interface between the first resin layer and the second resin layer is flush with the main surface of the wiring layer;
5. The semiconductor device according to claim 1 . The dimension of the first resin layer in the first direction is larger than the dimension of the second resin layer in the first direction,
6. The semiconductor device according to claim 1 . The first resin layer and the second resin layer are made of the same material,
7. The semiconductor device according to claim 1 . The columnar conductor faces a third direction orthogonal to both the first direction and the second direction, has a resin contact side surface in contact with the sealing resin, and has a resin contact side surface viewed in the first direction. and a projecting portion projecting in the third direction from
The protruding portion has a locking surface connected to the resin contact side surface and in contact with the sealing resin,
8. The semiconductor device according to claim 1 . The locking surface faces the same direction as the side exposed surface,
9. The semiconductor device according to claim 8 . further comprising a bonding layer interposed between the support substrate and the semiconductor element;
10. The semiconductor device according to claim 1 . preparing a support substrate having a substrate main surface and a substrate back surface facing opposite to each other in a first direction;
a step of mounting a semiconductor element having an element main surface and an element back surface facing opposite to each other in the first direction on the support substrate in a posture in which the element main surface and the substrate back surface are opposed to each other;
a first resin layer forming step of forming a first resin layer covering the semiconductor element while exposing the top surface of the columnar electrode formed on the back surface of the element;
forming a wiring layer having a wiring layer main surface and a wiring layer back surface facing opposite to each other in the first direction, the wiring layer main surface being in contact with the columnar electrode and the first resin layer;
forming a columnar conductor protruding in the first direction from the back surface of the wiring layer;
a second resin layer forming step of forming a second resin layer that is in contact with the first resin layer and covers a portion of the columnar conductor and the wiring layer;
an external electrode forming step of forming an external electrode covering the surface of the columnar conductor exposed from the second resin layer;
contains
The columnar conductor has a rear surface side exposed surface facing the same direction as the substrate rear surface and a side surface side exposed surface facing a second direction orthogonal to the first direction,
The exposed back surface and the exposed side surface are each exposed from the second resin layer and connected to each other,
the external electrode includes a side surface covering portion covering the side exposed surface and a back surface covering portion covering the back surface side exposed surface ;
A sealing resin is formed by the first resin layer and the second resin layer,
The sealing resin has a resin side surface facing the second direction, a resin back surface facing the same direction as the element back surface, and a resin main surface facing the opposite side of the resin back surface in the first direction. cage,
The resin side surface has a first side surface connected to the resin back surface and a second side surface connected to the resin main surface,
The first side surface is arranged inside the sealing resin relative to the second side surface when viewed in the first direction,
The first side surface and the exposed side surface are flush with each other,
the support substrate has a substrate side surface facing the second direction and contains an intrinsic semiconductor material in composition;
The substrate side surface and the second side surface are flush with each other,
A method of manufacturing a semiconductor device, characterized by: In the first resin layer forming step, after forming a first resin member covering all of the semiconductor element and the columnar electrode, the first resin member is applied until the top surface of the columnar electrode is exposed. Forming the first resin layer by grinding from the facing direction side,
12. The method of manufacturing a semiconductor device according to claim 11 . In the second resin layer forming step, after forming the second resin member covering all of the wiring layer and the columnar conductors, the second resin member is ground from the side in which the back surface of the substrate faces. Forming a second resin layer and forming the back surface side exposed surface,
13. The method of manufacturing a semiconductor device according to claim 11 or 12. In the second resin layer forming step, by half-cut dicing using a dicing blade, by forming a groove connecting the second resin layer to the first resin layer, exposed from the second resin layer in the groove forming the side exposed surface;
14. The method of manufacturing a semiconductor device according to claim 11 . The external electrode forming step is by electroless plating,
15. The method of manufacturing a semiconductor device according to claim 11 . After the second resin layer forming step, further comprising a supporting substrate grinding step of grinding the supporting substrate from the main surface of the substrate toward the back surface of the substrate,
16. The method of manufacturing a semiconductor device according to claim 11 .

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