JP7180911B2 - Trays for semiconductor integrated circuits - Google Patents

Description

The present invention relates to a semiconductor integrated circuit tray for housing a semiconductor integrated circuit (IC, etc.), and more particularly, the solder resist on the copper foil portion of the substrate of the semiconductor integrated circuit having relatively large dimensions is scratched or peeled off. The present invention relates to a tray for a semiconductor integrated circuit that suppresses

A semiconductor integrated circuit tray is formed with a plurality of pockets for accommodating semiconductor integrated circuits. In a conventional semiconductor integrated circuit tray (hereinafter also simply referred to as a "tray"), a supporting step portion for supporting the peripheral portion of the substrate of the semiconductor integrated circuit from below extends horizontally from the peripheral wall of the pocket. extends to Due to the presence of the support step, even when supporting a substrate of a grid array semiconductor integrated circuit such as PGA or BGA, the terminals on the bottom surface of the semiconductor integrated circuit may come into contact with the inner bottom surface of the pocket. do not have.

JP 2011-238660 A Japanese Patent No. 5051797

However, for large-sized semiconductor integrated circuit substrates having dimensions of, for example, 40 mm x 40 mm square or more, the contact area between the support surface of the support step formed in the pocket of the tray and the support surface is large. Sometimes, when the solder resist on the copper foil portion of the peripheral part of the bottom surface of the substrate of the semiconductor integrated circuit accommodated in the pocket of the tray contacts and rubs against the support surface of the support step of the tray, the solder resist is rubbed. Scratches and peeling may occur on the surface.

Alternatively, if the substrate of the semiconductor integrated circuit is warped due to an external force (stress) during manufacture or transportation of the semiconductor integrated circuit, the substrate may be damaged by repeatedly contacting the sharp edge of the support step. The solder resist applied to the top and bottom of the device may peel off little by little. Here, the case where the warp occurs includes the case where the semiconductor integrated circuit receives an external force and instantly warps.

Therefore, a semiconductor integrated circuit tray is provided that can prevent the solder resist applied to the top and bottom surfaces of the substrate of the semiconductor integrated circuit from being scratched or peeled off.

In a semiconductor integrated circuit tray having a plurality of pockets configured to accommodate a plurality of semiconductor integrated circuits individually, the supporting surface of the supporting stepped portion for supporting the peripheral edge portion of the substrate of the semiconductor integrated circuit from below is a horizontal plane. , extending from the wall of the peripheral edge of each pocket toward the inner side (closer to the center) of the pocket while being slightly inclined downward with respect to To provide a semiconductor integrated circuit tray characterized by being rounded with a predetermined radius of curvature.

In one embodiment, the depression angle of the support surface, which is slightly downward with respect to the horizontal plane, is an angle selected from the range of 3 degrees to 10 degrees.

In one embodiment, the predetermined radius of curvature is a radius of curvature selected from the range of 0.2 mm to 0.8 mm.

In a further embodiment, the pocket is configured to accommodate a predetermined semiconductor integrated circuit having a substantially rectangular substrate of 40 mm×40 mm square or more in plan view. As an example, it is configured to accommodate a semiconductor integrated circuit having a substrate of approximately 40 mm×60 mm in plan view.

In addition, recesses are formed on the back side of each pocket so that when a plurality of the semiconductor integrated circuit trays are superimposed, the semiconductor contained in the pocket of the semiconductor integrated circuit tray at the lower stage is placed on top of the semiconductor integrated circuit tray. While the ceiling surface of the stepped portion covering the periphery of the upper surface of the integrated circuit substrate has an elevation angle of 3 degrees to 10 degrees, from the peripheral wall of the recess of the upper semiconductor integrated circuit tray to the inside of the recess. The stepped portion is characterized in that it is rounded with a radius of curvature of 0.2 mm to 0.8 mm along the extended edge of the ceiling surface.

1 is a perspective view of a semiconductor integrated circuit tray in one embodiment; FIG. 1 is a perspective view showing (a) a top surface and (b) a bottom surface of a substrate of a semiconductor integrated circuit in one example; FIG. (a) A plan view of a semiconductor integrated circuit tray in one embodiment. (b) A cross-sectional view of the semiconductor integrated circuit tray taken along line AA shown in FIG. 3(a). (c) The figure which expands and shows the part enclosed with the dashed-dotted line in FIG.3(b). (a) An enlarged view showing a state in which a warp-free substrate of a semiconductor integrated circuit is accommodated in a tray. (b) An enlarged view showing a state in which a warped substrate of a semiconductor integrated circuit is accommodated in a tray. (a) A plan view of the back side of the tray for semiconductor integrated circuit. (b) A cross-sectional view of the semiconductor integrated circuit tray taken along line BB shown in FIG. 5(a). (c) The figure which expands and shows the part enclosed with the dashed-dotted line in FIG.5(b). (a) Diagram showing a stack of trays. (b) A view showing a state in which the stack of trays is turned upside down. Sectional drawing which expands and shows the inside of the tray of the part enclosed with the dashed-dotted line in FIG.6(b).

A semiconductor integrated circuit tray according to the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a perspective view of a semiconductor integrated circuit tray 1 in one embodiment. A plurality of pockets 2 are formed on the surface side of the tray 1 for individually accommodating semiconductor integrated circuit substrates 30 (see FIGS. 2(a) and 2(b)). The semiconductor integrated circuit tray 1 is made of, for example, a hard plastic material, and has three pockets so as to accommodate three semiconductor integrated circuits. However, in other embodiments, the semiconductor integrated circuit tray 1 may have a number of pockets other than three. Further, a support step portion 4 for supporting the peripheral edge portion of the substrate of the semiconductor integrated circuit from below extends slightly (for example, about 5 mm) toward the inside of the pocket 2 from the wall defining the peripheral edge of the pocket 2 . is doing. The substrate 30 of the semiconductor integrated circuit to be accommodated in the pocket 2 of the tray 1 is supported from below by the support step portion 4 as described above.

FIG. 2(a) shows the top surface of the substrate 30 of the semiconductor integrated circuit in one example. A solder resist 44 of a copper foil portion can be applied to the upper surface 42 of the substrate 30 of the semiconductor integrated circuit.

FIG. 2(b) shows the bottom surface 32 of the substrate 30 of the semiconductor integrated circuit in one example. As shown in FIG. 2B, a plurality of terminals 34 are provided on the bottom surface 32 when the semiconductor integrated circuit substrate 30 is a grid array (PGA/BGA) substrate. Furthermore, a solder resist 44 may be applied to this bottom surface 32 .

FIG. 3(a) is a plan view of the surface side of the semiconductor integrated circuit tray 1 of the present invention. In one embodiment, each pocket 2 is generally rectangular in plan view. In other embodiments, each pocket 2 may be formed in a shape other than a square according to the shape of the substrate of the semiconductor integrated circuit to be accommodated in the pocket 2. FIG. The tray 1 of the present invention is suitable for accommodating a large-sized semiconductor integrated circuit that is relatively prone to warping, and has a size of approximately 40 mm x 40 mm square or more in plan view (particularly, 50 mm x 50 mm square or more in plan view). A sufficient effect can be obtained when used as a tray for a predetermined semiconductor integrated circuit having a rectangular substrate.

FIG. 3(b) is a cross-sectional view of the tray 1 taken along line AA shown in FIG. 3(a). When stacking a plurality of trays 1, the user of the trays 1 stacks the plurality of trays 1 by engaging the vicinity of the outer peripheral wall 14 formed along the outer peripheral edges of the trays 1 with each other. can be positioned. Also, even if the substrate 30 of the semiconductor integrated circuit receives vibrations during transportation of the tray 1 and moves horizontally, the supporting step portion 4 in the pocket 2 of the tray 1 is not connected to the terminals 34 (see FIG. 2 ( b)) is designed not to come into contact with

FIG.3(c) is a figure which expands and shows the part enclosed by the dashed-dotted line in FIG.3(b). In the embodiment shown in FIG. 3(c), the supporting surface 6 of the supporting stepped portion 4 for supporting the peripheral portion 36 of the substrate 30 of the semiconductor integrated circuit from below has a depression angle of 5 degrees. Extending from the peripheral wall of the pocket 2 to the inside of the pocket 2, the support step 4 has a radius of curvature of 0.3 mm along the extended edge 8 of the support surface 6. That is, it is rounded. Even if the peripheral edge portion 36 of the substrate 30 of the semiconductor integrated circuit repeatedly contacts the leading end edge 8 of the support step portion 4 formed with such a roundness, the solder resist 44 on the bottom surface 32 of the substrate 30 is worn away. never.

FIG. 4(a) shows a state in which a warp-free substrate 30 of a semiconductor integrated circuit is accommodated in the pocket 2 of the tray 1 of the present invention. The supporting surface 6 of the supporting stepped portion 4 for supporting the peripheral edge portion 36 of the substrate 30 of the semiconductor integrated circuit from below extends from the peripheral edge wall of the pocket 2 to the inside of the pocket 2 while being slightly downwardly inclined with respect to the horizontal plane. As a result, only the edge of the peripheral portion 36 of the bottom surface 32 of the substrate 30 of the semiconductor integrated circuit to be supported by the support step 4 in the pocket 2 contacts the support surface 6 . In other words, the semiconductor integrated circuit tray 1 of the present invention has a very small contact area between the bottom surface 32 and the peripheral portion 36 of the substrate 30 of the semiconductor integrated circuit without warping. It has the advantage that the solder resist 44 on the copper foil portion of the 1 is less likely to be scratched.

FIG. 4(b) shows the warped substrate 30a of the semiconductor integrated circuit accommodated in the pocket 2 of the tray 1 of the present invention. Since the support surface 6 of the support step 4 in the pocket 2 of the tray 1 extends from the wall of the pocket 2 to the inside of the pocket 2 while being slightly inclined downward with respect to the horizontal plane, the substrate 30a of the semiconductor integrated circuit is In the case where the substrate 30a of the semiconductor integrated circuit to be supported by the supporting stepped portion 4 in the pocket 2 is warped, the peripheral edge portion 36 of the bottom surface 32 may become the supporting surface of the supporting stepped portion 4 depending on the degree of warping of the semiconductor integrated circuit substrate 30a. Gradually (gently) touch 6. Furthermore, since the leading end edge 8 of the support step portion 4 is rounded, the solder resist 44 on the bottom surface 32 of the substrate 30a of the semiconductor integrated circuit is less likely to wear out. The tray 1 of the present invention can thus also prevent the solder resist on the bottom surface 32 of the warped substrate 30a of the semiconductor integrated circuit from being scratched or peeled off.

FIG. 5(a) is a plan view showing the back side of the semiconductor integrated circuit tray 1a in one embodiment. In this semiconductor integrated circuit tray 1a, a recess 16 is formed at a position on the back side of the pocket 2, and this recess 16 is located in the pocket 2 of the lower tray 1a when a plurality of trays 1a are stacked. It is configured to cover the upper side of the substrate of the semiconductor integrated circuit to be housed therein. In one embodiment, the opening of the recess 16 is generally rectangular in plan view. Additionally, a step 18 extends from the peripheral wall within the recess 16 .

FIG. 5(b) is a sectional view of the tray 1a taken along line BB shown in FIG. 5(a). Also, FIG. 5(c) is an enlarged view of a portion surrounded by a dashed line in FIG. 5(b). The ceiling surface 20 of the stepped portion 18 of the recess 16 of the tray 1a extends inward from the peripheral wall of the recess 16 while having an elevation angle of 3 to 10 degrees (5 degrees elevation angle in FIG. 5(c)). In addition, along the boundary between the edge 22 of the stepped portion 18 and the side wall 26, a radius of curvature of 0.2 mm to 0.8 mm (a radius of curvature of 0.3 mm in FIG. 5C) is rounded. is formed.

FIG. 6(a) shows a stack in which a plurality of trays 1a are stacked and bundled with a binding band 28. FIG. The tray 1a-3 at the topmost position in the illustrated stack is used as a lid for the stack without containing the substrate 30 of the semiconductor integrated circuit. FIG. 6(b) shows the state when the stack is accidentally or intentionally turned upside down.

FIG. 7 is an enlarged cross-sectional view showing the inside of the tray surrounded by a dashed line in FIG. 6(b). The ceiling surface 20 of the stepped portion 18 of the recess 16 extends to the inside of the recessed portion 16 while having an elevation angle of 3 to 10 degrees, and the end edge 22 of the extended tip of the stepped portion 18 is rounded. When the stack of trays is turned upside down, the semiconductor integrated circuit which has been supported by the support surface 6 of the support step 4 of the pocket 2 of the tray 1a-2 until then. The substrate 30b falls into the recess 16 of the tray 1a-3 and is gently supported from below by the ceiling surface 20 of the stepped portion 18 which is slightly downwardly inclined from the wall of the recess 16. As shown in FIG. Further, even if the upper surface 42 of the substrate 30b of the semiconductor integrated circuit contacts the tip edge 22 of the stepped portion 18, the tip edge 22 of the stepped portion 18 inclines slightly downward with respect to the horizontal plane and the tip edge 22 is rounded. , the solder resist 44 on the upper surface 42 of the substrate 30b is less likely to be scratched.

As described above, the semiconductor integrated circuit trays 1 and 1a of the present invention have the depression angle of the stepped portion in the pocket and/or the elevation angle of the stepped portion in the recess, and the stepped support portion and/or the leading edge of the stepped portion. By combining with the formed roundness, the solder resist applied to the upper surface and the lower surface of the substrate of the semiconductor integrated circuit to be accommodated in the pocket can be prevented from being scratched or peeled off. there is

REFERENCE SIGNS LIST 1 Tray 1a Tray 1a-1 Tray 1a-2 Tray 1a-3 Tray 2 Pocket 4 Supporting stepped portion 6 Supporting surface 8 Leading edge (of supporting stepped portion) 10 Inside (of pocket) Bottom surface 12 Side wall 14 Peripheral wall 16 Recess 18 Stepped portion 20 Ceiling surface 22 Leading edge 24 Back surface 26 Side wall 28 Binding band 30 Semiconductor integrated circuit substrate 30a Semiconductor integrated Circuit substrate 30b Semiconductor integrated circuit substrate 32 Bottom surface 34 Terminal 36 Peripheral edge
4 2... Upper surface 44... Solder resist 46... Terminal 48... Periphery

Claims (5)

In a semiconductor integrated circuit tray having a plurality of pockets configured to individually accommodate a plurality of semiconductor integrated circuits,
While the supporting surface of the supporting step for supporting the peripheral edge of the substrate of the semiconductor integrated circuit from below has a depression angle of 3 to 10 degrees with respect to the horizontal plane, the peripheral edge of each pocket is substantially perpendicular to the pocket. and the supporting stepped portion is rounded with a predetermined radius of curvature along the extended edge of the supporting surface. . 2. The semiconductor integrated circuit according to claim 1, wherein said slope has a slope connected to an upper side of said substantially vertical wall of said peripheral edge, said slope being formed so as to increase an opening area of said pocket toward an entrance of said pocket. tray. 3. The semiconductor integrated circuit tray according to claim 1, wherein said predetermined radius of curvature is selected from the range of 0.2 mm to 0.8 mm. 4. The semiconductor integrated circuit according to claim 3, wherein said pocket is constructed so as to accommodate a predetermined semiconductor integrated circuit having a substantially rectangular substrate of 40 mm×40 mm square or more in plan view. tray. A recess is formed on the back side of each pocket, and the semiconductor integrated circuit accommodated in the pocket of the lower semiconductor integrated circuit tray when the plurality of semiconductor integrated circuit trays are superimposed. While the ceiling surface of the step covering the peripheral edge of the upper surface of the substrate has an elevation angle of 3 degrees to 10 degrees, from the peripheral wall of the recess of the upper semiconductor integrated circuit tray to the inside of the recess Claim 1, characterized in that the stepped portion is rounded with a curvature radius of 0.2 mm to 0.8 mm along the edge of the ceiling surface where the stepped portion extends. 5. The semiconductor integrated circuit tray according to any one of 1 to 4.

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