JP7181699B2 - Semiconductor laser device - Google Patents

Description

The present invention relates to a semiconductor laser device.

Patent Document 1 discloses a semiconductor laser device. This semiconductor laser device includes a double heterostructure having an n-type clad layer, an active layer and a p-type clad layer. A ridge stripe made of a p-type clad layer is formed on the p-type clad layer. A contact layer is formed on top of the p-type clad layer. This contact layer covers the entire top of the p-type cladding layer.

JP 2007-103783 A

An object of one embodiment of the present invention is to provide a semiconductor laser device capable of improving the output of laser light.

In one embodiment of the present invention, a first semiconductor layer of a first conductivity type, an active layer formed on the first semiconductor layer, and formed so as to protrude above the active layer, in plan view, a current confinement layer of a second conductivity type including a top portion having an area smaller than that of the active layer; and a contact layer.

According to this semiconductor laser device, the contact layer functions as a current constriction contact layer that constricts the current supplied to the current confinement layer. Thereby, the current constriction effect by the contact layer and the current confinement effect by the current confinement layer can be obtained. As a result, the directivity of the current flowing through the active layer can be improved, so that the output of laser light can be improved.

FIG. 1 is an exploded perspective view showing a stem for a semiconductor laser device on which a semiconductor laser device according to a first embodiment of the present invention is mounted. FIG. 2 is a circuit diagram showing the electrical structure of the stem for the semiconductor laser device shown in FIG. 3 is a perspective view of the semiconductor laser device shown in FIG. 1. FIG. 4 is a partially cutaway perspective view of the semiconductor laser device shown in FIG. 3. FIG. 5 is a plan view of the semiconductor laser device shown in FIG. 3. FIG. FIG. 6a is a cross-sectional view taken along line VIa-VIa shown in FIG. 6b is a cross-sectional view along line VIb-VIb shown in FIG. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. FIG. 8 is an enlarged view of area VIII shown in FIG. 6a. 9A to 9D are process diagrams showing an example of a method of manufacturing the semiconductor laser device shown in FIG. 10A is a cross-sectional view for explaining an example of a method of manufacturing the semiconductor laser device shown in FIG. 3. FIG. FIG. 10B is a cross-sectional view showing a step after FIG. 10A. FIG. 10C is a cross-sectional view showing a step after FIG. 10B. FIG. 10D is a cross-sectional view showing a step after FIG. 10C. FIG. 10E is a cross-sectional view showing a step after FIG. 10D. FIG. 10F is a cross-sectional view showing a step after FIG. 10E. FIG. 10G is a cross-sectional view showing a step after FIG. 10F. FIG. 10H is a cross-sectional view showing a step after FIG. 10G. FIG. 10I is a cross-sectional view showing a step after FIG. 10H. FIG. 11 is a graph showing characteristics of the semiconductor laser device shown in FIG. FIG. 12 is a graph showing characteristics of the semiconductor laser device shown in FIG. FIG. 13 is a graph showing characteristics of the semiconductor laser device shown in FIG. FIG. 14 is a cross-sectional view showing a semiconductor laser device according to a second embodiment of the invention. 15A to 15D are process diagrams showing an example of a method of manufacturing the semiconductor laser device shown in FIG. 16A is a cross-sectional view for explaining an example of a method of manufacturing the semiconductor laser device shown in FIG. 14. FIG. FIG. 16B is a cross-sectional view showing a step after FIG. 16A. FIG. 16C is a cross-sectional view showing a step after FIG. 16B. FIG. 16D is a cross-sectional view showing a step after FIG. 16C. FIG. 16E is a cross-sectional view showing a step after FIG. 16D. FIG. 16F is a cross-sectional view showing a step after FIG. 16E. FIG. 16G is a cross-sectional view showing a step after FIG. 16F. FIG. 16H is a cross-sectional view showing a step after FIG. 16G. FIG. 16I is a cross-sectional view showing a step after FIG. 16H. FIG. 16J is a cross-sectional view showing a step after FIG. 16I.

Embodiments of the present invention will be specifically described below with reference to the accompanying drawings.
FIG. 1 is an exploded perspective view showing a semiconductor laser device stem 2 on which a semiconductor laser device 1 according to a first embodiment of the present invention is mounted.
Referring to FIG. 1, a semiconductor laser device stem 2 includes a stem base 3, a first lead terminal 4, a second lead terminal 5, a third lead terminal 6, a first insulator 7, a second insulator 8, a sub It includes a mount 9 , a semiconductor laser device 1 , a semiconductor light emitting device 10 , a first conductor 12 , a second conductor 13 , a cap 14 and a condenser lens 15 .

Stem base 3 includes a plate-like member made of metal (for example, made of iron). The stem base 3 is disc-shaped in this embodiment. The stem base 3 has a first surface 16 on one side, a second surface 17 on the other side, and a side surface 18 connecting the first surface 16 and the second surface 17 .
A plurality of (three in this embodiment) notches are formed at intervals in an arbitrary region on the side surface 18 of the stem base 3 . The plurality of notches includes first notch 19 , second notch 20 and third notch 21 .

The first notch 19 is recessed toward the central portion of the stem base 3 . The second cutout portion 20 and the third cutout portion 21 are each recessed in a V shape toward the central portion of the stem base 3 .
The second notch 20 and the third notch 21 face each other with the center of the stem base 3 interposed therebetween. The first notch 19 , the second notch 20 and the third notch 21 may indicate the arrangement of the first lead terminal 4 , the second lead terminal 5 and the third lead terminal 6 .

The first lead terminal 4 , the second lead terminal 5 and the third lead terminal 6 are provided on the second surface 17 side of the stem base 3 with a space therebetween. The first lead terminal 4 , the second lead terminal 5 , and the third lead terminal 6 each extend along the normal direction of the second surface 17 in a rod shape, a columnar shape, or an axial shape.
The first lead terminal 4 is connected to the second surface 17 of the stem base 3 . Thereby, the first lead terminal 4 is electrically connected to the stem base 3 .

The second lead terminal 5 includes a lead portion 22 that extends from the second surface 17 side of the stem base 3 to the first surface 16 side of the stem base 3 . A lead portion 22 of the second lead terminal 5 is led out through a first through hole 23 formed in the stem base 3 .
The third lead terminal 6 includes a lead portion 24 that extends from the second surface 17 side of the stem base 3 to the first surface 16 side of the stem base 3 . A lead portion 24 of the third lead terminal 6 is led out through a second through hole 25 formed in the stem base 3 .

The first insulator 7 is interposed between the second lead terminal 5 and the stem base 3 inside the first through hole 23 . The first insulator 7 electrically insulates the second lead terminal 5 from the stem base 3 . The first insulator 7 supports the second lead terminal 5 .
The second insulator 8 is interposed between the third lead terminal 6 and the stem base 3 inside the second through hole 25 . A second insulator 8 electrically isolates the third lead terminal 6 from the stem base 3 . A second insulator 8 supports the third lead terminal 6 .

Submount 9 is provided on first surface 16 of stem base 3 . Submount 9 includes a block-shaped or plate-shaped member made of silicon, aluminum nitride, or metal (for example, iron).
The submount 9 may be formed integrally with the first surface 16 of the stem base 3 . The submount 9 may be arranged on the peripheral edge side of the stem base 3 with respect to the central portion of the stem base 3 in a plan view seen from the normal direction of the first surface 16 of the stem base 3 .

The submount 9 has a first mounting surface 26 on which the semiconductor laser device 1 is mounted. The first mounting surface 26 is oriented toward the central portion of the stem base 3 . The first mounting surface 26 extends along the normal direction of the first surface 16 of the stem base 3 .
The semiconductor laser device 1 is mounted on the first mounting surface 26 of the submount 9 . A semiconductor laser device 1 is electrically connected to a first lead terminal 4 via a stem base 3 .

Semiconductor light emitting device 10 may include a photodiode. Semiconductor light emitting device 10 is mounted on first surface 16 of stem base 3 . The semiconductor light emitting device 10 is mounted on the first surface 16 of the stem base 3 in a region facing the submount 9 with the central portion of the stem base 3 interposed therebetween.
In this embodiment, the semiconductor light emitting device 10 is mounted in a recess portion 27 formed by digging the first surface 16 of the stem base 3 . The recessed portion 27 has a second mounting surface 28 on which the semiconductor light emitting device 10 is mounted. A second mounting surface 28 is formed at the bottom of the recess portion 27 . Semiconductor light emitting device 10 is electrically connected to first lead terminal 4 via stem base 3 .

The first conductor 12 may be a bonding wire. A first conducting wire 12 electrically connects the semiconductor laser device 1 and the second lead terminal 5 . More specifically, the first conducting wire 12 is connected to the lead portion 22 of the second lead terminal 5 . Thereby, the semiconductor laser device 1 is electrically connected to the second lead terminal 5 through the first conducting wire 12 .
The second conducting wire 13 may be a bonding wire. Second conducting wire 13 electrically connects semiconductor light emitting device 10 and third lead terminal 6 . More specifically, the second conducting wire 13 is connected to the lead-out portion 24 of the third lead terminal 6 . Thereby, the semiconductor light emitting device 10 is electrically connected to the third lead terminal 6 via the second conducting wire 13 .

Cap 14 includes a tubular member made of metal (for example, iron). A cap 14 is provided on the first surface 16 of the stem base 3 . The cap 14 covers the submount 9 , the semiconductor laser device 1 , the semiconductor light emitting device 10 , the lead portion 22 of the second lead terminal 5 and the lead portion 24 of the third lead terminal 6 . Cap 14 more specifically includes opposing walls 29 , sidewalls 30 and flanges 31 .

The opposing wall 29 of the cap 14 is formed in a plate shape (disc shape in this embodiment). A facing wall 29 of the cap 14 faces the first surface 16 of the stem base 3 . A side wall 30 of the cap 14 is formed in a cylindrical shape (cylindrical shape in this embodiment). A side wall 30 of the cap 14 is erected on the outer peripheral edge of the facing wall 29 so that an opening 32 is defined on the opposite side of the facing wall 29 of the cap 14 .

A flange 31 of the cap 14 protrudes from the open end of the opening 32 toward the side opposite to the opening 32 . The flange 31 of the cap 14 is formed in an annular shape (annular shape in this embodiment) along the open end of the opening 32 . The cap 14 is fixed to the stem base 3 by attaching the flange 31 to the first surface 16 of the stem base 3 .
A light extraction window 33 is formed in the cap 14 . The light extraction window 33 extracts laser light generated by the semiconductor laser device 1 from inside the cap 14 to outside the cap 14 . The light extraction window 33 is formed in the opposing wall 29 of the cap 14 in this embodiment.

The condenser lens 15 is a blocking member that has translucency and blocks the light extraction window 33 . A condenser lens 15 is attached to the cap 14 so as to close the light extraction window 33 . The condensing lens 15 closes the light extraction window 33 from the inside of the cap 14 in this form. The condenser lens 15 may block the light extraction window 33 from the outside of the cap 14 . The condenser lens 15 enhances the directivity of the laser beam of the semiconductor laser device 1 by condensing.

FIG. 2 is a circuit diagram showing the electrical structure of the stem 2 for a semiconductor laser device.
Referring to FIG. 2, semiconductor laser device 1, in this embodiment, includes stem base 3 in such a manner that the cathode is electrically connected to first lead terminal 4 and the anode is electrically connected to second lead terminal 5. is mounted on the
In this embodiment, the semiconductor light emitting device 10 is mounted on the stem base 3 in such a manner that the cathode is electrically connected to the third lead terminal 6 and the anode is electrically connected to the first lead terminal 4. .

The connection mode of the semiconductor laser device 1 and the semiconductor light emitting device 10 is arbitrary. The semiconductor laser device 1 may be mounted in such a manner that the anode is electrically connected to the first lead terminal 4 and the cathode is electrically connected to the second lead terminal 5 . Moreover, the semiconductor light emitting device 10 may be mounted in such a manner that the anode is electrically connected to the third lead terminal 6 and the cathode is electrically connected to the first lead terminal 4 .

FIG. 3 is a perspective view showing the semiconductor laser device 1. FIG. FIG. 4 is a partially cutaway perspective view showing the semiconductor laser device 1. FIG. FIG. 5 is a plan view showing the semiconductor laser device 1. FIG. FIG. 6a is a cross-sectional view taken along line VIa-VIa shown in FIG. 6b is a cross-sectional view along line VIb-VIb shown in FIG. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. FIG. 8 is an enlarged view of area VIII shown in FIG. 6a.

3 to 7, semiconductor laser device 1 includes a substrate 41, a semiconductor laminated structure 42, an insulating layer 43, a base electrode layer 44, a first terminal electrode layer 45 and a second terminal electrode layer .
The substrate 41 is made of a semiconductor substrate formed in a rectangular parallelepiped shape in this embodiment. The semiconductor substrate contains GaAs (gallium-arsenide). The substrate 41 may be doped with Si (silicon) as an n-type impurity.

The substrate 41 includes a first major surface 47 on one side, a second major surface 48 on the other side, and a substrate side surface 49 connecting the first major surface 47 and the second major surface 48 . The substrate side surface 49 is a cut surface (more specifically, a cleaved surface) in this embodiment.
The substrate side surface 49 includes a pair of first substrate side surfaces 51 extending along the longitudinal direction and a pair of second substrate side surfaces 52 extending along the width direction. In this embodiment, the first main surface 47 and the second main surface 48 of the substrate 41 are formed in a rectangular shape in plan view (hereinafter simply referred to as "plan view") as seen from their normal direction.

Hereinafter, the longitudinal direction of the substrate 41 is simply referred to as "longitudinal direction X". Further, the lateral direction of the substrate 41 is simply referred to as "transverse direction Y". Further, the normal direction of the first main surface 47 and the second main surface 48 of the substrate 41 is simply referred to as "normal direction Z".
The length L1 of the first substrate side surface 51 may be 300 μm or more and 400 μm or less. The length L2 of the second substrate side surface 52 may be 100 μm or more and 200 μm or less. The thickness of the substrate 41 may be 50 μm or more and 150 μm or less.

The semiconductor laminated structure 42 is formed on the first major surface 47 of the substrate 41 . The semiconductor laminate structure 42 is a layer that generates light. The wavelength of light generated by the semiconductor laminated structure 42 is 630 nm or more and 680 nm or less. The semiconductor laminate structure 42 produces light in the red region.
The semiconductor laminate structure 42 has a semiconductor side surface 53 along the substrate side surface 49 of the substrate 41 . The semiconductor side surface 53 is a cut surface (more specifically, a cleaved surface) in this embodiment. The semiconductor side surface 53 includes a pair of first semiconductor side surfaces 54 extending along the longitudinal direction X and a pair of second semiconductor side surfaces 55 extending along the lateral direction Y. As shown in FIG.

A pair of second semiconductor side surfaces 55 extending along the lateral direction Y form resonator end surfaces of the semiconductor laminated structure 42 . The light generated by the semiconductor laminated structure 42 is amplified by stimulated emission while reciprocating between the pair of second semiconductor side surfaces 55 .
A part of the amplified light is extracted outside the semiconductor laminated structure 42 as laser light from the pair of second semiconductor side surfaces 55 . The semiconductor laser device 1 is mounted on the first mounting surface 26 (see FIG. 1) of the submount 9 with one of the pair of second semiconductor side surfaces 55 facing the light extraction window 33 .

The semiconductor laminated structure 42 is formed by laminating a plurality of semiconductor layers (compound semiconductor layers) containing at least one of In (indium), Ga (gallium), Al (aluminum), P (phosphorus), and As (arsenic). It has a laminated structure. A plurality of semiconductor layers (compound semiconductor layers) have different compositions.
In this embodiment, the semiconductor laminated structure 42 includes an n-type buffer layer 61, an n-type clad layer 62 (first semiconductor layer), an active layer 63, and a p-type clad layer 64 as an example of a plurality of semiconductor layers (compound semiconductor layers). (second semiconductor layer), p-type protective layer 65 , p-type current confinement layer 66 and p-type contact layer 67 .

N-type buffer layer 61 is formed on first main surface 47 of substrate 41 . The n-type buffer layer 61 contains GaAs (gallium-arsenic). The n-type buffer layer 61 may be doped with Si (silicon) as an n-type impurity.
The n-type impurity concentration of n-type buffer layer 61 may be 1.0×10 ¹⁷ cm ⁻³ or more and 1.0×10 ¹⁹ cm ⁻³ or less (for example, about 2.0×10 ¹⁸ cm ⁻³ ). . The thickness of n-type buffer layer 61 may be 500 Å or more and 2000 Å or less (for example, about 1000 Å).

The n-type clad layer 62 is formed on the n-type buffer layer 61 . The n-type cladding layer 62 contains InGaAlP (indium-gallium-aluminum-phosphorus) in this form. The n-type cladding layer 62 may be doped with Si (silicon) as an n-type impurity.
The n-type impurity concentration of the n-type cladding layer 62 may be 1.0×10 ¹⁷ cm ⁻³ or more and 1.0×10 ¹⁹ cm ⁻³ or less. The thickness of the n-type cladding layer 62 may be 20000 Å or more and 40000 Å or less (for example, about 30000 Å).

An active layer 63 is formed on the n-type clad layer 62 . The active layer 63 may have a quantum well structure including quantum well layers and barrier layers. The active layer 63 may have a multi-quantum well structure in which quantum well layers and barrier layers are alternately stacked for a plurality of periods.
The barrier layer has a bandgap greater than that of the quantum well layer. The quantum well layers may contain InGaP (indium-gallium-phosphorus). The barrier layer may comprise InGaAlP (Indium-Gallium-Aluminum-Phosphorus).

A p-type clad layer 64 is formed on the active layer 63 . The p-type cladding layer 64 contains InGaAlP (indium-gallium-aluminum-phosphorus) in this form. The p-type cladding layer 64 may be doped with Mg (magnesium) as a p-type impurity.
The p-type impurity concentration of the p-type cladding layer 64 may be 1.0×10 ¹⁷ cm ⁻³ or more and 1.0×10 ¹⁹ cm ⁻³ or less. The thickness of p-type cladding layer 64 may be 1000 Å or more and 4000 Å or less (for example, about 2000 Å).

The n-type clad layer 62, the active layer 63 and the p-type clad layer 64 form a double heterostructure layer. The n-type cladding layer 62 supplies electrons to the active layer 63 . The p-type cladding layer 64 supplies holes to the active layer 63 . Electrons from n-type cladding layer 62 and holes from p-type cladding layer 64 recombine in active layer 63 . Light is thereby generated in the active layer 63 .

A p-type protective layer 65 is formed on the p-type cladding layer 64 . The p-type protective layer 65 protects the p-type clad layer 64 and suppresses variations in the thickness of the p-type clad layer 64 . More specifically, the p-type protective layer 65 is formed as an etching stop layer and suppresses overetching of the p-type cladding layer 64 . P-type protective layer 65 includes a semiconductor material having a different composition than p-type current confinement layer 66 .

The p-type protective layer 65 contains InGaP (indium-gallium-phosphorus) in this form. The p-type protective layer 65 may be doped with Mg (magnesium) as a p-type impurity.
The p-type impurity concentration of the p-type protective layer 65 may be 1.0×10 ¹⁷ cm ⁻³ or more and 1.0×10 ¹⁹ cm ⁻³ or less. The thickness of p-type protective layer 65 may be 50 Å or more and 400 Å or less (for example, about 150 Å).

The p-type current confinement layer 66 is formed on the p-type protective layer 65 at the center in the lateral direction Y in plan view. Also, the p-type current confinement layer 66 is formed in a strip shape extending along the longitudinal direction X. As shown in FIG.
The p-type current confinement layer 66 is formed to protrude above the p-type protective layer 65 in the normal direction Z. As shown in FIG. The p-type current confinement layer 66 is formed in a trapezoidal shape (mesa shape). The p-type current confinement layer 66 has a top portion 71 , a base portion 72 , and side portions 73 connecting the top portion 71 and the base portion 72 .

The top portion 71 of the p-type current confinement layer 66 has an area smaller than that of the active layer 63 in plan view. The top portion 71 of the p-type current confinement layer 66 has an area smaller than that of the base portion 72 in plan view. A side portion 73 of the p-type current confinement layer 66 has an inclined surface that slopes downward from the top portion 71 toward the base portion 72 .
In this embodiment, the p-type current confinement layer 66 has a laminated structure including a p-type ridge cladding layer 74 (upper semiconductor layer) and a p-type band offset buffer layer 75 laminated in this order from above the p-type protective layer 65. is doing.

The p-type ridge cladding layer 74 contains InGaAlP (indium-gallium-aluminum-phosphorus) in this form. The p-type ridge cladding layer 74 may be doped with Mg (magnesium) as a p-type impurity.
The p-type impurity concentration of the p-type ridge cladding layer 74 may be 1.0×10 ¹⁷ cm ⁻³ or more and 1.0×10 ¹⁹ cm ⁻³ or less. The thickness of p-type ridge cladding layer 74 may be 8000 Å or more and 12000 Å or less (for example, about 10000 Å).

The p-type band offset buffer layer 75 contains InGaP (indium-gallium-phosphorus) in this form. The p-type band offset buffer layer 75 may be doped with Mg (magnesium) as a p-type impurity.
The p-type impurity concentration of the p-type band offset buffer layer 75 may be 1.0×10 ¹⁸ cm ⁻³ or more and 1.0×10 ²⁰ cm ⁻³ or less. The thickness of p-type ridge cladding layer 74 may be 100 Å or more and 500 Å or less (for example, about 300 Å).

In such a configuration, the p-type protective layer 65 covers the p-type cladding layer 64 from the region between the p-type cladding layer 64 and the p-type current confinement layer 66 while covering the p-type current confinement layer 66 . being pulled out into the outer realm. The p-type protective layer 65 covers the entire area of the p-type cladding layer 64 .
A portion of the upper surface of the p-type protective layer 65 covered with the p-type current confinement layer 66 and a portion exposed from the p-type current confinement layer 66 are connected to each other. The inclined surface of the p-type current confinement layer 66 is formed continuously with the upper surface of the p-type protective layer 65 exposed from the p-type current confinement layer 66 .

In many cases, the region of the p-type protective layer 65 outside the p-type current confinement layer 66 disappears during the process of forming the p-type current confinement layer 66 . This is because the p-type ridge cladding layer 74 and the p-type band offset buffer layer 75 are simultaneously removed by one wet etching process during the formation process of the p-type current confinement layer 66 .
That is, in this case, in order to reliably remove the p-type ridge cladding layer 74 and the p-type band offset buffer layer 75, the etching time is longer than the estimated time for exposing the p-type protective layer 65 from the p-type ridge cladding layer 74. Etch time is set.

Therefore, the p-type protective layer 65 is exposed to the etchant for a long time, and the p-type protective layer 65 is removed in addition to the p-type ridge cladding layer 74 and the p-type band offset buffer layer 75 .
As a result, the p-type cladding layer 64 is exposed from the region outside the p-type current confinement layer 66 . In this case, the optical confinement effect of the double heterostructure layer varies, so the output of laser light extracted from the semiconductor laminated structure 42 (hereinafter simply referred to as "optical output") decreases.

In particular, the film thickness of the p-type protective layer 65 is extremely small compared to the p-type ridge cladding layer 74, the p-type band offset buffer layer 75, and the like. Therefore, unless the p-type protective layer 65 is intentionally removed, it is not verified whether or not the p-type protective layer 65 has disappeared, and the actual situation is such that a decrease in optical output cannot be recognized.
In contrast, in this embodiment, a dry etching step and a wet etching step are performed during the step of forming the p-type current constriction layer 66 . The dry etching process may be performed by an anisotropic etching method. The anisotropic etching method may be an RIE (Reactive Ion Etching) method. The wet etching process may be performed by an isotropic etching method.

In the dry etching step, the p-type band offset buffer layer 75 and the p-type ridge cladding layer 74 are removed so as to leave a portion of the p-type ridge cladding layer 74 outside the region where the p-type current confinement layer 66 is to be formed. . Then, in a wet etching step, a portion of the p-type ridge cladding layer 74 remaining outside the region where the p-type current confinement layer 66 is to be formed is removed.
In this case, since the thinned p-type ridge cladding layer 74 may be removed in the wet etching process, the difficulty of managing the etching time can be reduced. Also, the exposure time of the p-type protective layer 65 to the etchant can be shortened. As a result, the thinned p-type ridge cladding layer 74 can be appropriately removed while the p-type protective layer 65 remains.

As a result, since the p-type cladding layer 64 can be appropriately protected by the p-type protective layer 65, variations in the thickness of the p-type cladding layer 64 can be suppressed. Therefore, the light confinement effect of the p-type cladding layer 64 can be properly maintained, and a decrease in light output can be suppressed.
A p-type contact layer 67 is formed on the top portion 71 of the p-type current confinement layer 66 . The p-type contact layer 67 is formed in a strip shape extending along the longitudinal direction X on the top portion 71 of the p-type current confinement layer 66 .

The side portions of the p-type contact layer 67 are formed at different angles with respect to the side portions 73 of the p-type current confinement layer 66 . More specifically, the side portion of the p-type contact layer 67 extends along the normal direction of the top portion 71 of the p-type current confinement layer 66 .
The p-type contact layer 67 exposes a portion of the top portion 71 of the p-type current confinement layer 66 . The p-type contact layer 67 is formed spaced apart from the peripheral edge of the top portion 71 of the p-type current confinement layer 66 in the inner region.

The p-type contact layer 67 has an area smaller than the area of the top portion 71 of the p-type current confinement layer 66 in plan view. The p-type contact layer 67 is formed narrower than the top portion 71 of the p-type current confinement layer 66 .
In this form, the p-type contact layer 67 exposes one side edge and the other side edge in the transverse direction Y at the top portion 71 of the p-type current confinement layer 66 . In this form, the p-type contact layer 67 exposes one side edge and the other side edge in the longitudinal direction X at the top portion 71 of the p-type current confinement layer 66 . The p-type contact layer 67 functions as a current constriction contact layer that constricts current supplied to the p-type current confinement layer 66 .

The p-type contact layer 67 contains GaAs (gallium-arsenic) in this form. The p-type contact layer 67 may be doped with C (carbon) or Zn (zinc) as a p-type impurity.
The p-type impurity concentration of the p-type contact layer 67 may be 1.0×10 ¹⁸ cm ⁻³ or more and 1.0×10 ²⁰ cm ⁻³ or less. The thickness of p-type contact layer 67 may be 1000 Å or more and 6000 Å or less (for example, about 4000 Å).

6a-8, an insulating layer 43 is formed over the semiconductor stack 42. As shown in FIG. Insulating layer 43 includes a top insulating layer 81 covering the portion exposed from p-type contact layer 67 at top 71 of p-type current confinement layer 66 . Insulating layer 43 includes side insulating layers 82 that cover side portions 73 of p-type current confinement layer 66 . Insulating layer 43 includes a top insulating layer 83 covering the top surface of p-type protective layer 65 .

In this embodiment, the top insulating layer 81 covers one edge and the other edge in the longitudinal direction X exposed from the p-type contact layer 67 at the top 71 of the p-type current confinement layer 66 . In this embodiment, the top insulating layer 81 covers one side edge and the other side edge in the lateral direction Y exposed from the p-type contact layer 67 at the top 71 of the p-type current confinement layer 66 .
The top insulating layer 81 exposes the top surface of the p-type contact layer 67 . More specifically, the top insulating layer 81 (insulating layer 43 ) does not cover the upper surface of the p-type contact layer 67 . The top insulating layer 81 insulates the portion exposed from the p-type contact layer 67 in the top portion 71 of the p-type current confinement layer 66 . As a result, the current confinement effect of the p-type contact layer 67 can be appropriately enhanced.

The top insulating layer 81 includes a first covering portion 84 that covers the top portion 71 (p-type band offset buffer layer 75) of the p-type current confinement layer 66, a second covering portion 85 that covers the side portions of the p-type contact layer 67, It also includes a connecting portion 86 that connects the first covering portion 84 and the second covering portion 85 .
The first cover portion 84 of the top insulating layer 81 is formed substantially parallel or parallel to the top portion 71 of the p-type current confinement layer 66 in this embodiment. The second covering portion 85 of the top insulating layer 81 extends along the sides of the p-type contact layer 67 . The second covering portion 85 of the top insulating layer 81 has an extension extending above the upper surface of the p-type contact layer 67 in this embodiment.

The connection portion 86 of the top insulating layer 81 is located above the upper surface of the p-type contact layer 67 with respect to the normal direction Z. As shown in FIG. That is, the upper surface of the p-type contact layer 67 is located on the top portion 71 side of the p-type current constriction layer 66 with respect to the normal direction Z with respect to the connection portion 86 of the top insulating layer 81 .
The first covering portion 84 of the top insulating layer 81 may be located on the top portion 71 side of the p-type current confinement layer 66 with respect to the normal direction Z with respect to the connecting portion 86 of the top insulating layer 81 . That is, the first covering portion 84 of the top insulating layer 81 may form a recess that is recessed from the connecting portion 86 toward the top portion 71 side of the p-type current confinement layer 66 in the normal direction Z.

In this case, the first covering portion 84 of the top insulating layer 81 may be located on the top portion 71 side of the p-type current confinement layer 66 with respect to the top surface of the p-type contact layer 67 with respect to the normal direction Z. That is, the first covering portion 84 is located on the top portion 71 side of the p-type current confinement layer 66 with respect to the upper surface of the p-type contact layer 67 with respect to the normal direction Z, while the connection portion 86 It may protrude above the upper surface of the p-type contact layer 67 in the Z direction.

A side insulating layer 82 covers the side portion 73 of the p-type current confinement layer 66 . The side insulating layer 82 covers almost the entire side portion 73 of the p-type current confinement layer 66 or the entire side portion. The side insulating layer 82 is integrated with the top insulating layer 81 at the top portion 71 of the p-type current confinement layer 66 .
The side insulating layer 82 has a protruding portion 87 that protrudes above the top portion 71 of the p-type current confinement layer 66 in the normal direction Z. As shown in FIG. Projecting portion 87 of side insulating layer 82 is formed along an edge portion connecting top portion 71 and side portion 73 of p-type current confinement layer 66 .

The protruding portion 87 of the side insulating layer 82 protrudes above the p-type contact layer 67 with respect to the normal direction Z. As shown in FIG. The protruding portion 87 of the side insulating layer 82 protrudes above the first covering portion 84 and the connecting portion 86 of the top insulating layer 81 with respect to the normal direction Z. As shown in FIG.
The upper surface insulating layer 83 covers substantially the entire surface of the upper surface of the p-type protective layer 65 outside the p-type current constriction layer 66 . The top insulating layer 83 is integrated with the side insulating layer 82 at the base 72 of the p-type current confinement layer 66 .

The underlying electrode layer 44 is formed on the p-type contact layer 67 . The underlying electrode layer 44 is drawn from above the p-type contact layer 67 onto the insulating layer 43 . The base electrode layer 44 is formed in a film shape along the upper surface of the p-type contact layer 67 and the upper surface of the insulating layer 43 .
The base electrode layer 44 covers the top insulating layer 81 , the side insulating layers 82 and the top insulating layer 83 in the insulating layer 43 . The base electrode layer 44 in this embodiment covers substantially the entire upper surface of the p-type contact layer 67 and the upper surface of the insulating layer 43 or the entire surface thereof.

The base electrode layer 44 has a laminated structure in which a plurality of electrode layers are laminated in this form. The multiple electrode layers include a first electrode layer 91 and a second electrode layer 92 stacked in this order from the p-type contact layer 67 side.
The first electrode layer 91 may contain Ti (titanium). The second electrode layer 92 may contain Au (gold). The thickness of the first electrode layer 91 may be 250 Å or more and 2000 Å or less. The thickness of the second electrode layer 92 may be 1000 Å or more and 3000 Å or less.

The first terminal electrode layer 45 is an anode terminal electrode. The first terminal electrode layer 45 is connected to the submount 9 (see also FIG. 1). The first terminal electrode layer 45 may be connected to the first lead terminal 4 via the first conducting wire 12 (see also FIG. 1).
The first terminal electrode layer 45 is formed on the underlying electrode layer 44 so as to be electrically connected to the p-type contact layer 67 through the underlying electrode layer 44 . The first terminal electrode layer 45 is formed in a strip shape extending along the longitudinal direction X. As shown in FIG.

The first terminal electrode layer 45 has a pair of first electrode side surfaces 93 extending along the first substrate side surface 51 of the substrate 41 and a pair of second electrode side surfaces 94 extending along the second substrate side surface 52 of the substrate 41 . include.
The first electrode side surface 93 and the second electrode side surface 94 are formed at positions spaced inward from the substrate side surface 49 of the substrate 41 in plan view. As a result, steps are formed in the region between the first electrode side surface 93 and the substrate side surface 49 and in the region between the second electrode side surface 94 and the substrate side surface 49 .

3 to 7, with respect to the lateral direction Y, the pair of first electrode side surfaces 93 of the first terminal electrode layer 45 are arranged with respect to the ends of the p-type contact layer 67. Located on the 93rd side.
Further, with respect to the longitudinal direction X, the pair of second electrode side surfaces 94 of the first terminal electrode layer 45 are located on the second substrate side surface 52 side of the substrate 41 with respect to the end portion of the p-type contact layer 67 . With such an aspect, the first terminal electrode layer 45 covers the entire area of the p-type contact layer 67 in plan view.

The portions of the underlying electrode layer 44 that cover both ends in the longitudinal direction X of the p-type current confinement layer 66 are exposed from the first terminal electrode layer 45 in this embodiment. That is, the first terminal electrode layer 45 does not face both ends in the longitudinal direction X of the p-type current confinement layer 66 with the underlying electrode layer 44 interposed therebetween.
In this form, the first terminal electrode layer 45 has a single-layer structure consisting of a single electrode layer. The first terminal electrode layer 45 may contain Au (gold). The first terminal electrode layer 45 may be an Au (gold) plating layer.

The length L3 of the first electrode side surface 93 may be 250 μm or more and 350 μm or less (for example, about 290 μm). The length L4 of the second electrode side surface 94 may be 50 μm or more and 150 μm or less (for example, about 100 μm). The thickness of the first terminal electrode layer 45 may be 2.0 μm or more and 10.0 μm or less (for example, about 7.0 μm).
The first terminal electrode layer 45 is a cathode terminal electrode. When the first terminal electrode layer 45 is connected to the submount 9, the second terminal electrode layer 46 is connected to the first lead terminal 4 via the first conductor 12 (see also FIG. 1). When the first terminal electrode layer 45 is connected to the first lead terminal 4 via the first conductor 12, the second terminal electrode layer 46 is connected to the submount 9 (see also FIG. 1).

The second terminal electrode layer 46 is formed on the second major surface 48 of the substrate 41 . In this form, the second terminal electrode layer 46 covers almost the entire surface or the entire surface of the second main surface 48 of the substrate 41 .
The second terminal electrode layer 46 has a laminated structure including a plurality of electrode layers in this embodiment. The multiple electrode layers include a first electrode layer 95 , a second electrode layer 96 and a third electrode layer 97 stacked in this order from the second main surface 48 side of the substrate 41 .

The first electrode layer 95 may contain Ni (nickel) and/or AuGe (gold-germanium alloy). The second electrode layer 96 may contain Ti (titanium). The third electrode layer 97 may contain Au (gold).
The thickness of the first electrode layer 95 may be between 1000 Å and 4000 Å. The thickness of the second electrode layer 96 may be between 100 Å and 1000 Å. The thickness of the third electrode layer 97 may be 500 Å or more and 4000 Å or less.

9A to 9D are process diagrams showing an example of a method for manufacturing the semiconductor laser device 1. FIG. 10A to 10I are cross-sectional views for explaining an example of the method of manufacturing the semiconductor laser device 1. FIG. 10A-10I are cross-sectional views of the part corresponding to FIG. 6a.
Referring to FIG. 10A, substrate 41 having first main surface 47 and second main surface 48 is prepared (step S1 in FIG. 9). Next, a semiconductor laminated structure 42 is formed on the first main surface 47 of the substrate 41 (step S2 in FIG. 9).

In this step, an n-type buffer layer 61, an n-type clad layer 62, an active layer 63, a p-type clad layer 64, a p-type protective layer 65, a p-type ridge clad layer 74, and a p-type band offset buffer layer 75 are formed by epitaxial growth. , a p-type contact layer 67 and a damage absorption layer 101 are formed on the first main surface 47 of the substrate 41 in this order.
The p-type ridge cladding layer 74 and the p-type band offset buffer layer 75 are formed here as base semiconductor layers serving as the base of the p-type current confinement layer 66 .

The damage absorption layer 101 is a layer for protecting the p-type contact layer 67 from damage caused during the subsequent dry etching process. Any material can be used for the damage absorption layer 101 as long as it can protect the p-type contact layer 67 .
In this embodiment, the damage absorption layer 101 is made of the same material as the p-type contact layer 67 . That is, a part (surface layer portion) of the p-type contact layer 67 is formed as the damage absorption layer 101 . The damage absorption layer 101 may have a thickness of 200 Å or more and 3000 Å or less. The thickness of the damage absorption layer 101 is preferably 500 Å or more and 2000 Å or less.

By increasing the thickness of the damage absorption layer 101, the amount of damage caused to the p-type contact layer 67 can be reduced. As a result, an increase in series resistance due to damage occurring in the p-type contact layer 67 can be suppressed.
The above numerical range of the thickness of the damage absorption layer 101 is an example, and the thickness of the damage absorption layer 101 is not limited to the above numerical range. The thickness of the damage absorption layer 101 can take various values based on the etching time for removing the damage absorption layer 101, the relationship between the thickness of the damage absorption layer 101 and the series resistance value, and the like.

Next, referring to FIG. 10B, a mask 102 having a predetermined pattern is formed on semiconductor lamination structure 42 (step S3 in FIG. 9). A mask 102 covers the region where the p-type current confinement layer 66 is to be formed. The mask 102 may be made of an insulator. The mask 102 may contain SiO ₂ (silicon oxide).
Next, referring to FIG. 10C, unnecessary portions of p-type contact layer 67, unnecessary portions of p-type band offset buffer layer 75, and unnecessary portions of p-type ridge cladding layer 74 are removed by dry etching through mask 102. Referring to FIG. A portion is removed (step S4 in FIG. 9). The dry etching method may be an anisotropic etching method. The anisotropic etching method may be an RIE (Reactive Ion Etching) method.

In this step, the etching time is set so that a portion of the p-type ridge cladding layer 74 located outside the mask 102 remains. Therefore, the p-type ridge cladding layer 74 is partially removed so that the p-type protective layer 65 is not exposed.
In p-type ridge cladding layer 74, the ratio of the thickness of the portion located outside mask 102 to the thickness of the portion located directly under mask 102 may be 0.04 or more and 0.16 or less. good. A portion of p-type ridge cladding layer 74 located outside mask 102 may have a thickness of 500 Å or more and 5000 Å or less (for example, about 3000 Å).

Also, in this step, a portion of the p-type contact layer 67 located directly below the peripheral edge of the mask 102 is removed. As a result, the region of the p-type current confinement layer 66 that will become the top portion 71 is exposed to the outside.
Furthermore, in this step, damage caused by dry etching is absorbed by the damage absorption layer 101 . The damage absorbing layer 101 after absorbing damage is indicated by cross-hatching for clarity.

Next, referring to FIG. 10D, wet etching is performed through mask 102 to remove portions of p-type ridge cladding layer 74 remaining outside mask 102 (step S5 in FIG. 9). The wet etching method may be an isotropic etching method.
The etchant may be hydrochloric acid. In this step, unnecessary portions of the p-type ridge cladding layer 74 are removed until the p-type protective layer 65 is exposed. Thus, a p-type current confinement layer 66 is formed.

In this way, the step of forming the p-type current confinement layer 66 includes a dry etching step and a wet etching step. In the dry etching step, p-type band offset buffer layer 75 and p-type ridge cladding layer 74 are removed so that a portion of p-type ridge cladding layer 74 remains outside mask 102 . In the wet etching process, the portion of the p-type ridge cladding layer 74 remaining outside the mask 102 is removed.

In this case, since the thinned p-type ridge cladding layer 74 may be removed in the wet etching process, the difficulty of managing the etching time can be reduced. Also, the exposure time of the p-type protective layer 65 to the etchant can be shortened. As a result, the thinned p-type ridge cladding layer 74 can be appropriately removed while the p-type protective layer 65 remains.
Next, referring to FIG. 10E, insulating layer 43 is formed on semiconductor laminated structure 42 (step S6 in FIG. 9). In this step, an insulating layer 43 is formed on the semiconductor multilayer structure 42 by epitaxial growth. The insulating layer 43 grows starting from the top surface of the p-type protective layer 65 in addition to the top portion 71 and side portions 73 of the p-type current confinement layer 66 .

A portion of the insulating layer 43 growing from the top portion 71 of the p-type current confinement layer 66 grows until it contacts the mask 102 . Thereby, the top insulating layer 81 is formed. A portion of the insulating layer 43 growing from the side portion 73 of the p-type current confinement layer 66 grows along the side portion 73 of the p-type current confinement layer 66 . Thereby, the side insulation layer 82 is formed.
Side insulating layer 82 overlaps top insulating layer 81 at the edge connecting top 71 and side 73 in p-type current confinement layer 66 . A portion of the side insulating layer 82 located above the top portion 71 of the p-type current confinement layer 66 is formed following the mask 102 .

As a result, protruding portions 87 that protrude above the top portion 71 of the p-type current confinement layer 66 are formed in the side insulating layers 82 along the edge portions of the p-type current confinement layer 66 . The protruding portion 87 protrudes above the p-type contact layer 67 in this form.
A portion of the insulating layer 43 growing from the upper surface of the p-type protective layer 65 grows along the upper surface of the p-type protective layer 65 . Thereby, the upper insulating layer 83 is formed.

Next, referring to FIG. 10F, mask 102 is removed (step S7 in FIG. 9). Mask 102 is removed by an etching method. Mask 102 may be removed by a wet etching method. The wet etching method may be an isotropic etching method. The etchant may contain hydrofluoric acid.
Next, the damage absorption layer 101 (surface layer portion of the p-type contact layer 67) is removed (step S8 in FIG. 9). The damage absorption layer 101 is removed by an etching method. The damage absorption layer 101 may be removed by wet etching. The wet etching method may be an isotropic etching method.

The etchant may contain a mixture of sulfuric acid and hydrogen peroxide. As a result, the upper surface of the p-type contact layer 67 is formed so as to be located on the p-type current confinement layer 66 side with respect to the connection portion 86 of the top insulating layer 81 .
Next, referring to FIG. 10G, base electrode layer 44 is formed on p-type contact layer 67 (step S9 in FIG. 9). This step includes stacking the first electrode layer 91 and the second electrode layer 92 on the p-type contact layer 67 .

The first electrode layer 91 may contain Ti (titanium). The second electrode layer 92 may contain Au (gold). The first electrode layer 91 and the second electrode layer 92 may each be formed by sputtering or vapor deposition.
Next, referring to FIG. 10H, a mask 103 having a predetermined pattern is formed on base electrode layer 44 (step S10 in FIG. 9). The mask 103 may contain photosensitive resin. The mask 103 has openings 104 that expose regions where the first terminal electrode layers 45 are to be formed.

Next, a first terminal electrode layer 45 is formed on portions of the base electrode layer 44 exposed through the openings 104 of the mask 103 . The first terminal electrode layer 45 may contain Au (gold). The first terminal electrode layer 45 may be formed by gold plating. After the first terminal electrode layer 45 is formed, the mask 103 is removed.
Next, referring to FIG. 10I, the second terminal electrode layer 46 is formed on the second main surface 48 of the substrate 41 (step S11 in FIG. 9). This step includes stacking the first electrode layer 95 , the second electrode layer 96 and the third electrode layer 97 in this order from the second main surface 48 side of the substrate 41 .

The first electrode layer 95 may contain Ni (nickel) and/or AuGe (gold-germanium alloy). The second electrode layer 96 may contain Ti (titanium). The third electrode layer 97 may contain Au (gold).
The first electrode layer 95, the second electrode layer 96 and the third electrode layer 97 may each be formed by a sputtering method or a vapor deposition method. The semiconductor laser device 1 is manufactured through the steps including the above.

FIG. 11 is a graph showing the characteristics of the semiconductor laser device 1. FIG. In FIG. 11, the left vertical axis represents optical output [mW], the right vertical axis represents operating voltage [V], and the horizontal axis represents operating current [mA].
The graph of FIG. 11 shows the characteristics of the semiconductor laser device 1 produced without forming the damage absorption layer 101 in step S2 of FIG. 9 and without performing steps S4 and S8 of FIG.

FIG. 11 shows the first optical output characteristic A1 and the second optical output characteristic A2. A first optical output characteristic A1 indicates a characteristic at room temperature (25° C.). A second optical output characteristic A2 indicates a characteristic at a high temperature (75° C.).
FIG. 11 shows the first voltage characteristic B1 and the second voltage characteristic B2. A first voltage characteristic B1 indicates a characteristic at room temperature (25° C.). A second voltage characteristic B2 indicates a characteristic at a high temperature (75° C.).

In the semiconductor laser device 1 according to FIG. 11, the operating current was 35 mA or more and the operating voltage was 2.2 V or more when the optical output was 5 mW at room temperature (25° C.). In the semiconductor laser device 1 according to FIG. 11, the operating current was 65 mA or more and the operating voltage was 2.2 V or more when the optical output was 5 mW at a high temperature (75° C.).
FIG. 12 is a graph showing the characteristics of the semiconductor laser device 1. FIG. In FIG. 12, the left vertical axis represents optical output [mW], the right vertical axis represents operating voltage [V], and the horizontal axis represents operating current [mA].

The graph of FIG. 12 shows the characteristics of the semiconductor laser device 1 produced without performing step S8 of FIG.
FIG. 12 shows the first optical output characteristic A3 and the second optical output characteristic A4. A first optical output characteristic A3 indicates a characteristic at room temperature (25° C.). A second optical output characteristic A4 indicates a characteristic at a high temperature (75° C.).

FIG. 12 also shows a first voltage characteristic B3 and a second voltage characteristic B4. A first voltage characteristic B3 indicates a characteristic at room temperature (25° C.). A second voltage characteristic B4 indicates a characteristic at a high temperature (75° C.).
In the semiconductor laser device 1 according to FIG. 12, the operating current was 30 mA or less and the operating voltage was about 2.6 V when the optical output was 5 mW at room temperature (25° C.). Further, in the semiconductor laser device 1 according to FIG. 12, when the optical output was 5 mW at a high temperature (75° C.), the operating current was 45 mA or less and the operating voltage was about 2.5V.

The operating current of the semiconductor laser device 1 shown in FIG. 12 is about 20% lower at room temperature (25° C.) and about 35% lower at high temperature (75° C.) than that of the semiconductor laser device 1 shown in FIG.
On the other hand, the operating voltage of the semiconductor laser device 1 shown in FIG. 12 is increased by about 18% at normal temperature (25° C.) and increased by about 12% at high temperature (75° C.) as compared with the semiconductor laser device 1 shown in FIG. did.

As described above, according to the semiconductor laser device 1 of FIG. 12, although the operating voltage was increased, the operating current could be greatly reduced. It is considered that the reason why the operating current is lowered is that overetching of the p-type protective layer 65 can be avoided and the high temperature characteristics are improved. It is considered that the reason why the operating voltage increased is that the series resistance increased due to the damage of the damage absorption layer 101 .

It was found that the semiconductor laser device 1 according to FIG. 12 can reduce the operating current required to achieve the same optical output as compared with the semiconductor laser device 1 according to FIG. That is, according to the semiconductor laser device 1 of FIG. 12, it was found that an optical output equivalent to that of the semiconductor laser device 1 of FIG. 11 can be realized with a small operating current.
FIG. 13 is a graph showing the characteristics of the semiconductor laser device 1. FIG. In FIG. 13, the left vertical axis represents optical output [mW], the right vertical axis represents operating voltage [V], and the horizontal axis represents operating current [mA].

The graph of FIG. 13 shows the characteristics of the semiconductor laser device 1 when all the steps shown in FIG. 9 are performed.
FIG. 13 shows the first optical output characteristic A5 and the second optical output characteristic A6. A first optical output characteristic A5 indicates a characteristic at room temperature (25° C.). A second optical output characteristic A6 indicates a characteristic at a high temperature (75° C.).

FIG. 13 also shows a first voltage characteristic B5 and a second voltage characteristic B6. A first voltage characteristic B5 indicates a characteristic at room temperature (25° C.). A second voltage characteristic B6 indicates a characteristic at a high temperature (75° C.).
In the semiconductor laser device 1 according to FIG. 13, the operating current was 30 mA or less and the operating voltage was 2.1 V or less when the optical output was 5 mW at room temperature (25° C.). Further, in the semiconductor laser device 1 according to FIG. 13, the operating current was 45 mA or less and the operating voltage was 2.1 V or less when the optical output was 5 mW at a high temperature (75° C.).

The operating current of the semiconductor laser device 1 shown in FIG. 13 is about 20% lower at room temperature (25° C.) and about 35% lower at high temperature (75° C.) than that of the semiconductor laser device 1 shown in FIG.
On the other hand, the operating voltage of the semiconductor laser device 1 shown in FIG. 13 is about 5% lower at room temperature (25° C.) and about 5% lower at high temperature (75° C.) than the semiconductor laser device 1 shown in FIG. did.

It has been found that the semiconductor laser device 1 of FIG. 13 can lower the operating voltage and operating current required to achieve the same optical output as compared with the semiconductor laser device 1 of FIG.
That is, according to the semiconductor laser device 1 of FIG. 13, it was found that an optical output equivalent to that of the semiconductor laser device 1 of FIG. 11 can be realized with a small operating voltage and a small operating current.

As described above, the semiconductor laser device 1 includes the p-type contact layer 67 . The p-type contact layer 67 is formed on the top portion 71 of the p-type current confinement layer 66 so as to partially expose the top portion 71 of the p-type current confinement layer 66 . This allows the p-type contact layer 67 to function as a current constriction contact layer that confines the current supplied to the p-type current confinement layer 66 .
As a result, the current confinement effect of the p-type contact layer 67 and the current confinement effect of the p-type current confinement layer 66 can be obtained. Therefore, the directivity of the current flowing through the active layer 63 can be improved, so that the light output can be improved.

The semiconductor laser device 1 also includes a top insulating layer 81 . The top insulating layer 81 covers the portion exposed from the p-type contact layer 67 in the top portion 71 of the p-type current confinement layer 66 . As a result, the portion exposed from the p-type contact layer 67 at the top portion 71 of the p-type current confinement layer 66 can be insulated, so that the current confinement effect of the p-type contact layer 67 can be enhanced appropriately.

The semiconductor laser device 1 also includes a p-type protective layer 65 . P-type protective layer 65 is interposed between p-type cladding layer 64 and p-type current confinement layer 66 . Also, the p-type protective layer 65 is drawn out to a region outside the p-type current confinement layer 66 while maintaining the state of covering the p-type clad layer 64 .
As a result, the p-type cladding layer 64 can be protected by the p-type protective layer 65, so that variations in the thickness of the p-type cladding layer 64p-type can be suppressed. Therefore, the light confinement effect of the p-type cladding layer 64 can be properly maintained, and a decrease in light output can be suppressed.

In the method for manufacturing the semiconductor laser device 1, the damage absorption layer 101 is formed during the formation of the semiconductor laminated structure 42 (step S2 in FIG. 9), and is removed after the p-type contact layer 67 is formed.
As a result, the damage accumulated in the damage absorbing layer 101 during dry etching can be removed, so that the resistance value of the series resistor connected to the p-type contact layer 67 can be reduced. Thereby, the optical output can be efficiently increased.

Further, in the manufacturing method of the semiconductor laser device 1, the surface layer portion of the p-type contact layer 67 is formed as the damage absorption layer 101, so the step of forming the damage absorption layer 101 can be omitted.
Moreover, by mounting the semiconductor laser device 1 having an increased optical output on the semiconductor laser device stem 2, the laser light generated by the semiconductor laser device 1 can be efficiently extracted and utilized.

FIG. 14 is a cross-sectional view showing a semiconductor laser device 111 according to a second embodiment of the invention. FIG. 14 is also a cross-sectional view of the part corresponding to FIG. 6a. In the following, structures corresponding to those of the semiconductor laser device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.
Referring to FIG. 14 , in semiconductor laser device 111 , semiconductor laminated structure 42 does not include p-type contact layer 67 . The insulating layer 43 is formed on the semiconductor laminated structure 42 so as to expose the top portion 71 of the p-type current confinement layer 66 . Insulating layer 43 more specifically includes side insulating layer 82 and top insulating layer 83 , but does not include top insulating layer 81 .

A protruding portion 87 of the side insulating layer 82 protrudes upward from an edge portion connecting the top portion 71 and the side portion 73 of the p-type current confinement layer 66 . The projecting portion 87 of the side insulating layer 82 forms a recessed space with the top portion 71 of the p-type current confinement layer 66 .
The p-type contact layer 67 is formed on the top portion 71 of the p-type current confinement layer 66 in a concave space partitioned by the protruding portion 87 of the side insulating layer 82 . The p-type contact layer 67 covers almost the entire top portion 71 of the p-type current confinement layer 66 or the entire area.

The p-type contact layer 67 has a lead portion 112 that is continuously drawn from the top portion 71 of the p-type current confinement layer 66 to the side insulating layer 82 . The lead portion 112 of the p-type contact layer 67 covers the projecting portion 87 of the side insulating layer 82 .
The lead portion 112 of the p-type contact layer 67 is continuously led from above the side insulating layer 82 and further above the upper insulating layer 83 . The p-type contact layer 67 covers almost the entire upper surface of the insulating layer 43 or the entire surface in this embodiment.

A recess 113 directed toward the top portion 71 of the p-type current confinement layer 66 is formed in a portion of the outer surface (upper surface) of the p-type contact layer 67 located above the top portion 71 of the p-type current confinement layer 66 . Recess 113 is defined by a portion covering top portion 71 of p-type current confinement layer 66 and a portion covering protruding portion 87 of side insulating layer 82 .
The underlying electrode layer 44 is formed on the p-type contact layer 67 . The underlying electrode layer 44 enters the recess 113 of the p-type contact layer 67 . A portion of the base electrode layer 44 covering the recess 113 faces the top portion 71 of the p-type current confinement layer 66 with the p-type contact layer 67 interposed therebetween.

The underlying electrode layer 44 is drawn from above the p-type contact layer 67 onto the insulating layer 43 . The base electrode layer 44 is formed in a film shape along the upper surface of the p-type contact layer 67 and the upper surface of the insulating layer 43 .
The underlying electrode layer 44 covers the side insulating layer 82 and the upper insulating layer 83 in the insulating layer 43 . The base electrode layer 44 in this embodiment covers substantially the entire upper surface of the p-type contact layer 67 and the upper surface of the insulating layer 43 or the entire surface thereof.

15A to 15D are process diagrams showing an example of a method for manufacturing the semiconductor laser device 111. FIG. 16A to 16J are cross-sectional views for explaining an example of the method of manufacturing the semiconductor laser device 111. FIG. 16A to 16J are cross-sectional views of the portion corresponding to FIG. 14. FIG.
Referring to FIG. 16A, substrate 41 having first main surface 47 and second main surface 48 is prepared (step S11 in FIG. 15). Next, the semiconductor laminated structure 42 is formed on the first main surface 47 of the substrate 41 (step S12 in FIG. 15).

In this step, an n-type buffer layer 61, an n-type clad layer 62, an active layer 63, a p-type clad layer 64, a p-type protective layer 65, a p-type ridge clad layer 74, and a p-type band offset buffer layer 75 are formed by epitaxial growth. and a damage absorption layer 114 are formed in this order from above the first main surface 47 of the substrate 41 .
The p-type ridge cladding layer 74 and the p-type band offset buffer layer 75 are formed here as base semiconductor layers serving as the base of the p-type current confinement layer 66 .

The damage absorption layer 114 is a layer for protecting the p-type band offset buffer layer 75 from damage caused during the subsequent dry etching process. Any material can be used for the damage absorption layer 114 as long as it can protect the p-type band offset buffer layer 75 .
The damage absorbing layer 114 contains GaAs (gallium-arsenic) in this form. The damage absorption layer 114 may have a thickness of 200 Å or more and 3000 Å or less. The thickness of the damage absorption layer 114 is preferably 500 Å or more and 2000 Å or less.

By increasing the thickness of the damage absorption layer 114, the amount of damage caused to the p-type current confinement layer 66 (p-type band offset buffer layer 75) can be reduced. This can suppress an increase in series resistance due to damage occurring in the p-type current confinement layer 66 (p-type band offset buffer layer 75).
The above numerical range of the thickness of the damage absorption layer 114 is an example, and the thickness of the damage absorption layer 114 is not limited to the above numerical range. The thickness of the damage absorption layer 114 can take various values based on the etching time for removing the damage absorption layer 114, the relationship between the thickness of the damage absorption layer 114 and the series resistance value, and the like.

Next, referring to FIG. 16B, a mask 102 having a predetermined pattern is formed on semiconductor lamination structure 42 (step S13 in FIG. 15). A mask 102 covers the region where the p-type current confinement layer 66 is to be formed. Mask 102 may be formed by insulating layer 43 . The mask 102 may contain SiO ₂ (silicon oxide).
Next, referring to FIG. 16C, unnecessary portions of damage absorbing layer 114, unnecessary portions of p-type band offset buffer layer 75, and unnecessary portions of p-type ridge cladding layer 74 are removed by dry etching through mask 102. Referring to FIG. is removed (step S14 in FIG. 15). The dry etching method may be an anisotropic etching method. The anisotropic etching method may be an RIE (Reactive Ion Etching) method.

In this step, the etching time is set so that a portion of the p-type ridge cladding layer 74 located outside the mask 102 remains. Therefore, the p-type ridge cladding layer 74 is partially removed so that the p-type protective layer 65 is not exposed.
In p-type ridge cladding layer 74, the ratio of the thickness of the portion located outside mask 102 to the thickness of the portion located directly under mask 102 may be 0.04 or more and 0.16 or less. good. A portion of p-type ridge cladding layer 74 located outside mask 102 may have a thickness of 500 Å or more and 5000 Å or less (for example, about 300 Å).

In this step, damage caused by dry etching is absorbed by the damage absorption layer 114 . Damage absorbing layer 114 after damage absorption is indicated by cross-hatching for clarity.
Next, referring to FIG. 16D, wet etching is performed through mask 102 to remove the portion of p-type ridge cladding layer 74 remaining outside mask 102 (step S15 in FIG. 15). The wet etching method may be an isotropic etching method.

The etchant may be hydrochloric acid. In this step, unnecessary portions of the p-type ridge cladding layer 74 are removed until the p-type protective layer 65 is exposed. Thus, a p-type current confinement layer 66 is formed.
In this embodiment, a dry etching step and a wet etching step are performed during the step of forming the p-type current confinement layer 66 . In the dry etching step, p-type band offset buffer layer 75 and p-type ridge cladding layer 74 are removed so that a portion of p-type ridge cladding layer 74 remains outside mask 102 . In the wet etching process, the portion of the p-type ridge cladding layer 74 remaining outside the mask 102 is removed.

In this case, since the thinned p-type ridge cladding layer 74 may be removed in the wet etching process, the difficulty of managing the etching time can be reduced. Also, the exposure time of the p-type protective layer 65 to the etchant can be shortened. As a result, the thinned p-type ridge cladding layer 74 can be appropriately removed while the p-type protective layer 65 remains.
Next, referring to FIG. 16E, insulating layer 43 is formed on semiconductor laminated structure 42 (step S16 in FIG. 15). In this step, an insulating layer 43 is formed on the semiconductor multilayer structure 42 by epitaxial growth. The insulating layer 43 grows starting from the upper surface of the p-type protective layer 65 in addition to the side portion 73 of the p-type current confinement layer 66 .

A portion of the insulating layer 43 growing from the side portion 73 of the p-type current confinement layer 66 grows along the side portion 73 of the p-type current confinement layer 66 . Thereby, the side insulation layer 82 is formed. A portion of the side insulating layer 82 located above the top portion 71 of the p-type current confinement layer 66 is formed following the mask 102 .
As a result, protruding portions 87 that protrude above the top portion 71 of the p-type current confinement layer 66 are formed in the side insulating layers 82 along the edge portions of the p-type current confinement layer 66 . The protruding portion 87 protrudes above the p-type contact layer 67 in this form.

A portion of the insulating layer 43 growing from the upper surface of the p-type protective layer 65 grows along the upper surface of the p-type protective layer 65 . Thereby, the upper insulating layer 83 is formed.
Next, referring to FIG. 16F, mask 102 is removed (step S17 in FIG. 15). Mask 102 is removed by an etching method. Mask 102 may be removed by a wet etching method. The wet etching method may be an isotropic etching method. The etchant may contain hydrofluoric acid.

Next, the damage absorption layer 114 is removed (step S18 in FIG. 15). The damage absorption layer 114 is removed by an etching method. The damage absorption layer 114 is removed by wet etching in this step. The wet etching method may be an isotropic etching method. The etchant may contain a mixture of sulfuric acid and hydrogen peroxide.

Next, referring to FIG. 16G, p-type contact layer 67 is formed on top portion 71 of p-type current constriction layer 66 (step S19 in FIG. 15). In this step, a p-type contact layer 67 is formed on the top portion 71 of the p-type current confinement layer 66 and on the top surface of the insulating layer 43 by epitaxial growth. Thus, the p-type contact layer 67 is formed to cover the top portion 71 of the p-type current confinement layer 66 and the upper surface of the insulating layer 43 .

Next, referring to FIG. 16H, base electrode layer 44 is formed on p-type contact layer 67 (step S20 in FIG. 15). This step includes stacking the first electrode layer 91 and the second electrode layer 92 on the p-type contact layer 67 .
The first electrode layer 91 may contain Ti (titanium). The second electrode layer 92 may contain Au (gold). The first electrode layer 91 and the second electrode layer 92 may each be formed by sputtering or vapor deposition.

Next, referring to FIG. 16I, a mask 103 having a predetermined pattern is formed on underlying electrode layer 44 (step S21 in FIG. 15). The mask 103 may contain photosensitive resin. The mask 103 has openings 104 that expose regions where the first terminal electrode layers 45 are to be formed.
Next, a first terminal electrode layer 45 is formed on portions of the base electrode layer 44 exposed through the openings 104 of the mask 103 . The first terminal electrode layer 45 may contain Au (gold). The first terminal electrode layer 45 may be formed by gold plating. After the first terminal electrode layer 45 is formed, the mask 103 is removed.

Next, referring to FIG. 16J, the second terminal electrode layer 46 is formed on the second main surface 48 of the substrate 41 (step S22 in FIG. 15). This step includes stacking the first electrode layer 95 , the second electrode layer 96 and the third electrode layer 97 in this order from the second main surface 48 side of the substrate 41 .
The first electrode layer 95 may contain Ni (nickel) and/or AuGe (gold-germanium alloy). The second electrode layer 96 may contain Ti (titanium). The third electrode layer 97 may contain Au (gold). The first electrode layer 95, the second electrode layer 96 and the third electrode layer 97 may each be formed by a sputtering method or a vapor deposition method. The semiconductor laser device 111 is manufactured through the above steps.

As described above, in the manufacturing process of the semiconductor laser device 111, the dry etching process and the wet etching process are performed so that the p-type protective layer 65 remains (steps S14 and S15 in FIG. 15).
In the manufacturing process of the semiconductor laser device 111, a damage absorption layer 114 is formed to absorb damage during the dry etching process (step S12 in FIG. 15). The damage absorption layer 114 is removed after the step of forming the p-type current confinement layer 66 (step S18 in FIG. 15).

Therefore, according to the semiconductor laser device 111, almost the same effects as those described for the semiconductor laser device 1 can be obtained except for the current constriction effect by the p-type contact layer 67. FIG.
Although the embodiments of the present invention have been described above, the present invention can also be implemented in other forms.

In each of the above-described embodiments, an example in which the p-type current confinement layer 66 includes the side portion 73 having a downwardly inclined surface has been described. However, the side portion 73 of the p-type current confinement layer 66 may extend along the normal direction Z of the first main surface 47 of the substrate 41 .
In each of the above embodiments, the p-type current confinement layer 66 without the p-type band offset buffer layer 75 may be employed. In this case, the p-type contact layer 67 is formed on the p-type ridge clad layer 74 so as to be in contact with the p-type ridge clad layer 74 .

In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be employed. That is, the p-type portion may be n-type, and the n-type portion may be p-type.
Examples of features extracted from this specification and drawings are given below.
[Item 1] A first semiconductor layer of a first conductivity type, an active layer formed on the first semiconductor layer, a second semiconductor layer of a second conductivity type formed on the active layer, a current confinement layer of a second conductivity type formed so as to protrude above the second semiconductor layer and constricting a current supplied to the active layer, and interposed between the second semiconductor layer and the current confinement layer a protective layer of a second conductivity type drawn from a region between the second semiconductor layer and the current confinement layer to a region outside the current confinement layer while maintaining a state of covering the second semiconductor layer; A semiconductor laser device, comprising:

According to this semiconductor laser device, since the second semiconductor layer can be protected by the protective layer, variations in the film thickness of the second semiconductor layer can be suppressed. Therefore, since the light confinement effect of the second semiconductor layer can be maintained, the decrease in laser light output can be suppressed.
[Item 2] The semiconductor laser device according to item 1, wherein the protective layer covers the entire area of the second semiconductor layer.

[Item 3] The semiconductor laser device according to item 1 or 2, wherein the protective layer includes a semiconductor material having a composition different from that of the second semiconductor layer.
[Item 4] The semiconductor laser according to any one of Items 1 to 3, wherein the portion of the protective layer covered with the current confinement layer and the portion exposed from the current confinement layer are formed continuously. Device.

[Item 5] The semiconductor laser device according to any one of items 1 to 4, further comprising a side insulating layer covering a side portion of the current confinement layer.
[Item 6] The semiconductor laser device according to Item 5, wherein the side insulating layer has a protruding portion that protrudes above the current confinement layer.
[Item 7] The semiconductor laser device according to any one of items 1 to 6, further comprising a top insulating layer covering the top of the current confinement layer.

[Item 8] The semiconductor laser according to any one of items 1 to 7, wherein the current confinement layer includes an upper semiconductor layer of the second conductivity type formed to protrude above the second semiconductor layer. Device.
[Item 9] The semiconductor laser device according to Item 8, wherein the current confinement layer includes a band offset buffer layer formed on the upper semiconductor layer to alleviate band discontinuity.
[Item 10] A metal stem base having a first surface on one side and a second surface on the other side, and a second surface provided on the second surface side of the stem base and electrically connected to the stem base. one terminal, a second terminal extending from the second surface side of the stem base through the stem base to the first surface side, and the stem base so as to be electrically connected to the stem base. 10. The semiconductor laser device according to any one of Items 1 to 9, placed on the first surface of the, a first conducting wire electrically connecting the second terminal and the semiconductor laser device; A stem for a semiconductor laser device, comprising:

[Item 11] The stem for a semiconductor laser device according to Item 10, further comprising a first insulator interposed between the stem base and the second terminal for electrically insulating the second terminal from the stem base. .
[Item 12] A light extraction window is mounted on the first surface of the stem base so as to accommodate the semiconductor laser device between the stem base and extracts laser light generated by the semiconductor laser device. 12. The stem for a semiconductor laser device according to Item 10 or 11, further comprising a cap having the

[Item 13] The stem for a semiconductor laser device according to Item 12, further comprising a translucent closing member attached to the cap so as to close the light extraction window.
[Item 14] A third terminal extending from the second surface side of the stem base to the first surface side through the stem base, and the stem base so as to be electrically connected to the stem base. and a second conducting wire electrically connecting the third terminal and the semiconductor light emitting device. 3. The stem for a semiconductor laser device according to .

[Item 15] The stem for a semiconductor laser device according to Item 14, further comprising a second insulator interposed between the stem base and the third terminal for electrically insulating the third terminal from the stem base. .
[Item 16] forming an active layer on a first semiconductor layer of a first conductivity type; forming a second semiconductor layer of a second conductivity type on the active layer; forming a second conductive type protective layer on the protective layer; forming a second conductive type base semiconductor layer to be a current constriction layer on the protective layer; forming the current confining layer on the base semiconductor layer; forming a mask covering a region where a narrowing layer is to be formed; and after partially removing the base semiconductor layer by dry etching through the mask, exposing the protective layer by wet etching through the mask. and forming a current constriction layer of a second conductivity type for constricting a current supplied to the active layer by removing the remaining portion of the base semiconductor layer until the current constriction layer is formed.

In this step, the protective layer is formed as an etching stop layer. In many cases, the region of the protective layer outside the current confinement layer disappears during the process of forming the current confinement layer. This is because the base semiconductor layer is removed by one wet etching step during the step of forming the current confinement layer.
That is, in this case, in order to reliably remove the base semiconductor layer, the etching time is set to be longer than the etching time estimated to expose the protective layer from the base semiconductor layer. Therefore, the exposure time of the protective layer to the etchant increases, and the protective layer is removed in addition to the base semiconductor layer.

As a result, the second semiconductor layer is exposed from the region outside the current confinement layer. In this case, the optical confinement effect fluctuates due to fluctuations in the thickness of the second semiconductor layer, so the optical output extracted from the active layer decreases.
In addition, except when the protective layer is intentionally removed, whether or not the protective layer has disappeared is not verified unless there is a rational reason. There is a fact that it is not possible.

In contrast, in this method of manufacturing a semiconductor laser device, a dry etching step and a wet etching step are performed during the step of forming the current confinement layer. In the dry etching step, the base semiconductor layer is partially removed so as to leave a portion of the base semiconductor layer outside the region where the current confinement layer is to be formed. Then, in a wet etching step, the remaining base semiconductor layer is removed until the protective layer is exposed.

In the wet etching process, the thinned base semiconductor layer can be removed, so the difficulty of managing the etching time can be reduced. Also, the exposure time of the protective layer to the etchant can be shortened. Thereby, the thinned base semiconductor layer can be appropriately removed while leaving the protective layer.
As a result, since the second semiconductor layer can be appropriately protected by the protective layer, variations in the film thickness of the second semiconductor layer can be suppressed. Therefore, the light confinement effect of the second semiconductor layer can be maintained, and a decrease in laser light output can be suppressed.

[Item 17] In the step of forming the current confinement layer, the protective layer is interposed between the second semiconductor layer and the current confinement layer, and the protective layer is provided between the second semiconductor layer and the current confinement layer. 17. The method of manufacturing a semiconductor laser device according to Item 16, wherein the second semiconductor layer is formed so as to be pulled out to a region outside the current confinement layer while the second semiconductor layer is kept covered.
[Item 18] The method of manufacturing a semiconductor laser device according to Item 16 or 17, wherein in the step of forming the current blocking layer, the protective layer is formed so as to cover the entire area of the second semiconductor layer.

[Item 19] The semiconductor laser according to any one of items 16 to 18, wherein in the step of forming the protective layer, the protective layer includes a semiconductor material having a composition different from that of the second semiconductor layer. Method of manufacturing the device.
[Item 20] Items 16 to 19, wherein in the step of forming the current confinement layer, the portion of the protective layer covered by the current confinement layer and the portion exposed from the current confinement layer are formed continuously with each other. A method for manufacturing a semiconductor laser device according to any one of Claims 1 to 3.

[Item 21] The semiconductor according to any one of Items 16 to 20, further comprising, after the step of forming the current confinement layer, the step of forming a side insulating layer covering a side portion of the current confinement layer. A method for manufacturing a laser device.
[Item 22] A method of manufacturing a semiconductor laser device according to Item 21, wherein in the step of forming the side insulating layer, the side insulating layer is formed to protrude above the current confinement layer.

[Item 23] The semiconductor laser device according to any one of Items 16 to 22, further comprising, after the step of forming the current confinement layer, the step of forming a top insulating layer covering the top of the current confinement layer. manufacturing method.
[Item 24] The semiconductor laser device according to any one of Items 16 to 23, wherein the step of forming the base semiconductor layer includes the step of forming an upper semiconductor layer of the second conductivity type on the active layer. manufacturing method.

[Item 25] The semiconductor laser according to Item 24, wherein the step of forming the base semiconductor layer includes the step of forming, on the upper semiconductor layer, a band offset buffer layer of the second conductivity type that alleviates band discontinuity. Method of manufacturing the device.
In addition, various design changes can be made within the scope of the matters described in the claims.

1 semiconductor laser device 2 semiconductor laser device stem 3 stem base 4 first lead terminal 5 second lead terminal 6 third lead terminal 7 first insulator 8 second insulator 12 first conductor 13 second conductor 14 cap 15 collection Optical lens 16 Stem base first surface 17 Stem base second surface 33 Cap light extraction window 43 Insulating layer 62 n-type clad layer 63 active layer 64 p-type clad layer 65 p-type protective layer 66 p-type current confinement layer 67 p-type contact layer 71 p-type current confinement layer top 74 p-type ridge cladding layer 75 p-type band offset buffer layer 81 top insulating layer 82 side insulating layer 111 semiconductor laser device

Claims (21)

a first semiconductor layer of a first conductivity type;
an active layer formed on the first semiconductor layer;
a mesa-shaped current confinement layer of the second conductivity type that is formed to protrude above the active layer and includes a top portion and side portions having an area smaller than that of the active layer in a plan view;
a contact layer formed on the top portion narrower than the top portion and spaced inwardly from a peripheral edge of the top portion to expose an edge portion of the top portion of the current confinement layer, the contact layer including a top surface and a side portion; When,
a top insulating layer covering the edge of the current confinement layer and the side of the contact layer so as to protrude above the top surface of the contact layer, and exposing the entire top surface of the contact layer;
a side insulating layer covering the side portion of the current confinement layer so as to be integral with the top insulating layer . 2. The semiconductor laser device according to claim 1, wherein said contact layer functions as a current constriction contact layer constricting a current supplied to said current confinement layer. 3. The side insulating layer has a protruding portion that protrudes upward from the top insulating layer in a portion along an edge portion connecting the top portion and the side portion of the current confinement layer . 3. The semiconductor laser device according to . 4. The semiconductor laser device according to claim 1 , wherein said contact layer is formed of a second conductivity type semiconductor layer. the current confinement layer includes an upper semiconductor layer of a second conductivity type formed to protrude above the active layer;
5. The semiconductor laser device according to claim 1 , wherein said contact layer is formed on said upper semiconductor layer. the current confinement layer includes a band offset buffer layer formed on the upper semiconductor layer to alleviate band discontinuity;
6. The semiconductor laser device according to claim 5 , wherein said contact layer is formed on said band offset buffer layer. further comprising a second semiconductor layer of a second conductivity type formed on the active layer;
7. The semiconductor laser device according to claim 1 , wherein said current confinement layer is formed on said second semiconductor layer. 8. The semiconductor laser device according to claim 7 , further comprising a protective layer of the second conductivity type interposed between said second semiconductor layer and said current confinement layer. 9. The protective layer extends from a region between the second semiconductor layer and the current confinement layer to a region outside the current confinement layer while covering the second semiconductor layer. 3. The semiconductor laser device according to . 10. The semiconductor laser device according to claim 9 , wherein said protective layer covers the entire area of said second semiconductor layer. 11. The semiconductor laser device according to claim 1, further comprising a first terminal electrode layer formed on said contact layer. 12. The semiconductor laser device according to claim 11, further comprising a base electrode layer interposed between said contact layer and said first terminal electrode layer. 13. The semiconductor laser device according to claim 12, wherein said base electrode layer has a portion covering said contact layer, a portion covering said top insulating layer, and a portion covering said side insulating layer. further comprising a substrate having a first major surface on one side and a second major surface on the other side;
14. The semiconductor laser device according to claim 1, wherein said first semiconductor layer is formed on said first main surface of said substrate. 15. The semiconductor laser device according to claim 14, further comprising a second terminal electrode layer formed on said second main surface of said substrate. a metal stem base having a first surface on one side and a second surface on the other side;
a first terminal provided on the second surface side of the stem base and electrically connected to the stem base;
a second terminal extending from the second surface side of the stem base to the first surface side through the stem base;
16. The semiconductor laser device according to claim 1, placed on said first surface of said stem base so as to be electrically connected to said stem base;
A stem for a semiconductor laser device, comprising: a first conducting wire electrically connecting the second terminal and the semiconductor laser device. 17. The stem for a semiconductor laser device according to claim 16, further comprising a first insulator interposed between said stem base and said second terminal to electrically insulate said second terminal from said stem base. a cap mounted on the first surface of the stem base so as to accommodate the semiconductor laser device between the stem base and having a light extraction window for extracting laser light generated by the semiconductor laser device; 18. The stem for a semiconductor laser device according to claim 16 or 17, comprising: 19. The stem for a semiconductor laser device according to claim 18, further comprising a translucent closing member attached to said cap so as to close said light extraction window. a third terminal extending from the second surface side of the stem base to the first surface side through the stem base;
a semiconductor light emitting device including a photodiode mounted on the first surface of the stem base so as to be electrically connected to the stem base;
20. The stem for a semiconductor laser device according to claim 16, further comprising a second conducting wire electrically connecting said third terminal and said semiconductor light emitting device. 21. The stem for a semiconductor laser device according to claim 20, further comprising a second insulator interposed between said stem base and said third terminal to electrically insulate said third terminal from said stem base.

Images