JP7183657B2 - processor, information processing method, program - Google Patents

Description

The present invention relates to a processor, an information processing method, and a program for executing vector instructions.

2. Description of the Related Art In recent years, due to the miniaturization of semiconductor processes, the number of logic circuits that can be mounted on LSIs (Large Scale Integration) has increased dramatically, and the arithmetic performance of CPUs (Central Processing Units) has improved. This improvement in arithmetic performance is greatly contributed by multi-core, which increases the number of cores, and the improvement in performance per single core is slowing down. However, since there are many programs that are difficult to parallelize in order to enjoy the performance improvement of multi-core, the performance improvement of a single core is very important.

SIMD (Single Instruction Multiple Data) technology and vector technology are widely known as techniques for improving the performance of a single core. In particular, in vector processors that use vector technology, conventionally, when the vector length is long, the number of elements to be processed is large, so the processing cycle for issuing, executing, and completing each instruction becomes long, leaving sufficient margin for each processing time. and tended to produce high performance.

JP 2012-203544 A

However, the shorter the vector length, the smaller the number of elements to be processed, and the shorter the processing cycle for issuing, executing, and terminating each instruction. In other words, the shorter the vector length, which is the number of elements processed by one vector instruction, the more important it is to improve the vector instruction issue rate in order to improve performance.

For example, consider the configuration of the vector calculator shown in FIG. In this configuration, one VPU (Vector Processing Unit) consists of 32 vector arithmetic unit units, and in the case of a configuration in which two instructions can be processed simultaneously per vector arithmetic unit unit, sustained peak performance is obtained. Calculating the instruction issue rate for

If the vector length is 256: Processing time for one vector instruction=256/32=8 clocks. Also, since two instructions can be processed at the same time, it is essential to issue one vector instruction every 8/2=4 clocks.
If the vector length is 128: Processing time for one vector instruction=128/32=4 clocks. Also, since two instructions can be processed at the same time, it is essential to issue one vector instruction every 4/2=2 clocks.
When the vector length is 64: Processing time for one vector instruction=64/32=2 clocks. Also, since two instructions can be processed at the same time, it is essential to issue one vector instruction every 2/2=1 clock.
When the vector length is 32: Processing time for one vector instruction=32/32=1 clock. Also, since two instructions can be processed at the same time, it is essential to issue one vector instruction every 1/2=0.5 clocks. In other words, it is necessary to issue two vector instructions per clock.

As in the above example, it is clear that the shorter the vector length, the more the vector instruction issue rate needs to be improved.

Here, as a technique for improving the instruction issue rate, there is a multi-pipelining of the instruction issue pipeline. However, each pipeline requires a function of judging the dependency with the preceding instruction and issuing the instruction, which poses a problem of significant complication of the instruction issuance control function. For example, if it is composed of one instruction issue pipeline (pipe 1), it is sufficient to check the preceding instruction of pipe 1, but if it is composed of two instruction issue pipelines (pipe 1 and pipe 2), An instruction in pipe 1 must see a predecessor in pipe 1 and a predecessor in pipe 2, and an instruction in pipe 2 must see a predecessor in pipe 2 and a predecessor in pipe 1. Therefore, it is necessary to determine the dependency with four times the preceding instruction, which inevitably complicates the control circuit.

As another technique for improving the instruction issue rate, there is a method of increasing only the frequency of the instruction issue unit.

Further, as described in Japanese Patent Laid-Open No. 2002-200010, a technique for combining instruction packets for scalar store instructions is also disclosed. However, this technique cannot be applied to vector operation instructions, and the above-mentioned problem still remains.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a processor, an information processing method, and a program capable of improving the issue rate of vector instructions.

One aspect of the present invention is a processor comprising:
A processor comprising a scalar processing unit that performs scalar operations and a vector processing unit that performs vector operations,
The scalar processing unit issues to the vector processing unit an integrated vector operation instruction in which two or more of the simultaneously decoded vector operation instructions are integrated as one instruction,
The vector processing unit restores the integrated vector operation instruction to two or more vector operation instructions before integration, and performs vector operations respectively according to the two or more vector operation instructions.
take the configuration.

Further, an information processing method, which is one embodiment of the present invention, comprises:
An information processing method by a processor comprising a scalar processing unit that performs scalar operations and a vector processing unit that performs vector operations,
The scalar processing unit issues to the vector processing unit an integrated vector operation instruction in which two or more of the simultaneously decoded vector operation instructions are integrated as one instruction,
The vector processing unit restores the integrated vector operation instruction to two or more vector operation instructions before integration, and performs vector operations respectively according to the two or more vector operation instructions.
take the configuration.

Further, a program that is one embodiment of the present invention is
to the processor,
Realizing a scalar processing unit that performs scalar operations and a vector processing unit that performs vector operations,
The scalar processing unit issues to the vector processing unit an integrated vector operation instruction in which two or more of the simultaneously decoded vector operation instructions are integrated as one instruction,
The vector processing unit restores the integrated vector operation instruction to two or more vector operation instructions before integration, and performs vector operations respectively according to the two or more vector operation instructions.
make it happen
take the configuration.

The present invention can improve the issue rate of vector instructions by being configured as described above.

It is a figure for demonstrating the background technology of this invention. 3 is a block diagram showing the configuration of a processor according to Embodiment 1 of the present invention; FIG. 3 illustrates an example of information processed by the processor disclosed in FIG. 2; FIG. FIG. 3 is a diagram for explaining a state of processing by the processor disclosed in FIG. 2; FIG. FIG. 3 is a diagram for explaining a state of processing by the processor disclosed in FIG. 2; FIG. 3 illustrates an example of information processed by the processor disclosed in FIG. 2; FIG. 3 illustrates an example of information processed by the processor disclosed in FIG. 2; FIG. 3 illustrates an example of information processed by the processor disclosed in FIG. 2; FIG. FIG. 3 is a diagram for explaining a state of processing by the processor disclosed in FIG. 2; FIG. 3 illustrates an example of information processed by the processor disclosed in FIG. 2; FIG. FIG. 3 is a diagram for explaining a state of processing by the processor disclosed in FIG. 2; FIG. FIG. 3 is a diagram for explaining a state of processing by the processor disclosed in FIG. 2; FIG. FIG. 3 is a diagram showing how the processor disclosed in FIG. 2 performs processing; FIG. FIG. 3 is a diagram showing how the processor disclosed in FIG. 2 performs processing; FIG. FIG. 4 is a block diagram showing the configuration of a processor according to Embodiment 2 of the present invention;

<Embodiment 1>
A first embodiment of the invention will be described with reference to FIGS. FIG. 2 is a diagram for explaining the configuration of the processor, and FIGS. 3 to 14 are diagrams for explaining the state of processing by the processor.

[Constitution]
As shown in FIG. 2, the processor of the present invention includes an SPU (scalar processing unit) 100 for performing scalar operations and a VPU (vector processing unit) 200 for performing vector operations, and executes vector operation instructions. . In particular, the processor in this embodiment has a function of simultaneously decoding a plurality of instructions (it has a four-instruction simultaneous decoding configuration). IC), that is, the function of outputting address information representing the storage location of the operation instruction. In addition to this function, the processor of the present invention provides a function of compressing and decompressing a plurality of vector instructions into one instruction as will be described later.

Moreover, the processor in this embodiment executes a four-operand format instruction as shown in FIG. 3, which will be described later, as a processor capable of executing vector instructions. For example, a Fused Multiply ADD(FMA) instruction can execute an instruction such as VFMA V0←V1+(V2*V3). Further, instructions such as VFMA V0←S1+(V2*V3) and VFMA V0←V1+(S1*V3), which can designate scalar registers such as S1 instead of V1 and V2, can be executed. In addition, a mask register for mask operation can be specified. However, the mask operation does not affect the control of compression/decompression of instructions executed in the present invention, so the explanation is omitted. The vector length is a value for setting the number of elements processed by one vector instruction, and uses the value of a vector length setting register (not shown). In this embodiment, the vector length is assumed to be a value from 0 to 256. It is also assumed that the IC is a 56-bit address, and the operation exception IC is provided with a reference IC every 256 bytes.

Hereinafter, the configuration of the processor in this embodiment will be specifically described with reference to FIG. The SPU 100 has an instruction cache 101 , an instruction decoder 121 , an instruction scheduler 141 , a scalar register 161 and a vector instruction issue controller 181 . Further, the instruction decoder 121 has an instruction decoder control unit 122 , a vector operation instruction determination unit 123 , a vector operation exception IC register 124 and a vector operation instruction compression control unit 125 .

The VPU 200 also has an instruction decoder 201 , an instruction scheduler 221 , a vector register 241 and a vector operation unit group 261 . The instruction decoder 201 has an instruction decoder control unit 202 , a vector operation exception IC register 203 and a vector operation instruction restoration control unit 204 .

The SPU 100 and VPU 200 also have signal lines 110, 130, 131, 132, 133, 134, 135, 150, 170, 190, 210, 211, 212, 213, 230, and 250 that connect the components.

An outline of the configurations of the SPU 100 and VPU 200 described above will be described below. The details of each configuration will be explained in more detail when explaining the operation.

When the instruction decoder 121 of the SPU 100 processes the vector operation instruction of the format (instruction length is 8 bytes) shown in FIG. 3, it determines whether or not the vector operation instruction can be compressed by judging two conditions. .
Condition 1: Whether vector operation instructions are subject to instruction compression among instructions that can be simultaneously decoded in the combinations shown in FIG. In other words, are the instructions consecutive to each other among the instructions that can be decoded at the same time?
Condition 2: Is the operation exception IC register of the reference instruction shown in FIG. 5 valid and does the operation exception IC of the vector operation instruction match? That is, does the upper address, which is part of the address of the operation exception IC of the vector operation instruction, match?

Specifically, the configuration of the instruction decoder 121 of the SPU 100 will be further detailed. When detecting a vector operation instruction, the instruction decoder 121 compares the IC of the vector operation instruction with the operation exception IC register of the reference instruction. At this time, as shown in FIG. 5, if the operation exception IC of the reference instruction is "valid bit=0", the valid vector operation instruction IC is not registered. , is registered as an operation exception IC of the reference instruction, and it is determined that there is no instruction compression. Here, if a reference IC is provided every 256 bytes, the lower 8 bits of the IC can be omitted. That is, only the upper address, which is part of the address information indicating the storage location of the vector operation instruction, is registered as the operation exception IC of the reference instruction. As a result, the address information representing the storage location of 32 consecutive vector operation instructions is registered as the operation exception IC of the reference instruction.

When the operation exception IC of the reference instruction is "effective bit=1" as shown in FIG. It compares the high-order address of the IC of the operation instruction. If they match, it is determined that there is instruction compression, and if they do not match, it is determined that there is no instruction compression, and the IC of the corresponding vector operation instruction is newly registered as the operation exception IC of the reference instruction. In other words, since part of the IC of the preceding vector operation instruction is registered as the operation exception IC of the reference instruction, the upper address, which is part of the IC of the preceding vector operation instruction, and the IC of the subsequent vector operation instruction If the upper address, which is a part, matches, it is determined that there is instruction compression.

As described above, when the instruction decoder 121 determines that the instruction is not to be compressed, the instruction is stored in the entry of the instruction scheduler 141 of the SPU 100 in the form of a normal vector operation instruction as shown in FIG. At this time, the instruction decoder 121 simultaneously adds the IC of the corresponding vector operation instruction to the entry as an operation exception IC and stores it in the entry.

When the instruction decoder 121 determines that there is instruction compression, it compresses the target two vector operation instructions, and converts the two vector operation instructions into one unified vector operation instruction in the format shown in FIG. , and stored in one entry of the instruction scheduler 141 of the SPU 100 . When the instruction is compressed, the instruction decoder 121 uses the "byte14" part, which is part of the entry shown in FIG. 7, as the relative IC from the operation exception IC of the reference instruction. Specifically, as shown in FIG. 8, the "byte14" part is set to unused bits 5 to 7 (lower 3 bits are unused in the case of an architecture in which the instruction has a fixed length of 8 bytes) as "instruction compression bit ” is provided, and “1” is set to this bit.

The instruction scheduler 141 of the SPU 100 determines whether an instruction can be issued for each entry, and issues an instruction for each entry when the necessary resources are ready. Note that the SPU 100 issues vector instructions in-order. At this time, the instruction scheduler 141 confirms whether the dependent scalar register 161 data for one instruction has been prepared if the instruction is not a vector operation instruction or if the instruction is a vector operation instruction and the instruction compression bit=0. In the case of the vector operation instruction and the instruction compression bit=1, it is confirmed whether or not the dependent scalar register 161 data for the original two instructions that are compressed and integrated into one instruction have been prepared. The SPU 100 then reads data from the scalar register 161 specified by the vector operation instruction and sends it to the vector instruction issue control unit 181 .

The vector instruction issue control unit 181 issues various information and scalar register data for one instruction to the VPU 200 if the instruction is not a vector operation instruction. When the instruction compression bit=0, various information for one instruction, an operation exception IC, and one scalar register data as shown in FIG. 6 are issued to the VPU 200 . In the case of instruction compression bit=1, various information for two instructions integrated into one instruction as shown in FIG. .

The instruction decoder 201 of the VPU 200 has the function of operating as follows in response to an instruction received from the SPU 100 . First, if the instruction is not a vector operation instruction, various information for one instruction is stored in the instruction scheduler 221 of the VPU 200 .

Also, when the instruction compression bit=0, the instruction decoder 201 stores various information for one instruction and the operation exception IC in one entry of the instruction scheduler 221 of the VPU 200 . At the same time, the operation exception IC shown in FIG. 9 included in this instruction is registered and saved in the operation exception IC register of the reference instruction. At this time, the upper 6 bytes of the operation exception IC included in one instruction are registered as the operation exception IC of the reference instruction.

Further, when the instruction compression bit=1, the instruction decoder 201 stores various information and operation exception IC for two instructions, which are one vector operation instruction, in two entries of the instruction scheduler 221 of the VPU 200, and stores two Restore to order. At this time, in two entries, that is, two instructions, as for the operation exception IC, as shown in FIG. 10, as the upper 6 bytes of the operation exception IC of the first instruction, the operation The exception IC is used, and the lower 1 byte is combined with the "relative IC from the reference instruction" located at byte 14 of the instruction received from the SPU 100, and the operation exception IC before compression is restored and stored. The operation exception IC of the second instruction uses the operation exception IC of the registered reference instruction as the upper 6 bytes, and the lower 1 byte is the "relative to reference instruction" located at byte 14 of the instruction received from the SPU 100. IC"+"instruction length (+8 in the case of an 8-byte instruction)" is calculated, and the operation exception IC before compression is restored and stored.

The instruction scheduler 221 of the VPU 200 determines whether an instruction can be issued for each entry, and issues an instruction for each entry when the necessary resources are ready. The VPU 200 executes vector instructions out of order. The VPU 200 then sends the data of the vector register 241 specified by the instruction to the read vector operation unit group 261 . The vector operation unit group 261 receives data from the vector register 241 and performs operations.

[motion]
Next, the operation of the processor described above will be described. In the following description, instructions to the processor are divided into cases where they are vector operation instructions and cases where they are not vector operation instructions.

• In case of vector operation instruction First, the processing in the SPU 100 will be described. The instruction cache 101 simultaneously outputs a plurality of instructions (four instructions in this embodiment) to the instruction decoder control section 122 via the signal line 110 .

The instruction decoder control unit 122 simultaneously decodes a plurality of instructions (four instructions in this embodiment), and outputs the result of instruction decoding and various information associated with the instructions to the vector operation instruction compression control unit 125 via the signal line 130 . . The instruction decoder control unit 122 also outputs the instruction decoding result to the vector operation instruction determination unit 123 via the signal line 131 .

The vector operation instruction determination unit 123 checks from the instruction decoding result whether or not the four instructions decoded at the same time are consecutive vector operation instructions in the 16 combinations of instructions shown in FIG. At this time, if vector operation instructions are consecutive, it is determined to be subject to instruction compression, and if not, it is determined not to be subject to instruction compression. Then, the vector operation instruction determination unit 123 determines whether or not the instruction is subject to instruction compression, and outputs seven combinations of instructions excluding overlapping cases to the vector operation instruction compression control unit 125 via the signal line 132. do.

Subsequently, the vector operation instruction determination unit 123 outputs the decode information of the vector operation instruction and the instruction IC to the vector operation exception IC register 124 via the signal line 133 . Then, the vector operation instruction determining unit 123 compares the IC of the vector operation instruction with the vector operation exception IC register 124 . At this time, among the vector operation instructions decoded at the same timing, the ICs are compared from the preceding instruction.

If part of the IC of the instruction compared with the vector operation exception IC register 124 matches, the IC comparison result is output to the vector operation instruction compression control unit 125 via the signal line 134 . If the ICs do not match (the mismatch includes valid bit=0), the IC of the vector operation instruction that does not match is registered in the vector operation exception IC register 124 as the operation exception IC of the reference instruction, and the valid bit= Make it 1. Note that the succeeding vector operation instruction is treated as an IC match because the preceding vector operation instruction always matches the IC registered in the vector operation exception IC register 124 . Such an IC comparison result is output to the vector operation instruction compression controller 125 via the signal line 134 .

The vector operation instruction compression control unit 125 selects no instruction compression or instruction compression according to the combinations shown in FIG. judge. That is, among a plurality of (here, four) vector operation instructions decoded at the same time, the instructions are consecutive to each other, and the preset high-order bits of the IC, which is the address information representing the storage location of the instructions, are A matching vector operation instruction is determined to have instruction compression.

Then, the vector operation instruction compression control unit 125 outputs the instruction to the instruction scheduler 141 via the signal line 135 in the case of “no instruction compression”. The instruction scheduler 141 stores the received instructions one by one in one entry in the form of a normal uncompressed vector operation instruction of the instruction 1 shown in FIG. At the same time, the IC of the corresponding instruction is added to the entry as an operation exception IC and stored in the entry. Also, the instruction compression bit is set to 0 at byte 14 shown in FIG.

Further, the vector operation instruction compression control unit 125 outputs the instruction to the instruction scheduler 141 via the signal line 135 when "instruction compression is present". The instruction scheduler 141 stores the received instructions in the form of one vector operation instruction in which the two instructions shown in FIG. 7 are integrated and compressed, two instructions per entry. At the same time, the lower byte of the operation exception IC of the first instruction is added to byte 14 of one entry as a relative IC from the reference instruction and stored in the entry. Also, the instruction compression bit is set to 1 at byte 14 shown in FIG.

The subsequent operation differs depending on the value of the above-described "instruction compression bit" included in byte 14 of the vector operation instruction stored as an entry in the instruction scheduler 141 of the SPU 100. FIG.

A case of "instruction compression bit=0" will be described. The instruction scheduler 141 determines whether an instruction can be issued for each stored entry, and outputs an instruction for each entry via a signal line 150 when the necessary resources are ready and the order of instructions can be guaranteed. Here, it is confirmed whether the data of the scalar register having the dependency for one instruction has been prepared for the scalar register. Regarding instruction order guarantee, the SPU 100 issues vector instructions in-order. The scalar register 161 outputs the data of the scalar register via the signal line 170 when the read instruction of the scalar register exists in the received instruction. The vector instruction issue control unit 181 issues various information and scalar register data for one instruction to the VPU 200 via the signal line 190 .

Processing within the VPU 200 will be described. The instruction decoder control unit 202 decodes the received instruction and outputs the instruction decoding result and various information accompanying the instruction to the vector operation instruction restoration control unit 204 via the signal line 210 . It also outputs the instruction decode result and the operation exception IC to the vector operation exception IC register 203 via the signal line 211 . The vector operation exception IC register 203 registers the high-order 6 bytes of the vector operation exception IC of the corresponding instruction as the operation exception IC of the reference instruction shown in FIG. Set bit=1.

If the vector operation instruction and the instruction compression bit=0, the vector operation instruction restoration control unit 204 determines that the instruction is not compressed, and outputs the instruction as it is to the instruction scheduler 221 via the signal line 213 without restoring the instruction. do. The instruction scheduler 221 stores the received instructions one by one in one entry. The instruction scheduler 221 determines whether an instruction can be issued for each stored entry, and outputs an instruction for each entry via a signal line 230 when the necessary resources are ready and the order of instructions can be guaranteed. Regarding instruction order guarantee, the VPU 200 issues vector instructions out of order. The vector register 241 outputs the data of the vector register via the signal line 250 when there is a vector register read designation in the received instruction. The vector operation unit group 261 receives data in vector registers and performs operations specified by instructions.

Next, the case of "instruction compression bit=1" will be described. The instruction scheduler 141 of the SPU 100 determines whether or not an instruction can be issued for each stored entry, and outputs an instruction for each entry via a signal line 150 when the necessary resources are ready and the instruction order can be guaranteed. do. Here, since instructions are compressed with respect to the scalar registers, it is confirmed whether the data of the dependent scalar registers for two instructions has been prepared. Regarding instruction order guarantee, the SPU 100 issues vector instructions in-order. The scalar register 161 outputs the data of the scalar register via the signal line 170 when the read instruction of the scalar register exists in the received instruction. The vector instruction issue control unit 181 issues various information and scalar register data for two instructions to the VPU 200 via the signal line 190 .

Processing within the VPU 200 will be described. The instruction decoder control unit 202 decodes the received instruction and outputs the instruction decoding result and various information accompanying the instruction to the vector operation instruction restoration control unit 204 via the signal line 210 . It also outputs the instruction decode result and the operation exception IC to the vector operation exception IC register 203 via the signal line 211 . The vector operation exception IC register 203 does not newly register the operation exception IC of the registered reference instruction in the case of the vector operation instruction and the instruction compression bit=1. Output to the restoration control unit 204 .

When the vector operation instruction and the instruction compression bit=1, the vector operation instruction restoration control unit 204 determines that there is instruction compression, and outputs the restored two instructions from one instruction to the instruction scheduler 221 . Regarding the method of restoring the operation exception IC, as shown in FIG. "Relative IC from reference instruction" included in . For the second instruction, the upper 6 bytes are the operation exception IC of the registered reference instruction, and the 7th byte is the "relative IC from the reference instruction" + "instruction compressed 1 The instruction length of the instruction number (8 bytes in the example of the present invention).

The instruction scheduler 221 stores the received instructions one by one in one entry. Here, two instructions are stored in two entries. The instruction scheduler 221 determines whether an instruction can be issued for each stored entry, and outputs an instruction for each entry via a signal line 230 when the necessary resources are ready and the order of instructions can be guaranteed. Regarding instruction order guarantee, the VPU 200 issues vector instructions out of order. The vector register 241 outputs the data of the vector register via the signal line 250 when there is a vector register read designation in the received instruction. The vector operation unit group 261 receives data in vector registers and performs operations specified by instructions.

Non-Vector Operation Instruction Next, a case where the instruction to the processor is not a vector operation instruction will be described. Within the SPU 100 , the instruction cache 101 simultaneously outputs a plurality of instructions (four instructions in this embodiment) to the instruction decoder control section 122 via the signal line 110 . The instruction decoder control unit 122 simultaneously decodes a plurality of instructions (four instructions in this embodiment), and outputs the result of instruction decoding and various information associated with the instructions to the vector operation instruction compression control unit 125 via the signal line 130 . . Also, the instruction decoding result is output to the vector operation instruction determination unit 123 via the signal line 131 .

The vector operation instruction determination unit 123 checks whether the vector operation instructions are consecutive in the 16 combinations of instructions shown in FIG. The correct combination of instructions is output to the vector operation instruction compression controller 125 via the signal line 132 . In this case, since no vector operation instruction is included, all of them are excluded from the compression target.

The vector operation instruction compression control unit 125 outputs instructions to the instruction scheduler 141 via the signal line 135 . The instruction scheduler 141 stores one instruction per entry in the form of a normal instruction without compressing the received instruction. The instruction scheduler 141 determines whether an instruction can be issued for each stored entry, and outputs an instruction for each entry via a signal line 150 when the necessary resources are ready and the order of instructions can be guaranteed. Regarding instruction order guarantee, the SPU 100 issues vector instructions in-order. The scalar register 161 outputs the data of the scalar register via the signal line 170 when the read instruction of the scalar register exists in the received instruction. The vector instruction issue control unit 181 issues various information and scalar register data for one instruction to the VPU 200 via the signal line 190 .

Within the VPU 200 , the instruction decoder control unit 202 decodes the received instruction and outputs the instruction decoding result and various information associated with the instruction to the vector operation instruction restoration control unit 204 via the signal line 210 . If the vector operation instruction is not a vector operation instruction, the vector operation instruction restoration control unit 204 determines that the instruction is not compressed, and outputs the instruction as it is to the instruction scheduler 221 via the signal line 213 without restoring the instruction.

The instruction scheduler 221 stores the received instructions one by one in one entry. The instruction scheduler 221 determines whether an instruction can be issued for each stored entry, and outputs an instruction for each entry via a signal line 230 when the necessary resources are ready and the order of instructions can be guaranteed. Regarding the instruction order guarantee, the VPU issues vector instructions out of order. The vector register 241 outputs the data of the vector register via the signal line 250 when there is a vector register read designation in the received instruction. The vector operation unit group 261 receives data in vector registers and performs operations specified by instructions.

[effect]
As explained above, the present invention has the following effects. First, in a processor that executes vector instructions, instruction compression control by the instruction decoder 121 of the SPU 100 and instruction decompression control by the instruction decoder 201 of the VPU 200 enable the SPU 100 to issue a plurality of vector operation instructions in one clock. . This makes it possible to improve the issue rate of vector operation instructions between SPU-VPU units. In addition, since it can be realized only by hardware functions, it is possible to enjoy an improvement in the vector operation instruction issue rate without changing existing software.

Further, by utilizing the field of the operation exception IC, it is possible to store the compressed instruction with the minimum increase in the circuit amount of the instruction scheduler. In addition, by compressing instructions, even with a configuration having the same number of entries as the conventional instruction scheduler, the number of instructions to be stored can be increased, so performance improvement can be expected.

Here, the effect of improving the issue rate of specific vector instructions is calculated. First, assuming that the ratio of vector load instructions and vector operation instructions is 1 byte/Flops as an instruction string, consider an instruction string that outputs the calculation result with a vector store instruction. As input data for calculation, a total of 8 bytes×3=24 bytes (VLD instruction×3 instructions) and VFMA instruction is 2 flops/instruction, resulting in a combination of 24/2=12 instructions. Finally, since the output of the calculation result is an instruction sequence containing a vector store instruction, 16 clocks are required to issue a vector instruction without the instruction compression shown in FIG. can be reduced to Also, when using VFMP (floating point multiplication) instructions and VFAD (floating point addition) instructions instead of VFMA instructions as vector operation instructions, 28 clocks are required to issue vector instructions if there is no instruction compression shown in FIG. However, it can be reduced to 17 clocks by the instruction compression of the present invention.

In this way, the greater the number of vector operation instructions, the greater the effect of the present invention. Also, the efficiency of storing instructions in the instruction scheduler of the SPU is similarly improved. For example, in the example of FIG. 13, 16 entries are required without instruction compression, but this is reduced to 11 entries with instruction compression. Similarly, in the example of FIG. 14, 28 entries are required without instruction compression, but this is reduced to 17 entries with instruction compression.

In the above description, the instruction decoder has a 4-instruction simultaneous decoding configuration as a function of decoding a plurality of instructions at the same time. Moreover, although the above example illustrates the case where two instructions are integrated into one, three or more instructions may be integrated into one.

Further, although the pipeline for issuing vector instructions is configured with one pipeline, it may be configured with two or more pipelines. Also, although the instruction length is 8 bytes, any number of bytes may be used. As a vector operation instruction, an instruction in a 4-operand format has been described, but other operand formats may be used. For example, a 3-operand format that performs VFAD V0←V1+V2 with a vector floating point addition instruction may be used. Although an example of compressing and decompressing two vector operation instructions at the same time has been shown, any number of instructions may be compressed and decompressed.

Also, although the IC has a 56-bit address, any number of bits may be used. Although the reference IC is provided for every 256 bytes as the operation exception IC, the reference may be provided for any number of bytes. By increasing the size of the standard IC, the range of instruction compression is widened, but the number of bits required to express the relative IC increases.

In the above, a processor including the SPU 100 and VPU 200 configured by hardware is exemplified, but functions equivalent to those of the SPU 100 and VPU 200 may be realized by incorporating a software program into the processor.

<Embodiment 2>
A second embodiment of the present invention will now be described with reference to FIG. FIG. 15 is a block diagram showing a configuration of a processor according to the second embodiment; Note that the present embodiment shows an outline of the configuration of the processor described in the first embodiment.

As shown in FIG. 15, the processor 300 in this embodiment
It comprises a scalar processing unit 310 that performs scalar operations and a vector processing unit 320 that performs vector operations.
Then, the scalar processing unit 310 issues to the vector processing unit 320 an integrated vector operation instruction in which two or more of the simultaneously decoded vector operation instructions are integrated as one instruction,
The vector processing unit 320 restores the integrated vector operation instruction to two or more vector operation instructions before integration, and performs vector operations respectively according to the two or more vector operation instructions.
take the configuration.

Note that the scalar processing unit 310 and the vector processing unit 320 may be implemented by the processor 300 executing a program.

According to the above invention, multiple vector instructions are compressed into one instruction after instruction decoding by the scalar processing unit 310, stored in the instruction scheduler, and the vector instruction is issued to the vector processing unit 320 in the compressed format. The vector processing unit 320 then provides the function of decompressing the compressed instructions. As a result, the vector instruction issue rate between the scalar processing unit 310 and the vector processing unit 320 can be improved without impairing the normal functions of the vector processor.

<Appendix>
Some or all of the above embodiments may also be described as the following appendices. The outline of the configuration of the processor, the information processing method, and the program according to the present invention will be described below. However, the present invention is not limited to the following configurations.

(Appendix 1)
A processor comprising a scalar processing unit that performs scalar operations and a vector processing unit that performs vector operations,
The scalar processing unit issues to the vector processing unit an integrated vector operation instruction in which two or more of the simultaneously decoded vector operation instructions are integrated as one instruction,
The vector processing unit restores the integrated vector operation instruction to two or more vector operation instructions before integration, and performs vector operations respectively according to the two or more vector operation instructions.
processor.

(Appendix 2)
1. The processor of Clause 1,
wherein the scalar processing unit integrates two or more consecutive vector operation instructions among a plurality of simultaneously decoded vector operation instructions into one instruction;
processor.

(Appendix 3)
The processor according to Appendix 1 or 2,
The scalar processing unit integrates two or more vector operation instructions out of a plurality of simultaneously decoded vector operation instructions into one instruction based on address information representing the respective storage locations of the vector operation instructions.
processor.

(Appendix 4)
3. The processor of Appendix 3,
The scalar processing unit integrates, among a plurality of vector operation instructions decoded at the same time, two or more vector operation instructions whose address information representing the respective storage locations of the vector operation instructions is partially identical as one instruction.
processor.

(Appendix 5)
The processor according to any one of Appendices 1 to 4,
In the scalar processing unit, of the plurality of vector operation instructions decoded at the same time, the predetermined high-order addresses that are successive to each other and are part of the address information representing the storage locations of the respective vector operation instructions match. Integrating two or more vector operation instructions as one instruction,
processor.

(Appendix 6)
The processor according to any one of Appendices 1 to 5,
The scalar processing unit transmits a non-integrated vector operation instruction including address information representing a storage location of the vector operation instruction to the vector processing unit, and stores two or more vector operations before integration in the integrated vector operation instruction. transmitting to the vector processing unit including a portion of address information representing at least one storage location of instructions;
processor.

(Appendix 7)
6. The processor of clause 6,
The scalar processing unit transmits to the vector processing unit the integrated vector operation instruction including a preset lower address of address information representing a storage location of one vector operation instruction before integration,
The vector processing unit performs two or more vector operations before integration of the integrated vector operation instruction based on the address information included in the non-integrated vector operation instruction and the lower address included in the integrated vector operation instruction. Acquire address information representing the storage location of instructions,
processor.

(Appendix 8)
An information processing method by a processor comprising a scalar processing unit that performs scalar operations and a vector processing unit that performs vector operations,
The scalar processing unit issues to the vector processing unit an integrated vector operation instruction in which two or more of the simultaneously decoded vector operation instructions are integrated as one instruction,
The vector processing unit restores the integrated vector operation instruction to two or more vector operation instructions before integration, and performs vector operations respectively according to the two or more vector operation instructions.
Information processing methods.

(Appendix 9)
to the processor,
Realizing a scalar processing unit that performs scalar operations and a vector processing unit that performs vector operations,
The scalar processing unit issues to the vector processing unit an integrated vector operation instruction in which two or more of the simultaneously decoded vector operation instructions are integrated as one instruction,
The vector processing unit restores the integrated vector operation instruction to two or more vector operation instructions before integration, and performs vector operations respectively according to the two or more vector operation instructions.
program to make it happen. .

It should be noted that the above program can be stored and supplied to the computer using various types of non-transitory computer readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (eg, flexible discs, magnetic tapes, hard disk drives), magneto-optical recording media (eg, magneto-optical discs), CD-ROMs (Read Only Memory), CD-Rs, CD-R/W, semiconductor memory (eg, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)). The program may also be delivered to the computer on various types of transitory computer readable medium. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transitory computer-readable media can deliver the program to the computer via wired channels, such as wires and optical fibers, or wireless channels.

Although the present invention has been described with reference to the above-described embodiments and the like, the present invention is not limited to the above-described embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

100 SPU (scalar processing unit)
101 Instruction cache 121 Instruction decoder 122 Instruction decoder control unit 123 Vector operation instruction determination unit 124 Vector operation exception IC register 125 Vector operation instruction compression control unit 141 Instruction scheduler 161 Scalar register 181 Vector instruction issue control unit 200 VPU (Vector Processing Unit)
201 instruction decoder 202 instruction decoder control unit 203 vector operation exception IC register 204 vector operation instruction restoration control unit 221 instruction scheduler 241 vector register 261 vector operation unit group 300 processor 310 scalar processing unit 320 vector processing unit

Claims (8)

A processor comprising a scalar processing unit that performs scalar operations and a vector processing unit that performs vector operations,
The scalar processing unit issues to the vector processing unit an integrated vector operation instruction in which two or more of the simultaneously decoded vector operation instructions are integrated as one instruction,
The vector processing unit restores the integrated vector operation instruction to two or more vector operation instructions before integration, and performs vector operations respectively according to the two or more vector operation instructions,
processor.
Further, the scalar processing unit transmits the non-integrated vector operation instruction including address information representing the storage location of the vector operation instruction to the vector processing unit, and the integrated vector operation instruction includes the two or more pre-integrated vector operation instructions. transmitting to the vector processing unit including a portion of address information representing at least one storage location of a vector operation instruction;
processor. 2. The processor of claim 1, comprising:
wherein the scalar processing unit integrates two or more consecutive vector operation instructions among a plurality of simultaneously decoded vector operation instructions into one instruction;
processor. 3. A processor according to claim 1 or 2, comprising:
The scalar processing unit integrates two or more vector operation instructions out of the simultaneously decoded vector operation instructions into one instruction based on address information representing the respective storage locations of the vector operation instructions.
processor. 4. The processor of claim 3, comprising:
The scalar processing unit integrates, among a plurality of vector operation instructions decoded at the same time, two or more vector operation instructions whose address information representing the respective storage locations of the vector operation instructions is partially identical as one instruction.
processor. A processor according to any one of claims 1 to 4,
In the scalar processing unit, of the plurality of vector operation instructions decoded at the same time, the predetermined high-order addresses that are successive to each other and are part of the address information representing the storage locations of the respective vector operation instructions match. Integrating two or more vector operation instructions as one instruction,
processor. A processor according to any one of claims 1 to 5 ,
The scalar processing unit transmits to the vector processing unit the integrated vector operation instruction including a preset lower address of address information representing a storage location of one vector operation instruction before integration,
The vector processing unit performs two or more vector operations before integration of the integrated vector operation instruction based on the address information included in the non-integrated vector operation instruction and the lower address included in the integrated vector operation instruction. Acquire address information representing the storage location of instructions,
processor. An information processing method by a processor comprising a scalar processing unit that performs scalar operations and a vector processing unit that performs vector operations,
The scalar processing unit issues to the vector processing unit an integrated vector operation instruction in which two or more of the simultaneously decoded vector operation instructions are integrated as one instruction,
The vector processing unit restores the integrated vector operation instruction to two or more vector operation instructions before integration, and performs vector operations respectively according to the two or more vector operation instructions,
Further, the scalar processing unit transmits the non-integrated vector operation instruction including address information representing the storage location of the vector operation instruction to the vector processing unit, and the integrated vector operation instruction includes the two or more pre-integrated vector operation instructions. transmitting to the vector processing unit including a portion of address information representing at least one storage location of a vector operation instruction;
Information processing methods. to the processor,
Realizing a scalar processing unit that performs scalar operations and a vector processing unit that performs vector operations,
The scalar processing unit issues to the vector processing unit an integrated vector operation instruction in which two or more of the simultaneously decoded vector operation instructions are integrated as one instruction,
The vector processing unit restores the integrated vector operation instruction to two or more vector operation instructions before integration, and performs vector operations respectively according to the two or more vector operation instructions,
Further, the scalar processing unit transmits the non-integrated vector operation instruction including address information representing the storage location of the vector operation instruction to the vector processing unit, and the integrated vector operation instruction includes the two or more pre-integrated vector operation instructions. transmitting to the vector processing unit including a portion of address information representing at least one storage location of a vector operation instruction;
program to make it happen.

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