JP7189441B2 - Implementation method - Google Patents

Description

The present invention relates to a method of mounting a light emitting element.

Light-emitting devices are widely used in fields such as optical communication, display devices, and lighting. A light-emitting element is mounted on a wiring board for current injection and packaged as necessary. Generally, a light emitting element is flip-chip mounted on a wiring board using protruding electrodes called bumps.

In mounting a light-emitting element, it has been proposed to make the height of the bumps provided on the light-emitting element sufficiently larger than the amount of substrate warpage of the element, and to form submicron-sized irregularities on the bonding surface of the bumps (for example, , see Patent Document 1).

JP 2014-93339 A

In the above Patent Document 1, the warpage of the substrate is absorbed by making the height of the bumps sufficiently larger than the amount of warpage of the substrate, and nanoimprinting or plasma etching is performed on the bonding surface in order to absorb variations in the height of the bumps. to form unevenness of several hundred nm.

The method of Patent Document 1 requires a step of nanoimprinting or plasma etching in addition to the step of forming bumps.

By the way, when manufacturing a light-emitting device such as an LED or a laser diode, if a compound semiconductor layer having a thermal expansion coefficient different from that of the substrate is formed on the substrate, the obtained chip is warped. When the light emitting element is mounted on a wiring board such as a printed circuit board, the outer peripheral portion of the light emitting element is warped and lifted, resulting in insufficient bonding between the light emitting element and the wiring board. In general, it is conceivable to increase the load at the time of bonding in order to strengthen the bonding, but increasing the load causes damage to the light emitting element.

An object of the present invention is to provide a mounting method capable of stably bonding a light emitting element to a wiring board without increasing the load.

In one aspect of the present invention, a mounting method for mounting a light-emitting element having a substrate on a wiring board includes forming a plurality of first connection portions in an outer peripheral area of a main surface of the light-emitting element and an inner area inside the outer peripheral area. forming a plurality of second connection portions having a smaller upper area than the first connection portions on each of the plurality of first connection portions formed in the inner region; a step of forming a plurality of third connection portions having an upper area smaller than that of the second connection portion on each of the plurality of formed first connection portions; 3 bonding to the wiring board via a connecting portion.

By the mounting method described above, the light emitting element can be stably mounted on the wiring board without increasing the load.

FIG. 4 is a schematic diagram illustrating warping of a substrate when mounting a light emitting device according to an embodiment of the present invention. 1 is a schematic plan view of a bonding surface of a light emitting element, which is an example of a light emitting element; FIG. FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. 2; 1 is a schematic diagram of a bump structure according to one embodiment of the present invention; FIG. 1 is a schematic diagram of a bump structure according to one embodiment of the present invention; FIG. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the light emitting element of one Embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the light emitting element of one Embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the light emitting element of one Embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the light emitting element of one Embodiment of this invention. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the light emitting element of one Embodiment of this invention. It is a schematic diagram of the bump structure of the modification of this invention. It is a schematic diagram of the bump structure of the modification of this invention. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the light emitting element of the modification of this invention. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the light emitting element of a modification. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the light emitting element of a modification. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the light emitting element of a modification. It is a schematic diagram which shows the state which mounted the light emitting element in the wiring board. 1 is a schematic diagram of a light-emitting device in which a light-emitting element is mounted on a wiring board; FIG.

FIG. 1 is a diagram for explaining warpage of a substrate when mounting a light-emitting element 20 according to an embodiment. The light emitting device 20 has a substrate 201 and a semiconductor layer 202 formed on the substrate 201 . The substrate 201 may be any substrate as long as the semiconductor layer 202 can be epitaxially grown thereon. desirable. Sapphire (Al ₂ O ₃ ), spinel (MgAl ₂ O ₄ ), gallium oxide (Ga 2 O 3 ), and the like are used as such growth substrates. The size of the substrate 201 when viewed from above is, for example, 500 μm or more and 2000 μm or less on a side. Moreover, the top view shape of the board|substrate 201 is a rectangular shape, for example. When a sapphire substrate is used for the substrate 201, the thickness of the substrate 201 can be set to 100 μm or more and 300 μm or less, for example.

When a semiconductor layer 202 such as gallium nitride (GaN) is formed on the substrate 201 , the difference in thermal expansion coefficient between the substrate 201 and the semiconductor layer 202 causes warping of the chipped light emitting elements 20 . For example, a sapphire substrate has a thermal expansion coefficient of 8.5×10 ⁻⁶ /K in the c-axis direction and a thermal expansion coefficient of 7.5×10 ⁻⁶ /K in the a-axis direction. On the other hand, the thermal expansion coefficient of GaN in the c-axis direction is 7.75×10 ⁻⁶ /K, and the thermal expansion coefficient in the a-axis direction is 5.59×10 ⁻⁶ /K. rate difference is large. The thickness of the semiconductor layer 202 formed on the substrate 201 is, for example, 5 μm or more and 15 μm or less.

Since the coefficient of thermal expansion of the sapphire substrate is larger than that of GaN, the substrate 201 deforms more than the semiconductor layer 202 and bends toward the substrate 201 as shown in FIG.

More specifically, the wafer is flat at the stage of growing the semiconductor layer 202 of GaN on the substrate 201 in the reactor. When the wafer is removed from the reactor and cooled, the wafer is warped such that the central portion of the substrate 201 is convex with respect to the semiconductor layer 202 . This is caused by the substrate 201 shrinking more than the semiconductor layer 202 . Due to such warping of the wafer, warps remain in each chip after the wafer is cut into individual chips.

When the semiconductor layer 202 of the light emitting element 20 faces the mounting surface of the wiring board 11 and is joined to the electrodes on the wiring pattern 14, a load is applied to join the electrodes of the light emitting element 20 and the electrodes on the wiring board 11 side. multiply. If the outer peripheral portion of the light emitting element 20 is lifted, the bonding at the outer peripheral portion may become insufficient. If the load on the outer peripheral portion is increased, the bonding strength can be obtained, but the damage on the outer peripheral portion increases.

In the embodiment, the reliability of bonding between the light emitting element 20 and the wiring substrate 11 is improved by reducing bonding defects caused by warping of the substrate 201 of the light emitting element 20 without increasing the load. Also, the heat dissipation effect at the junction is enhanced.

FIG. 2 is a plan view of a bonding surface of a light emitting element 20A that is an example of the light emitting element 20. FIG. The bonding surface is a surface facing the wiring substrate 11 when the light emitting element 20 and the wiring substrate 11 are bonded.

The light emitting element 20A has an outer peripheral region RB and an inner region RA inside the outer peripheral region RB. Here, the outer peripheral region RB is a region from the outer edge of the substrate 201 to a distance of 15% of the length of one side of the substrate 201 . As described with reference to FIG. 1, in the outer peripheral region RB, the bonded portion tends to be more raised than the inner region RA due to the warp of the substrate. In other words, the bonding surface in the outer peripheral region RB tends to separate from the wiring board 11 more easily than in the inner region RA, which may make bonding difficult during mounting. In the embodiment, the reliability of bonding is improved without increasing the load by devising the bump structure that serves as the bonding portion.

As shown in FIG. 3, the light emitting element 20A is formed on a substrate 201 and includes a semiconductor layer of a first conductivity type (hereinafter referred to as a "first semiconductor layer 23"), a light emitting layer 24, and a semiconductor layer of a second conductivity type. A first electrode 26 electrically connected to the first semiconductor layer 23 is provided on the bonding surface side of the light emitting element 20A. and a second electrode 27 electrically connected to the second semiconductor layer 25. In this example, the first semiconductor layer 23 is an n-type semiconductor layer, and the second semiconductor layer 25 is a p-type semiconductor layer. It is a semiconductor layer.

In each of the first electrode 26 and the second electrode 27, the first bump 21 is formed in the inner region RA, and the second bump 22 is formed in the outer region RB. The first bumps 21 and the second bumps 22 protrude from the bonding surface of the light emitting element 20A in order to be bonded to the wiring substrate 11 for electrical connection. The shape of the first bumps 21 and the second bumps 22 can be, for example, a columnar shape, a ball shape, or the like. The first bumps 21 and the second bumps 22 are regularly or randomly arranged on the joint surface side of the light emitting element 20A so that the current supplied to the light emitting element 20A is not concentrated in a part of the area.

As will be described later, the first bumps 21 in the inner area RA and the second bumps 22 in the outer area RB differ in the structure of their joint ends. A plurality of protrusions having a first diameter are formed on the connection end surface of the first bump 21 in the inner area RA. A plurality of protrusions having a second diameter larger than the first diameter are formed on the connection end surface of the second bump 22 in the outer peripheral region RB.

FIG. 3 is a cross-sectional view taken along line III--III in FIG. The cross section along line III-III shows the second bump 22 on the second electrode 27 in the outer peripheral region RB, the exposed portion 23a of the first semiconductor layer 23 described later in the outer peripheral region RB, and the first electrode 26 in the inner region RA. is a cross section including the first bump 21 of .

The light-emitting element 20A has a substrate 201 and a semiconductor layer 202 provided on the substrate 201 . As shown in FIG. 3, the surface of the substrate 201 may have fine unevenness for light scattering. The fine unevenness has the effect of improving light extraction efficiency and suppressing dislocations that occur when the semiconductor layer 202 having a lattice constant different from that of the substrate 201 is grown. A buffer layer that alleviates lattice mismatch may be formed on the surface of the substrate 201 . When the substrate 201 is a sapphire substrate and the semiconductor layer 202 is a gallium nitride semiconductor, GaN, aluminum nitride (AlN), gallium aluminum nitride (AlGaN), or the like can be used as the buffer layer.

As shown in FIG. 3, the semiconductor layer 202 includes a first semiconductor layer 23, a light emitting layer 24, and a semiconductor layer 25 of the second conductivity type stacked in this order. In the first semiconductor layer 23, the light emitting layer 24 and the second semiconductor layer 25 are removed from the second semiconductor layer 25 side, and a part of the first semiconductor layer 23 is exposed from the light emitting layer 24 and the second semiconductor layer 25. An exposed portion 23a is formed. As shown in FIG. 2, the semiconductor layer 202 is formed with a plurality of exposed portions 23a. The first semiconductor layer 23 is formed of a semiconductor layer containing GaN, for example, and includes a semiconductor layer doped with Si as an impurity. The light emitting layer 24 is, for example, a single quantum well (SQW) or a multilayer quantum well (MQW) in which an InGaN well layer is sandwiched between GaN barrier layers. The second semiconductor layer 25 is formed of a semiconductor layer containing GaN, for example, and includes a semiconductor layer doped with Mg as an impurity. The first semiconductor layer 23 has a contact layer with the first electrode 26 and supplies electrons to the light emitting layer 24 . The second semiconductor layer 25 has a contact layer with the second electrode 27 and supplies holes to the light emitting layer 24 . The injected electrons and holes combine, and the semiconductor layer 202 emits light with a wavelength corresponding to the bandgap energy of the well layer.

As shown in FIG. 3, a metal film 205 having a predetermined pattern is formed on the second semiconductor layer 25 of the semiconductor layer 202 . The metal film 205 functions as a reflective film and is made of a material having high reflectivity with respect to light generated by the light emitting layer 24 . The metal film 205 is made of, for example, Ag, Al, or an alloy containing these metals as a main component. The metal film 205 reflects the light generated by the light emitting layer 24 to the substrate 201 side.

An insulating film 206 is formed to cover the metal film 205 provided on the second semiconductor layer 25 . The insulating film 206 is formed with an opening 206a on the metal film 205 through which the metal film 205 is exposed. The material of the insulating film 206 is not limited, and any electrically insulating material such as metal oxide, metal nitride, or oxynitride can be used. As an example, the insulating film 206 is made of SiN.

As shown in FIG. 3, the protective film 207 is provided to cover the insulating film 206, the second semiconductor layer 25, the light emitting layer 24, and the first semiconductor layer 23. As shown in FIG. In the protective film 207, an n-side opening 207n provided on the exposed portion 23a of the first semiconductor layer 23 and a p-side opening 207p provided on the opening 206a of the insulating film 206 are formed. there is The material used for the protective film 207 is not limited, and for example, an SiO ₂ film, a SiN film, or an oxide film containing aluminum, a nitride film, an oxynitride film, or the like can be used.

The first electrode 26 is electrically connected to the first semiconductor layer 23 at the n-side opening 207n. A portion of the first electrode 26 is provided on the second semiconductor layer 25 via the insulating film 206 and the protective film 207 .

The second electrode 27 is provided on the metal film 205 and electrically connected to the metal film 205 through the opening 206a and the p-side opening 207p. The second electrode 27 is electrically connected to the second semiconductor layer 25 via the metal film 205 . A portion of the second electrode 27 may be provided on the insulating film 206 .

The first electrode 26 and the second electrode 27 are made of any metal material, and the material is not limited. For the first electrode 26 and the second electrode 27, for example, Al, Ag, or alloys containing these metals as main components can be used.

In the inner region RA, a first bump 21 is provided on the first electrode 26, and a plurality of protrusions are provided on the upper surface of the first bump 21. As shown in FIG. In the outer peripheral region RB, the second bumps 22A are provided on the second electrodes 27, and projections are provided on the upper surfaces of the second bumps 22A at a narrower pitch than the projections of the first bumps 21. As shown in FIG. Here, the "upper surface" is the upper surface of the light emitting element 20A when viewed in the stacking direction, and even the surface facing the wiring board 11 when mounted is the "upper surface" when viewed in the stacking direction.

Instead of the III-III cross section in FIG. Also in the cross section passing through the two bumps 22 and the first bumps 21 in the inner area RA, the configuration of the bump bonding end is like the second bumps 22A and the first bumps 21 in FIG.

4A and 4B are schematic diagrams showing the bump structure of the embodiment. FIG. 4A shows the first bump 21 formed in the inner area RA. Also, FIG. 4B shows the second bump 22A formed in the outer peripheral region RB. Since FIGS. 4A and 4B are drawn in the state of flip-chip mounting, the first bump 21 and the second bump 22A in FIG. 3 are upside down.

The first bump 21 has a first connection portion 211 and a second connection portion 212 provided on the first connection portion 211 . The second bump 22</b>A has a first connection portion 211 and a third connection portion 213 provided on the first connection portion 211 . The first connecting portion 211 is provided on the first electrode 26 and the second electrode 27 . The materials of the first connecting portion 211, the second connecting portion 212, and the third connecting portion 213 may be the same or different.

The area of the end surface 211s of the first connection portion 211 of the first bump 21 and the area of the end surface 211s of the first connection portion 211 of the second bump 22A are substantially the same or the difference is small. The end surface 211s corresponds to the "upper surface" in the bump formation process. Although the planar shape of the end face 211s is not limited, for example, it can be circular or rectangular. When the planar shape of the end surface 211s is circular, the diameter of the end surface 211s can be, for example, 40 μm to 60 μm.

In the first bump 21, a plurality of second connection portions 212 are formed on the end face 211s of the first connection portion 211 at a pitch P1. In the second bump 22A, a plurality of third connection portions 213 are formed on the end surface 211s of the first connection portion 211 at a pitch P2. Here, the pitch means the distance between two adjacent second connection portions 212 . Also, the pitch means the distance between two adjacent third connection portions 213 .

The pitch P1 of the second connection portion 212 is larger than the pitch P2 of the third connection portion 213 (P1>P2). The top area of the second connection portion 212 is larger than the top area of the third connection portion 213 . The upper areas of the second connecting portion 212 and the third connecting portion 213 mean the areas of the surfaces of the second connecting portion 212 and the third connecting portion 213 opposite to the surfaces in contact with the end surface 211s.

The pitch P1 and the pitch P2 are appropriately set according to the amount of warpage of the substrate, the load at the time of bonding, and the like so that the relationship P1>pitch P2 is satisfied. For example, when the warp amount of the substrate is large, the pitch P2 is made smaller than the pitch P1. Also, when the load at the time of joining is small, the pitch P2 is made smaller than the pitch P1. By setting such a pitch relationship, the area where the third connecting portion 213 is formed increases, and heat dissipation in the outer peripheral region RB where the third connecting portion 213 is formed can be ensured. As an example, when a sapphire substrate is used for the substrate 201 and GaN is used for the semiconductor layer 202, the average warp amount of the outer peripheral region RB of the substrate is 0.5 μm to 0.6 μm. In this case, the pitch P1 can be, for example, 5 μm to 30 μm. The pitch P2 can be 1 μm to 10 μm.

The height of the second connection portion 212 of the first bump 21 and the height of the third connection portion 213 of the second bump 22A are both L1 in the example of FIG. The height L1 is, for example, about 1/10 to 1/2 of the height of the first connecting portion 211. As shown in FIG.

When the outer peripheral region RB of the light emitting element 20 is lifted, it is conceivable to reduce the diameter of the second bumps 22A in the outer peripheral region RB in accordance with the decrease in the load applied to the outer peripheral region RB during bonding. However, if the bump diameter is simply reduced, there is a risk that the heat dissipation effect through the bumps will be impaired. In the embodiment, by not partially reducing the size of the first connection portion 211 arranged on the side of the light emitting element 20 in the bump, the area where the bump and the light emitting element 20 are bonded is ensured and the heat dissipation effect through the bump is ensured. Decrease can be suppressed.

In the present embodiment, by making the area of the end surface 211s of the first connection portion 211 uniform over the entire element on the base side of the bump, a uniform heat dissipation effect can be ensured.

On the other hand, in the second connection portion 212 and the third connection portion 213 located on the wiring board 11 side of the bump, the top area of the third connection portion 213 is made smaller than the top area of the second connection portion 212 . This makes it easier for the third connection portion 213 to be crushed by a smaller load than the second connection portion 212 . Therefore, the second bumps 22A can be reliably bonded to the wiring substrate 11 even if the load applied to the outer peripheral region RB is reduced due to the warp of the substrate 201 . Conversely, the second bumps 22A can be bonded to the wiring substrate 11 and the heat dissipation effect can be maintained without increasing the load in the outer peripheral region RB where the substrate warps greatly.

The number of the second connection portions 212 formed on each first connection portion 211 is less than the number of the third connection portions 213 formed on each first connection portion 211 . As a result, the area where the third connecting portion 213 is formed increases, and the heat dissipation in the outer peripheral region RB where the third connecting portion 213 is formed can be ensured.

When the bonding in the outer peripheral region RB is insufficient, if the light emitting element 20A is separated from the wiring substrate 11 in the evaluation test after bonding, the interface breakdown between the first bumps 21 and the electrodes on the wiring substrate 11 occurs in the inner region RA. , the bump material remains on the peeled surface of the wiring substrate 11 . However, since the second bumps 22A are not bonded or the bonding by the second bumps 22A is weak in the outer peripheral region RB, no bump material remains on the peeled surface of the wiring substrate 11. FIG.

On the other hand, in the configuration of the embodiment, since the first bumps 21 and the second bumps 22A are bonded over the entire light emitting element 20A, after peeling in the evaluation test, both the inner area RA and the outer area RB are bonded to the wiring board. Bump material remains on 11 .

The total area of the tip surface of the second connection portion 212 and the total area of the tip surface of the third connection portion 213 per bump may be the same. The number and size of the second connection portions 212 and the third connection portions 213 are limited as long as the second connection portions 212 and the third connection portions 213 are thermocompression-bonded to the electrodes on the wiring substrate 11 and integrated with the electrodes at the time of bonding. , pitch, etc. can be designed appropriately.

5A to 5E are manufacturing process diagrams of the light emitting device 20A of the embodiment. These manufacturing process diagrams show states in respective manufacturing processes on the III-III cross section of FIG.

In FIG. 5A, a resist 40 having a predetermined opening pattern is formed while the device structure including the first electrode 26 and the second electrode 27 is formed on the substrate 201 . As for the device structure, for example, the semiconductor layer 202 is formed by growing the first semiconductor layer 23 , the light emitting layer 24 and the second semiconductor layer 25 in this order on the substrate 201 . Prior to forming the first semiconductor layer 23, the surface of the substrate 201 may be roughened by, for example, reactive ion etching.

A metal film 205 having a predetermined pattern is formed on the surface of the second semiconductor layer 25 of the semiconductor layer 202 , and an insulating film 206 is formed to cover the surface of the second semiconductor layer 25 and the metal film 205 . After that, the insulating film 206, the second semiconductor layer 25, and part of the light emitting layer 24 are removed to form an exposed portion 23a at a predetermined location. Next, the surfaces of the insulating film 206 , the second semiconductor layer 25 , the light emitting layer 24 and the first semiconductor layer 23 are covered with a protective film 207 . Then, a part of the protective film 207 is removed, an n-side opening 207n and a p-side opening 207p are formed, and a first electrode 26 and a second electrode 27 are formed on the protective film 207, respectively. is obtained.

The resist 40 has an opening pattern including an n-side opening 41 and a p-side opening 42 . The opening pattern is formed by normal photolithography by exposure and development. In this example along the III-III section, the n-side opening 41 is formed in the inner region RA and the p-side opening 42 is formed in the outer region RB. The diameters of the n-side opening 41 and the p-side opening 42 are, for example, 40 μm to 60 μm.

In FIG. 5B, the first connecting portion 211 is grown by plating in the n-side opening 41 of the inner region RA and the p-side opening 42 of the outer peripheral region RB (first plating process). The first connection part 211 is formed of a material suitable for bump bonding, such as Au, Ag, Cu, Pt, Ni, Sn, or an alloy of two or more of these. In this example, the first connecting portion 211 is formed by electrolytic plating of Au, which is excellent in heat dissipation and corrosion resistance and whose resistance value changes little over time. The thickness of the first connecting portion 211 is 15 μm to 25 μm.

In FIG. 5C, a first mask 44 having a second opening pattern is formed over the resist 40 . The first mask 44 has an opening 442 in the inner area RA and an opening 443 in the outer area RB. The opening shape of the opening 442 in the inner area RA and the opening 443 in the outer area RB included in the second opening pattern are different. The pitch or diameter of openings 442 is greater than the pitch or diameter of openings 443 . The upper surface of the first connection portion 211 is exposed inside the openings 442 and 443 .

In FIG. 5D, a conductive film 47a and a conductive film 47b are simultaneously plated into the opening 442 of the inner area RA and the opening 443 of the outer area RB (second plating process). The conductive films 47 a and 47 b may be made of the same material as the first connecting portion 211 . In this example, the conductive films 47a and 47b are formed using the same Au as the first connecting portion 211. As shown in FIG. Since the pitch or diameter of the openings 442 formed in the first mask 44 is larger than the pitch or diameter of the openings 443, the pitch or diameter of the conductive film 47a formed in the openings 442 is formed in the openings 443. It becomes larger than the pitch or diameter of the conductive film 47b.

In FIG. 5E, by removing the resist 40 and the first mask 44, the first bumps 21 in the inner area RA and the second bumps 22A in the outer area RB are obtained. The first bump 21 has a first connection portion 211 on the light emitting element 20 side and a second connection portion 212 formed on the upper surface of the first connection portion 211 . The second connection portion 212 is formed of the conductive film 47a shown in FIG. 5D. The second bump 22A has a first connection portion 211 on the light emitting element 20 side and a third connection portion 213 formed on the upper surface of the first connection portion 211 . The third connecting portion 213 is formed of the conductive film 47b shown in FIG. 5D.

The upper areas of the first connection portions 211 are substantially equal between the first bumps 21 and the second bumps 22A. The top area of the third connection portion 213 is made smaller than the top area of the second connection portion 212 . This makes it easier for the third connection portion 213 to be crushed by a smaller load than the second connection portion 212 . By forming the third connection portion 213 having a small diameter in the outer peripheral region RB, when the light emitting element is thermocompression bonded onto the wiring board 11, stable bonding can be achieved even if the load is reduced. The pitch of the third connection portions 213 can be made smaller than the pitch of the second connection portions 212 while making the top area of the third connection portions 213 smaller than the top area of the second connection portions 212 . As a result, it is possible to increase the area in which the third connecting portion 213 is formed, and to ensure heat dissipation in the outer peripheral region RB in which the third connecting portion 213 is formed. Further, while making the top area of the third connection portion 213 smaller than the top area of the second connection portion 212, the number of the second connection portions 212 formed on each of the first connection portions 211 is reduced to 1. It can be less than the third connecting portion 213 formed on the first connecting portion 211 for each hit. As a result, it is possible to increase the area in which the second connecting portion 212 is formed and secure the bondability in the outer peripheral region RB in which the third connecting portion 213 is formed while ensuring the heat dissipation in the inner region RA.

<Modification>
6A and 6B show variations of the bump structure. In the modified example, the height of the bumps in the outer peripheral region RB is made higher than that of the bumps in the inner region RA.

FIG. 6A is a schematic diagram of the first bumps 21 formed in the inner area RA. FIG. 6B is a schematic diagram of the second bumps 22B formed in the outer peripheral region RB.

The first bump 21 has a first connection portion 211 on the light emitting element 20 side and a second connection portion 212 on the wiring substrate 11 side. The second bump 22B has a first connection portion 211 on the light emitting element 20 side and a third connection portion 223 on the wiring board 11 side. The materials of the first connecting portion 211, the second connecting portion 212 and the third connecting portion 223 may be the same or different.

The area of the end surface 211s of the first connection portion 211 of the first bump 21 and the area of the end surface 211s of the first connection portion 211 of the second bump 22B are substantially the same, or the area difference is small. 211 s of end surfaces become the upper surface in the process of manufacturing an element. As an example, the diameter of the first connection portion 211 is 40 μm to 60 μm. By making the area of the end surface 211s of the first connecting portion 211 uniform over the entire element on the base side of the bump, a uniform heat dissipation effect is ensured.

In the first bump 21, a plurality of second connection portions 212 are formed on the end face 211s of the first connection portion 211 at a pitch P1.

In the second bump 22B, a plurality of third connection portions 223 are formed on the end surface 211s of the first connection portion 211 at a pitch P2. As described above, “pitch” means the distance between two adjacent second connection portions 212 or the distance between two adjacent third connection portions 223 .

The pitch P1 of the second connection portions 212 is larger than the pitch P2 of the third connection portions 223 (P1>P2). Alternatively, the top area of the second connection portion 212 is larger than the top area of the third connection portion 223 . The top area of the second connection portion 212 and the top area of the third connection portion 223 mean the area of the surface opposite to the surface where the second connection portion 212 and the third connection portion contact the end surface 211s. The pitches P1 and P2 are appropriately set so as to satisfy P1>P2 according to the warp amount of the substrate, the load at the time of bonding, etc., as described above.

The height L2 of the third connection portion 223 of the second bump 22B is higher than the height L1 of the second connection portion 212 of the first bump 21 (L2>L1). It is desirable that the difference between the height L2 of the third connection portion 223 and the height L1 of the second connection portion 212 is an amount that can absorb the warpage of the substrate. For example, it is preferable that the difference between the height L2 of the third connecting portion 223 and the height L1 of the second connecting portion 212 is about the average amount of warp in the outer peripheral region RB of the substrate.

By making the top area of the third connection portion 223 smaller than the top area of the second connection portion 212, or by making the pitch P2 of the third connection portion 223 smaller than the pitch P1 of the second connection portion 212, light emission is The second bumps 22B can be bonded to the wiring board 11 even if the load in the outer peripheral region RB is reduced due to the warp of the element 20 .

Further, by making the height L2 of the third connecting portion 223 larger than the height L1 of the second connecting portion 212, the second bumps 22B can be reliably secured to the wiring substrate 11 even if the warping of the light emitting element 20 becomes large. is spliced to

7A to 7C are manufacturing process diagrams of a light emitting element 20B of a modified example. FIG. 7A shows the same state as FIG. 5E, after the first mask 44 has been removed.

In the inner area RA, a plurality of conductive films 47a are formed on the upper surface of the first connecting portion 211 formed on the first electrode 26. As shown in FIG. In the outer peripheral region RB, a plurality of conductive films 47b are formed on the upper surface of the first connecting portion 211 formed on the second electrode 27. As shown in FIG. The pitch of the plurality of conductive films 47b formed in the outer peripheral region RB is smaller than the pitch of the plurality of conductive films 47a formed in the inner region RA.

In FIG. 7B, a second mask 46 is formed on the entire surface. The second mask 46 has a plurality of openings 444 in the outer peripheral region RB. In each opening 444, the upper surface of the narrow-pitch conductive film 47b is exposed. The openings 444 of the second mask 46 have substantially the same pattern as the openings 443 of the outer peripheral region RB of the first mask 44 used in the second plating process.

In FIG. 7C, a conductive film 49 is plated in the opening 444 (third plating process). The conductive film 49 may be made of the same material as the conductive film 47b formed by the second plating treatment, or may be made of a different material. In this example, the conductive film 49 is formed using the same Au as the conductive film 47b.

In FIG. 7C, the second mask 46 is removed to form the first bumps 21 and second bumps 22B shown in FIG. 7D. In the inner area RA, the first bump 21 having the second connection portion 212 is formed on the upper surface of the first connection portion 211 . A second bump 22B having a third connection portion 223 is formed on the upper surface of the first connection portion 211 in the outer peripheral region RB. The third connection portion 223 has a height that is the sum of the thickness of the conductive film 44 b and the thickness of the conductive film 49 .

According to such a modification, the height of the bumps 22B in the outer peripheral region RB is made higher than the height of the first bumps 21 in the inner region RA, thereby enhancing the reliability of bonding in the outer peripheral region RB.

<Mounting of light-emitting element>
FIG. 8 is a diagram showing mounting of the light emitting element 20 on the wiring substrate 11. As shown in FIG. The light emitting element 20 is flip-chip mounted on the wiring board 11 using the first bumps 21 in the inner area RA and the second bumps 22 in the outer area RB. The second bump 22 may be the second bump 22A of the embodiment or the second bump 22B of the modified example. As described with reference to FIGS. 4A, 4B, 6A, and 6B, the first bump 21 includes a first connection portion 211 on the light emitting element 20 side and a plurality of second connection portions on the wiring board 11 side. 212. The second bump 22 has a first connection portion 211 on the light emitting element 20 side and a plurality of third connection portions 213 on the wiring substrate 11 side.

The first bumps 21 and the second bumps 22 are aligned with the electrode pads formed on the wiring pattern 14 of the wiring board 11 and are joined to the wiring board 11 by ultrasonic fusion or the like. During bonding, the second connection portion 212 and the third connection portion 213 are pressed against the electrode pads on the wiring pattern 14 . Both the second connection portion 212 and the third connection portion 213 may have a smaller pitch or diameter than the first connection portion 211, and the load applied during bonding may be relatively small.

At each first bump 21 , the plurality of second connection portions 212 are integrated and joined to the electrode pads on the wiring pattern 14 by pressing and melting by ultrasonic vibration. At each second bump 22 , the plurality of third connection portions 213 are integrated and joined to the electrode pads on the wiring pattern 14 by pressing and melting by ultrasonic vibration.

The pitch or joint surface area of the third connection portion 213 is smaller than the pitch or joint surface area of the second connection portion 212, and the third connection portion 213 is more likely to collapse than the second connection portion 212 during joining. Therefore, even if the load is reduced in the outer peripheral region RB due to the warping of the light emitting element 20, the bonding between the third connecting portion 213 and the wiring board 11 is ensured.

On the other hand, the first connecting portion 211 hardly deforms under the load for ultrasonically bonding the second connecting portion 212 and the third connecting portion 213, and maintains its mechanical strength and heat dissipation effect. Therefore, even if the second connection portion 212 and the third connection portion 213 are pressure-melted, the first bump 21 and the second bump 22 maintain a sufficient height.

FIG. 9 is a schematic diagram of the light emitting device 10 in which the light emitting element 20 is mounted. The light emitting device 10 has a wiring board 11 , a light emitting element 20 mounted on the wiring board 11 , and a light diffusion member 16 filled between the light emitting element 20 and the wiring board 11 . The light diffusion member 16 covers the side surface of the light emitting element 20 and part or all of the mounting surface of the wiring board 11 .

The light diffusing member 16 is made of, for example, a resin having light reflectivity or light shielding properties. Examples of resins that can be used include silicone resins, modified silicone resins, epoxy resins, modified epoxy resins, acrylic resins, and hybrid resins containing one or more of these resins. Titanium oxide, silicon oxide, zirconium oxide, potassium titanate, alumina, aluminum nitride, boron nitride, mullite, or the like may be added to the light diffusion member 16 as a substance that imparts light reflectivity.

A translucent member 15 is provided on the side opposite to the mounting surface of the light emitting element 20 . The translucent member 15 is made of a material that transmits light emitted from the light emitting element 20 . The translucent member 15 may contain a phosphor that absorbs part of the light emitted from the light emitting element 20 and emits light with a wavelength different from that of the light from the light emitting element 20 .

The light emitting element 20 is connected to the electrodes on the wiring pattern 14 by the connecting portion 28 . As described above, the connecting portion 28 is formed by bonding using the first bumps 21 in the inner area RA and the second bumps 22 in the outer area RB.

In general, the connection portion 28 tends to generate heat due to current injection into the light emitting element 20, but in the light emitting element 20 of the embodiment, the first connection portion 211 having a large surface area is used over the entire bonding surface, and the heat dissipation effect is improved. high. In addition, the first connection portion 211 is less deformed by a load and retains the shape before joining to some extent, so the connection portion 28 has a sufficient height. Since a sufficient space is secured between the light emitting element 20 and the wiring board 11 , the light diffusion member 16 can easily enter between the connecting portions 28 . Thereby, the light diffusion member 16 can be efficiently arranged between the light emitting element 20 and the wiring board 11, and the light extraction efficiency of the light emitting device can be improved.

In the light emitting device 10, the reliability of bonding between the light emitting element 20 and the wiring substrate 11 is improved, and good light emission characteristics are obtained.

The present invention is not limited to the specific embodiments and modifications described above, and various applications and modifications are possible. The mounting method of the embodiment is applicable to mounting of all light emitting elements that warp due to the difference in thermal expansion coefficient between the substrate and the semiconductor layer. The semiconductor layer is not limited to GaN, and in the chemical formula In _x Al _y Ga _1-x-y N (0≦x≦1, 0≦y≦1, x+y≦1), the composition ratios x and y are within the respective ranges. can be used.

Instead of mounting the light-emitting elements 20 on each wiring board 11, a plurality of light-emitting elements 20 may be bonded to a large-area wiring board having a plurality of mounting areas. In this case, a plurality of light emitting devices 10 can be cut out by dividing along predetermined scribe regions after bonding.

The light emitting device 10 of the embodiment can be used as various light sources such as illumination light sources, various indicator light sources, in-vehicle light sources, display light sources, backlight light sources, sensor light sources, and traffic lights.

10 Light-emitting device 11 Wiring board 14 Wiring pattern 16 Light diffusion member 20, 20A, 20B Light-emitting element 21 First bump 211 First connection portion 211s End surface 212 Second connection portion 22, 22A, 22B Second bumps 213, 223 Third connection Part 44 First mask 46 Second mask RA Inner region RB Peripheral regions P1, P2 Pitch

Claims (7)

A mounting method for mounting a light emitting element having a substrate on a wiring board,
a step of forming a plurality of first connection portions in an outer peripheral region of the main surface of the light emitting element and an inner region inside the outer peripheral region;
forming a plurality of second connection portions having a smaller top area than the first connection portions on each of the plurality of first connection portions formed in the inner region;
forming a plurality of third connection portions having a smaller top area than the second connection portion on each of the plurality of first connection portions formed in the outer peripheral region;
bonding the light emitting element to the wiring substrate via the second connection portion and the third connection portion;
An implementation method that has 2. The mounting method according to claim 1, wherein the pitch of said third connection portion is made smaller than the pitch of said second connection portion. 3. The number of said second connection portions formed per said first connection portion is smaller than the number of said third connection portions formed per said first connection portion. 3. The mounting method according to 1 or 2. 4. The mounting method according to claim 1, wherein the first connecting portion is formed by a first plating process. After the first plating process, using a first mask provided on the upper surface of the first connection part, perform a second plating process for forming the second connection part and the third connection part. have
5. The mounting method according to claim 4, wherein said first mask has a plurality of openings exposing the upper surface of said first connecting portion. After the second plating process, a third plating process for making the height of the third connection part higher than that of the second connection part using a second mask provided on the upper surface of the third connection part. having a step of performing
6. The mounting method according to claim 5, wherein said second mask has a plurality of openings exposing the upper surface of said third connecting portion. 7. The mounting method according to claim 1, further comprising filling a space between the light emitting element and the wiring board with a light diffusing member after the step of bonding the light emitting element to the wiring board. .

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