JP7196265B2 - semiconductor equipment - Google Patents

Description

TECHNICAL FIELD Embodiments of the present invention relate to semiconductor devices.

Silicon carbide is expected as a material for next-generation semiconductor devices. Silicon carbide has excellent physical properties such as three times the bandgap, about ten times the breakdown field strength, and about three times the thermal conductivity as compared to silicon. By utilizing this characteristic, it is possible to realize a semiconductor device with low loss and capable of operating at high temperatures.

A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using silicon carbide has an operation mode called a reverse conduction state in addition to a normal operation mode. In a normal mode of operation, the drain electrode is positively biased with respect to the source electrode and current flows from the drain electrode to the source electrode. On the other hand, in the reverse conducting state, the drain electrode is negatively biased with respect to the source electrode, and current flows from the source electrode to the drain electrode. In the reverse conduction state, current flows by turning on the built-in diode of the MOSFET.

The built-in diode of the MOSFET is a pn junction diode. In the reverse conduction state, holes are injected into the drift layer from the source electrode side, and electrons are injected from the drain electrode side. The recombination energy of holes and electrons injected into the drift layer can cause stacking faults to grow from dislocations in the drift layer. Growth of stacking faults in the drift layer increases the on-resistance. This problem is called conduction degradation. The reliability of the MOSFET is lowered due to deterioration of the energization.

Japanese Patent No. 4066946

A problem to be solved by the present invention is to provide a semiconductor device capable of suppressing energization deterioration.

A semiconductor device according to an embodiment includes a first electrode, a second electrode, a silicon carbide layer at least partially provided between the first electrode and the second electrode, and the silicon carbide layer. an n-type first silicon carbide region provided in the silicon carbide layer; and an n-type first silicon carbide region provided in the silicon carbide layer and between the n-type first silicon carbide region and the first electrode. and a plurality of p-type second silicon carbide regions extending in the direction of and provided in the silicon carbide layer between the plurality of p-type second silicon carbide regions and the first electrode. a plurality of n-type third silicon carbide regions having a higher n-type impurity concentration than the n-type first silicon carbide region and electrically connected to the first electrode; is in contact with the n-type first silicon carbide region provided between two adjacent ones of the n-type second silicon carbide regions, extends in the first direction, and is provided at a first period; A plurality of first conductive layers electrically connected to the first electrode and provided between two adjacent ones of the plurality of first conductive layers and extending in the first direction n (n=2, 3, 4, 5) first gate electrodes and a plurality of n-type first silicon carbide regions provided between the n first gate electrodes and the n-type first silicon carbide region a portion of the first electrode in contact with a first gate insulating layer and one of the plurality of n-type third silicon carbide regions closest to one of the plurality of first conductive layers; and an insulating film provided between one of the plurality of first conductive layers .

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment; FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment; FIG. 4A and 4B are diagrams for explaining actions and effects of the semiconductor device of the first embodiment; FIG. 4A and 4B are diagrams for explaining actions and effects of the semiconductor device of the first embodiment; FIG. 4A and 4B are diagrams for explaining actions and effects of the semiconductor device of the first embodiment; FIG. 4A and 4B are diagrams for explaining actions and effects of the semiconductor device of the first embodiment; FIG. 4A and 4B are diagrams for explaining actions and effects of the semiconductor device of the first embodiment; FIG. 4A and 4B are diagrams for explaining actions and effects of the semiconductor device of the first embodiment; FIG. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to a second embodiment; FIG. 10 is a schematic plan view of a semiconductor device according to a third embodiment; FIG. 11 is a schematic plan view of gate finger regions of the third embodiment; FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a third embodiment; FIG. 11 is a schematic plan view of gate finger regions of the third embodiment; FIG. 10 is a schematic cross-sectional view of gate finger regions according to the third embodiment; Explanatory drawing of the operation and effect of the semiconductor device of the third embodiment. Explanatory drawing of the operation and effect of the semiconductor device of the third embodiment. Explanatory drawing of the operation and effect of the semiconductor device of the third embodiment. Explanatory drawing of the operation and effect of the semiconductor device of the third embodiment. Explanatory drawing of the operation and effect of the semiconductor device of the third embodiment. Explanatory drawing of the operation and effect of the semiconductor device of the third embodiment. The schematic plan view of the gate finger area|region of 4th Embodiment. The schematic plan view of the gate finger area|region of 4th Embodiment. The schematic plan view of the gate finger area|region of 5th Embodiment. The schematic plan view of the gate finger area|region of 5th Embodiment. FIG. 11 is a schematic plan view of gate finger regions according to the sixth embodiment; FIG. 11 is a schematic plan view of gate finger regions according to the sixth embodiment; FIG. 11 is a schematic cross-sectional view of a gate finger region according to the sixth embodiment; The schematic plan view of the gate finger area|region of 7th Embodiment. FIG. 11 is a schematic cross-sectional view of gate finger regions according to the seventh embodiment;

Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same or similar members and the like are denoted by the same reference numerals, and the description of the members and the like that have already been described will be omitted as appropriate.

Also, in the following description, n ⁺ , n, n ⁻ and p ⁺ , p, p ⁻ represent relative levels of impurity concentration in each conductivity type. That is, n ⁺ indicates that the concentration of n-type impurities is relatively higher than that of n, and n ⁻ indicates that the concentration of n-type impurities is relatively lower than that of n. Also, p ⁺ indicates that the p-type impurity concentration is relatively higher than p ^- type impurity concentration, and p- indicates that the p-type impurity concentration is relatively lower than p-type impurity concentration. Note that n ⁺ -type and n ^- -type are sometimes simply referred to as n-type, and p ⁺ -type and p ^- -type are simply referred to as p-type.

The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). Also, the relative level of the impurity concentration can be determined from the level of the carrier concentration obtained by SCM (Scanning Capacitance Microscopy), for example. Further, the distance such as the depth of the impurity region can be obtained by SIMS, for example. Also. The distance such as the depth of the impurity region can be obtained from, for example, a composite image of an SCM image and an AFM (Atomic Force Microscope) image.

(First embodiment)
The semiconductor device of the present embodiment includes a first electrode, a second electrode, a silicon carbide layer at least partially provided between the first electrode and the second electrode, and a silicon carbide layer in the silicon carbide layer. a provided n-type first silicon carbide region, provided in the silicon carbide layer, provided between the n-type first silicon carbide region and the first electrode, and extending in the first direction; a plurality of p-type second silicon carbide regions; and an n-type first silicon carbide provided in the silicon carbide layer and between the p-type second silicon carbide regions and the first electrode. a plurality of n-type third silicon carbide regions having a higher n-type impurity concentration than the region and electrically connected to the first electrode; contacting a first n-type silicon carbide region provided between two p-type second silicon carbide regions, extending in a first direction, provided with a first period, and supplying electric current to the first electrode; a plurality of first conductive layers electrically connected to each other and an n (n =2, 3, 4, 5) first gate electrodes and a plurality of first gate insulators provided between the n first gate electrodes and the n-type first silicon carbide region a layer;

FIG. 1 is a schematic cross-sectional view of the semiconductor device of this embodiment. The semiconductor device of the present embodiment is an n-type vertical MOSFET 100 using silicon carbide and using electrons as carriers. The MOSFET 100 of this embodiment has a Schottky barrier diode (SBD) in the chip.

The MOSFET 100 comprises regularly arranged MOSFET cells (MC) and SBD cells (SC). A case where n=3 will be described below as an example.

The MOSFET 100 includes a silicon carbide layer 10, a source electrode (first electrode) 12, a drain electrode (second electrode) 14, an anode electrode (first conductive layer) 16, an SBD region 17, a gate electrode (first gate electrode) 18 , a gate insulating film (first gate insulating layer) 20 , an interlayer insulating film 22 , and a gate connection layer (gate layer) 34 .

In the silicon carbide layer 10, an n ⁺ -type drain region 24, an n ⁻ -type drift region (n-type first silicon carbide region) 26, a p-type base region (p-type second silicon carbide region ) 28 , an n ⁺ -type source region (n-type third silicon carbide region) 30 and a p ⁺ -type contact region (p-type fourth silicon carbide region) 32 .

Silicon carbide layer 10 is single crystal SiC. Silicon carbide layer 10 is, for example, 4H—SiC. At least part of silicon carbide layer 10 is provided between source electrode 12 and drain electrode 14 .

Silicon carbide layer 10 has a first surface (“P1” in FIG. 1) and a second surface (“P2” in FIG. 1). Hereinafter, the first surface is also referred to as the front surface, and the second surface is also referred to as the back surface. In addition, hereinafter, "depth" means the depth with the first surface as a reference.

The first plane is, for example, a plane inclined from 0 degrees to 8 degrees with respect to the (0001) plane. Also, the second plane is, for example, a plane inclined from 0 degrees to 8 degrees with respect to the (000-1) plane. The (0001) plane is called the silicon plane. The (000-1) plane is called the carbon plane.

n ⁺ -type drain region 24 is provided on the back surface side of silicon carbide layer 10 . The drain region 24 contains, for example, nitrogen (N) as an n-type impurity. The impurity concentration of the n-type impurity in the drain region 24 is, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less.

An n ⁻ -type drift region 26 is provided over the drain region 24 . The drift region 26 contains, for example, nitrogen (N) as an n-type impurity. The impurity concentration of the n-type impurities in the drift region 26 is lower than the impurity concentration of the n-type impurities in the drain region 24 .

The impurity concentration of the n-type impurities in the drift region 26 is, for example, 4×10 ¹⁴ cm ⁻³ or more and 6×10 ¹⁶ cm ⁻³ or less. The thickness of the drift region 26 is, for example, 5 μm or more and 150 μm or less.

A p-type base region 28 is provided between the drift region 26 and the source electrode 12 . Base region 28 is provided between drift region 26 and the surface of silicon carbide layer 10 . Base region 28 functions as the channel region of MOSFET 100 .

The p-type base regions 28 are provided, for example, with a predetermined second period in the second direction. The second period is a second period that is 1/(n+1) of the first period described later, where n is the number of gate electrodes 18 provided between two adjacent anode electrodes 16 . be provided. In this embodiment, since the number of gate electrodes 18 is three, the second period is 1/4 of the first period.

The base region 28 contains, for example, aluminum (Al) as a p-type impurity. The impurity concentration of the p-type impurity in the base region 28 is, for example, 1×10 ¹⁷ cm ⁻³ or more and 5×10 ¹⁷ cm ⁻³ or less. The depth of the base region 28 is, for example, 0.2 μm or more and 0.6 μm or less.

An n ⁺ -type source region 30 is provided between the base region 28 and the source electrode 12 . Source region 30 is provided between base region 28 and the surface of silicon carbide layer 10 .

Source region 30 contains, for example, phosphorus (P) as an n-type impurity. The impurity concentration of the n-type impurities in the source region 30 is higher than the impurity concentration of the n-type impurities in the drift region 26 .

The impurity concentration of the n-type impurity in the source region 30 is, for example, 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less. The depth of the source region 30 is shallower than the depth of the base region 28, and is, for example, 0.1 μm or more and 0.3 μm or less.

A p ⁺ -type contact region 32 is provided between the base region 28 and the source electrode 12 . A contact region 32 is provided between the source regions 30 . The impurity concentration of the p-type impurities in the contact region 32 is higher than the impurity concentration of the p-type impurities in the base region 28 .

The contact region 32 has the function of reducing the contact resistance of the source electrode 12 .

The contact region 32 contains, for example, aluminum (Al) as a p-type impurity.

FIG. 2 is a schematic plan view of the semiconductor device of this embodiment. FIG. 2 shows the arrangement of the anode electrode 16 and the gate electrode 18 .

Anode electrode 16 is provided in contact with drift region 26 between two adjacent base regions 28 . Anode electrode 16 extends in a first direction as shown in FIG. The anode electrodes 16 are repeatedly provided in a first period in a second direction orthogonal to the first direction.

The anode electrode 16 functions as an anode electrode for the SBD.

The anode electrode 16 is p-type polycrystalline silicon containing p-type impurities. The anode electrode 16 is made of the same material as the gate electrode 18, for example. The anode electrode 16 is formed at the same time as the gate electrode 18, for example. The anode electrode 16 may be made of n-type polycrystalline silicon containing n-type impurities.

The anode electrode 16 is in contact with the drift region 26 through an opening provided in the gate insulating film 20 . A portion where the anode electrode 16 and the drift region 26 are in contact is the SBD region 17 .

The junction between anode electrode 16 and drift region 26 is a heterojunction. A junction between p-type polycrystalline silicon and SiC achieves current-voltage characteristics similar to a Schottky junction with a heterojunction barrier of about 1.5 eV.

Anode electrode 16 is electrically connected to source electrode 12 . The anode electrode 16 is in contact with the source electrode 12 at an opening 36 (broken-line square in FIG. 2) provided in the interlayer insulating film 22 .

A gate electrode 18 is provided between two adjacent anode electrodes 16 . In this embodiment, three gate electrodes 18 are provided between two adjacent anode electrodes 16 . The number of gate electrodes 18 provided between two adjacent anode electrodes 16 may be two, four, or five.

As shown in FIG. 2, the gate electrode 18, like the anode electrode 16, extends in the first direction. An end of the gate electrode 18 is connected to a gate connection layer 34 extending in the second direction. The anode electrode 16 is separated from the gate connection layer 34 and a potential is applied independently of the gate electrode 18 .

The gate electrode 18 of this embodiment is p-type polycrystalline silicon containing p-type impurities. The gate electrode 18 may be n-type polycrystalline silicon containing n-type impurities.

The gate insulating film 20 is provided between the gate electrode 18 and the drift region 26 between two adjacent base regions 28 . Also, the gate insulating film 20 is provided between the gate electrode 18 and the two adjacent base regions 28 .

The gate insulating film 20 is, for example, a silicon oxide film. A high-k insulating film (high dielectric constant insulating film), for example, can be applied to the gate insulating film 20 .

An interlayer insulating film 22 is provided on the gate electrode 18 . The interlayer insulating film 22 is, for example, a silicon oxide film.

Source electrode 12 is provided on the surface of silicon carbide layer 10 . Source electrode 12 contacts source region 30 and contact region 32 .

Source electrode 12 contains a metal. The metal forming the source electrode 12 is, for example, a laminated structure of titanium (Ti) and aluminum (Al). Source electrode 12 may contain metal silicide or metal carbide in contact with silicon carbide layer 10 .

Drain electrode 14 is provided on the back surface of silicon carbide layer 10 . The drain electrode 14 contacts the drain region 24 .

Drain electrode 14 is, for example, a metal or metal-semiconductor compound. The drain electrode 14 includes, for example, a material selected from the group consisting of nickel silicide (NiSi), titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

In the MOSFET 100 of this embodiment, MOSFET cells (MC) and SBD cells (SC) are periodically arranged in the second direction. A MOSFET cell includes one gate electrode 18 and an SBD cell includes one anode electrode 16 .

In this embodiment, one SBD cell is arranged for three MOSFET cells. For example, if the length of each cell in the second direction is 4 μm, three MOSFET cells and one SBD cell are arranged on the entire chip with a period of 16 μm. In this case, the first period of MOSFET 100 is 16 μm.

Actions and effects of the semiconductor device of the embodiment will be described below. 3 to 8 are explanatory diagrams of the action and effect of this embodiment.

First, the operation of MOSFET 900 without an SBD cell (SC) will be described. FIG. 3 is a schematic cross-sectional view of MOSFET 900. As shown in FIG. MOSFET 900 has the same configuration as MOSFET 100 except that it does not have an SBD cell.

The primary operation of MOSFET 900 is to control the on and off of the current between drain electrode 14 and source electrode 12 when drain electrode 14 is positively biased with respect to source electrode 12 .

An electron channel is formed between the source region 30 and the drift region 26 when a positive voltage is applied between the gate electrode 18 and the source electrode 12 to induce electrons at the interface between the base region 28 and the gate insulating film 20 . Therefore, current flows between the drain electrode 14 and the source electrode 12, and the MOSFET 900 is turned on.

On the other hand, when the voltage between the gate electrode 18 and the source electrode 12 is lowered to reduce the concentration of electrons induced at the interface between the base region 28 and the gate insulating film 20, conduction between the source region 30 and the drift region 26 is interrupted. MOSFET 900 is turned off.

When current is interrupted, a depletion layer extends from base region 28 to drift region 26 and supports the voltage difference between drain electrode 14 and source electrode 12 . The impurity concentration and thickness of the drift region 26 are set so as to maintain a desired withstand voltage.

The main operations of the MOSFET 900 have been described above, but in addition to the main operations, there is an operation mode called a reverse conduction state. Reverse conduction is the operation when the drain electrode 14 is negatively biased with respect to the source electrode 12 .

When the drain electrode 14 is negatively biased with respect to the source electrode 12 , the p-type base region 28 is positively biased with respect to the n-type drift region 26 . Therefore, when the rising voltage of the pn junction diode between the p-type base region 28 and the n-type drift region 26 is exceeded, current flows from the source electrode 12 to the drain electrode 14 . This is the reverse conduction state.

A diode formed between the p-type base region 28 and the n-type drift region 26 is referred to as an internal diode. In the reverse conduction state, holes from the base region 28 and electrons from the n ⁺ -type drain region 24 are injected into the drift region 26 and recombine within the drift region 26 .

Conduction deterioration of the built-in diode occurs in the reverse conduction state. If dislocations along the (0001) plane of SiC exist in the drift region 26 or in the vicinity thereof, the dislocations that have acquired recombination energy are decomposed, and stacking faults grow and expand in the (0001) plane.

SiC substrates are usually cut from the <0001> direction with a low off-angle (for example, 4°). Therefore, stacking faults extend in an orientation substantially perpendicular to the direction of current flow.

The stacking period is disturbed in the portion where the stacking fault exists. As a result, the bandgap changes and a potential barrier against conduction electrons is generated. Therefore, since a planar potential barrier appears perpendicular to the current path, the resistance increases as the built-in diode is energized.

This stacking fault acts as a potential barrier not only in the reverse conduction state but also in the forward direction state in which current flows from the drain to the source. As a result, the on-resistance in the forward direction also increases.

In particular, when dislocations along the (0001) plane of SiC, which cause stacking faults, are present at high density in the chip, the area ratio of the stacking faults in the chip increases as the built-in diode is energized. In such a state, the on-resistance becomes extremely large, which eventually causes serious problems such as malfunction of the circuit or destruction of the element due to increased heat generation.

One possible way to solve the problem of conduction deterioration of the built-in diode is to improve the crystallinity of SiC and eliminate dislocations along the (0001) plane that cause stacking faults. As another method, the presence or absence of dislocations along the (0001) plane, which is the source of stacking faults, is checked by a photoluminescence method or the like, and chips with dislocations are selected and removed. None of the methods have led to a satisfactory solution.

As another method of solving the problem of conduction deterioration of the built-in diode, it is conceivable to connect an external diode in parallel with the SiC-MOSFET between the drain and source of the SiC-MOSFET as shown in FIG. Also shown in FIG. 4 is a built-in diode.

As the external diode, for example, a Schottky barrier diode (SBD) made of SiC is used. The on-voltage of the SiC pn junction diode is about 2.5V, while the on-voltage of the Schottky barrier diode is as low as about 1V. Therefore, the reverse conduction current mainly flows through the external SBD. In such a circuit, if the current flowing through the built-in diode can be suppressed, holes will not be injected into the drift region 26 and expansion of stacking faults can be prevented.

However, in order to sufficiently suppress the current flowing through the built-in diode, the chip area of the external SBD becomes large, and there is a possibility that the cost will increase compared to the case of using SiC-MOSFET alone. Also, the chip area of the external SBD is increased, which may increase the switching loss.

The MOSFET 100 of this embodiment has an SBD cell for passing a reverse conduction current in the same chip as the SiC-MOSFET. The operation of the MOSFET 100 of this embodiment will be described below.

The anode electrode 16 of this embodiment is p-type polycrystalline silicon. The rise voltage of the heterojunction diode of p-type polysilicon and n ⁻ -type drift region 26 is about 1.2V. On the other hand, the rising voltage of the pn junction diode of the p-type base region 28 and the n ⁻ -type drift region 26 is about 2.5V.

The anode potentials of the heterojunction diode and the pn junction diode are both connected to the source electrode 12 and become equal. Therefore, when a current flows in the reverse conducting direction, the current first starts flowing from the heterojunction diode of the SBD cell with a small rising voltage.

A heterojunction diode is a unipolar device with only electrons as carriers. Therefore, even if a reverse conduction current flows through a heterojunction diode, stacking faults do not grow and expand due to recombination energy of carriers, unlike a pn junction diode which is a bipolar device.

FIG. 5 is a diagram showing simulation results of the current distribution and voltage distribution in the reverse conduction state of the MOSFET 100 of this embodiment. In the MOSFET structure assumed in the simulation, one SBD cell is arranged for three MOSFET cells. Each cell has a length (long side) of 1.6 mm in the first direction and a length (short side) of 4 μm in the second direction. The width of the base regions 28 in the second direction is 2.5 μm, and the distance between the base regions 28 in the second direction is 1.5 μm. For example, 1360 cells are arranged to form a chip of 6×6 mm ² . The forward rated current of the chip is, for example, 120 A (amperes).

FIG. 5 shows the distribution of the region surrounded by the dashed-dotted line in FIG. 1 and having a length of 8 μm in the second direction. FIG. 5 shows current distribution and voltage distribution in the drift region 26 when a reverse current of 120 A equal to the rated current flows through the chip.

In FIG. 5 the potential reference is at the source electrode 12 . Therefore, the potential in the drift region 26 takes a negative value. The potential immediately below the SBD is -1.2 V, which is equal to the rising voltage of the SBD.

On the other hand, the voltage of the drift region 26 in contact with the base region 28 has a minimum value of -2.23 V at a point 7.25 μm away from the center of the SBD. Therefore, the full current flows through the SBD since it does not exceed the rising voltage of the pn junction diode (-2.5V). Therefore, holes are not injected into the drift region 26 from the base region 28 .

When the current is further increased and the reverse current reaches 150 A, the potential of the n-drift region 26 in contact with the base region 28 exceeds the rising voltage of the pn junction of 2.5 V, and current begins to flow through the pn junction.

FIG. 6 shows the reverse current-voltage characteristics at 175° C. of a SiC-MOSFET with a chip size of 6×6 mm ² having the above MOSFET cell and SBD cell. The rated current of this MOSFET is 120A.

The reverse current rises when the voltage between the source and the drain exceeds 1.2 V, changes when the current reaches 150 A, and exhibits characteristics such that the current increases rapidly. The potential at the inflection point is 3.4V.

When the source-drain voltage becomes 3.4 V or higher, current flows through the pn junction of the built-in diode. Therefore, the resistance of the drift region 26 decreases due to conductivity modulation, and the current increases rapidly.

In the MOSFET 100 of the present embodiment, even if a voltage that greatly exceeds the rise voltage 2.5 V of the built-in diode of the MOSFET cell is applied between the source electrode 12 and the drain electrode 14, the built-in diode No current flows through the pn junction of In other words, below the range of the rated current of the MOSFET 100, current flow through the pn junction of the built-in diode is suppressed. Therefore, energization deterioration is suppressed. Therefore, the reliability of MOSFET 100 is improved.

Also, in this embodiment, the ratio is one SBD cell to three MOSFET cells. Therefore, the rate of increase in the chip area due to the provision of the SBD cells is as small as about 30%. Therefore, an increase in the manufacturing cost of MOSFET 100 is suppressed.

Further, in the MOSFET 100 of this embodiment, the only process added to the normal MOSFET manufacturing process is to form an opening for forming the anode electrode 16 in the gate insulating film 20 . Therefore, also from this point of view, an increase in the manufacturing cost of MOSFET 100 is suppressed.

Also, in the MOSFET 100 of this embodiment, the SBD cell and the MOSFET cell have the same cell size. Also, all the base regions 28 can be arranged with the same period. Therefore, processing during lithography and etching is stable, and the MOSFET 100 suitable for miniaturization can be realized.

Further, in the MOSFET 100 of the present embodiment, the contact regions 32 are provided in the base region 28 and are connected to the source electrode 12 with low resistance. Therefore, even if the voltage applied to MOSFET 100 increases and holes flow in when avalanche breakdown occurs, the potential rise in base region 28 is suppressed. Therefore, secondary breakdown can be prevented, and MOSFET 100 with excellent avalanche resistance can be realized.

In addition, in the MOSFET 100 of the present embodiment, as the drain-source voltage increases, the electric force line density from the n ⁺ -type drain region 24 to the anode electrode 16 of the SBD cell also increases. However, when a voltage of several volts or more is applied, the width of the depletion layer extending from the base region 28 to the drift region 26 reaches the separation distance of the base region 28, for example, 1.5 μm, and the electric line of force ends at It becomes towards the base region 28 . As a result, the increase in the electric field strength under the anode electrode 16 of the SBD cell becomes moderate, and even if a high voltage is applied between the drain and the source, an increase in leak current in the SBD cell region can be suppressed.

In addition, in the MOSFET 100 of the present embodiment, when a very large surge current that greatly exceeds the rated current enters in the reverse conduction direction, holes are injected from the base region 28 into the drift region 26 as shown in FIG. be. Therefore, the potential drop in the drift region 26 is suppressed by the conductivity modulation, and the occurrence of thermal breakdown of the MOSFET 100 is suppressed. Therefore, the MOSFET 100 having a large reverse surge current resistance is realized.

Even if holes are injected into the drift region 26 from the base region 28 when the surge current is applied, they are not injected for a long time. Therefore, an increase in on-resistance due to multiplication of stacking faults does not occur.

In the MOSFET 100 of this embodiment, a reverse current equal to the rated current can flow in the SBD cell. At that time, the potential drop between the source and the drain is as large as 3.4 V, and the heat generation density also increases. Therefore, passing a reverse current through the SBD for a long period of time is not preferable in that the element temperature rises.

To deal with such a problem, the potential drop between the source and the drain can be suppressed by turning on the gate of the MOSFET 100 while the current is flowing in the reverse direction. In the MOSFET 100 of this embodiment, the source-drain voltage when the rated current is applied is 1.7 V when the element temperature is 175.degree. Therefore, heat generation density can be reduced to 43%.

That is, in the MOSFET 100 of this embodiment, when the gate is in the ON state, a constant load current flows from the drain electrode 14 to the source electrode 12 like an inductive load. Current is passed through the SBD cell only at the moment when the direction is changed. Then, after the current direction is changed, the gate is turned on again to flow the current in the opposite direction to the MOSFET cell. By applying such a synchronous rectification mode, the heat generation of the element can be suppressed, and highly reliable operation becomes possible.

Next, consider the proper ratio of MOSFET cells to SBD cells. In other words, the appropriate number n of gate electrodes 18 provided between two adjacent anode electrodes 16 is considered.

First, Table 1 shows typical design parameters of a drift layer in a breakdown voltage system from 650 V to 3.3 kV, which is considered to be mainly applied to SiC-MOSFETs.

The rated current is determined by comprehensively considering the thermal resistance and reliability of the element. Table 1 lists the rated current of a chip with a size of 6×6 mm ² under the condition that the heat generation density of the drift region 26 is virtually 360 W/cm ² or less.

Here, the ratio of effective area to the total area of the chip is 83%. The rated current density J ₀ shown in Table 1 can be expressed approximately as in formula (1) based on the chip area

Here, BV represents the withstand voltage system in kV. Note that the element temperature was set to 175° C. in this trial calculation.

FIG. 7 shows the result of calculating the critical current at which current does not flow through the pn junction of the built-in diode of the MOSFET as a function of n. The device parameters for each withstand voltage system shown in Table 1 were used. Then, in the structure shown in FIG. 1, the critical current is calculated when the number of the gate electrodes 18 of the 4 μm-wide MOSFET cell is n, and the number of the anode electrode 16 of the 4 μm-wide SBD cell is one. did.

When n=1, that is, when MOSFETs and SBDs are arranged at a ratio of 1:1, the critical current at which the pn junction operates becomes very large. However, it is clearly excessive for the rated current, and it is not preferable from the viewpoint of increased manufacturing cost and increased switching loss.

The setting of the rated current and the setting of the finger size may vary according to individual design conditions, but a range of 50% above and below the value shown in formula (1) is considered practical. Therefore, from the results shown in FIG. 7, it is desirable that n=2 or more and n=5 or less.

If n is below the above range, manufacturing costs and switching loss may increase. Also, if n exceeds the above range, there is a risk of energization deterioration.

As described above, according to the present embodiment, the MOSFET 100 that suppresses energization deterioration and enables improvement in reliability is realized.

(Second embodiment)
The semiconductor device of this embodiment differs from that of the first embodiment in that the first conductive layer is part of the first electrode. Hereinafter, the description of the content that overlaps with the first embodiment will be omitted.

FIG. 8 is a schematic cross-sectional view of the semiconductor device of this embodiment. The semiconductor device of the present embodiment is an n-type vertical MOSFET 200 that uses silicon carbide and uses electrons as carriers.

FIG. 9 is a schematic plan view of the semiconductor device of this embodiment. FIG. 9 shows the arrangement of the anode electrode 16 and the gate electrode 18 .

Anode electrode 16 is provided in contact with drift region 26 between two adjacent base regions 28 . Anode electrode 16 extends in a first direction as shown in FIG. The anode electrodes 16 are repeatedly provided in a first period in a second direction orthogonal to the first direction.

Anode electrode 16 is part of source electrode 12 . Therefore, the anode electrode 16 is made of the same material as the source electrode 12 .

Anode electrode 16 contains a metal. The metal forming the anode electrode 16 is, for example, a laminated structure of titanium (Ti) and aluminum (Al). A junction between the anode electrode 16 and the drift region 26 is a Schottky junction.

The anode electrode 16 of this embodiment is formed simultaneously with the source electrode 12 . For example, in the region where the anode electrode 16 is to be formed, the material of the gate electrode 18 is removed when the gate electrode 18 is formed. A contact hole for the anode electrode 16 is also formed when the contact hole for the source electrode 12 is formed.

As described above, according to the present embodiment, the MOSFET 200 that suppresses energization deterioration and enables improvement in reliability is realized.

(Third Embodiment)
The semiconductor device of the present embodiment includes a third electrode electrically connected to the first electrode, and a silicon carbide layer provided in the silicon carbide layer between the n-type first silicon carbide region and the third electrode. and a plurality of p-type fifth silicon carbide regions extending in the first direction provided in the silicon carbide layer and between the p-type fifth silicon carbide region and the third electrode. a plurality of n-type sixth silicon carbide regions provided and having a higher n-type impurity concentration than the n-type first silicon carbide region and electrically connected to the third electrode; contacting a first n-type silicon carbide region provided between two adjacent p-type fifth silicon carbide regions in the fifth silicon carbide region, extending in a first direction, and provided between a plurality of second conductive layers electrically connected to the third electrode and two adjacent second conductive layers among the plurality of second conductive layers n (n=2, 3, 4, 5) second gate electrodes extending in the first direction, and the n second gate electrodes and the n-type first silicon carbide region. a plurality of second gate insulating layers provided therebetween; and end portions of the n first gate electrodes provided between the n first gate electrodes and the n second gate electrodes; a gate layer connected to the ends of the n second gate electrodes and wider than the n first gate electrodes and the n second gate electrodes; and an insulating layer thicker than the first gate insulating layer and the second gate insulating layer; and an n-type first silicon carbide layer provided in the silicon carbide layer. Two adjacent second conductive layers are provided between the region and the insulating layer and are connected to a p-type second silicon carbide region provided between two adjacent first conductive layers. and a p-type seventh silicon carbide region connected to the p-type fifth silicon carbide region provided between. a distance between an arbitrary position of the p-type seventh silicon carbide region and a portion where one of the two adjacent first conductive layers is in contact with the n-type first silicon carbide region, or , the distance between any one of the two adjacent second conductive layers and the portion where the n-type first silicon carbide region is in contact is less than half of 6/(n+1) of the first period. In particular, in the present embodiment, any position of the p-type seventh silicon carbide region and a portion where any one of the two adjacent first conductive layers is in contact with the n-type first silicon carbide region or the distance between any one of the two adjacent second conductive layers and the portion where the n-type first silicon carbide region is in contact is less than half the first period. Hereinafter, the description of the content that overlaps with the first embodiment will be omitted.

FIG. 10 is a schematic plan view of the semiconductor device of this embodiment. The semiconductor device of the present embodiment is an n-type vertical MOSFET 300 using silicon carbide and using electrons as carriers. FIG. 10 is an overall view of a MOSFET 300 chip.

MOSFET 300 comprises main region 50 , gate pad region 52 , gate finger regions 54 and termination regions 56 .

The main area 50 is the area where the MOSFET cells and SBD cells are located. The gate pad region 52 is a region for applying a gate voltage signal to the gate electrode of the MOSFET cell. Gate finger regions 54 are regions for transmitting gate voltage signals to the gate electrodes of MOSFET cells throughout the chip. The termination region 56 is a region for suppressing electric field concentration at the edge of the main region 50 . Gate pad region 52, gate finger region 54, and termination region 56 are extrinsic regions.

FIG. 11 is a schematic plan view of the gate finger regions of this embodiment. 11 is an enlarged view of the portion of the frame line 58 of FIG. 10; FIG. FIG. 11 shows the pattern of field oxide, anode electrode, gate electrode, and gate connection layer in gate finger region 54 .

The gate finger region 54 has a first cell block and a second cell block with the gate connection layer (gate layer) 34 interposed therebetween. The first cell block has, for example, the structure shown in FIG. 1 of the first embodiment.

FIG. 12 is a schematic cross-sectional view of the semiconductor device of this embodiment. FIG. 12 is the MM′ section of FIG. 11 . FIG. 12 is a schematic cross-sectional view of the second cell block. The second cell block also has the same structure as the first cell block.

The second cell block comprises regularly arranged MOSFET cells (MC) and SBD cells (SC). A case where n=3 will be described below as an example.

The second cell block includes a silicon carbide layer 10, a source electrode (third electrode) 62, a drain electrode (second electrode) 14, an anode electrode (second conductive layer) 66, an SBD region 67, a gate electrode ( A second gate electrode) 68 , a gate insulating film (second gate insulating layer) 70 , an interlayer insulating film 22 , and a gate connection layer (gate layer) 34 are provided.

In the silicon carbide layer 10, there are an n ⁺ -type drain region 24, an n ⁻ -type drift region (n-type first silicon carbide region) 26, a p-type base region (p-type fifth silicon carbide region ) 78 , an n ⁺ -type source region (n-type sixth silicon carbide region) 80 , and a p ⁺ -type contact region 82 .

The gate connection layer 34 is provided between the three gate electrodes 18 and the three gate electrodes 68 . Ends of the three gate electrodes 18 are connected to the gate connection layer 34 . Also, the ends of the three gate electrodes 68 are connected to the gate connection layer 34 . The gate connection layer 34 is divided in the second direction.

The gate connection layer 34 is, for example, p-type polycrystalline silicon containing p-type impurities. The gate connection layer 34 is made of the same material as the gate electrodes 18 and 68 . The gate connection layer 34 is formed at the same time as the gate electrodes 18,68. The gate connection layer 34 is wider than the gate electrode 18 and the gate electrode 68 .

A field oxide film (insulating layer) 81 is provided between the gate connection layer 34 and the drift region 26 . Field oxide film 81 is divided in the second direction.

Field oxide film 81 is thicker than gate insulating films 20 and 70 . Field oxide film 81 is, for example, a silicon oxide film.

The anode electrode 16 and the anode electrode 66 are connected. No field oxide film 81 is provided between the anode electrodes 16 , 66 and the drift region 26 .

FIG. 13 is a schematic plan view of the gate finger regions of this embodiment. The same area as in FIG. 11 is shown. FIG. 13 shows the pattern of p-type silicon carbide regions and SBD regions in gate finger regions 54 .

MOSFET 300 has a p-type region (p-type seventh silicon carbide region) 84 . P-type region 84 is provided in silicon carbide layer 10 . P-type region 84 is provided between drift region 26 and field oxide film 81 .

The p-type region 84 is connected to four base regions 28 provided between two adjacent anode electrodes 16 . Also, the p-type region 84 is connected to four base regions 78 provided between two adjacent anode electrodes 66 .

P-type region 84 has substantially the same p-type impurity concentration and depth as base region 28 and base region 78 . P-type region 84 is formed at the same time as base region 28 and base region 78 .

The p-type regions 84 are segmented in the second direction. SBD region 17 and SBD region 67 are connected and located between p-type regions 84 that are separated.

The distance between any position of the p-type region 84 and the portion where any one of the two adjacent anode electrodes 16 and the drift region 26 are in contact, or the distance between any one of the adjacent anode electrodes 66 and the drift region 26 is less than half of 6/(n+1) of the first period. In other words, the distance between any position of p-type region 84 and SBD region 17 or SBD region 67 is less than half of 6/(n+1) of the first period. For example, when n=3, the distance between any position of p-type region 84 and SBD region 17 or SBD region 67 is less than half of 3/2 of the first period.

The distance between any position of p-type region 84 and SBD region 17 or SBD region 67 is preferably less than half the first period.

FIG. 14 is a schematic cross-sectional view of the gate finger region of this embodiment. FIG. 14 is the AA' section of FIGS. 11 and 13. FIG.

The gate connection layers 34 separated in the second direction are electrically connected by gate metal lines 86 . The gate metal wiring 86 is made of the same material as the source electrodes 12 and 62, for example. The gate metal line 86 is formed at the same time as the source electrodes 12, 62, for example.

Next, the operation and effects of this embodiment will be described. 15 to 20 are explanatory diagrams of the action and effect of this embodiment.

First, the structure and function of the gate finger regions will be described by taking the MOSFET 900 of FIG. 3 without an SBD cell as an example.

15 and 16 are schematic plan views of gate finger regions without SBD cells. FIG. 15 shows the pattern of field oxide, anode electrode, gate electrode and gate connection layer in the gate finger region. FIG. 16 shows the pattern of p-type silicon carbide regions in the gate finger regions.

The gate finger region has a first cell block and a second cell block with a gate connection layer (gate layer) 34 interposed therebetween. The first cell block and the second cell block comprise, for example, the structure without SBD cells shown in FIG.

The gate finger region comprises a structure in which a low resistance metal electrode (not shown) is placed over the gate connection layer 34 . The sheet resistance of the gate connection layer 34 made of the same material as that of the gate electrode 18 is usually about several tens of ohms square, which is relatively large. Therefore, it is difficult to transmit the gate signal from the gate electrode 18 to the entire chip at high speed.

For this reason, a finger-shaped metal wiring connected to the gate connection layer 34 is provided over the entire chip to transmit the gate signal to the entire chip at high speed. Normally, this metal wiring is made of the same metal material as the source electrode 12 .

In order to allow a large current to flow through the source electrode 12, a metal junction is formed directly above the MOSFET cell to connect to the outside by bonding or the like. For this reason, an aluminum layer or the like having a thickness of several μm or more is used.

Etching of such a thick metal layer inevitably causes side etching equal to or greater than the thickness. Considering the manufacturing margin, therefore, it is desirable to ensure the width of the gate finger region on the order of several tens of μm.

For example, the width in the first direction (“W1” in the figure) of the gate connection layer 34 shown in FIG. 15 is 60 μm. A gate electrode 18 extends in a first direction from both sides of the gate connection layer 34 toward the main region 50 where the MOSFET cells are located.

As shown in FIG. 16, a p-type region 84 is provided under the wide gate connection layer 34 . The p-type region 84 is provided to shield the high electric field extending from the drain electrode 14 side from the gate connection layer 34 and the field oxide film 81 .

Therefore, a pn junction consisting of wide p-type region 84 and drift region 26 exists in the gate finger region. For example, the width (“W2” in the drawing) of the p-type region 84 shown in FIG. 16 is 70 μm from the viewpoint of completely covering the gate connection layer 34 .

Next, problems when applying the structure of the gate finger regions shown in FIGS. 15 and 16 to, for example, the MOSFET 100 including the SBD cell of the first embodiment will be described.

17 and 18 are schematic plan views of gate finger regions in the case of having SBD cells. FIG. 17 shows the pattern of the field oxide film, anode electrode, gate electrode and gate connection layer in the gate finger region. FIG. 18 shows patterns of p-type silicon carbide regions and SBD regions in gate finger regions.

As shown in FIG. 17, the anode electrode 16 and the anode electrode 66 are separated with the gate connection layer 34 interposed therebetween. Therefore, as shown in FIG. 18, the SBD region 17 and the SBD region 67 are also separated.

For example, if W2=70 μm, the distance from the SBD regions 17 and 67 to the central point X of the p-type region 84 is at least 35 μm, which is extremely large. Therefore, the pn junction diode formed by the p-type region 84 and the drift region 26 is hardly affected by the parallel-connected SBD cells.

Therefore, the pn junction diode formed by the p-type region 84 and the drift region 26 allows current to flow at an ON voltage of approximately 2.5 V, as indicated by the dotted line in FIG. In the main region 50, as indicated by the solid line in FIG. 19, injection of holes from the base region 28 to the drift region 26 does not occur until 3.4V. However, in the structures of FIGS. 17 and 18, when the voltage between the source and the drain exceeds 2.5 V, holes start to be injected into the drift region 26 at the pn junction of the gate finger region, which may cause conduction deterioration. be.

Therefore, in addition to the main region 50, the SBD regions are also arranged at predetermined intervals in the pn junctions of the incidental regions such as the gate finger regions 54 to suppress injection of holes from the pn junctions of the incidental regions into the drift region 26. is desirable.

In this embodiment, the p-type regions 84 are segmented in the second direction. SBD region 17 and SBD region 67 are connected and located between p-type regions 84 that are separated.

Therefore, as shown in FIG. 20, the distance from the SBD regions 17 and 67 to the point X ("d" in FIG. 20) is shortened. For example, if the width of the base region 28 is 2.5 μm and the interval is 1.5 μm, even if W2=70 μm, the distance d is 7.25 μm or less. Therefore, current flow through the pn junction diode formed by p-type region 84 and drift region 26 is suppressed.

The repetition period of the combination of SBD cells and MOSFET cells in the main region 50 is the first period. In the primary region 50, for the first period, the maximum distance from the SBD region 17 to the base region 28 is less than half the first period.

As described in the first embodiment, when n MOSFET cells are arranged for one SBD cell, n is preferably 5 or less from the viewpoint of suppressing conduction deterioration. Regardless of n in the main region 50, at least in the auxiliary regions, it is desirable that the distance from the SBD region to the pn junction in the main region 50 does not exceed the distance from the SBD region to the pn junction in the case of n=5.

As a function of n, the first period corresponding to n=5 is 6/(n+1) of the first period of the main region. Therefore, the distance from the SBD region of the incident region to the pn junction is preferably less than half of 6/(n+1) of the first period.

Further, from the viewpoint of making the distance from the SBD region to the pn junction equal to that of the main region 50, it is more desirable that the distance from the SBD region to the pn junction in the accessory region is less than half the first period.

In this embodiment, if the width of the base region 28 is 2.5 μm and the interval is 1.5 μm, half of 6/(n+1) of the first period is 12 μm because n=3. Also, half of the first period is 8 μm. Since the distance d is 7.25 μm or less, it satisfies both less than half of the first period of 6/(n+1) and less than half of the first period.

According to this embodiment, in addition to the main region 50, current is suppressed from flowing through the pn junction diode of the gate finger region 54, which is an auxiliary region. Therefore, it is possible to further suppress energization deterioration and improve reliability more than in the first embodiment.

(Fourth embodiment)
The semiconductor device of this embodiment differs from that of the third embodiment in the structure of the gate finger regions. The description of the content that overlaps with the third embodiment is omitted.

21 and 22 are schematic plan views of the gate finger regions of this embodiment. FIG. 21 shows the pattern of the field oxide film, anode electrode, gate electrode and gate connection layer in the gate finger region. FIG. 22 shows patterns of p-type silicon carbide regions and SBD regions in gate finger regions.

In the present embodiment, the gate connection layer 34 and the p-type region 84 are not separated in the second direction, and the width of the gate connection layer 34 in the first direction (“W1” in FIG. 21) and the p-type The width of the region 84 in the first direction (“W2” in FIG. 22) is narrowed. This shortens the distance from the SBD regions 17 and 67 to the point X ("d" in FIG. 22).

For example, if the width of the base region 28 is 2.5 μm, the interval is 1.5 μm, and W1=3 μm, the distance d from the SBD regions 17 and 67 to the point X is 8.3 μm or less.

In this embodiment, if the width of the base region 28 is 2.5 μm and the interval is 1.5 μm, half of 6/(n+1) of the first period is 12 μm because n=3. Also, half of the first period is 8 μm. Therefore, less than half of 6/(n+1) of the first period will be satisfied, but less than half of the first period will not be satisfied.

According to the present embodiment, as in the third embodiment, in addition to the main region 50, current is suppressed from flowing through the pn junction diodes of the gate finger regions 54, which are auxiliary regions. Therefore, it is possible to further suppress energization deterioration and improve reliability more than in the first embodiment.

(Fifth embodiment)
The semiconductor device of this embodiment differs from the third and fourth embodiments in the structure of the gate finger regions. Descriptions of the contents that overlap with those of the third and fourth embodiments are omitted.

23 and 24 are schematic plan views of the gate finger regions of this embodiment. FIG. 23 shows the pattern of the field oxide film, anode electrode, gate electrode and gate connection layer in the gate finger region. FIG. 24 shows patterns of p-type silicon carbide regions and SBD regions in gate finger regions.

In this embodiment, the anode electrodes 16 and the anode electrodes 66 are arranged with a half period shift between the first cell block and the second cell block. This shortens the distance from the SBD regions 17 and 67 to the point X ("d" in FIG. 24).

For example, if the width of the base region 28 is 2.5 μm, the interval is 1.5 μm, and W1=3 μm, the distance d from the SBD regions 17 and 67 to the point X is 7.6 μm or less.

In this embodiment, if the width of the base region 28 is 2.5 μm and the interval is 1.5 μm, half of 6/(n+1) of the first period is 12 μm because n=3. Also, half of the first period is 8 μm. Therefore, less than half of 6/(n+1) of the first period and less than half of the first period are both satisfied.

According to this embodiment, as in the third and fourth embodiments, in addition to the main region 50, current is suppressed from flowing through the pn junction diode of the gate finger region 54, which is an auxiliary region. Therefore, it is possible to further suppress energization deterioration and improve reliability more than in the first embodiment.

(Sixth embodiment)
In contrast to the first embodiment, the semiconductor device of the present embodiment includes a third electrode electrically connected to the first electrode, and an n-type first silicon carbide region provided in the silicon carbide layer. and a third electrode and extending in the first direction; and a fifth p-type silicon carbide region provided in the silicon carbide layer. a plurality of n-type sixth silicon carbide regions provided between the third electrode, having a higher n-type impurity concentration than the n-type first silicon carbide region, and electrically connected to the third electrode; region and an n-type first silicon carbide region provided between two adjacent p-type fifth silicon carbide regions among the plurality of p-type fifth silicon carbide regions, a plurality of second conductive layers extending in the direction of , provided in a first period and electrically connected to the third electrode, and two adjacent second conductive layers among the plurality of second conductive layers n (n=2, 3, 4, 5) second gate electrodes provided between the two conductive layers and extending in the first direction; a plurality of second gate insulating layers provided between the silicon carbide regions; n first gate electrodes provided between the n first gate electrodes and the n second gate electrodes; a gate layer connected to ends of the gate electrodes, connected to ends of n second gate electrodes, and wider than the first gate electrodes and the second gate electrodes; an insulating layer provided between the first silicon carbide region and thicker than the first gate insulating layer and the second gate insulating layer; and an n-type first silicon carbide region provided in the silicon carbide layer. and an insulating layer, connected to a p-type second silicon carbide region provided between two adjacent first conductive layers, and between two adjacent second conductive layers a p-type eighth silicon carbide region connected to a p-type fifth silicon carbide region provided therebetween and having a p-type impurity concentration lower than that of the p-type second silicon carbide region and the p-type fifth silicon carbide region; and a silicon carbide region of The description of the content that overlaps with the first and third embodiments is omitted.

25 and 26 are schematic plan views of the gate finger regions of this embodiment. FIG. 25 shows the pattern of the field oxide film, anode electrode, gate electrode and gate connection layer in the gate finger region. FIG. 26 shows patterns of p-type silicon carbide regions and SBD regions in the gate finger regions.

The gate finger region 54 has a first cell block and a second cell block with the gate connection layer (gate layer) 34 interposed therebetween. The first cell block has, for example, the structure shown in FIG. 1 of the first embodiment. The second cell block has, for example, the structure shown in FIG. 12 of the third embodiment.

As the first cell block and the second cell block, for example, the structure shown in FIG. 8 of the second embodiment can be applied.

FIG. 27 is a schematic cross-sectional view of the gate finger region of this embodiment. FIG. 27 is a BB' section of FIGS. 25 and 26. FIG.

This embodiment includes a p ⁻ -type region (p-type eighth silicon carbide region) 88 . P ⁻ -type region 88 is provided in silicon carbide layer 10 . A p ⁻ -type region 88 is provided between drift region 26 and field oxide film 81 .

The p ⁻ -type region 88 is connected to four base regions 28 provided between two adjacent anode electrodes 16 . Also, the p ⁻ -type region 88 is connected to four base regions 78 provided between two adjacent anode electrodes 66 .

The p-type impurity concentration of p ⁻ -type region 88 is less than the p-type impurity concentration of base region 28 and base region 78 . The p-type impurity concentration of the p ⁻ -type region 88 is lower than the p-type impurity concentrations of the base regions 28 and 78 by one order of magnitude or more, for example. The p-type impurity concentration of the p ⁻ -type region 88 is, for example, 1×10 ¹⁶ cm ⁻³ or more and 5×10 ¹⁶ cm ⁻³ or less.

Also, for example, p ^- type region 88 is shallower than base region 28 and base region 78 . The depth of the base region 28 is, for example, 0.1 μm or more and 0.3 μm or less.

Base region 28 and base region 78 do not extend under field oxide film 81 . Therefore, when the potential between the drain and the source is increased, the electric field concentrates at the ends of the base regions 28 and 78 of the cell near the gate finger regions 54, and there is a possibility that the withstand voltage is deteriorated.

In this embodiment, to prevent this, a lightly p-doped p ^- type region 88 is extended from the end of the base region 28, 78 of the cell near the gate finger regions 54 to under the field oxide 81. doing.

By doing so, when the reverse bias applied between the drain and the source is increased, the ends of the electric lines of force from the drain region 24 to the base regions 28 and 78 are dispersed in the p ⁻ -type region 88, Concentration at the base region 28, 78 edge of the cell is avoided.

This lightly doped p ^- type region 88 can be formed, for example, at the same time as the step of forming the chip peripheral termination region 56 (FIG. 10). Therefore, it can be realized without increasing the chip manufacturing process.

Moreover, even if a forward bias is applied to the junction between the drain and the source, the lightly doped p ⁻ -type region 88 has a very high resistance, so that almost no current flows. Therefore, almost no holes are injected into the drift region 26, and reliability problems due to expansion of stacking faults can be avoided.

According to this embodiment, in addition to the main region 50, current is suppressed from flowing through the pn junction diode of the gate finger region 54, which is an auxiliary region. Therefore, it is possible to further suppress energization deterioration and improve reliability more than in the first embodiment.

(Seventh embodiment)
In contrast to the first embodiment, the semiconductor device of the present embodiment includes a third electrode electrically connected to the first electrode, and an n-type first silicon carbide region provided in the silicon carbide layer. and a third electrode and extending in the first direction; and a fifth p-type silicon carbide region provided in the silicon carbide layer. a plurality of n-type sixth silicon carbide regions provided between the third electrode, having a higher n-type impurity concentration than the n-type first silicon carbide region, and electrically connected to the third electrode; region and an n-type first silicon carbide region provided between two adjacent p-type fifth silicon carbide regions among the plurality of p-type fifth silicon carbide regions, a plurality of second conductive layers extending in the direction of , provided in a first period and electrically connected to the third electrode, and two adjacent second conductive layers among the plurality of second conductive layers n (n=2, 3, 4, 5) second gate electrodes provided between the two conductive layers and extending in the first direction; a plurality of second gate insulating layers provided between the silicon carbide regions; n first gate electrodes provided between the n first gate electrodes and the n second gate electrodes; a gate layer connected to ends of the gate electrodes, connected to ends of the n second gate electrodes, and wider than the n first gate electrodes and the n second gate electrodes; an insulating layer provided between the gate layer and the n-type first silicon carbide region and thicker than the first gate insulating layer and the second gate insulating layer; p-type second silicon carbide provided between the first silicon carbide region and the insulating layer, provided between the p-type second silicon carbide region and the p-type fifth silicon carbide region, and a p-type ninth silicon carbide region spaced apart from the region and the p-type fifth silicon carbide region. Hereinafter, the description of the contents overlapping with those of the first and third embodiments will be omitted.

FIG. 28 is a schematic plan view of the gate finger regions of this embodiment. FIG. 28 shows patterns of p-type silicon carbide regions and SBD regions in gate finger regions.

The gate finger region 54 has a first cell block and a second cell block with the gate connection layer (gate layer) 34 interposed therebetween. The first cell block has, for example, the structure shown in FIG. 1 of the first embodiment. The second cell block has, for example, the structure shown in FIG. 12 of the third embodiment.

As the first cell block and the second cell block, for example, the structure shown in FIG. 8 of the second embodiment can be applied.

FIG. 29 is a schematic cross-sectional view of the gate finger region of this embodiment. FIG. 29 is a CC' section of FIG.

This embodiment includes a p-type region (ninth silicon carbide region) 90 . P-type region 90 is provided in silicon carbide layer 10 . P-type region 90 is provided between drift region 26 and field oxide film 81 .

P-type region 90 is provided between base region 28 and base region 78 . Also, the p-type region 90 and the base region 28 are separated. Also, the p-type region 90 and the base region 78 are separated.

P-type region 90 has substantially the same p-type impurity concentration and depth as base region 28 and base region 78 . P-type region 90 is formed at the same time as base region 28 and base region 78 .

P-type region 90 is not electrically connected to either source electrode 12 or source electrode 62 . P-type region 90 is in a floating state in which the potential is not fixed.

The p-type region 90 is not connected to the source electrodes 12,62. Therefore, even if a forward bias is applied between the drain and the source, holes are not injected into the drift region 26 under the gate finger regions 54 .

On the other hand, when a reverse bias is applied between the drain and the source, if the distance between the p-type region 90 and the base regions 28, 78 of the MOSFET cell portion is small, the potential of the p-type region 90 will be becomes substantially equal to the potential of the base regions 28 and 78 of the . Therefore, the ends of the lines of electric force are substantially uniform even under the gate finger regions 54, and the occurrence of problems such as a decrease in withstand voltage due to electric field concentration can be avoided.

From the viewpoint of alleviating electric field concentration, the distance between the p-type region 90 and the base region 28 is equal to or less than the distance between the adjacent base regions 28, and the distance between the p-type region 90 and the base region 78 is equal to or less than the distance between the adjacent base regions 78. should be less than or equal to the distance of

According to this embodiment, in addition to the main region 50, current is suppressed from flowing through the pn junction diode of the gate finger region 54, which is an auxiliary region. Therefore, it is possible to further suppress energization deterioration and improve reliability more than in the first embodiment.

In the third to seventh embodiments, the gate finger region 54 is used as an example of the incidental region. Also in other incidental regions such as the termination region 56 having a pn junction composed of the p-type base regions 28, 78 and the n ⁻ -type drift region 26 and the gate pad region 52, the pn junction region is divided or the pn junction region is notched. , disposing an electrode material that forms a Schottky junction with the drift region 26 in the dividing boundary or cut region of the pn junction region, connecting the Schottky junction material to the source electrodes 12 and 62, A Schottky junction connected in parallel with the pn junction of the can be placed in close proximity to raise the current and voltage thresholds at which the pn junction enters the on state. In addition, if necessary, an aluminum wiring layer is provided on the additional region via an insulating film, and if necessary, an opening is provided in the insulating film to ensure electrical connection between the aluminum electrode and a predetermined portion of the additional region. can maintain the functionality of the ancillary area.

In the first to seventh embodiments, the crystal structure of SiC is 4H—SiC, but the present invention is applicable to devices using SiC having other crystal structures such as 6H—SiC and 3C—SiC. It is also possible to apply It is also possible to apply a plane other than the (0001) plane to the surface of silicon carbide layer 10 .

Although aluminum (Al) is used as the p-type impurity in the first to seventh embodiments, boron (B) can also be used. Nitrogen (N) and phosphorus (P) have been exemplified as n-type impurities, but arsenic (As), antimony (Sb), etc. can also be used.

While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. For example, components of one embodiment may be substituted or modified with components of another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

10 silicon carbide layer 12 source electrode (first electrode)
14 drain electrode (second electrode)
16 anode electrode (first conductive layer)
18 gate electrode (first gate electrode)
20 gate insulating film (first gate insulating layer)
26 n ⁻ type drift region (first silicon carbide region)
28 p-type base region (p-type second silicon carbide region)
30 n ⁺ -type source region (n-type third silicon carbide region)
32 p ⁺ -type contact region (p-type fourth silicon carbide region)
34 gate connection layer (gate layer)
62 source electrode (third electrode)
66 anode electrode (second conductive layer)
68 gate electrode (second gate electrode)
70 gate insulating film (second gate insulating layer)
78 p-type base region (p-type fifth silicon carbide region)
80 n ⁺ -type source region (n-type sixth silicon carbide region)
81 field oxide film (insulating layer)
84 p-type region (p-type seventh silicon carbide region)
88 p ⁻ type region (p type eighth silicon carbide region)
90 p-type region (p-type ninth silicon carbide region)
100 MOSFET (semiconductor device)
200 MOSFET (semiconductor device)
300 MOSFET (semiconductor device)

Claims (5)

a first electrode;
a second electrode;
a silicon carbide layer at least partially provided between the first electrode and the second electrode;
an n-type first silicon carbide region provided in the silicon carbide layer;
a plurality of p-type second silicon carbide regions provided in the silicon carbide layer, provided between the n-type first silicon carbide region and the first electrode, and extending in a first direction; When,
provided in the silicon carbide layer, provided between the plurality of p-type second silicon carbide regions and the first electrode, and having a higher n-type impurity concentration than the n-type first silicon carbide region; a plurality of n-type third silicon carbide regions electrically connected to the first electrode;
contacting the n-type first silicon carbide region provided between two adjacent ones of the plurality of p-type second silicon carbide regions, extending in the first direction, and having a first period a plurality of first conductive layers provided in and electrically connected to the first electrode;
n (n=2, 3, 4, 5) first gate electrodes provided between two adjacent ones of the plurality of first conductive layers and extending in the first direction;
a plurality of first gate insulating layers provided between the n first gate electrodes and the n-type first silicon carbide region;
a portion of the first electrode in contact with one of the plurality of n-type third silicon carbide regions closest to one of the plurality of first conductive layers; an insulating film provided between one of the conductive layers;
A semiconductor device comprising 2. The semiconductor device according to claim 1 , wherein a junction between said plurality of first conductive layers and said first n-type silicon carbide region is a heterojunction or a Schottky junction. 3. The semiconductor device according to claim 1 , wherein said plurality of second p-type silicon carbide regions are provided with a second period of 1/(n+1) of said first period. 4. The semiconductor device according to claim 1, wherein said plurality of first conductive layers are part of said first electrode. 5. The semiconductor device according to claim 4, wherein said plurality of first conductive layers are made of the same material as said first electrode.

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