JP7199302B2 - Communication interface circuit - Google Patents

Description

The present invention relates to communication interface circuits.

Data transmission between transmitting and receiving circuits according to a common clock is widely used. In recent years, parallel data transmission between devices has become faster as the bandwidth of communication has increased. As a result, relative fluctuations in the clock phase between the transmitting side and the receiving side occur due to factors such as temperature fluctuations during communication. It is necessary to respond to

For example, Japanese Patent Application Laid-Open No. 2011-114387 (Patent Document 1) discloses that by adjusting the phase of an input clock, a reception clock, a first sampling clock whose phase is earlier than the reception clock, and a first sampling clock that is earlier than the reception clock. A communication interface circuit is described that is capable of coping with phase fluctuations in the validity period of a data window by using a three-phase clock of a second sampling clock with a slow phase.

Specifically, in the communication interface circuit of Patent Document 1, by comparing the results of sampling parallel data with the three-phase clocks, the start edge and end edge of the valid period of the data window are detected as the data capture of the reception clock. Edge proximity is detected, ie a reduction in timing margin. When a decrease in the timing margin is detected, the phase of the receive clock is adjusted in a direction to eliminate the closeness. As a result, when the clock phase fluctuates due to the influence of temperature drift or the like, the clock phase can be adjusted so as to compensate for the decrease in the timing margin with respect to the edge of the valid period of the data window.

JP 2011-114387 A

However, in the communication interface circuit of Patent Document 1, when the results of sampling the same data by the three-phase clocks do not match, the decrease in the timing margin is detected. There is concern that the timing margin cannot be confirmed. Further, as will be described later, the communication interface circuit of Patent Document 1 tends to adjust the clock phase near the boundary where the timing margin is allowed, so there is room for improvement in securing the timing margin.

SUMMARY OF THE INVENTION An object of the present invention is to provide a communication system having a clock phase control function for securing a timing margin for data transmission in response to fluctuations in the clock phase. An object of the present invention is to provide an interface circuit.

According to one aspect of the present invention, a communication interface circuit between a transmitting circuit and a receiving circuit for transmitting data signals in synchronization with a transmitting clock signal and a receiving clock signal based on a common clock is designed to have the same delay time. a phase sweep circuit; a timing margin test signal generator; a timing margin test circuit; and a phase control circuit. A first signal path carries a data signal from the transmitting circuit to the receiving circuit. The phase sweep circuit periodically sweeps the phase shift amount. The timing margin test signal generator generates a timing margin test signal whose signal level changes in phase according to the phase shift amount set by the phase sweep circuit in each clock cycle of the transmission clock signal. A second signal path conveys the timing margin test signal from the transmitter circuit to the receiver circuit. The timing margin test circuit is configured such that the timing at which the signal level of the timing margin test signal transmitted through the second signal path changes in the receiving circuit falls within an appropriate phase range in which a timing margin is ensured in data reception synchronized with the received clock signal. Determine whether or not it is included in The phase control circuit controls the phase of the transmission clock signal using the determination result of the timing margin test circuit for each swept phase shift amount.

According to the present invention, the range of the phase shift amount in which the timing margin is ensured can be obtained sequentially by using the timing margin test signal transmitted separately from the data signal. clock phase control for securing a timing margin of

2 is a block diagram illustrating the configuration of a communication interface circuit according to Embodiment 1; FIG. 4 is a waveform diagram for explaining an operation example of the communication interface circuit according to the first embodiment; FIG. 8 is a block diagram illustrating a configuration example of a communication interface circuit according to a second embodiment; FIG. 4 is a waveform diagram illustrating an example of multiphase clocks output from the voltage controlled oscillator shown in FIG. 3; FIG. 4 is a circuit diagram illustrating a configuration example of a voltage controlled oscillator shown in FIG. 3; FIG. 8 is a block diagram illustrating characteristics of an output buffer of a transmission circuit of a communication interface circuit according to a second embodiment; FIG. 10 is a flowchart for explaining control processing of a phase shift amount of a transmission clock signal in a communication interface circuit according to a third embodiment;

BEST MODE FOR CARRYING OUT THE INVENTION Below, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the same reference numerals are given to the same or corresponding parts in the drawings, and the description thereof will not be repeated in principle.

Embodiment 1.
FIG. 1 is a block diagram illustrating the configuration of a communication interface circuit according to Embodiment 1. FIG.

Referring to FIG. 1, communication interface circuit 10 according to the first embodiment is arranged as part of the configuration of transmission circuit 100 and reception circuit 200 that transmit data according to clock CLK supplied from oscillator 5. can be done.

In the configuration example of FIG. 1, the communication interface circuit 10 includes a timing margin test signal generator 110, a phase sweep circuit 140, and a phase control circuit 150 provided in the transmission circuit 100, and a timing signal generator 110 provided in the reception circuit 200. and a margin test circuit 210 .

Transmission circuit 100 includes data transmission circuit 160 . Data transmission circuit 160 outputs data signal SD in synchronization with transmission clock signal CLK-D. Data receiving circuit 220 receives data signal SD output from data transmitting circuit 160 in synchronization with reception clock signal CLK-RX obtained by propagation delay of clock CLK. Data transmission between the transmission circuit 100 and the reception circuit 200 is executed by transmission/reception of the data signal SD by the data transmission circuit 160 and the data reception circuit 220 .

In the transmission circuit 100, the phase sweep circuit 140 and the phase control circuit 150 are supplied with a clock signal CLK-TX obtained by delaying the propagation of the clock CLK.

Phase sweep circuit 140 generates a swept clock signal CLK-P having a periodically slowly swept phase based on clock signal CLK-TX. Phase shift amount Psh of sweep clock signal CLK-P with respect to clock signal CLK-TX changes stepwise and cyclically within the range of 0 [deg] to 360 [deg]. For example, when sweeping is performed in 32 steps at intervals of 1 [ms], the phase shift amount increases by Δθu=11.25 [deg] every 1 [ms]. That is, the phase shift amount Psh changes stepwise from 0 [deg], 11.25 [deg], 22.5 [deg], . = 0 [deg]), it again changes cyclically to 11.25 [deg], 22.5 [deg], . The time interval at which the phase shift amount Psh changes is set longer than the period (clock cycle) of the clock signal CLK-TX.

Phase sweep circuit 140 outputs phase shift amount Psh of sweep clock signal CLK-P to phase control circuit 150 together with sweep clock signal CLK-P. For example, when the phase is swept in 32 stages as described above, the count value i (i: an integer that cycles in the range of 0 to 31) is used and is expressed as Psh=i Δθu. It is also possible to use the value i equivalently to the phase shift amount Psh. In the phase sweep circuit 140, the sweep step Δθu corresponds to the “first unit phase”, and the number of sweep steps (360/Δθu) corresponds to the “first number”.

The timing margin test signal generator 110 generates a timing margin test signal Sp for timing margin confirmation, which is toggled for each clock cycle for timing margin confirmation, separately from the data signal SD. For example, the timing margin test signal generator 110 can be configured by a T-type flip-flop that receives the sweep clock signal CLK-P from the phase sweep circuit 140 and outputs the timing margin test signal Sp. As a result, the timing margin test signal Sp changes in signal level in phase according to the phase shift amount swept by the phase sweep circuit 140 in each clock cycle. The timing margin test signal Sp is transmitted from the transmitter circuit 100 to the timing margin test circuit 210 of the receiver circuit 200 via the signal path 102 .

The timing margin test circuit 210 receives the reception clock signal CLK-RX input to the data reception circuit 220 and the timing margin test signal Sp from the timing margin test signal generator 110, and outputs the timing margin determination result signal Sf. do. The timing at which the signal level of the timing margin test signal Sp changes in the timing margin determination result signal Sf is within a region (data window valid period), it is set to a logic high level (hereinafter simply referred to as "H level"). be set). Timing margin determination result signal Sf is input to phase control circuit 150 of transmission circuit 100 .

The timing margin determination result signal Sf and the phase shift amount Psh in the phase sweep circuit 140 are input to the phase control circuit 150 . As described above, while the phase shift amount Psh (count value i) is swept, the timing margin determination result signal Sf also periodically changes between the H level and the L level. The phase control circuit 150 collects the timing margin determination result signal Sf for each phase shift amount within the range of 0 [deg] to 360 [deg], thereby obtaining the phase shift amount at which the timing margin determination result signal Sf=H level. range can be obtained. For example, the phase control circuit 150 can determine the optimum phase shift amount Psh* that maximizes the timing margin according to the median value of the phase shift amount range (Sf=H level). The optimum phase shift amount Psh* can also be set to an intermediate value of phase shift amounts that are set stepwise by the phase sweep circuit 140 . In this manner, the phase control circuit 150 sets the optimum phase shift amount Psh* using the timing margin determination result signal Sf, that is, the determination result of the timing margin test circuit 210 .

Phase control circuit 150 generates transmission clock signal CLK-D so as to have a phase shift amount according to optimum phase shift amount Psh* with respect to clock signal CLK-TX. Similarly to the phase shift amount in the phase sweep circuit 140, the amount of phase shift in the phase control circuit 150 is set in increments of 360/J [deg] according to a predetermined number of stages J (J: an integer of 3 or more). It can be done step by step. That is, the number of stages J in the phase control circuit 150 corresponds to the "second number", and 360/L [deg] corresponds to the "second unit phase".

A case in which the number of stages of the phase shift amount in phase sweep circuit 140 and the number of stages L in phase control circuit 150 are the same will be described below as a representative example. It may be greater than the number of steps in the phase shift amount in circuit 140 . In this case, as described above, it is possible to set the optimum phase shift amount Psh* to the intermediate value of the phase shift amounts that are set stepwise by the phase sweep circuit 140 .

Data transmission circuit 160 outputs data signal SD in synchronization with transmission clock signal CLK-D whose phase is controlled by phase control circuit 150 . For example, the data transmission circuit 160 can be configured by a D-type flip-flop in which a transmission clock signal CLK-D is input to a C (clock) terminal and transmission data is input to a D (data) terminal.

Data signal SD is transmitted from transmitting circuit 100 to data receiving circuit 220 via signal path 101 . The signal path 101 for the data signal SD and the signal path 102 for the timing margin test signal Sp are designed to have the same delay time. Data reception circuit 220 receives data signal SD in synchronization with reception clock signal CLK-RX. Signal path 101 corresponds to one embodiment of "first signal path" and signal path 102 corresponds to one embodiment of "second signal path."

FIG. 2 shows a waveform diagram for explaining an operation example of the communication interface circuit according to the first embodiment.

Referring to FIG. 2, a period (phase range) in which a timing margin is ensured and a period (phase range) in which the timing margin is not ensured are defined in data reception synchronized with reception clock signal CLK-RX. In FIG. 5 , the phase range in which the timing margin is not ensured is shaded, and the phase range in which the timing margin is ensured (hereinafter also referred to as “appropriate phase range”) is outlined.

The reception clock signal CLK-RX in the reception circuit 200 and the clock signal CLK-TX input to the phase sweep circuit 140 and the phase control circuit 150 are delays of the common clock CLK. Therefore, the sweep clock signal CLK-P, whose phase shift amount with respect to the clock signal CLK-TX periodically changes in the range of 0 [deg] to 360 [deg], is also 0 [deg] with respect to the reception clock signal CLK-RX. deg] to 360 [deg].

Timing margin test signal Sp is toggled at each rising edge (transition from L level to H level) of sweep clock signal CLK-P, and repeats transition between H level and L level. As described above, changes in the signal level of timing margin test signal Sp occur at the phases swept by phase sweep circuit 140 .

In the example of FIG. 2, at time ta, the phase shift amount Psh=0 [deg] between the timing margin test signal Sp and the received clock signal CLK-RX, and at time tb thereafter, the phase shift amount Psh=Δθu [deg]. ]. Furthermore, since the phase shift amount by the phase sweep circuit 140 changes with the passage of time, the phase shift amount Psh=180 [deg] at time tc, and the phase shift amount Psh=300 [deg] at time td. be.

The timing margin determination result signal Sf is set to H level when the level transition timing of the timing margin test signal Sp is within the proper phase range. On the other hand, when the level transition timing of the timing margin test signal Sp is outside the proper phase range, the timing margin determination result signal Sf is set to L level.

In the example of FIG. 2, at times ta, tb, and td, the level of the timing margin test signal Sp transitions within the proper phase range, so the timing margin determination result signal Sf is set to H level. On the other hand, at time tc, the level of the timing margin test signal Sp transitions outside the proper phase range, so the timing margin determination result signal Sf is set to L level.

Therefore, the phase shift amount of the transmission clock signal CLK-D with respect to the clock signal CLK-TX corresponds to the phase shift amount for one cycle (0 [deg] to 360 [deg]) including the phase shift amount at the time tc. The optimum value can be set according to the appropriate phase range in which the timing margin for the received clock signal CLK-RX is ensured, based on the timing margin determination result signal Sf. For example, the optimum phase shift amount Psh* can be set to an optimum value corresponding to the vicinity of the center of the proper phase range. In the example of FIG. 2, the optimum phase shift amount Psh* is set so that the sweep clock signal CLK-P and the transmission clock signal CLK-D at time ta have the same phase. Data signal SD is transmitted from data transmission circuit 160 in synchronization with transmission clock signal CLK-D.

The data receiving circuit 220 receives the data signal SD transmitted in synchronization with the phase-controlled transmission clock signal CLK-D. This enables reception near the center of the phase range in which the timing margin is ensured. For example, a delay time difference between the timing margin test signal Sp and the data signal SD, a phase quantization error caused by discretely sweeping the phase of the timing margin test signal Sp, and a phase error caused by discretely setting the phase of the data signal SD Quantization error, detection error of the timing margin test circuit 210, etc. may have an effect, but in general, when the phase range in which the timing margin is ensured is divided into three equal parts, reception occurs in the middle 1/3 period. It is expected to be possible.

On the other hand, in Patent Document 1, as described above, the phase of the reception clock is adjusted so as to avoid the state where the edge of the valid period exists between the reception clock and the first or second sampling clock. Since it is adjusted, the clock phase tends to be adjusted near the boundary where the timing margin is allowed, so it cannot be expected to be received in the middle ⅓ period. As a result, a sufficient timing margin cannot always be ensured, and there is concern that resistance to power supply voltage fluctuations, crosstalk noise, and the like will be insufficient.

The optimum phase shift amount Psh* may also be determined by adding an offset value corresponding to the delay time difference between the timing margin test signal Sp and the data signal SD to the optimum value set according to the proper phase range. It is possible. Even when adding such an offset value, the phase shift amount (optimal phase shift amount Psh*) of the transmission clock signal CLK-D is set according to the appropriate phase range in which the timing margin for the reception clock signal CLK-RX is ensured. It is understood that

As a result, according to the communication interface circuit of the first embodiment, the timing margin confirmation test for the swept clock phase can be executed in parallel with the transmission of the data signal SD. Then, the optimum phase shift amount Psh* under the current phase fluctuation can be dynamically obtained from the timing margin test signal Sp for each swept phase shift amount. As a result, it is possible to realize a clock phase control function for securing a timing margin for data transmission in response to phase fluctuations.

Embodiment 2.
In the second embodiment, a configuration example of the communication interface circuit in the transmission circuit 100 will be further described.

FIG. 3 is a block diagram illustrating a configuration example of a communication interface circuit according to the second embodiment.

Referring to FIG. 3 , transmission circuit 100 includes a PLL (Phase Locked Loop) circuit 300 , a counter 360 and a control circuit 370 . The PLL circuit 300 has a voltage controlled oscillator (VCO) 310, a phase detector 330, a loop filter 340, and phase selection circuits 351-353.

The voltage controlled oscillator 310 generates J (J: an integer of 3 or more) clocks CLKM-j (j: an integer of 1 to J) with different phases corresponding to the number of stages J of phase shift amount adjustment in the phase control circuit 150. ) to generate a multiphase clock.

FIG. 4 is a waveform diagram illustrating an example of the multiphase clocks output from the voltage controlled oscillator 310. As shown in FIG.

Referring to FIG. 4, clocks CLKM-j (j=1 to J) forming a multiphase clock have the same frequency as clock signal CLK-TX and are out of phase with each other. For example, CLKM-1 (j=1) has a phase shift amount (phase delay) of Δθu with respect to the reference phase indicated by the dotted line, and CLKM-2 (j=2) has and has a phase shift amount (phase delay) of Δθu.

CLKM-l (l = J/2) has a phase shift amount of Psh = 180 [deg] with respect to the reference phase indicated by the dotted line, and CLKM-J (j = J) is indicated by the dotted line. It is in phase with the reference phase. Thus, the multiphase clock is composed of a plurality of (J) clocks CLKM-j whose phases are different in stages.

FIG. 5 shows a configuration example of the voltage controlled oscillator 310 for generating the multiphase clocks of FIG.

Referring to FIG. 5, voltage controlled oscillator 310 includes a plurality of series-connected (K stages: odd number of stages) inverters 311 forming an inverter chain, and variable current sources arranged corresponding to each inverter 311. 315a and 315b. The drive current Id of each inverter 311 is increased or decreased according to the control voltage Vlp from the loop filter 340 by each variable current source 315a, 315b.

The plurality of inverters 311 constitute a ring oscillator by connecting the output of the inverter 311 at the final stage to the input of the inverter 311 at the first stage. The oscillation frequency of the ring oscillator varies depending on the driving current Id that determines the delay time of each inverter 311. FIG. Therefore, by changing the driving current Id of each inverter 311 according to the control voltage Vlp, the oscillation frequency of the ring oscillator is controlled.

J clocks CLKM-j constituting the multi-phase clock shown in FIG. 4 can be generated by appropriately extracting outputs of different nodes of the inverter chain formed by the plurality of inverters 311, that is, outputs of different inverters 311. .

Referring to FIG. 3 again, clocks CLKM-j forming a multiphase clock are input to phase selection circuits 351-353. Each of phase selection circuits 351-353 selectively outputs one of J clocks CLKM-j (j=1 to J) forming a multiphase clock.

Phase selection circuit 352 selects a fixed specific phase clock (CLKMk) from among multiphase clocks CLKMj and outputs the selected clock (CLKMk) to output buffer 152 . The clock CLKMk is output to the outside of the transmission circuit 100 via the output buffer 112 and then re-input to the transmission circuit 100 via the input buffer 104 . Clock CLKMk is input to phase detector 330 of PLL circuit 300 as a feedback input of a phase locked loop (PLL). Phase detector 330 also receives clock signal CLK-TX as a reference input for a phase locked loop (PLL).

Phase detector 330 outputs a pulse voltage having a duty corresponding to the amount of phase shift between clock signal CLK-TX (reference input) and feedback input (clock CLKMk). A pulse voltage from the phase detector 330 is converted into a control voltage Vlp by a loop filter 340 composed of a low-pass filter. The control voltage Vlp corresponds to the integrated value of the pulse voltage from phase detector 330 .

The drive current Id of each inverter 311 is controlled by the variable current sources 315a and 315b of FIG. 5 according to the control voltage Vlp, thereby forming a phase-locked loop that feeds back the clock CLKMk of the specific phase described above. As a result, the multiphase clocks CLKMj output from the voltage controlled oscillator 310 are maintained at the same frequency.

The counter 360 increments or decrements the count value i by 1 each time a predetermined time elapses. Alternatively, the count value i may be incremented or decremented by 1 every N cycles (N: natural number) of the clock signal CLK-TX. The count value i is incremented or decremented so as to circulate within the range from the minimum value 0 to the maximum value I (I: natural number). The maximum value I can correspond to the number J of clocks forming the multiphase clock CLKM-j (I+1=J). The count value i is given to the phase selection circuit 351 and the control circuit 370 as information indicating the phase shift amount Psh.

The phase selection circuit 351 sequentially selects and outputs one of the clocks CLKM-1 to CLKM-J forming the multiphase clock according to the count value i (for example, selects as j=i). Thus, by sequentially selecting one of the J clocks with different phases in stages, the phase shift amount Psh with respect to the clock signal CLK-TX is within the range of 0 [deg] to 360 [deg]. A swept, swept clock signal CLK-P can be obtained.

The sweep clock signal CLK-P is input to a T-type flip-flop (not shown) that constitutes the timing margin test signal generator 110 . The output signal of the T-type flip-flop is output from the transmission circuit 100 via the output buffer 112 as the timing margin test signal Sp. As shown in FIG. 1, timing margin test signal Sp is conveyed by signal path 101 to timing margin test circuit 210 of receiver circuit 200 .

A timing margin determination result signal Sf from the timing margin test circuit 210 (receiving circuit 200 ) is input to the control circuit 370 via the input buffer 154 . Furthermore, the count value i from the counter 360 is input to the control circuit 370 . As a result, the control circuit 370 provides a count value i (phase shift amount) at which the timing margin determination result signal Sf changes from H level to L level, and a count value at which the timing margin determination result signal Sf changes from L level to H level. By storing information indicating the value i (phase shift amount), a phase range in which a timing margin is secured within the range of the phase shift amount for one cycle (Psh=0 [deg] to 360 [deg]). , and the phase range in which the timing margin is not ensured can be distinguished by the range of the count value i. Therefore, the control circuit 370 can determine the optimum count value i* corresponding to the optimum phase shift amount Psh* in the current phase fluctuation situation according to the count value i indicating the median value of the phase range in which the timing margin is ensured. can.

The phase selection circuit 353 selects one of the clocks CLKm-1 to CLKm-J constituting the multiphase clocks according to the optimum phase shift amount Psh* (optimum count value i*) determined by the control circuit 370. . The selected clock is output as the transmission clock signal CLK-D.

The transmission clock signal CLK-D is input to a D-type flip-flop (not shown) forming the data transmission circuit 160 . The output signal of the D-type flip-flop is output from the transmission circuit 100 via the output buffer 162 as the data signal SD. As shown in FIG. 1, data signal SD is transmitted to data receiving circuit 220 of receiving circuit 200 through signal path 102 designed to have the same delay time as signal path 101 .

As described above, according to the configuration example of FIG. 3 according to the second embodiment, the multiphase clocks generated by the PLL circuit 300 are shared by the PLL circuit 300, the counter 360, and the phase selection circuit 351. In addition to realizing the function of the phase sweep circuit 140 of FIG. 1, the function of the phase control circuit 150 of FIG. As a result, the phase sweep circuit 140 and the phase control circuit 150 can be efficiently configured with a small area.

In the configuration example of FIG. 3, the phase sweep circuit 140 generates the sweep clock signal CLK-P by sequentially selecting all of the J clocks that make up the multiphase clocks. can be thinned out to generate the sweep clock signal CLK-P such that the phase shift amount changes in (J/2) steps within the range of 0 [deg] to 360 [deg], for example. For example, by changing the count value i by the counter 360 by +n or -n (n: an integer of 2 or more, for example, n = 2), one cycle (Psh = 0 [deg] to 360 [deg]) A timing margin test based on the amount of phase shift can be performed in a relatively short period of time. On the other hand, phase control circuit 150 selects J clocks that make up the multiphase clock, and uses the intermediate value of the phase shift amount sequentially set by phase sweep circuit 140 to adjust the phase of transmission clock signal CLK-D. It is possible to control the shift amount with the same precision as in the example of FIG.

Furthermore, as shown in FIG. 6, in the communication interface circuit according to the second embodiment, in the transmission circuit 100 shown in FIG. It can be configured such that there is a correlation in the delay time change characteristics. In the present embodiment, the correlation between the change characteristic of the delay time with respect to the temperature change means that at least the polarity of the change (increase or decrease) of the delay time with respect to the temperature change is the same, or further, the change at that time shall indicate that the slopes are equivalent. For example, such delay temperature characteristics can be realized by fabricating output buffers 112, 152, and 162 using cells belonging to the same library provided by a semiconductor vendor.

According to the configuration of FIG. 6, the reference input (clock CLKM-k) of the PLL circuit 300 is once output to the outside of the transmission circuit 100 in the same way as the timing margin test signal Sp and the data signal SD, and then the transmission circuit 100 can be fed back to the PLL circuit 300 (phase detector 330).

Furthermore, the output buffer 152 through which the reference input (clock CLKM-k) of the PLL circuit 300 passes has a correlation with the delay temperature characteristics of the output buffers 112 and 162 through which the timing margin test signal Sp and the data signal SD pass. there is As a result, even if the delay in the output buffer, which is a dominant factor in the delay occurring in the transmission circuit 100, fluctuates depending on the temperature change, the temperature fluctuation can be absorbed by the PLL.

Embodiment 3.
Details of the phase shift amount control in the phase control circuit 150 in the communication interface circuit according to the first or second embodiment will be described.

FIG. 7 is a flowchart for explaining control processing of the phase shift amount of the transmission clock signal in the communication interface circuit according to the third embodiment. The control process shown in FIG. 7 can be executed each time the phase of the sweep clock signal CLK-P is swept by 360 [deg] and the optimum phase shift amount Psh* is updated.

Referring to FIG. 7, phase control circuit 150, in step (hereinafter simply referred to as “S”) 110, determines the optimum phase shift amount Psh* obtained by the timing margin confirmation test under the current phase fluctuation situation. After obtaining the latest value, the phase shift amount Psh currently selected by the phase selection circuit 353 is compared with the optimum phase shift amount Psh* in S120. In the configuration example of FIG. 3, based on the optimum count value i* (corresponding to the currently selected phase shift amount Psh) currently used by the phase selection circuit 353 to select the multiphase clock, and the timing margin confirmation test, The newly calculated latest optimum count value i* (corresponding to the latest optimum phase shift amount Psh*) is compared.

If the optimum phase shift amount Psh* and the current phase shift amount Psh match (YES in S120), the phase control circuit 150 maintains the current phase shift amount Psh in S130. Thereby, the selection of the multiphase clocks by the phase selection circuit 353 is maintained.

If the optimum phase shift amount Psh* and the current phase shift amount Psh do not match (NO determination in S120), the phase control circuit 150 performs S140 to determine the optimum phase shift amount Psh* and the current phase shift amount. Determine the polarity of the difference in Psh. Furthermore, in order to reduce the phase difference between the optimum phase shift amount Psh* and the current phase shift amount Psh, the phase control circuit 150 determines whether the current phase shift amount Psh should be changed in the positive direction or the negative direction. is determined by S140 to S145.

When Psh*>Psh (YES in S140), the phase control circuit 150 calculates the positive phase difference parameter ΔPsh+=Psh*−Ph in S141, and calculates the negative phase difference parameter ΔPsh+=Psh*−Ph in S142. Calculate the parameter ΔPsh-=Psh+360 [deg]-Psh*.

On the other hand, when Psh*<Psh (NO in S140), the phase control circuit 150 calculates the phase difference parameter ΔPsh+ and the phase difference parameter ΔPsh−, contrary to the case of Psh*>Psh. do. Specifically, the positive direction phase difference parameter ΔPsh+=Psh*+360 [deg]−Psh is calculated in S143, and the negative direction phase difference parameter ΔPsh−=Psh−Psh* is calculated in S144.

At S145, the phase control circuit 150 compares the phase difference parameter ΔPsh+ and the phase difference parameter ΔPsh− calculated at S141 to S144. When ΔPsh+<ΔPsh− (YES in S145), the phase difference in the positive direction is smaller, so the phase shift amount Psh is changed by +1 step through S150. As a result, the selection of the multiphase clocks by the phase selection circuit 353 is shifted by one in the direction of increasing the phase shift amount. For example, in the configuration example of FIG. 3, the phase selection circuit 353 selects the transmission clock signal CLK-D from the clock CLKM-m (m: an integer of 2 to (J-1)) to the clock CLKM-(m+1). switch.

On the other hand, when ΔPsh+>ΔPsh− (NO determination in S145), the phase difference in the negative direction is smaller, so the phase shift amount Psh is changed by -1 step through S160. As a result, the selection of the multiphase clocks by the phase selection circuit 353 is shifted by one in the direction of decreasing the phase shift amount. For example, in the configuration example of FIG. Toggle selection.

Rather than performing simple comparison processing between the optimum phase shift amount Psh* and the current phase shift amount Psh, the determination processing from S141] to S145 enables the optimum phase shift amount Psh* and the current phase shift amount Psh to be 0 [ deg] (or 360 [deg]), it is possible to appropriately adjust the increase or decrease of the phase shift amount.

As described above, in the communication interface circuit according to the third embodiment, in the configuration example of FIG. 3, the phase shift amount is controlled in steps of 360/J [deg], and the phase shift amount is is approximated by 360/J [deg] (that is, in steps of 1). As a result, in the clock phase control for securing the timing margin corresponding to the phase fluctuations, glitches are generated in the transmission clock signal CLK-D due to rapid phase fluctuations, and data is garbled due to setup/hold violations in the data transmission circuit 220. can be prevented.

It should be considered that the embodiments disclosed this time are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the scope of the claims rather than the above description, and is intended to include all modifications within the scope and meaning equivalent to the scope of the claims.

5 oscillator, 10 communication interface circuit, 100 transmission circuit, 101, 102 signal path, 104, 154 input buffer, 110 timing margin test signal generator, 112, 152, 162 output buffer, 140 phase sweep circuit, 150 phase control circuit, 160 data transmission circuit, 200 reception circuit, 210 timing margin test circuit, 220 data reception circuit, 300 PLL circuit, 310 voltage controlled oscillator, 311 inverter, 315 variable current source, 330 phase detector, 340 loop filter, 351 to 353 phase Selection circuit 360 Counter 370 Control circuit CLK Clock CLK-D Transmission clock signal CLK-P Sweep clock signal CLK-RX Reception clock signal CLKM-j Multiphase clock CLKM-k Reference clock (PLL circuit) , Psh phase shift amount, Psh* optimum phase shift amount, SD data signal, Sf timing margin determination result signal, Sp timing margin test signal, Vlp control voltage (PLL circuit), i count value, i* optimum count value.

Claims (7)

A communication interface circuit between a transmitting circuit and a receiving circuit that transmits a data signal in synchronization with a transmitting clock signal and a receiving clock signal based on a common clock,
a first signal path that communicates the data signal from the transmitting circuit to the receiving circuit;
a phase sweep circuit that periodically sweeps the phase shift amount;
a timing margin test signal generator for generating a timing margin test signal whose signal level changes in phase according to the phase shift amount set by the phase sweep circuit in each clock cycle of the transmission clock signal;
a second signal path designed to have a delay time equal to that of the first signal path for transmitting the timing margin test signal from the transmission circuit to the reception circuit;
In the receiving circuit, the timing at which the signal level of the timing margin test signal transmitted through the second signal path changes is within an appropriate phase range in which a timing margin is ensured in data reception synchronized with the received clock signal. a timing margin test circuit for determining whether or not it is included;
and a phase control circuit that controls the phase of the transmission clock signal using the determination result of the timing margin test circuit for each of the swept phase shift amounts. 2. The communication interface circuit according to claim 1, wherein said phase control circuit changes the phase of said transmission clock signal according to said phase shift amount range determined to be included in said proper phase range. The phase sweep circuit changes the phase shift amount step by step by a first unit phase obtained by dividing the phase for one cycle by a first number,
2. The phase control circuit sets the phase of the transmission clock signal according to a multiple of a second unit phase obtained by dividing the phase for one cycle by a second number larger than the first number. 3. The communication interface circuit according to 2. the phase sweep circuit generates a sweep clock signal having the same frequency as the clock and a phase according to the swept phase shift amount;
3. The communication interface circuit of claim 1, wherein said timing margin test signal generator changes said signal level of said timing margin test signal in response to one edge of said sweep clock signal. further comprising a PLL circuit including a voltage oscillator circuit having an inverter chain;
the voltage oscillator circuit generates a plurality of clocks output from different nodes of the inverter chain and having different phases in stages;
The phase sweep circuit generates the sweep clock signal by sequentially selecting one of at least a portion of the plurality of clocks;
The phase control circuit selects, from the plurality of clocks, a clock having a phase shift amount close to the center of the phase shift amount range determined to be included in the proper phase range, and uses it as the transmission clock signal. 5. The communication interface circuit according to claim 4, controlling the phase of said transmission clock signal by outputting. a first output buffer for outputting the data signal to the outside of the transmission circuit;
a second output buffer for outputting the timing margin test signal to the outside of the transmission circuit;
a third output buffer for outputting a fixed-phase reference clock out of the plurality of clocks generated by the voltage oscillator circuit to the outside of the transmission circuit;
an input buffer for inputting the reference clock to the transmission circuit;
the third output buffer is configured to have a correlation between the first output buffer and the second output buffer in delay time change characteristics with respect to temperature change,
6. The communication interface circuit according to claim 5, wherein said PLL circuit forms a phase-locked loop in which said reference clock that has passed through said third output buffer and said input buffer is fed back to generate said plurality of clocks. The phase of the transmission clock signal is controlled in steps obtained by dividing the phase of one cycle by a predetermined number of divisions,
The phase control circuit is
When the optimum phase shift amount corresponding to the center of the range of phase shift amounts determined to be included in the proper phase range is different from the current phase shift amount, the phase shift amount is increased by one step. 7. The communication interface circuit according to any one of claims 4 to 6, wherein the phase of said transmission clock signal is changed so as to approach the amount of phase shift.

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